Lines Matching refs:rs1
797 Reg rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FpBinOp() argument
800 (assembler->*opS)(rd, rs1, rs2); in FpBinOp()
803 (assembler->*opD)(rd, rs1, rs2); in FpBinOp()
808 FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FAdd() argument
809 FpBinOp<FRegister, &Riscv64Assembler::FAddS, &Riscv64Assembler::FAddD>(rd, rs1, rs2, type); in FAdd()
813 FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FSub() argument
814 FpBinOp<FRegister, &Riscv64Assembler::FSubS, &Riscv64Assembler::FSubD>(rd, rs1, rs2, type); in FSub()
818 FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FDiv() argument
819 FpBinOp<FRegister, &Riscv64Assembler::FDivS, &Riscv64Assembler::FDivD>(rd, rs1, rs2, type); in FDiv()
823 FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FMul() argument
824 FpBinOp<FRegister, &Riscv64Assembler::FMulS, &Riscv64Assembler::FMulD>(rd, rs1, rs2, type); in FMul()
828 FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FMin() argument
829 FpBinOp<FRegister, &Riscv64Assembler::FMinS, &Riscv64Assembler::FMinD>(rd, rs1, rs2, type); in FMin()
833 FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FMax() argument
834 FpBinOp<FRegister, &Riscv64Assembler::FMaxS, &Riscv64Assembler::FMaxD>(rd, rs1, rs2, type); in FMax()
838 XRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FEq() argument
839 FpBinOp<XRegister, &Riscv64Assembler::FEqS, &Riscv64Assembler::FEqD>(rd, rs1, rs2, type); in FEq()
843 XRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FLt() argument
844 FpBinOp<XRegister, &Riscv64Assembler::FLtS, &Riscv64Assembler::FLtD>(rd, rs1, rs2, type); in FLt()
848 XRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FLe() argument
849 FpBinOp<XRegister, &Riscv64Assembler::FLeS, &Riscv64Assembler::FLeD>(rd, rs1, rs2, type); in FLe()
856 Reg rd, FRegister rs1, DataType::Type type) { in FpUnOp() argument
859 (assembler->*opS)(rd, rs1); in FpUnOp()
862 (assembler->*opD)(rd, rs1); in FpUnOp()
867 FRegister rd, FRegister rs1, DataType::Type type) { in FAbs() argument
868 FpUnOp<FRegister, &Riscv64Assembler::FAbsS, &Riscv64Assembler::FAbsD>(rd, rs1, type); in FAbs()
872 FRegister rd, FRegister rs1, DataType::Type type) { in FNeg() argument
873 FpUnOp<FRegister, &Riscv64Assembler::FNegS, &Riscv64Assembler::FNegD>(rd, rs1, type); in FNeg()
877 FRegister rd, FRegister rs1, DataType::Type type) { in FMv() argument
878 FpUnOp<FRegister, &Riscv64Assembler::FMvS, &Riscv64Assembler::FMvD>(rd, rs1, type); in FMv()
882 XRegister rd, FRegister rs1, DataType::Type type) { in FMvX() argument
883 FpUnOp<XRegister, &Riscv64Assembler::FMvXW, &Riscv64Assembler::FMvXD>(rd, rs1, type); in FMvX()
887 XRegister rd, FRegister rs1, DataType::Type type) { in FClass() argument
888 FpUnOp<XRegister, &Riscv64Assembler::FClassS, &Riscv64Assembler::FClassD>(rd, rs1, type); in FClass()
892 Location out, XRegister rs1, int32_t offset, DataType::Type type) { in Load() argument
896 __ Loadbu(out.AsRegister<XRegister>(), rs1, offset); in Load()
899 __ Loadb(out.AsRegister<XRegister>(), rs1, offset); in Load()
902 __ Loadhu(out.AsRegister<XRegister>(), rs1, offset); in Load()
905 __ Loadh(out.AsRegister<XRegister>(), rs1, offset); in Load()
908 __ Loadw(out.AsRegister<XRegister>(), rs1, offset); in Load()
911 __ Loadd(out.AsRegister<XRegister>(), rs1, offset); in Load()
914 __ Loadwu(out.AsRegister<XRegister>(), rs1, offset); in Load()
917 __ FLoadw(out.AsFpuRegister<FRegister>(), rs1, offset); in Load()
920 __ FLoadd(out.AsFpuRegister<FRegister>(), rs1, offset); in Load()
931 Location value, XRegister rs1, int32_t offset, DataType::Type type) { in Store() argument
938 __ Storew(tmp, rs1, offset); in Store()
945 __ Storeb(InputXRegisterOrZero(value), rs1, offset); in Store()
949 __ Storeh(InputXRegisterOrZero(value), rs1, offset); in Store()
953 __ FStorew(value.AsFpuRegister<FRegister>(), rs1, offset); in Store()
959 __ Storew(InputXRegisterOrZero(value), rs1, offset); in Store()
963 __ FStored(value.AsFpuRegister<FRegister>(), rs1, offset); in Store()
968 __ Stored(InputXRegisterOrZero(value), rs1, offset); in Store()
979 XRegister rs1, in StoreSeqCst() argument
997 XRegister addr = rs1; in StoreSeqCst()
1000 __ AddConst64(addr, rs1, offset); in StoreSeqCst()
1013 Store(value, rs1, offset, type); in StoreSeqCst()
1022 XRegister rd, XRegister rs1, XRegister rs2, DataType::Type type) { in ShNAdd() argument
1028 __ Add(rd, rs1, rs2); in ShNAdd()
1033 __ Sh1Add(rd, rs1, rs2); in ShNAdd()
1039 __ Sh2Add(rd, rs1, rs2); in ShNAdd()
1044 __ Sh3Add(rd, rs1, rs2); in ShNAdd()
1584 XRegister rs1 = locations->InAt(0).AsRegister<XRegister>(); in GenerateIntLongCondition() local
1594 __ Sub(rd, rs1, rs2); // SUB is OK here even for 32-bit comparison. in GenerateIntLongCondition()
1597 __ Addi(rd, rs1, -imm); // ADDI is OK here even for 32-bit comparison. in GenerateIntLongCondition()
1600 __ Seqz(rd, (use_imm && imm == 0) ? rs1 : rd); in GenerateIntLongCondition()
1602 __ Snez(rd, (use_imm && imm == 0) ? rs1 : rd); in GenerateIntLongCondition()
1610 __ Slti(rd, rs1, imm); in GenerateIntLongCondition()
1612 __ Slt(rd, rs1, rs2); in GenerateIntLongCondition()
1623 __ Slti(rd, rs1, imm + 1); in GenerateIntLongCondition()
1625 __ Slt(rd, rs2, rs1); in GenerateIntLongCondition()
1639 __ Sltiu(rd, rs1, imm); in GenerateIntLongCondition()
1641 __ Sltu(rd, rs1, rs2); in GenerateIntLongCondition()
1655 __ Sltiu(rd, rs1, imm + 1); in GenerateIntLongCondition()
1657 __ Sltu(rd, rs2, rs1); in GenerateIntLongCondition()
1800 FRegister rs1 = locations->InAt(0).AsFpuRegister<FRegister>(); in GenerateFpCondition() local
1806 FEq(rd, rs1, rs2, type); in GenerateFpCondition()
1809 FEq(rd, rs1, rs2, type); in GenerateFpCondition()
1814 FLt(rd, rs1, rs2, type); in GenerateFpCondition()
1816 FLe(rd, rs2, rs1, type); in GenerateFpCondition()
1822 FLe(rd, rs1, rs2, type); in GenerateFpCondition()
1824 FLt(rd, rs2, rs1, type); in GenerateFpCondition()
1830 FLe(rd, rs1, rs2, type); in GenerateFpCondition()
1833 FLt(rd, rs2, rs1, type); in GenerateFpCondition()
1838 FLt(rd, rs1, rs2, type); in GenerateFpCondition()
1841 FLe(rd, rs2, rs1, type); in GenerateFpCondition()
2157 XRegister rs1 = locations->InAt(0).AsRegister<XRegister>(); in HandleBinaryOp() local
2166 __ Andi(rd, rs1, imm); in HandleBinaryOp()
2168 __ And(rd, rs1, rs2); in HandleBinaryOp()
2172 __ Ori(rd, rs1, imm); in HandleBinaryOp()
2174 __ Or(rd, rs1, rs2); in HandleBinaryOp()
2178 __ Xori(rd, rs1, imm); in HandleBinaryOp()
2180 __ Xor(rd, rs1, rs2); in HandleBinaryOp()
2185 __ Addiw(rd, rs1, instruction->IsSub() ? -imm : imm); in HandleBinaryOp()
2187 __ Addw(rd, rs1, rs2); in HandleBinaryOp()
2190 __ Subw(rd, rs1, rs2); in HandleBinaryOp()
2194 __ Addi(rd, rs1, instruction->IsSub() ? -imm : imm); in HandleBinaryOp()
2196 __ Add(rd, rs1, rs2); in HandleBinaryOp()
2199 __ Sub(rd, rs1, rs2); in HandleBinaryOp()
2204 __ Min(rd, rs1, use_imm ? Zero : rs2); in HandleBinaryOp()
2208 __ Max(rd, rs1, use_imm ? Zero : rs2); in HandleBinaryOp()
2215 FRegister rs1 = locations->InAt(0).AsFpuRegister<FRegister>(); in HandleBinaryOp() local
2218 FAdd(rd, rs1, rs2, type); in HandleBinaryOp()
2220 FSub(rd, rs1, rs2, type); in HandleBinaryOp()
2225 DCHECK_NE(rd, rs1); // Requested `Location::kOutputOverlap`. in HandleBinaryOp()
2232 FClass(tmp, rs1, type); in HandleBinaryOp()
2234 FMv(rd, rs1, type); in HandleBinaryOp()
2242 FMin(rd, rs1, rs2, type); in HandleBinaryOp()
2244 FMax(rd, rs1, rs2, type); in HandleBinaryOp()
2364 XRegister rs1 = locations->InAt(0).AsRegister<XRegister>(); in HandleShift() local
2373 if (rd != rs1) { in HandleShift()
2374 __ Mv(rd, rs1); in HandleShift()
2378 __ Slliw(rd, rs1, shamt); in HandleShift()
2380 __ Sraiw(rd, rs1, shamt); in HandleShift()
2382 __ Srliw(rd, rs1, shamt); in HandleShift()
2385 __ Roriw(rd, rs1, shamt); in HandleShift()
2389 __ Slli(rd, rs1, shamt); in HandleShift()
2391 __ Srai(rd, rs1, shamt); in HandleShift()
2393 __ Srli(rd, rs1, shamt); in HandleShift()
2396 __ Rori(rd, rs1, shamt); in HandleShift()
2403 __ Sllw(rd, rs1, rs2); in HandleShift()
2405 __ Sraw(rd, rs1, rs2); in HandleShift()
2407 __ Srlw(rd, rs1, rs2); in HandleShift()
2410 __ Rorw(rd, rs1, rs2); in HandleShift()
2414 __ Sll(rd, rs1, rs2); in HandleShift()
2416 __ Sra(rd, rs1, rs2); in HandleShift()
2418 __ Srl(rd, rs1, rs2); in HandleShift()
2421 __ Ror(rd, rs1, rs2); in HandleShift()
6646 XRegister rs1) { in EmitPcRelativeAddiPlaceholder() argument
6649 __ Addi(rd, rs1, /*imm12=*/ kLinkTimeOffsetPlaceholderLow); in EmitPcRelativeAddiPlaceholder()
6654 XRegister rs1) { in EmitPcRelativeLwuPlaceholder() argument
6657 __ Lwu(rd, rs1, /*offset=*/ kLinkTimeOffsetPlaceholderLow); in EmitPcRelativeLwuPlaceholder()
6662 XRegister rs1) { in EmitPcRelativeLdPlaceholder() argument
6665 __ Ld(rd, rs1, /*offset=*/ kLinkTimeOffsetPlaceholderLow); in EmitPcRelativeLdPlaceholder()