Lines Matching refs:vixl32

35 namespace vixl32 = vixl::aarch32;  variable
40 inline dwarf::Reg DWARFReg(vixl32::Register reg) { in DWARFReg()
44 inline dwarf::Reg DWARFReg(vixl32::SRegister reg) { in DWARFReg()
68 class ArmVIXLMacroAssembler final : public vixl32::MacroAssembler {
75 : vixl32::MacroAssembler(ArmVIXLMacroAssembler::kDefaultCodeBufferCapacity) {} in ArmVIXLMacroAssembler()
86 void CompareAndBranchIfZero(vixl32::Register rn,
87 vixl32::Label* label,
89 void CompareAndBranchIfNonZero(vixl32::Register rn,
90 vixl32::Label* label,
103 void (func_name)(vixl32::Register rd, vixl32::Register rn, const vixl32::Operand& operand) { \
104 MacroAssembler::func_name(vixl32::DontCare, rd, rn, operand); \
128 void (func_name)(vixl32::Register rd, const vixl32::Operand& operand) { \
129 MacroAssembler::func_name(vixl32::DontCare, rd, operand); \
139 void Rrx(vixl32::Register rd, vixl32::Register rn) { in Rrx()
140 MacroAssembler::Rrx(vixl32::DontCare, rd, rn); in Rrx()
144 void Mul(vixl32::Register rd, vixl32::Register rn, vixl32::Register rm) { in Mul()
145 MacroAssembler::Mul(vixl32::DontCare, rd, rn, rm); in Mul()
151 void Add(vixl32::Register rd, vixl32::Register rn, const vixl32::Operand& operand) { in Add()
155 MacroAssembler::Add(vixl32::DontCare, rd, rn, operand); in Add()
161 void B(vixl32::Label* label);
165 void B(vixl32::Condition cond, vixl32::Label* label, bool is_far_target = true);
168 void Vmov(vixl32::DRegister rd, double imm) { in Vmov()
178 void Mrrc(vixl32::Register r1, vixl32::Register r2, int coproc, int opc1, int crm) { in Mrrc()
242 void PoisonHeapReference(vixl32::Register reg);
244 void UnpoisonHeapReference(vixl32::Register reg);
246 void MaybePoisonHeapReference(vixl32::Register reg);
248 void MaybeUnpoisonHeapReference(vixl32::Register reg);
257 void GenerateMarkingRegisterCheck(vixl32::Register temp, int code = 0);
260 vixl32::Register reg,
261 vixl32::Register base,
263 void StoreSToOffset(vixl32::SRegister source, vixl32::Register base, int32_t offset);
264 void StoreDToOffset(vixl32::DRegister source, vixl32::Register base, int32_t offset);
266 void LoadImmediate(vixl32::Register dest, int32_t value);
268 vixl32::Register reg,
269 vixl32::Register base,
271 void LoadSFromOffset(vixl32::SRegister reg, vixl32::Register base, int32_t offset);
272 void LoadDFromOffset(vixl32::DRegister reg, vixl32::Register base, int32_t offset);
286 vixl32::Register temp,
287 vixl32::Register base,
292 void AddConstant(vixl32::Register rd, int32_t value);
293 void AddConstant(vixl32::Register rd, vixl32::Register rn, int32_t value);
294 void AddConstantInIt(vixl32::Register rd,
295 vixl32::Register rn,
297 vixl32::Condition cond = vixl32::al);
303 vixl32::RawLiteral::kPlacedWhenUsed, in CreateLiteralDestroyedWithPool()
304 vixl32::RawLiteral::kDeletedOnPoolDestruction); in CreateLiteralDestroyedWithPool()
314 extern const vixl32::Register tr;
316 extern const vixl32::Register mr;