1281 void Riscv64Assembler::CLw(XRegister rd_s, XRegister rs1_s, int32_t offset) {  in CLw()  argument
1283   EmitCM(0b010u, ExtractOffset52_6(offset), rs1_s, rd_s, 0b00u);  in CLw()
1286 void Riscv64Assembler::CLd(XRegister rd_s, XRegister rs1_s, int32_t offset) {  in CLd()  argument
1288   EmitCM(0b011u, ExtractOffset53_76(offset), rs1_s, rd_s, 0b00u);  in CLd()
1291 void Riscv64Assembler::CFLd(FRegister rd_s, XRegister rs1_s, int32_t offset) {  in CFLd()  argument
1294   EmitCM(0b001u, ExtractOffset53_76(offset), rs1_s, rd_s, 0b00u);  in CFLd()
1360 void Riscv64Assembler::CAddi4Spn(XRegister rd_s, uint32_t nzuimm) {  in CAddi4Spn()  argument
1372   EmitCIW(0b000u, uimm, rd_s, 0b00u);  in CAddi4Spn()
1382 void Riscv64Assembler::CSrli(XRegister rd_s, int32_t shamt) {  in CSrli()  argument
1386   EmitCBArithmetic(0b100u, 0b00u, shamt, rd_s, 0b01u);  in CSrli()
1389 void Riscv64Assembler::CSrai(XRegister rd_s, int32_t shamt) {  in CSrai()  argument
1393   EmitCBArithmetic(0b100u, 0b01u, shamt, rd_s, 0b01u);  in CSrai()
1396 void Riscv64Assembler::CAndi(XRegister rd_s, int32_t imm) {  in CAndi()  argument
1399   EmitCBArithmetic(0b100u, 0b10u, imm, rd_s, 0b01u);  in CAndi()
1416 void Riscv64Assembler::CAnd(XRegister rd_s, XRegister rs2_s) {  in CAnd()  argument
1418   EmitCAReg(0b100011u, rd_s, 0b11u, rs2_s, 0b01u);  in CAnd()
1421 void Riscv64Assembler::COr(XRegister rd_s, XRegister rs2_s) {  in COr()  argument
1423   EmitCAReg(0b100011u, rd_s, 0b10u, rs2_s, 0b01u);  in COr()
1426 void Riscv64Assembler::CXor(XRegister rd_s, XRegister rs2_s) {  in CXor()  argument
1428   EmitCAReg(0b100011u, rd_s, 0b01u, rs2_s, 0b01u);  in CXor()
1431 void Riscv64Assembler::CSub(XRegister rd_s, XRegister rs2_s) {  in CSub()  argument
1433   EmitCAReg(0b100011u, rd_s, 0b00u, rs2_s, 0b01u);  in CSub()
1436 void Riscv64Assembler::CAddw(XRegister rd_s, XRegister rs2_s) {  in CAddw()  argument
1438   EmitCAReg(0b100111u, rd_s, 0b01u, rs2_s, 0b01u);  in CAddw()
1441 void Riscv64Assembler::CSubw(XRegister rd_s, XRegister rs2_s) {  in CSubw()  argument
1443   EmitCAReg(0b100111u, rd_s, 0b00u, rs2_s, 0b01u);  in CSubw()
1448 void Riscv64Assembler::CLbu(XRegister rd_s, XRegister rs1_s, int32_t offset) {  in CLbu()  argument
1450   EmitCAReg(0b100000u, rs1_s, EncodeOffset0_1(offset), rd_s, 0b00u);  in CLbu()
1453 void Riscv64Assembler::CLhu(XRegister rd_s, XRegister rs1_s, int32_t offset) {  in CLhu()  argument
1457   EmitCAReg(0b100001u, rs1_s, BitFieldExtract<uint32_t>(offset, 1, 1), rd_s, 0b00u);  in CLhu()
1460 void Riscv64Assembler::CLh(XRegister rd_s, XRegister rs1_s, int32_t offset) {  in CLh()  argument
1464   EmitCAReg(0b100001u, rs1_s, 0b10 | BitFieldExtract<uint32_t>(offset, 1, 1), rd_s, 0b00u);  in CLh()
1509 void Riscv64Assembler::CMul(XRegister rd_s, XRegister rs2_s) {  in CMul()  argument
1511   EmitCAReg(0b100111u, rd_s, 0b10u, rs2_s, 0b01u);  in CMul()