Lines Matching refs:rs
6119 void Riscv64Assembler::Mv(XRegister rd, XRegister rs) { Addi(rd, rs, 0); } in Mv() argument
6121 void Riscv64Assembler::Not(XRegister rd, XRegister rs) { Xori(rd, rs, -1); } in Not() argument
6123 void Riscv64Assembler::Neg(XRegister rd, XRegister rs) { Sub(rd, Zero, rs); } in Neg() argument
6125 void Riscv64Assembler::NegW(XRegister rd, XRegister rs) { Subw(rd, Zero, rs); } in NegW() argument
6127 void Riscv64Assembler::SextB(XRegister rd, XRegister rs) { in SextB() argument
6129 if (IsExtensionEnabled(Riscv64Extension::kZcb) && rd == rs && IsShortReg(rd)) { in SextB()
6132 ZbbSextB(rd, rs); in SextB()
6135 Slli(rd, rs, kXlen - 8u); in SextB()
6140 void Riscv64Assembler::SextH(XRegister rd, XRegister rs) { in SextH() argument
6142 if (IsExtensionEnabled(Riscv64Extension::kZcb) && rd == rs && IsShortReg(rd)) { in SextH()
6145 ZbbSextH(rd, rs); in SextH()
6148 Slli(rd, rs, kXlen - 16u); in SextH()
6153 void Riscv64Assembler::SextW(XRegister rd, XRegister rs) { in SextW() argument
6154 if (IsExtensionEnabled(Riscv64Extension::kZca) && rd != Zero && (rd == rs || rs == Zero)) { in SextW()
6155 if (rd == rs) { in SextW()
6161 Addiw(rd, rs, 0); in SextW()
6165 void Riscv64Assembler::ZextB(XRegister rd, XRegister rs) { in ZextB() argument
6166 if (IsExtensionEnabled(Riscv64Extension::kZcb) && rd == rs && IsShortReg(rd)) { in ZextB()
6169 Andi(rd, rs, 0xff); in ZextB()
6173 void Riscv64Assembler::ZextH(XRegister rd, XRegister rs) { in ZextH() argument
6175 if (IsExtensionEnabled(Riscv64Extension::kZcb) && rd == rs && IsShortReg(rd)) { in ZextH()
6178 ZbbZextH(rd, rs); in ZextH()
6181 Slli(rd, rs, kXlen - 16u); in ZextH()
6186 void Riscv64Assembler::ZextW(XRegister rd, XRegister rs) { in ZextW() argument
6188 if (IsExtensionEnabled(Riscv64Extension::kZcb) && rd == rs && IsShortReg(rd)) { in ZextW()
6191 AddUw(rd, rs, Zero); in ZextW()
6194 Slli(rd, rs, kXlen - 32u); in ZextW()
6199 void Riscv64Assembler::Seqz(XRegister rd, XRegister rs) { Sltiu(rd, rs, 1); } in Seqz() argument
6201 void Riscv64Assembler::Snez(XRegister rd, XRegister rs) { Sltu(rd, Zero, rs); } in Snez() argument
6203 void Riscv64Assembler::Sltz(XRegister rd, XRegister rs) { Slt(rd, rs, Zero); } in Sltz() argument
6205 void Riscv64Assembler::Sgtz(XRegister rd, XRegister rs) { Slt(rd, Zero, rs); } in Sgtz() argument
6207 void Riscv64Assembler::FMvS(FRegister rd, FRegister rs) { FSgnjS(rd, rs, rs); } in FMvS() argument
6209 void Riscv64Assembler::FAbsS(FRegister rd, FRegister rs) { FSgnjxS(rd, rs, rs); } in FAbsS() argument
6211 void Riscv64Assembler::FNegS(FRegister rd, FRegister rs) { FSgnjnS(rd, rs, rs); } in FNegS() argument
6213 void Riscv64Assembler::FMvD(FRegister rd, FRegister rs) { FSgnjD(rd, rs, rs); } in FMvD() argument
6215 void Riscv64Assembler::FAbsD(FRegister rd, FRegister rs) { FSgnjxD(rd, rs, rs); } in FAbsD() argument
6217 void Riscv64Assembler::FNegD(FRegister rd, FRegister rs) { FSgnjnD(rd, rs, rs); } in FNegD() argument
6219 void Riscv64Assembler::Beqz(XRegister rs, int32_t offset) { in Beqz() argument
6220 Beq(rs, Zero, offset); in Beqz()
6223 void Riscv64Assembler::Bnez(XRegister rs, int32_t offset) { in Bnez() argument
6224 Bne(rs, Zero, offset); in Bnez()
6243 void Riscv64Assembler::Bgt(XRegister rs, XRegister rt, int32_t offset) { in Bgt() argument
6244 Blt(rt, rs, offset); in Bgt()
6247 void Riscv64Assembler::Ble(XRegister rs, XRegister rt, int32_t offset) { in Ble() argument
6248 Bge(rt, rs, offset); in Ble()
6251 void Riscv64Assembler::Bgtu(XRegister rs, XRegister rt, int32_t offset) { in Bgtu() argument
6252 Bltu(rt, rs, offset); in Bgtu()
6255 void Riscv64Assembler::Bleu(XRegister rs, XRegister rt, int32_t offset) { in Bleu() argument
6256 Bgeu(rt, rs, offset); in Bleu()
6263 void Riscv64Assembler::Jr(XRegister rs) { Jalr(Zero, rs, 0); } in Jr() argument
6265 void Riscv64Assembler::Jalr(XRegister rs) { Jalr(RA, rs, 0); } in Jalr() argument
6267 void Riscv64Assembler::Jalr(XRegister rd, XRegister rs) { Jalr(rd, rs, 0); } in Jalr() argument
6287 void Riscv64Assembler::Csrw(uint32_t csr, XRegister rs) { in Csrw() argument
6288 Csrrw(Zero, csr, rs); in Csrw()
6291 void Riscv64Assembler::Csrs(uint32_t csr, XRegister rs) { in Csrs() argument
6292 Csrrs(Zero, csr, rs); in Csrs()
6295 void Riscv64Assembler::Csrc(uint32_t csr, XRegister rs) { in Csrc() argument
6296 Csrrc(Zero, csr, rs); in Csrc()
6444 void Riscv64Assembler::Beqz(XRegister rs, Riscv64Label* label, bool is_bare) { in Beqz() argument
6445 Beq(rs, Zero, label, is_bare); in Beqz()
6448 void Riscv64Assembler::Bnez(XRegister rs, Riscv64Label* label, bool is_bare) { in Bnez() argument
6449 Bne(rs, Zero, label, is_bare); in Bnez()
6452 void Riscv64Assembler::Blez(XRegister rs, Riscv64Label* label, bool is_bare) { in Blez() argument
6453 Ble(rs, Zero, label, is_bare); in Blez()
6456 void Riscv64Assembler::Bgez(XRegister rs, Riscv64Label* label, bool is_bare) { in Bgez() argument
6457 Bge(rs, Zero, label, is_bare); in Bgez()
6460 void Riscv64Assembler::Bltz(XRegister rs, Riscv64Label* label, bool is_bare) { in Bltz() argument
6461 Blt(rs, Zero, label, is_bare); in Bltz()
6464 void Riscv64Assembler::Bgtz(XRegister rs, Riscv64Label* label, bool is_bare) { in Bgtz() argument
6465 Bgt(rs, Zero, label, is_bare); in Bgtz()
6468 void Riscv64Assembler::Beq(XRegister rs, XRegister rt, Riscv64Label* label, bool is_bare) { in Beq() argument
6469 Bcond(label, is_bare, kCondEQ, rs, rt); in Beq()
6472 void Riscv64Assembler::Bne(XRegister rs, XRegister rt, Riscv64Label* label, bool is_bare) { in Bne() argument
6473 Bcond(label, is_bare, kCondNE, rs, rt); in Bne()
6476 void Riscv64Assembler::Ble(XRegister rs, XRegister rt, Riscv64Label* label, bool is_bare) { in Ble() argument
6477 Bcond(label, is_bare, kCondLE, rs, rt); in Ble()
6480 void Riscv64Assembler::Bge(XRegister rs, XRegister rt, Riscv64Label* label, bool is_bare) { in Bge() argument
6481 Bcond(label, is_bare, kCondGE, rs, rt); in Bge()
6484 void Riscv64Assembler::Blt(XRegister rs, XRegister rt, Riscv64Label* label, bool is_bare) { in Blt() argument
6485 Bcond(label, is_bare, kCondLT, rs, rt); in Blt()
6488 void Riscv64Assembler::Bgt(XRegister rs, XRegister rt, Riscv64Label* label, bool is_bare) { in Bgt() argument
6489 Bcond(label, is_bare, kCondGT, rs, rt); in Bgt()
6492 void Riscv64Assembler::Bleu(XRegister rs, XRegister rt, Riscv64Label* label, bool is_bare) { in Bleu() argument
6493 Bcond(label, is_bare, kCondLEU, rs, rt); in Bleu()
6496 void Riscv64Assembler::Bgeu(XRegister rs, XRegister rt, Riscv64Label* label, bool is_bare) { in Bgeu() argument
6497 Bcond(label, is_bare, kCondGEU, rs, rt); in Bgeu()
6500 void Riscv64Assembler::Bltu(XRegister rs, XRegister rt, Riscv64Label* label, bool is_bare) { in Bltu() argument
6501 Bcond(label, is_bare, kCondLTU, rs, rt); in Bltu()
6504 void Riscv64Assembler::Bgtu(XRegister rs, XRegister rt, Riscv64Label* label, bool is_bare) { in Bgtu() argument
6505 Bcond(label, is_bare, kCondGTU, rs, rt); in Bgtu()
7046 XRegister rs, in EmitBcond() argument
7052 B##cond(rs, rt, offset); \ in EmitBcond()
7640 auto addi = [&](XRegister rd, XRegister rs, int32_t imm) { Addi(rd, rs, imm); }; in LoadImmediate() argument
7641 auto addiw = [&](XRegister rd, XRegister rs, int32_t imm) { Addiw(rd, rs, imm); }; in LoadImmediate() argument
7642 auto slli = [&](XRegister rd, XRegister rs, int32_t imm) { Slli(rd, rs, imm); }; in LoadImmediate() argument