100 void Riscv64Assembler::Jalr(XRegister rd, XRegister rs1, int32_t offset) {  in Jalr()  argument
102     if (rd == RA && rs1 != Zero && offset == 0) {  in Jalr()
103       CJalr(rs1);  in Jalr()
105     } else if (rd == Zero && rs1 != Zero && offset == 0) {  in Jalr()
106       CJr(rs1);  in Jalr()
111   EmitI(offset, rs1, 0x0, rd, 0x67);  in Jalr()
116 void Riscv64Assembler::Beq(XRegister rs1, XRegister rs2, int32_t offset) {  in Beq()  argument
118     if (rs2 == Zero && IsShortReg(rs1) && IsInt<9>(offset)) {  in Beq()
119       CBeqz(rs1, offset);  in Beq()
121     } else if (rs1 == Zero && IsShortReg(rs2) && IsInt<9>(offset)) {  in Beq()
127   EmitB(offset, rs2, rs1, 0x0, 0x63);  in Beq()
130 void Riscv64Assembler::Bne(XRegister rs1, XRegister rs2, int32_t offset) {  in Bne()  argument
132     if (rs2 == Zero && IsShortReg(rs1) && IsInt<9>(offset)) {  in Bne()
133       CBnez(rs1, offset);  in Bne()
135     } else if (rs1 == Zero && IsShortReg(rs2) && IsInt<9>(offset)) {  in Bne()
141   EmitB(offset, rs2, rs1, 0x1, 0x63);  in Bne()
144 void Riscv64Assembler::Blt(XRegister rs1, XRegister rs2, int32_t offset) {  in Blt()  argument
145   EmitB(offset, rs2, rs1, 0x4, 0x63);  in Blt()
148 void Riscv64Assembler::Bge(XRegister rs1, XRegister rs2, int32_t offset) {  in Bge()  argument
149   EmitB(offset, rs2, rs1, 0x5, 0x63);  in Bge()
152 void Riscv64Assembler::Bltu(XRegister rs1, XRegister rs2, int32_t offset) {  in Bltu()  argument
153   EmitB(offset, rs2, rs1, 0x6, 0x63);  in Bltu()
156 void Riscv64Assembler::Bgeu(XRegister rs1, XRegister rs2, int32_t offset) {  in Bgeu()  argument
157   EmitB(offset, rs2, rs1, 0x7, 0x63);  in Bgeu()
162 void Riscv64Assembler::Lb(XRegister rd, XRegister rs1, int32_t offset) {  in Lb()  argument
164   EmitI(offset, rs1, 0x0, rd, 0x03);  in Lb()
167 void Riscv64Assembler::Lh(XRegister rd, XRegister rs1, int32_t offset) {  in Lh()  argument
171     if (IsShortReg(rd) && IsShortReg(rs1) && IsUint<2>(offset) && IsAligned<2>(offset)) {  in Lh()
172       CLh(rd, rs1, offset);  in Lh()
177   EmitI(offset, rs1, 0x1, rd, 0x03);  in Lh()
180 void Riscv64Assembler::Lw(XRegister rd, XRegister rs1, int32_t offset) {  in Lw()  argument
184     if (rd != Zero && rs1 == SP && IsUint<8>(offset) && IsAligned<4>(offset)) {  in Lw()
187     } else if (IsShortReg(rd) && IsShortReg(rs1) && IsUint<7>(offset) && IsAligned<4>(offset)) {  in Lw()
188       CLw(rd, rs1, offset);  in Lw()
193   EmitI(offset, rs1, 0x2, rd, 0x03);  in Lw()
196 void Riscv64Assembler::Ld(XRegister rd, XRegister rs1, int32_t offset) {  in Ld()  argument
200     if (rd != Zero && rs1 == SP && IsUint<9>(offset) && IsAligned<8>(offset)) {  in Ld()
203     } else if (IsShortReg(rd) && IsShortReg(rs1) && IsUint<8>(offset) && IsAligned<8>(offset)) {  in Ld()
204       CLd(rd, rs1, offset);  in Ld()
209   EmitI(offset, rs1, 0x3, rd, 0x03);  in Ld()
212 void Riscv64Assembler::Lbu(XRegister rd, XRegister rs1, int32_t offset) {  in Lbu()  argument
216     if (IsShortReg(rd) && IsShortReg(rs1) && IsUint<2>(offset)) {  in Lbu()
217       CLbu(rd, rs1, offset);  in Lbu()
222   EmitI(offset, rs1, 0x4, rd, 0x03);  in Lbu()
225 void Riscv64Assembler::Lhu(XRegister rd, XRegister rs1, int32_t offset) {  in Lhu()  argument
229     if (IsShortReg(rd) && IsShortReg(rs1) && IsUint<2>(offset) && IsAligned<2>(offset)) {  in Lhu()
230       CLhu(rd, rs1, offset);  in Lhu()
235   EmitI(offset, rs1, 0x5, rd, 0x03);  in Lhu()
238 void Riscv64Assembler::Lwu(XRegister rd, XRegister rs1, int32_t offset) {  in Lwu()  argument
240   EmitI(offset, rs1, 0x6, rd, 0x3);  in Lwu()
245 void Riscv64Assembler::Sb(XRegister rs2, XRegister rs1, int32_t offset) {  in Sb()  argument
249     if (IsShortReg(rs2) && IsShortReg(rs1) && IsUint<2>(offset)) {  in Sb()
250       CSb(rs2, rs1, offset);  in Sb()
255   EmitS(offset, rs2, rs1, 0x0, 0x23);  in Sb()
258 void Riscv64Assembler::Sh(XRegister rs2, XRegister rs1, int32_t offset) {  in Sh()  argument
262     if (IsShortReg(rs2) && IsShortReg(rs1) && IsUint<2>(offset) && IsAligned<2>(offset)) {  in Sh()
263       CSh(rs2, rs1, offset);  in Sh()
268   EmitS(offset, rs2, rs1, 0x1, 0x23);  in Sh()
271 void Riscv64Assembler::Sw(XRegister rs2, XRegister rs1, int32_t offset) {  in Sw()  argument
275     if (rs1 == SP && IsUint<8>(offset) && IsAligned<4>(offset)) {  in Sw()
278     } else if (IsShortReg(rs2) && IsShortReg(rs1) && IsUint<7>(offset) && IsAligned<4>(offset)) {  in Sw()
279       CSw(rs2, rs1, offset);  in Sw()
284   EmitS(offset, rs2, rs1, 0x2, 0x23);  in Sw()
287 void Riscv64Assembler::Sd(XRegister rs2, XRegister rs1, int32_t offset) {  in Sd()  argument
291     if (rs1 == SP && IsUint<9>(offset) && IsAligned<8>(offset)) {  in Sd()
294     } else if (IsShortReg(rs2) && IsShortReg(rs1) && IsUint<8>(offset) && IsAligned<8>(offset)) {  in Sd()
295       CSd(rs2, rs1, offset);  in Sd()
300   EmitS(offset, rs2, rs1, 0x3, 0x23);  in Sd()
305 void Riscv64Assembler::Addi(XRegister rd, XRegister rs1, int32_t imm12) {  in Addi()  argument
308       if (rs1 == Zero && IsInt<6>(imm12)) {  in Addi()
312         if (rd == rs1) {  in Addi()
322         } else if (IsShortReg(rd) && rs1 == SP && IsUint<10>(imm12) && IsAligned<4>(imm12)) {  in Addi()
326       } else if (rs1 != Zero) {  in Addi()
327         CMv(rd, rs1);  in Addi()
330     } else if (rd == rs1 && imm12 == 0) {  in Addi()
336   EmitI(imm12, rs1, 0x0, rd, 0x13);  in Addi()
339 void Riscv64Assembler::Slti(XRegister rd, XRegister rs1, int32_t imm12) {  in Slti()  argument
340   EmitI(imm12, rs1, 0x2, rd, 0x13);  in Slti()
343 void Riscv64Assembler::Sltiu(XRegister rd, XRegister rs1, int32_t imm12) {  in Sltiu()  argument
344   EmitI(imm12, rs1, 0x3, rd, 0x13);  in Sltiu()
347 void Riscv64Assembler::Xori(XRegister rd, XRegister rs1, int32_t imm12) {  in Xori()  argument
349     if (rd == rs1 && IsShortReg(rd) && imm12 == -1) {  in Xori()
355   EmitI(imm12, rs1, 0x4, rd, 0x13);  in Xori()
358 void Riscv64Assembler::Ori(XRegister rd, XRegister rs1, int32_t imm12) {  in Ori()  argument
359   EmitI(imm12, rs1, 0x6, rd, 0x13);  in Ori()
362 void Riscv64Assembler::Andi(XRegister rd, XRegister rs1, int32_t imm12) {  in Andi()  argument
364     if (rd == rs1 && IsShortReg(rd) && IsInt<6>(imm12)) {  in Andi()
370   EmitI(imm12, rs1, 0x7, rd, 0x13);  in Andi()
374 void Riscv64Assembler::Slli(XRegister rd, XRegister rs1, int32_t shamt) {  in Slli()  argument
378     if (rd == rs1 && rd != Zero && shamt != 0) {  in Slli()
384   EmitI6(0x0, shamt, rs1, 0x1, rd, 0x13);  in Slli()
388 void Riscv64Assembler::Srli(XRegister rd, XRegister rs1, int32_t shamt) {  in Srli()  argument
392     if (rd == rs1 && IsShortReg(rd) && shamt != 0) {  in Srli()
398   EmitI6(0x0, shamt, rs1, 0x5, rd, 0x13);  in Srli()
402 void Riscv64Assembler::Srai(XRegister rd, XRegister rs1, int32_t shamt) {  in Srai()  argument
406     if (rd == rs1 && IsShortReg(rd) && shamt != 0) {  in Srai()
412   EmitI6(0x10, shamt, rs1, 0x5, rd, 0x13);  in Srai()
417 void Riscv64Assembler::Add(XRegister rd, XRegister rs1, XRegister rs2) {  in Add()  argument
420       if (rs1 != Zero || rs2 != Zero) {  in Add()
421         if (rs1 == Zero) {  in Add()
426           DCHECK_NE(rs1, Zero);  in Add()
427           CMv(rd, rs1);  in Add()
429         } else if (rd == rs1) {  in Add()
434           DCHECK_NE(rs1, Zero);  in Add()
435           CAdd(rd, rs1);  in Add()
449   EmitR(0x0, rs2, rs1, 0x0, rd, 0x33);  in Add()
452 void Riscv64Assembler::Sub(XRegister rd, XRegister rs1, XRegister rs2) {  in Sub()  argument
454     if (rd == rs1 && IsShortReg(rd) && IsShortReg(rs2)) {  in Sub()
460   EmitR(0x20, rs2, rs1, 0x0, rd, 0x33);  in Sub()
463 void Riscv64Assembler::Slt(XRegister rd, XRegister rs1, XRegister rs2) {  in Slt()  argument
464   EmitR(0x0, rs2, rs1, 0x02, rd, 0x33);  in Slt()
467 void Riscv64Assembler::Sltu(XRegister rd, XRegister rs1, XRegister rs2) {  in Sltu()  argument
468   EmitR(0x0, rs2, rs1, 0x03, rd, 0x33);  in Sltu()
471 void Riscv64Assembler::Xor(XRegister rd, XRegister rs1, XRegister rs2) {  in Xor()  argument
474       if (rd == rs1 && IsShortReg(rs2)) {  in Xor()
477       } else if (rd == rs2 && IsShortReg(rs1)) {  in Xor()
478         CXor(rd, rs1);  in Xor()
484   EmitR(0x0, rs2, rs1, 0x04, rd, 0x33);  in Xor()
487 void Riscv64Assembler::Or(XRegister rd, XRegister rs1, XRegister rs2) {  in Or()  argument
490       if (rd == rs1 && IsShortReg(rs2)) {  in Or()
493       } else if (rd == rs2 && IsShortReg(rs1)) {  in Or()
494         COr(rd, rs1);  in Or()
500   EmitR(0x0, rs2, rs1, 0x06, rd, 0x33);  in Or()
503 void Riscv64Assembler::And(XRegister rd, XRegister rs1, XRegister rs2) {  in And()  argument
506       if (rd == rs1 && IsShortReg(rs2)) {  in And()
509       } else if (rd == rs2 && IsShortReg(rs1)) {  in And()
510         CAnd(rd, rs1);  in And()
516   EmitR(0x0, rs2, rs1, 0x07, rd, 0x33);  in And()
519 void Riscv64Assembler::Sll(XRegister rd, XRegister rs1, XRegister rs2) {  in Sll()  argument
520   EmitR(0x0, rs2, rs1, 0x01, rd, 0x33);  in Sll()
523 void Riscv64Assembler::Srl(XRegister rd, XRegister rs1, XRegister rs2) {  in Srl()  argument
524   EmitR(0x0, rs2, rs1, 0x05, rd, 0x33);  in Srl()
527 void Riscv64Assembler::Sra(XRegister rd, XRegister rs1, XRegister rs2) {  in Sra()  argument
528   EmitR(0x20, rs2, rs1, 0x05, rd, 0x33);  in Sra()
533 void Riscv64Assembler::Addiw(XRegister rd, XRegister rs1, int32_t imm12) {  in Addiw()  argument
536       if (rd == rs1) {  in Addiw()
539       } else if (rs1 == Zero) {  in Addiw()
546   EmitI(imm12, rs1, 0x0, rd, 0x1b);  in Addiw()
549 void Riscv64Assembler::Slliw(XRegister rd, XRegister rs1, int32_t shamt) {  in Slliw()  argument
551   EmitR(0x0, shamt, rs1, 0x1, rd, 0x1b);  in Slliw()
554 void Riscv64Assembler::Srliw(XRegister rd, XRegister rs1, int32_t shamt) {  in Srliw()  argument
556   EmitR(0x0, shamt, rs1, 0x5, rd, 0x1b);  in Srliw()
559 void Riscv64Assembler::Sraiw(XRegister rd, XRegister rs1, int32_t shamt) {  in Sraiw()  argument
561   EmitR(0x20, shamt, rs1, 0x5, rd, 0x1b);  in Sraiw()
566 void Riscv64Assembler::Addw(XRegister rd, XRegister rs1, XRegister rs2) {  in Addw()  argument
569       if (rd == rs1 && IsShortReg(rs2)) {  in Addw()
572       } else if (rd == rs2 && IsShortReg(rs1)) {  in Addw()
573         CAddw(rd, rs1);  in Addw()
579   EmitR(0x0, rs2, rs1, 0x0, rd, 0x3b);  in Addw()
582 void Riscv64Assembler::Subw(XRegister rd, XRegister rs1, XRegister rs2) {  in Subw()  argument
584     if (rd == rs1 && IsShortReg(rd) && IsShortReg(rs2)) {  in Subw()
590   EmitR(0x20, rs2, rs1, 0x0, rd, 0x3b);  in Subw()
593 void Riscv64Assembler::Sllw(XRegister rd, XRegister rs1, XRegister rs2) {  in Sllw()  argument
594   EmitR(0x0, rs2, rs1, 0x1, rd, 0x3b);  in Sllw()
597 void Riscv64Assembler::Srlw(XRegister rd, XRegister rs1, XRegister rs2) {  in Srlw()  argument
598   EmitR(0x0, rs2, rs1, 0x5, rd, 0x3b);  in Srlw()
601 void Riscv64Assembler::Sraw(XRegister rd, XRegister rs1, XRegister rs2) {  in Sraw()  argument
602   EmitR(0x20, rs2, rs1, 0x5, rd, 0x3b);  in Sraw()
648 void Riscv64Assembler::Mul(XRegister rd, XRegister rs1, XRegister rs2) {  in Mul()  argument
653       if (rd == rs1 && IsShortReg(rs2)) {  in Mul()
656       } else if (rd == rs2 && IsShortReg(rs1)) {  in Mul()
657         CMul(rd, rs1);  in Mul()
663   EmitR(0x1, rs2, rs1, 0x0, rd, 0x33);  in Mul()
666 void Riscv64Assembler::Mulh(XRegister rd, XRegister rs1, XRegister rs2) {  in Mulh()  argument
668   EmitR(0x1, rs2, rs1, 0x1, rd, 0x33);  in Mulh()
671 void Riscv64Assembler::Mulhsu(XRegister rd, XRegister rs1, XRegister rs2) {  in Mulhsu()  argument
673   EmitR(0x1, rs2, rs1, 0x2, rd, 0x33);  in Mulhsu()
676 void Riscv64Assembler::Mulhu(XRegister rd, XRegister rs1, XRegister rs2) {  in Mulhu()  argument
678   EmitR(0x1, rs2, rs1, 0x3, rd, 0x33);  in Mulhu()
681 void Riscv64Assembler::Div(XRegister rd, XRegister rs1, XRegister rs2) {  in Div()  argument
683   EmitR(0x1, rs2, rs1, 0x4, rd, 0x33);  in Div()
686 void Riscv64Assembler::Divu(XRegister rd, XRegister rs1, XRegister rs2) {  in Divu()  argument
688   EmitR(0x1, rs2, rs1, 0x5, rd, 0x33);  in Divu()
691 void Riscv64Assembler::Rem(XRegister rd, XRegister rs1, XRegister rs2) {  in Rem()  argument
693   EmitR(0x1, rs2, rs1, 0x6, rd, 0x33);  in Rem()
696 void Riscv64Assembler::Remu(XRegister rd, XRegister rs1, XRegister rs2) {  in Remu()  argument
698   EmitR(0x1, rs2, rs1, 0x7, rd, 0x33);  in Remu()
703 void Riscv64Assembler::Mulw(XRegister rd, XRegister rs1, XRegister rs2) {  in Mulw()  argument
705   EmitR(0x1, rs2, rs1, 0x0, rd, 0x3b);  in Mulw()
708 void Riscv64Assembler::Divw(XRegister rd, XRegister rs1, XRegister rs2) {  in Divw()  argument
710   EmitR(0x1, rs2, rs1, 0x4, rd, 0x3b);  in Divw()
713 void Riscv64Assembler::Divuw(XRegister rd, XRegister rs1, XRegister rs2) {  in Divuw()  argument
715   EmitR(0x1, rs2, rs1, 0x5, rd, 0x3b);  in Divuw()
718 void Riscv64Assembler::Remw(XRegister rd, XRegister rs1, XRegister rs2) {  in Remw()  argument
720   EmitR(0x1, rs2, rs1, 0x6, rd, 0x3b);  in Remw()
723 void Riscv64Assembler::Remuw(XRegister rd, XRegister rs1, XRegister rs2) {  in Remuw()  argument
725   EmitR(0x1, rs2, rs1, 0x7, rd, 0x3b);  in Remuw()
732 void Riscv64Assembler::LrW(XRegister rd, XRegister rs1, AqRl aqrl) {  in LrW()  argument
735   EmitR4(0x2, enum_cast<uint32_t>(aqrl), 0x0, rs1, 0x2, rd, 0x2f);  in LrW()
738 void Riscv64Assembler::LrD(XRegister rd, XRegister rs1, AqRl aqrl) {  in LrD()  argument
741   EmitR4(0x2, enum_cast<uint32_t>(aqrl), 0x0, rs1, 0x3, rd, 0x2f);  in LrD()
744 void Riscv64Assembler::ScW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {  in ScW()  argument
747   EmitR4(0x3, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x2, rd, 0x2f);  in ScW()
750 void Riscv64Assembler::ScD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {  in ScD()  argument
753   EmitR4(0x3, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x3, rd, 0x2f);  in ScD()
756 void Riscv64Assembler::AmoSwapW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {  in AmoSwapW()  argument
758   EmitR4(0x1, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x2, rd, 0x2f);  in AmoSwapW()
761 void Riscv64Assembler::AmoSwapD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {  in AmoSwapD()  argument
763   EmitR4(0x1, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x3, rd, 0x2f);  in AmoSwapD()
766 void Riscv64Assembler::AmoAddW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {  in AmoAddW()  argument
768   EmitR4(0x0, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x2, rd, 0x2f);  in AmoAddW()
771 void Riscv64Assembler::AmoAddD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {  in AmoAddD()  argument
773   EmitR4(0x0, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x3, rd, 0x2f);  in AmoAddD()
776 void Riscv64Assembler::AmoXorW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {  in AmoXorW()  argument
778   EmitR4(0x4, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x2, rd, 0x2f);  in AmoXorW()
781 void Riscv64Assembler::AmoXorD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {  in AmoXorD()  argument
783   EmitR4(0x4, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x3, rd, 0x2f);  in AmoXorD()
786 void Riscv64Assembler::AmoAndW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {  in AmoAndW()  argument
788   EmitR4(0xc, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x2, rd, 0x2f);  in AmoAndW()
791 void Riscv64Assembler::AmoAndD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {  in AmoAndD()  argument
793   EmitR4(0xc, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x3, rd, 0x2f);  in AmoAndD()
796 void Riscv64Assembler::AmoOrW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {  in AmoOrW()  argument
798   EmitR4(0x8, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x2, rd, 0x2f);  in AmoOrW()
801 void Riscv64Assembler::AmoOrD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {  in AmoOrD()  argument
803   EmitR4(0x8, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x3, rd, 0x2f);  in AmoOrD()
806 void Riscv64Assembler::AmoMinW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {  in AmoMinW()  argument
808   EmitR4(0x10, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x2, rd, 0x2f);  in AmoMinW()
811 void Riscv64Assembler::AmoMinD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {  in AmoMinD()  argument
813   EmitR4(0x10, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x3, rd, 0x2f);  in AmoMinD()
816 void Riscv64Assembler::AmoMaxW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {  in AmoMaxW()  argument
818   EmitR4(0x14, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x2, rd, 0x2f);  in AmoMaxW()
821 void Riscv64Assembler::AmoMaxD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {  in AmoMaxD()  argument
823   EmitR4(0x14, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x3, rd, 0x2f);  in AmoMaxD()
826 void Riscv64Assembler::AmoMinuW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {  in AmoMinuW()  argument
828   EmitR4(0x18, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x2, rd, 0x2f);  in AmoMinuW()
831 void Riscv64Assembler::AmoMinuD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {  in AmoMinuD()  argument
833   EmitR4(0x18, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x3, rd, 0x2f);  in AmoMinuD()
836 void Riscv64Assembler::AmoMaxuW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {  in AmoMaxuW()  argument
838   EmitR4(0x1c, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x2, rd, 0x2f);  in AmoMaxuW()
841 void Riscv64Assembler::AmoMaxuD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {  in AmoMaxuD()  argument
843   EmitR4(0x1c, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x3, rd, 0x2f);  in AmoMaxuD()
852 void Riscv64Assembler::Csrrw(XRegister rd, uint32_t csr, XRegister rs1) {  in Csrrw()  argument
854   EmitI(ToInt12(csr), rs1, 0x1, rd, 0x73);  in Csrrw()
857 void Riscv64Assembler::Csrrs(XRegister rd, uint32_t csr, XRegister rs1) {  in Csrrs()  argument
859   EmitI(ToInt12(csr), rs1, 0x2, rd, 0x73);  in Csrrs()
862 void Riscv64Assembler::Csrrc(XRegister rd, uint32_t csr, XRegister rs1) {  in Csrrc()  argument
864   EmitI(ToInt12(csr), rs1, 0x3, rd, 0x73);  in Csrrc()
888 void Riscv64Assembler::FLw(FRegister rd, XRegister rs1, int32_t offset) {  in FLw()  argument
890   EmitI(offset, rs1, 0x2, rd, 0x07);  in FLw()
893 void Riscv64Assembler::FLd(FRegister rd, XRegister rs1, int32_t offset) {  in FLd()  argument
897     if (rs1 == SP && IsUint<9>(offset) && IsAligned<8>(offset)) {  in FLd()
900     } else if (IsShortReg(rd) && IsShortReg(rs1) && IsUint<8>(offset) && IsAligned<8>(offset)) {  in FLd()
901       CFLd(rd, rs1, offset);  in FLd()
906   EmitI(offset, rs1, 0x3, rd, 0x07);  in FLd()
909 void Riscv64Assembler::FSw(FRegister rs2, XRegister rs1, int32_t offset) {  in FSw()  argument
911   EmitS(offset, rs2, rs1, 0x2, 0x27);  in FSw()
914 void Riscv64Assembler::FSd(FRegister rs2, XRegister rs1, int32_t offset) {  in FSd()  argument
918     if (rs1 == SP && IsUint<9>(offset) && IsAligned<8>(offset)) {  in FSd()
921     } else if (IsShortReg(rs2) && IsShortReg(rs1) && IsUint<8>(offset) && IsAligned<8>(offset)) {  in FSd()
922       CFSd(rs2, rs1, offset);  in FSd()
927   EmitS(offset, rs2, rs1, 0x3, 0x27);  in FSd()
933     FRegister rd, FRegister rs1, FRegister rs2, FRegister rs3, FPRoundingMode frm) {  in FMAddS()  argument
935   EmitR4(rs3, 0x0, rs2, rs1, enum_cast<uint32_t>(frm), rd, 0x43);  in FMAddS()
939     FRegister rd, FRegister rs1, FRegister rs2, FRegister rs3, FPRoundingMode frm) {  in FMAddD()  argument
941   EmitR4(rs3, 0x1, rs2, rs1, enum_cast<uint32_t>(frm), rd, 0x43);  in FMAddD()
945     FRegister rd, FRegister rs1, FRegister rs2, FRegister rs3, FPRoundingMode frm) {  in FMSubS()  argument
947   EmitR4(rs3, 0x0, rs2, rs1, enum_cast<uint32_t>(frm), rd, 0x47);  in FMSubS()
951     FRegister rd, FRegister rs1, FRegister rs2, FRegister rs3, FPRoundingMode frm) {  in FMSubD()  argument
953   EmitR4(rs3, 0x1, rs2, rs1, enum_cast<uint32_t>(frm), rd, 0x47);  in FMSubD()
957     FRegister rd, FRegister rs1, FRegister rs2, FRegister rs3, FPRoundingMode frm) {  in FNMSubS()  argument
959   EmitR4(rs3, 0x0, rs2, rs1, enum_cast<uint32_t>(frm), rd, 0x4b);  in FNMSubS()
963     FRegister rd, FRegister rs1, FRegister rs2, FRegister rs3, FPRoundingMode frm) {  in FNMSubD()  argument
965   EmitR4(rs3, 0x1, rs2, rs1, enum_cast<uint32_t>(frm), rd, 0x4b);  in FNMSubD()
969     FRegister rd, FRegister rs1, FRegister rs2, FRegister rs3, FPRoundingMode frm) {  in FNMAddS()  argument
971   EmitR4(rs3, 0x0, rs2, rs1, enum_cast<uint32_t>(frm), rd, 0x4f);  in FNMAddS()
975     FRegister rd, FRegister rs1, FRegister rs2, FRegister rs3, FPRoundingMode frm) {  in FNMAddD()  argument
977   EmitR4(rs3, 0x1, rs2, rs1, enum_cast<uint32_t>(frm), rd, 0x4f);  in FNMAddD()
982 void Riscv64Assembler::FAddS(FRegister rd, FRegister rs1, FRegister rs2, FPRoundingMode frm) {  in FAddS()  argument
984   EmitR(0x0, rs2, rs1, enum_cast<uint32_t>(frm), rd, 0x53);  in FAddS()
987 void Riscv64Assembler::FAddD(FRegister rd, FRegister rs1, FRegister rs2, FPRoundingMode frm) {  in FAddD()  argument
989   EmitR(0x1, rs2, rs1, enum_cast<uint32_t>(frm), rd, 0x53);  in FAddD()
992 void Riscv64Assembler::FSubS(FRegister rd, FRegister rs1, FRegister rs2, FPRoundingMode frm) {  in FSubS()  argument
994   EmitR(0x4, rs2, rs1, enum_cast<uint32_t>(frm), rd, 0x53);  in FSubS()
997 void Riscv64Assembler::FSubD(FRegister rd, FRegister rs1, FRegister rs2, FPRoundingMode frm) {  in FSubD()  argument
999   EmitR(0x5, rs2, rs1, enum_cast<uint32_t>(frm), rd, 0x53);  in FSubD()
1002 void Riscv64Assembler::FMulS(FRegister rd, FRegister rs1, FRegister rs2, FPRoundingMode frm) {  in FMulS()  argument
1004   EmitR(0x8, rs2, rs1, enum_cast<uint32_t>(frm), rd, 0x53);  in FMulS()
1007 void Riscv64Assembler::FMulD(FRegister rd, FRegister rs1, FRegister rs2, FPRoundingMode frm) {  in FMulD()  argument
1009   EmitR(0x9, rs2, rs1, enum_cast<uint32_t>(frm), rd, 0x53);  in FMulD()
1012 void Riscv64Assembler::FDivS(FRegister rd, FRegister rs1, FRegister rs2, FPRoundingMode frm) {  in FDivS()  argument
1014   EmitR(0xc, rs2, rs1, enum_cast<uint32_t>(frm), rd, 0x53);  in FDivS()
1017 void Riscv64Assembler::FDivD(FRegister rd, FRegister rs1, FRegister rs2, FPRoundingMode frm) {  in FDivD()  argument
1019   EmitR(0xd, rs2, rs1, enum_cast<uint32_t>(frm), rd, 0x53);  in FDivD()
1022 void Riscv64Assembler::FSqrtS(FRegister rd, FRegister rs1, FPRoundingMode frm) {  in FSqrtS()  argument
1024   EmitR(0x2c, 0x0, rs1, enum_cast<uint32_t>(frm), rd, 0x53);  in FSqrtS()
1027 void Riscv64Assembler::FSqrtD(FRegister rd, FRegister rs1, FPRoundingMode frm) {  in FSqrtD()  argument
1029   EmitR(0x2d, 0x0, rs1, enum_cast<uint32_t>(frm), rd, 0x53);  in FSqrtD()
1032 void Riscv64Assembler::FSgnjS(FRegister rd, FRegister rs1, FRegister rs2) {  in FSgnjS()  argument
1034   EmitR(0x10, rs2, rs1, 0x0, rd, 0x53);  in FSgnjS()
1037 void Riscv64Assembler::FSgnjD(FRegister rd, FRegister rs1, FRegister rs2) {  in FSgnjD()  argument
1039   EmitR(0x11, rs2, rs1, 0x0, rd, 0x53);  in FSgnjD()
1042 void Riscv64Assembler::FSgnjnS(FRegister rd, FRegister rs1, FRegister rs2) {  in FSgnjnS()  argument
1044   EmitR(0x10, rs2, rs1, 0x1, rd, 0x53);  in FSgnjnS()
1047 void Riscv64Assembler::FSgnjnD(FRegister rd, FRegister rs1, FRegister rs2) {  in FSgnjnD()  argument
1049   EmitR(0x11, rs2, rs1, 0x1, rd, 0x53);  in FSgnjnD()
1052 void Riscv64Assembler::FSgnjxS(FRegister rd, FRegister rs1, FRegister rs2) {  in FSgnjxS()  argument
1054   EmitR(0x10, rs2, rs1, 0x2, rd, 0x53);  in FSgnjxS()
1057 void Riscv64Assembler::FSgnjxD(FRegister rd, FRegister rs1, FRegister rs2) {  in FSgnjxD()  argument
1059   EmitR(0x11, rs2, rs1, 0x2, rd, 0x53);  in FSgnjxD()
1062 void Riscv64Assembler::FMinS(FRegister rd, FRegister rs1, FRegister rs2) {  in FMinS()  argument
1064   EmitR(0x14, rs2, rs1, 0x0, rd, 0x53);  in FMinS()
1067 void Riscv64Assembler::FMinD(FRegister rd, FRegister rs1, FRegister rs2) {  in FMinD()  argument
1069   EmitR(0x15, rs2, rs1, 0x0, rd, 0x53);  in FMinD()
1072 void Riscv64Assembler::FMaxS(FRegister rd, FRegister rs1, FRegister rs2) {  in FMaxS()  argument
1074   EmitR(0x14, rs2, rs1, 0x1, rd, 0x53);  in FMaxS()
1077 void Riscv64Assembler::FMaxD(FRegister rd, FRegister rs1, FRegister rs2) {  in FMaxD()  argument
1078   EmitR(0x15, rs2, rs1, 0x1, rd, 0x53);  in FMaxD()
1082 void Riscv64Assembler::FCvtSD(FRegister rd, FRegister rs1, FPRoundingMode frm) {  in FCvtSD()  argument
1084   EmitR(0x20, 0x1, rs1, enum_cast<uint32_t>(frm), rd, 0x53);  in FCvtSD()
1087 void Riscv64Assembler::FCvtDS(FRegister rd, FRegister rs1, FPRoundingMode frm) {  in FCvtDS()  argument
1090   EmitR(0x21, 0x0, rs1, enum_cast<uint32_t>(frm), rd, 0x53);  in FCvtDS()
1095 void Riscv64Assembler::FEqS(XRegister rd, FRegister rs1, FRegister rs2) {  in FEqS()  argument
1097   EmitR(0x50, rs2, rs1, 0x2, rd, 0x53);  in FEqS()
1100 void Riscv64Assembler::FEqD(XRegister rd, FRegister rs1, FRegister rs2) {  in FEqD()  argument
1102   EmitR(0x51, rs2, rs1, 0x2, rd, 0x53);  in FEqD()
1105 void Riscv64Assembler::FLtS(XRegister rd, FRegister rs1, FRegister rs2) {  in FLtS()  argument
1107   EmitR(0x50, rs2, rs1, 0x1, rd, 0x53);  in FLtS()
1110 void Riscv64Assembler::FLtD(XRegister rd, FRegister rs1, FRegister rs2) {  in FLtD()  argument
1112   EmitR(0x51, rs2, rs1, 0x1, rd, 0x53);  in FLtD()
1115 void Riscv64Assembler::FLeS(XRegister rd, FRegister rs1, FRegister rs2) {  in FLeS()  argument
1117   EmitR(0x50, rs2, rs1, 0x0, rd, 0x53);  in FLeS()
1120 void Riscv64Assembler::FLeD(XRegister rd, FRegister rs1, FRegister rs2) {  in FLeD()  argument
1122   EmitR(0x51, rs2, rs1, 0x0, rd, 0x53);  in FLeD()
1127 void Riscv64Assembler::FCvtWS(XRegister rd, FRegister rs1, FPRoundingMode frm) {  in FCvtWS()  argument
1129   EmitR(0x60, 0x0, rs1, enum_cast<uint32_t>(frm), rd, 0x53);  in FCvtWS()
1132 void Riscv64Assembler::FCvtWD(XRegister rd, FRegister rs1, FPRoundingMode frm) {  in FCvtWD()  argument
1134   EmitR(0x61, 0x0, rs1, enum_cast<uint32_t>(frm), rd, 0x53);  in FCvtWD()
1137 void Riscv64Assembler::FCvtWuS(XRegister rd, FRegister rs1, FPRoundingMode frm) {  in FCvtWuS()  argument
1139   EmitR(0x60, 0x1, rs1, enum_cast<uint32_t>(frm), rd, 0x53);  in FCvtWuS()
1142 void Riscv64Assembler::FCvtWuD(XRegister rd, FRegister rs1, FPRoundingMode frm) {  in FCvtWuD()  argument
1144   EmitR(0x61, 0x1, rs1, enum_cast<uint32_t>(frm), rd, 0x53);  in FCvtWuD()
1147 void Riscv64Assembler::FCvtLS(XRegister rd, FRegister rs1, FPRoundingMode frm) {  in FCvtLS()  argument
1149   EmitR(0x60, 0x2, rs1, enum_cast<uint32_t>(frm), rd, 0x53);  in FCvtLS()
1152 void Riscv64Assembler::FCvtLD(XRegister rd, FRegister rs1, FPRoundingMode frm) {  in FCvtLD()  argument
1154   EmitR(0x61, 0x2, rs1, enum_cast<uint32_t>(frm), rd, 0x53);  in FCvtLD()
1157 void Riscv64Assembler::FCvtLuS(XRegister rd, FRegister rs1, FPRoundingMode frm) {  in FCvtLuS()  argument
1159   EmitR(0x60, 0x3, rs1, enum_cast<uint32_t>(frm), rd, 0x53);  in FCvtLuS()
1162 void Riscv64Assembler::FCvtLuD(XRegister rd, FRegister rs1, FPRoundingMode frm) {  in FCvtLuD()  argument
1164   EmitR(0x61, 0x3, rs1, enum_cast<uint32_t>(frm), rd, 0x53);  in FCvtLuD()
1167 void Riscv64Assembler::FCvtSW(FRegister rd, XRegister rs1, FPRoundingMode frm) {  in FCvtSW()  argument
1169   EmitR(0x68, 0x0, rs1, enum_cast<uint32_t>(frm), rd, 0x53);  in FCvtSW()
1172 void Riscv64Assembler::FCvtDW(FRegister rd, XRegister rs1, FPRoundingMode frm) {  in FCvtDW()  argument
1175   EmitR(0x69, 0x0, rs1, enum_cast<uint32_t>(frm), rd, 0x53);  in FCvtDW()
1178 void Riscv64Assembler::FCvtSWu(FRegister rd, XRegister rs1, FPRoundingMode frm) {  in FCvtSWu()  argument
1180   EmitR(0x68, 0x1, rs1, enum_cast<uint32_t>(frm), rd, 0x53);  in FCvtSWu()
1183 void Riscv64Assembler::FCvtDWu(FRegister rd, XRegister rs1, FPRoundingMode frm) {  in FCvtDWu()  argument
1186   EmitR(0x69, 0x1, rs1, enum_cast<uint32_t>(frm), rd, 0x53);  in FCvtDWu()
1189 void Riscv64Assembler::FCvtSL(FRegister rd, XRegister rs1, FPRoundingMode frm) {  in FCvtSL()  argument
1191   EmitR(0x68, 0x2, rs1, enum_cast<uint32_t>(frm), rd, 0x53);  in FCvtSL()
1194 void Riscv64Assembler::FCvtDL(FRegister rd, XRegister rs1, FPRoundingMode frm) {  in FCvtDL()  argument
1196   EmitR(0x69, 0x2, rs1, enum_cast<uint32_t>(frm), rd, 0x53);  in FCvtDL()
1199 void Riscv64Assembler::FCvtSLu(FRegister rd, XRegister rs1, FPRoundingMode frm) {  in FCvtSLu()  argument
1201   EmitR(0x68, 0x3, rs1, enum_cast<uint32_t>(frm), rd, 0x53);  in FCvtSLu()
1204 void Riscv64Assembler::FCvtDLu(FRegister rd, XRegister rs1, FPRoundingMode frm) {  in FCvtDLu()  argument
1206   EmitR(0x69, 0x3, rs1, enum_cast<uint32_t>(frm), rd, 0x53);  in FCvtDLu()
1211 void Riscv64Assembler::FMvXW(XRegister rd, FRegister rs1) {  in FMvXW()  argument
1213   EmitR(0x70, 0x0, rs1, 0x0, rd, 0x53);  in FMvXW()
1216 void Riscv64Assembler::FMvXD(XRegister rd, FRegister rs1) {  in FMvXD()  argument
1218   EmitR(0x71, 0x0, rs1, 0x0, rd, 0x53);  in FMvXD()
1221 void Riscv64Assembler::FMvWX(FRegister rd, XRegister rs1) {  in FMvWX()  argument
1223   EmitR(0x78, 0x0, rs1, 0x0, rd, 0x53);  in FMvWX()
1226 void Riscv64Assembler::FMvDX(FRegister rd, XRegister rs1) {  in FMvDX()  argument
1228   EmitR(0x79, 0x0, rs1, 0x0, rd, 0x53);  in FMvDX()
1233 void Riscv64Assembler::FClassS(XRegister rd, FRegister rs1) {  in FClassS()  argument
1235   EmitR(0x70, 0x0, rs1, 0x1, rd, 0x53);  in FClassS()
1238 void Riscv64Assembler::FClassD(XRegister rd, FRegister rs1) {  in FClassD()  argument
1240   EmitR(0x71, 0x0, rs1, 0x1, rd, 0x53);  in FClassD()
1519 void Riscv64Assembler::CJr(XRegister rs1) {  in CJr()  argument
1521   DCHECK_NE(rs1, Zero);  in CJr()
1522   EmitCR(0b1000u, rs1, Zero, 0b10u);  in CJr()
1525 void Riscv64Assembler::CJalr(XRegister rs1) {  in CJalr()  argument
1527   DCHECK_NE(rs1, Zero);  in CJalr()
1528   EmitCR(0b1001u, rs1, Zero, 0b10u);  in CJalr()
1560 void Riscv64Assembler::AddUw(XRegister rd, XRegister rs1, XRegister rs2) {  in AddUw()  argument
1562   EmitR(0x4, rs2, rs1, 0x0, rd, 0x3b);  in AddUw()
1565 void Riscv64Assembler::Sh1Add(XRegister rd, XRegister rs1, XRegister rs2) {  in Sh1Add()  argument
1567   EmitR(0x10, rs2, rs1, 0x2, rd, 0x33);  in Sh1Add()
1570 void Riscv64Assembler::Sh1AddUw(XRegister rd, XRegister rs1, XRegister rs2) {  in Sh1AddUw()  argument
1572   EmitR(0x10, rs2, rs1, 0x2, rd, 0x3b);  in Sh1AddUw()
1575 void Riscv64Assembler::Sh2Add(XRegister rd, XRegister rs1, XRegister rs2) {  in Sh2Add()  argument
1577   EmitR(0x10, rs2, rs1, 0x4, rd, 0x33);  in Sh2Add()
1580 void Riscv64Assembler::Sh2AddUw(XRegister rd, XRegister rs1, XRegister rs2) {  in Sh2AddUw()  argument
1582   EmitR(0x10, rs2, rs1, 0x4, rd, 0x3b);  in Sh2AddUw()
1585 void Riscv64Assembler::Sh3Add(XRegister rd, XRegister rs1, XRegister rs2) {  in Sh3Add()  argument
1587   EmitR(0x10, rs2, rs1, 0x6, rd, 0x33);  in Sh3Add()
1590 void Riscv64Assembler::Sh3AddUw(XRegister rd, XRegister rs1, XRegister rs2) {  in Sh3AddUw()  argument
1592   EmitR(0x10, rs2, rs1, 0x6, rd, 0x3b);  in Sh3AddUw()
1595 void Riscv64Assembler::SlliUw(XRegister rd, XRegister rs1, int32_t shamt) {  in SlliUw()  argument
1597   EmitI6(0x2, shamt, rs1, 0x1, rd, 0x1b);  in SlliUw()
1604 void Riscv64Assembler::Andn(XRegister rd, XRegister rs1, XRegister rs2) {  in Andn()  argument
1606   EmitR(0x20, rs2, rs1, 0x7, rd, 0x33);  in Andn()
1609 void Riscv64Assembler::Orn(XRegister rd, XRegister rs1, XRegister rs2) {  in Orn()  argument
1611   EmitR(0x20, rs2, rs1, 0x6, rd, 0x33);  in Orn()
1614 void Riscv64Assembler::Xnor(XRegister rd, XRegister rs1, XRegister rs2) {  in Xnor()  argument
1616   EmitR(0x20, rs2, rs1, 0x4, rd, 0x33);  in Xnor()
1619 void Riscv64Assembler::Clz(XRegister rd, XRegister rs1) {  in Clz()  argument
1621   EmitR(0x30, 0x0, rs1, 0x1, rd, 0x13);  in Clz()
1624 void Riscv64Assembler::Clzw(XRegister rd, XRegister rs1) {  in Clzw()  argument
1626   EmitR(0x30, 0x0, rs1, 0x1, rd, 0x1b);  in Clzw()
1629 void Riscv64Assembler::Ctz(XRegister rd, XRegister rs1) {  in Ctz()  argument
1631   EmitR(0x30, 0x1, rs1, 0x1, rd, 0x13);  in Ctz()
1634 void Riscv64Assembler::Ctzw(XRegister rd, XRegister rs1) {  in Ctzw()  argument
1636   EmitR(0x30, 0x1, rs1, 0x1, rd, 0x1b);  in Ctzw()
1639 void Riscv64Assembler::Cpop(XRegister rd, XRegister rs1) {  in Cpop()  argument
1641   EmitR(0x30, 0x2, rs1, 0x1, rd, 0x13);  in Cpop()
1644 void Riscv64Assembler::Cpopw(XRegister rd, XRegister rs1) {  in Cpopw()  argument
1646   EmitR(0x30, 0x2, rs1, 0x1, rd, 0x1b);  in Cpopw()
1649 void Riscv64Assembler::Min(XRegister rd, XRegister rs1, XRegister rs2) {  in Min()  argument
1651   EmitR(0x5, rs2, rs1, 0x4, rd, 0x33);  in Min()
1654 void Riscv64Assembler::Minu(XRegister rd, XRegister rs1, XRegister rs2) {  in Minu()  argument
1656   EmitR(0x5, rs2, rs1, 0x5, rd, 0x33);  in Minu()
1659 void Riscv64Assembler::Max(XRegister rd, XRegister rs1, XRegister rs2) {  in Max()  argument
1661   EmitR(0x5, rs2, rs1, 0x6, rd, 0x33);  in Max()
1664 void Riscv64Assembler::Maxu(XRegister rd, XRegister rs1, XRegister rs2) {  in Maxu()  argument
1666   EmitR(0x5, rs2, rs1, 0x7, rd, 0x33);  in Maxu()
1669 void Riscv64Assembler::Rol(XRegister rd, XRegister rs1, XRegister rs2) {  in Rol()  argument
1671   EmitR(0x30, rs2, rs1, 0x1, rd, 0x33);  in Rol()
1674 void Riscv64Assembler::Rolw(XRegister rd, XRegister rs1, XRegister rs2) {  in Rolw()  argument
1676   EmitR(0x30, rs2, rs1, 0x1, rd, 0x3b);  in Rolw()
1679 void Riscv64Assembler::Ror(XRegister rd, XRegister rs1, XRegister rs2) {  in Ror()  argument
1681   EmitR(0x30, rs2, rs1, 0x5, rd, 0x33);  in Ror()
1684 void Riscv64Assembler::Rorw(XRegister rd, XRegister rs1, XRegister rs2) {  in Rorw()  argument
1686   EmitR(0x30, rs2, rs1, 0x5, rd, 0x3b);  in Rorw()
1689 void Riscv64Assembler::Rori(XRegister rd, XRegister rs1, int32_t shamt) {  in Rori()  argument
1692   EmitI6(0x18, shamt, rs1, 0x5, rd, 0x13);  in Rori()
1695 void Riscv64Assembler::Roriw(XRegister rd, XRegister rs1, int32_t shamt) {  in Roriw()  argument
1698   EmitI6(0x18, shamt, rs1, 0x5, rd, 0x1b);  in Roriw()
1701 void Riscv64Assembler::OrcB(XRegister rd, XRegister rs1) {  in OrcB()  argument
1703   EmitR(0x14, 0x7, rs1, 0x5, rd, 0x13);  in OrcB()
1706 void Riscv64Assembler::Rev8(XRegister rd, XRegister rs1) {  in Rev8()  argument
1708   EmitR(0x35, 0x18, rs1, 0x5, rd, 0x13);  in Rev8()
1711 void Riscv64Assembler::ZbbSextB(XRegister rd, XRegister rs1) {  in ZbbSextB()  argument
1713   EmitR(0x30, 0x4, rs1, 0x1, rd, 0x13);  in ZbbSextB()
1716 void Riscv64Assembler::ZbbSextH(XRegister rd, XRegister rs1) {  in ZbbSextH()  argument
1718   EmitR(0x30, 0x5, rs1, 0x1, rd, 0x13);  in ZbbSextH()
1721 void Riscv64Assembler::ZbbZextH(XRegister rd, XRegister rs1) {  in ZbbZextH()  argument
1723   EmitR(0x4, 0x0, rs1, 0x4, rd, 0x3b);  in ZbbZextH()
1730 void Riscv64Assembler::VSetvli(XRegister rd, XRegister rs1, uint32_t vtypei) {  in VSetvli()  argument
1733   EmitI(vtypei, rs1, enum_cast<uint32_t>(VAIEncoding::kOPCFG), rd, 0x57);  in VSetvli()
1743 void Riscv64Assembler::VSetvl(XRegister rd, XRegister rs1, XRegister rs2) {  in VSetvl()  argument
1745   EmitR(0x40, rs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPCFG), rd, 0x57);  in VSetvl()
1752 void Riscv64Assembler::VLe8(VRegister vd, XRegister rs1, VM vm) {  in VLe8()  argument
1756   EmitR(funct7, 0b00000, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLe8()
1759 void Riscv64Assembler::VLe16(VRegister vd, XRegister rs1, VM vm) {  in VLe16()  argument
1763   EmitR(funct7, 0b00000, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLe16()
1766 void Riscv64Assembler::VLe32(VRegister vd, XRegister rs1, VM vm) {  in VLe32()  argument
1770   EmitR(funct7, 0b00000, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLe32()
1773 void Riscv64Assembler::VLe64(VRegister vd, XRegister rs1, VM vm) {  in VLe64()  argument
1777   EmitR(funct7, 0b00000, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLe64()
1780 void Riscv64Assembler::VSe8(VRegister vs3, XRegister rs1, VM vm) {  in VSe8()  argument
1783   EmitR(funct7, 0b00000, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27);  in VSe8()
1786 void Riscv64Assembler::VSe16(VRegister vs3, XRegister rs1, VM vm) {  in VSe16()  argument
1789   EmitR(funct7, 0b00000, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27);  in VSe16()
1792 void Riscv64Assembler::VSe32(VRegister vs3, XRegister rs1, VM vm) {  in VSe32()  argument
1795   EmitR(funct7, 0b00000, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27);  in VSe32()
1798 void Riscv64Assembler::VSe64(VRegister vs3, XRegister rs1, VM vm) {  in VSe64()  argument
1801   EmitR(funct7, 0b00000, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27);  in VSe64()
1804 void Riscv64Assembler::VLm(VRegister vd, XRegister rs1) {  in VLm()  argument
1807   EmitR(funct7, 0b01011, rs1, enum_cast<uint32_t>(VectorWidth::kMask), vd, 0x7);  in VLm()
1810 void Riscv64Assembler::VSm(VRegister vs3, XRegister rs1) {  in VSm()  argument
1813   EmitR(funct7, 0b01011, rs1, enum_cast<uint32_t>(VectorWidth::kMask), vs3, 0x27);  in VSm()
1816 void Riscv64Assembler::VLe8ff(VRegister vd, XRegister rs1) {  in VLe8ff()  argument
1819   EmitR(funct7, 0b10000, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLe8ff()
1822 void Riscv64Assembler::VLe16ff(VRegister vd, XRegister rs1) {  in VLe16ff()  argument
1825   EmitR(funct7, 0b10000, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLe16ff()
1828 void Riscv64Assembler::VLe32ff(VRegister vd, XRegister rs1) {  in VLe32ff()  argument
1831   EmitR(funct7, 0b10000, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLe32ff()
1834 void Riscv64Assembler::VLe64ff(VRegister vd, XRegister rs1) {  in VLe64ff()  argument
1837   EmitR(funct7, 0b10000, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLe64ff()
1840 void Riscv64Assembler::VLse8(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLse8()  argument
1844   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLse8()
1847 void Riscv64Assembler::VLse16(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLse16()  argument
1851   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLse16()
1854 void Riscv64Assembler::VLse32(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLse32()  argument
1858   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLse32()
1861 void Riscv64Assembler::VLse64(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLse64()  argument
1865   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLse64()
1868 void Riscv64Assembler::VSse8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSse8()  argument
1871   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27);  in VSse8()
1874 void Riscv64Assembler::VSse16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSse16()  argument
1877   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27);  in VSse16()
1880 void Riscv64Assembler::VSse32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSse32()  argument
1883   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27);  in VSse32()
1886 void Riscv64Assembler::VSse64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSse64()  argument
1889   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27);  in VSse64()
1892 void Riscv64Assembler::VLoxei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxei8()  argument
1896   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLoxei8()
1899 void Riscv64Assembler::VLoxei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxei16()  argument
1903   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLoxei16()
1906 void Riscv64Assembler::VLoxei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxei32()  argument
1910   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLoxei32()
1913 void Riscv64Assembler::VLoxei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxei64()  argument
1917   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLoxei64()
1920 void Riscv64Assembler::VLuxei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxei8()  argument
1924   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLuxei8()
1927 void Riscv64Assembler::VLuxei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxei16()  argument
1931   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLuxei16()
1934 void Riscv64Assembler::VLuxei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxei32()  argument
1938   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLuxei32()
1941 void Riscv64Assembler::VLuxei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxei64()  argument
1945   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLuxei64()
1948 void Riscv64Assembler::VSoxei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxei8()  argument
1951   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27);  in VSoxei8()
1954 void Riscv64Assembler::VSoxei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxei16()  argument
1957   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27);  in VSoxei16()
1960 void Riscv64Assembler::VSoxei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxei32()  argument
1963   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27);  in VSoxei32()
1966 void Riscv64Assembler::VSoxei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxei64()  argument
1969   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27);  in VSoxei64()
1972 void Riscv64Assembler::VSuxei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxei8()  argument
1975   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27);  in VSuxei8()
1978 void Riscv64Assembler::VSuxei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxei16()  argument
1981   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27);  in VSuxei16()
1984 void Riscv64Assembler::VSuxei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxei32()  argument
1987   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27);  in VSuxei32()
1990 void Riscv64Assembler::VSuxei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxei64()  argument
1993   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27);  in VSuxei64()
1996 void Riscv64Assembler::VLseg2e8(VRegister vd, XRegister rs1, VM vm) {  in VLseg2e8()  argument
2000   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLseg2e8()
2003 void Riscv64Assembler::VLseg2e16(VRegister vd, XRegister rs1, VM vm) {  in VLseg2e16()  argument
2007   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLseg2e16()
2010 void Riscv64Assembler::VLseg2e32(VRegister vd, XRegister rs1, VM vm) {  in VLseg2e32()  argument
2014   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLseg2e32()
2017 void Riscv64Assembler::VLseg2e64(VRegister vd, XRegister rs1, VM vm) {  in VLseg2e64()  argument
2021   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLseg2e64()
2024 void Riscv64Assembler::VLseg3e8(VRegister vd, XRegister rs1, VM vm) {  in VLseg3e8()  argument
2028   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLseg3e8()
2031 void Riscv64Assembler::VLseg3e16(VRegister vd, XRegister rs1, VM vm) {  in VLseg3e16()  argument
2035   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLseg3e16()
2038 void Riscv64Assembler::VLseg3e32(VRegister vd, XRegister rs1, VM vm) {  in VLseg3e32()  argument
2042   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLseg3e32()
2045 void Riscv64Assembler::VLseg3e64(VRegister vd, XRegister rs1, VM vm) {  in VLseg3e64()  argument
2049   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLseg3e64()
2052 void Riscv64Assembler::VLseg4e8(VRegister vd, XRegister rs1, VM vm) {  in VLseg4e8()  argument
2056   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLseg4e8()
2059 void Riscv64Assembler::VLseg4e16(VRegister vd, XRegister rs1, VM vm) {  in VLseg4e16()  argument
2063   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLseg4e16()
2066 void Riscv64Assembler::VLseg4e32(VRegister vd, XRegister rs1, VM vm) {  in VLseg4e32()  argument
2070   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLseg4e32()
2073 void Riscv64Assembler::VLseg4e64(VRegister vd, XRegister rs1, VM vm) {  in VLseg4e64()  argument
2077   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLseg4e64()
2080 void Riscv64Assembler::VLseg5e8(VRegister vd, XRegister rs1, VM vm) {  in VLseg5e8()  argument
2084   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLseg5e8()
2087 void Riscv64Assembler::VLseg5e16(VRegister vd, XRegister rs1, VM vm) {  in VLseg5e16()  argument
2091   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLseg5e16()
2094 void Riscv64Assembler::VLseg5e32(VRegister vd, XRegister rs1, VM vm) {  in VLseg5e32()  argument
2098   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLseg5e32()
2101 void Riscv64Assembler::VLseg5e64(VRegister vd, XRegister rs1, VM vm) {  in VLseg5e64()  argument
2105   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLseg5e64()
2108 void Riscv64Assembler::VLseg6e8(VRegister vd, XRegister rs1, VM vm) {  in VLseg6e8()  argument
2112   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLseg6e8()
2115 void Riscv64Assembler::VLseg6e16(VRegister vd, XRegister rs1, VM vm) {  in VLseg6e16()  argument
2119   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLseg6e16()
2122 void Riscv64Assembler::VLseg6e32(VRegister vd, XRegister rs1, VM vm) {  in VLseg6e32()  argument
2126   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLseg6e32()
2129 void Riscv64Assembler::VLseg6e64(VRegister vd, XRegister rs1, VM vm) {  in VLseg6e64()  argument
2133   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLseg6e64()
2136 void Riscv64Assembler::VLseg7e8(VRegister vd, XRegister rs1, VM vm) {  in VLseg7e8()  argument
2140   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLseg7e8()
2143 void Riscv64Assembler::VLseg7e16(VRegister vd, XRegister rs1, VM vm) {  in VLseg7e16()  argument
2147   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLseg7e16()
2150 void Riscv64Assembler::VLseg7e32(VRegister vd, XRegister rs1, VM vm) {  in VLseg7e32()  argument
2154   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLseg7e32()
2157 void Riscv64Assembler::VLseg7e64(VRegister vd, XRegister rs1, VM vm) {  in VLseg7e64()  argument
2161   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLseg7e64()
2164 void Riscv64Assembler::VLseg8e8(VRegister vd, XRegister rs1, VM vm) {  in VLseg8e8()  argument
2168   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLseg8e8()
2171 void Riscv64Assembler::VLseg8e16(VRegister vd, XRegister rs1, VM vm) {  in VLseg8e16()  argument
2175   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLseg8e16()
2178 void Riscv64Assembler::VLseg8e32(VRegister vd, XRegister rs1, VM vm) {  in VLseg8e32()  argument
2182   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLseg8e32()
2185 void Riscv64Assembler::VLseg8e64(VRegister vd, XRegister rs1, VM vm) {  in VLseg8e64()  argument
2189   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLseg8e64()
2192 void Riscv64Assembler::VSseg2e8(VRegister vs3, XRegister rs1, VM vm) {  in VSseg2e8()  argument
2195   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27);  in VSseg2e8()
2198 void Riscv64Assembler::VSseg2e16(VRegister vs3, XRegister rs1, VM vm) {  in VSseg2e16()  argument
2201   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27);  in VSseg2e16()
2204 void Riscv64Assembler::VSseg2e32(VRegister vs3, XRegister rs1, VM vm) {  in VSseg2e32()  argument
2207   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27);  in VSseg2e32()
2210 void Riscv64Assembler::VSseg2e64(VRegister vs3, XRegister rs1, VM vm) {  in VSseg2e64()  argument
2213   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27);  in VSseg2e64()
2216 void Riscv64Assembler::VSseg3e8(VRegister vs3, XRegister rs1, VM vm) {  in VSseg3e8()  argument
2219   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27);  in VSseg3e8()
2222 void Riscv64Assembler::VSseg3e16(VRegister vs3, XRegister rs1, VM vm) {  in VSseg3e16()  argument
2225   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27);  in VSseg3e16()
2228 void Riscv64Assembler::VSseg3e32(VRegister vs3, XRegister rs1, VM vm) {  in VSseg3e32()  argument
2231   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27);  in VSseg3e32()
2234 void Riscv64Assembler::VSseg3e64(VRegister vs3, XRegister rs1, VM vm) {  in VSseg3e64()  argument
2237   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27);  in VSseg3e64()
2240 void Riscv64Assembler::VSseg4e8(VRegister vs3, XRegister rs1, VM vm) {  in VSseg4e8()  argument
2243   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27);  in VSseg4e8()
2246 void Riscv64Assembler::VSseg4e16(VRegister vs3, XRegister rs1, VM vm) {  in VSseg4e16()  argument
2249   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27);  in VSseg4e16()
2252 void Riscv64Assembler::VSseg4e32(VRegister vs3, XRegister rs1, VM vm) {  in VSseg4e32()  argument
2255   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27);  in VSseg4e32()
2258 void Riscv64Assembler::VSseg4e64(VRegister vs3, XRegister rs1, VM vm) {  in VSseg4e64()  argument
2261   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27);  in VSseg4e64()
2264 void Riscv64Assembler::VSseg5e8(VRegister vs3, XRegister rs1, VM vm) {  in VSseg5e8()  argument
2267   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27);  in VSseg5e8()
2270 void Riscv64Assembler::VSseg5e16(VRegister vs3, XRegister rs1, VM vm) {  in VSseg5e16()  argument
2273   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27);  in VSseg5e16()
2276 void Riscv64Assembler::VSseg5e32(VRegister vs3, XRegister rs1, VM vm) {  in VSseg5e32()  argument
2279   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27);  in VSseg5e32()
2282 void Riscv64Assembler::VSseg5e64(VRegister vs3, XRegister rs1, VM vm) {  in VSseg5e64()  argument
2285   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27);  in VSseg5e64()
2288 void Riscv64Assembler::VSseg6e8(VRegister vs3, XRegister rs1, VM vm) {  in VSseg6e8()  argument
2291   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27);  in VSseg6e8()
2294 void Riscv64Assembler::VSseg6e16(VRegister vs3, XRegister rs1, VM vm) {  in VSseg6e16()  argument
2297   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27);  in VSseg6e16()
2300 void Riscv64Assembler::VSseg6e32(VRegister vs3, XRegister rs1, VM vm) {  in VSseg6e32()  argument
2303   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27);  in VSseg6e32()
2306 void Riscv64Assembler::VSseg6e64(VRegister vs3, XRegister rs1, VM vm) {  in VSseg6e64()  argument
2309   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27);  in VSseg6e64()
2312 void Riscv64Assembler::VSseg7e8(VRegister vs3, XRegister rs1, VM vm) {  in VSseg7e8()  argument
2315   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27);  in VSseg7e8()
2318 void Riscv64Assembler::VSseg7e16(VRegister vs3, XRegister rs1, VM vm) {  in VSseg7e16()  argument
2321   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27);  in VSseg7e16()
2324 void Riscv64Assembler::VSseg7e32(VRegister vs3, XRegister rs1, VM vm) {  in VSseg7e32()  argument
2327   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27);  in VSseg7e32()
2330 void Riscv64Assembler::VSseg7e64(VRegister vs3, XRegister rs1, VM vm) {  in VSseg7e64()  argument
2333   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27);  in VSseg7e64()
2336 void Riscv64Assembler::VSseg8e8(VRegister vs3, XRegister rs1, VM vm) {  in VSseg8e8()  argument
2339   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27);  in VSseg8e8()
2342 void Riscv64Assembler::VSseg8e16(VRegister vs3, XRegister rs1, VM vm) {  in VSseg8e16()  argument
2345   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27);  in VSseg8e16()
2348 void Riscv64Assembler::VSseg8e32(VRegister vs3, XRegister rs1, VM vm) {  in VSseg8e32()  argument
2351   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27);  in VSseg8e32()
2354 void Riscv64Assembler::VSseg8e64(VRegister vs3, XRegister rs1, VM vm) {  in VSseg8e64()  argument
2357   EmitR(funct7, 0b00000u, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27);  in VSseg8e64()
2360 void Riscv64Assembler::VLseg2e8ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg2e8ff()  argument
2364   EmitR(funct7, 0b10000u, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLseg2e8ff()
2367 void Riscv64Assembler::VLseg2e16ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg2e16ff()  argument
2371   EmitR(funct7, 0b10000u, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLseg2e16ff()
2374 void Riscv64Assembler::VLseg2e32ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg2e32ff()  argument
2378   EmitR(funct7, 0b10000u, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLseg2e32ff()
2381 void Riscv64Assembler::VLseg2e64ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg2e64ff()  argument
2385   EmitR(funct7, 0b10000u, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLseg2e64ff()
2388 void Riscv64Assembler::VLseg3e8ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg3e8ff()  argument
2392   EmitR(funct7, 0b10000u, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLseg3e8ff()
2395 void Riscv64Assembler::VLseg3e16ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg3e16ff()  argument
2399   EmitR(funct7, 0b10000u, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLseg3e16ff()
2402 void Riscv64Assembler::VLseg3e32ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg3e32ff()  argument
2406   EmitR(funct7, 0b10000u, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLseg3e32ff()
2409 void Riscv64Assembler::VLseg3e64ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg3e64ff()  argument
2413   EmitR(funct7, 0b10000u, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLseg3e64ff()
2416 void Riscv64Assembler::VLseg4e8ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg4e8ff()  argument
2420   EmitR(funct7, 0b10000u, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLseg4e8ff()
2423 void Riscv64Assembler::VLseg4e16ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg4e16ff()  argument
2427   EmitR(funct7, 0b10000u, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLseg4e16ff()
2430 void Riscv64Assembler::VLseg4e32ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg4e32ff()  argument
2434   EmitR(funct7, 0b10000u, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLseg4e32ff()
2437 void Riscv64Assembler::VLseg4e64ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg4e64ff()  argument
2441   EmitR(funct7, 0b10000u, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLseg4e64ff()
2444 void Riscv64Assembler::VLseg5e8ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg5e8ff()  argument
2448   EmitR(funct7, 0b10000u, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLseg5e8ff()
2451 void Riscv64Assembler::VLseg5e16ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg5e16ff()  argument
2455   EmitR(funct7, 0b10000u, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLseg5e16ff()
2458 void Riscv64Assembler::VLseg5e32ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg5e32ff()  argument
2462   EmitR(funct7, 0b10000u, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLseg5e32ff()
2465 void Riscv64Assembler::VLseg5e64ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg5e64ff()  argument
2469   EmitR(funct7, 0b10000u, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLseg5e64ff()
2472 void Riscv64Assembler::VLseg6e8ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg6e8ff()  argument
2476   EmitR(funct7, 0b10000u, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLseg6e8ff()
2479 void Riscv64Assembler::VLseg6e16ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg6e16ff()  argument
2483   EmitR(funct7, 0b10000u, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLseg6e16ff()
2486 void Riscv64Assembler::VLseg6e32ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg6e32ff()  argument
2490   EmitR(funct7, 0b10000u, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLseg6e32ff()
2493 void Riscv64Assembler::VLseg6e64ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg6e64ff()  argument
2497   EmitR(funct7, 0b10000u, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLseg6e64ff()
2500 void Riscv64Assembler::VLseg7e8ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg7e8ff()  argument
2504   EmitR(funct7, 0b10000u, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLseg7e8ff()
2507 void Riscv64Assembler::VLseg7e16ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg7e16ff()  argument
2511   EmitR(funct7, 0b10000u, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLseg7e16ff()
2514 void Riscv64Assembler::VLseg7e32ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg7e32ff()  argument
2518   EmitR(funct7, 0b10000u, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLseg7e32ff()
2521 void Riscv64Assembler::VLseg7e64ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg7e64ff()  argument
2525   EmitR(funct7, 0b10000u, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLseg7e64ff()
2528 void Riscv64Assembler::VLseg8e8ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg8e8ff()  argument
2532   EmitR(funct7, 0b10000u, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLseg8e8ff()
2535 void Riscv64Assembler::VLseg8e16ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg8e16ff()  argument
2539   EmitR(funct7, 0b10000u, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLseg8e16ff()
2542 void Riscv64Assembler::VLseg8e32ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg8e32ff()  argument
2546   EmitR(funct7, 0b10000u, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLseg8e32ff()
2549 void Riscv64Assembler::VLseg8e64ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg8e64ff()  argument
2553   EmitR(funct7, 0b10000u, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLseg8e64ff()
2556 void Riscv64Assembler::VLsseg2e8(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg2e8()  argument
2560   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLsseg2e8()
2563 void Riscv64Assembler::VLsseg2e16(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg2e16()  argument
2567   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLsseg2e16()
2570 void Riscv64Assembler::VLsseg2e32(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg2e32()  argument
2574   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLsseg2e32()
2577 void Riscv64Assembler::VLsseg2e64(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg2e64()  argument
2581   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLsseg2e64()
2584 void Riscv64Assembler::VLsseg3e8(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg3e8()  argument
2588   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLsseg3e8()
2591 void Riscv64Assembler::VLsseg3e16(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg3e16()  argument
2595   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLsseg3e16()
2598 void Riscv64Assembler::VLsseg3e32(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg3e32()  argument
2602   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLsseg3e32()
2605 void Riscv64Assembler::VLsseg3e64(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg3e64()  argument
2609   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLsseg3e64()
2612 void Riscv64Assembler::VLsseg4e8(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg4e8()  argument
2616   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLsseg4e8()
2619 void Riscv64Assembler::VLsseg4e16(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg4e16()  argument
2623   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLsseg4e16()
2626 void Riscv64Assembler::VLsseg4e32(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg4e32()  argument
2630   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLsseg4e32()
2633 void Riscv64Assembler::VLsseg4e64(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg4e64()  argument
2637   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLsseg4e64()
2640 void Riscv64Assembler::VLsseg5e8(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg5e8()  argument
2644   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLsseg5e8()
2647 void Riscv64Assembler::VLsseg5e16(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg5e16()  argument
2651   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLsseg5e16()
2654 void Riscv64Assembler::VLsseg5e32(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg5e32()  argument
2658   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLsseg5e32()
2661 void Riscv64Assembler::VLsseg5e64(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg5e64()  argument
2665   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLsseg5e64()
2668 void Riscv64Assembler::VLsseg6e8(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg6e8()  argument
2672   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLsseg6e8()
2675 void Riscv64Assembler::VLsseg6e16(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg6e16()  argument
2679   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLsseg6e16()
2682 void Riscv64Assembler::VLsseg6e32(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg6e32()  argument
2686   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLsseg6e32()
2689 void Riscv64Assembler::VLsseg6e64(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg6e64()  argument
2693   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLsseg6e64()
2696 void Riscv64Assembler::VLsseg7e8(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg7e8()  argument
2700   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLsseg7e8()
2703 void Riscv64Assembler::VLsseg7e16(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg7e16()  argument
2707   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLsseg7e16()
2710 void Riscv64Assembler::VLsseg7e32(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg7e32()  argument
2714   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLsseg7e32()
2717 void Riscv64Assembler::VLsseg7e64(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg7e64()  argument
2721   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLsseg7e64()
2724 void Riscv64Assembler::VLsseg8e8(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg8e8()  argument
2728   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLsseg8e8()
2731 void Riscv64Assembler::VLsseg8e16(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg8e16()  argument
2735   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLsseg8e16()
2738 void Riscv64Assembler::VLsseg8e32(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg8e32()  argument
2742   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLsseg8e32()
2745 void Riscv64Assembler::VLsseg8e64(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg8e64()  argument
2749   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLsseg8e64()
2752 void Riscv64Assembler::VSsseg2e8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg2e8()  argument
2755   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27);  in VSsseg2e8()
2758 void Riscv64Assembler::VSsseg2e16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg2e16()  argument
2761   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27);  in VSsseg2e16()
2764 void Riscv64Assembler::VSsseg2e32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg2e32()  argument
2767   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27);  in VSsseg2e32()
2770 void Riscv64Assembler::VSsseg2e64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg2e64()  argument
2773   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27);  in VSsseg2e64()
2776 void Riscv64Assembler::VSsseg3e8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg3e8()  argument
2779   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27);  in VSsseg3e8()
2782 void Riscv64Assembler::VSsseg3e16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg3e16()  argument
2785   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27);  in VSsseg3e16()
2788 void Riscv64Assembler::VSsseg3e32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg3e32()  argument
2791   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27);  in VSsseg3e32()
2794 void Riscv64Assembler::VSsseg3e64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg3e64()  argument
2797   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27);  in VSsseg3e64()
2800 void Riscv64Assembler::VSsseg4e8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg4e8()  argument
2803   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27);  in VSsseg4e8()
2806 void Riscv64Assembler::VSsseg4e16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg4e16()  argument
2809   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27);  in VSsseg4e16()
2812 void Riscv64Assembler::VSsseg4e32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg4e32()  argument
2815   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27);  in VSsseg4e32()
2818 void Riscv64Assembler::VSsseg4e64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg4e64()  argument
2821   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27);  in VSsseg4e64()
2824 void Riscv64Assembler::VSsseg5e8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg5e8()  argument
2827   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27);  in VSsseg5e8()
2830 void Riscv64Assembler::VSsseg5e16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg5e16()  argument
2833   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27);  in VSsseg5e16()
2836 void Riscv64Assembler::VSsseg5e32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg5e32()  argument
2839   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27);  in VSsseg5e32()
2842 void Riscv64Assembler::VSsseg5e64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg5e64()  argument
2845   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27);  in VSsseg5e64()
2848 void Riscv64Assembler::VSsseg6e8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg6e8()  argument
2851   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27);  in VSsseg6e8()
2854 void Riscv64Assembler::VSsseg6e16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg6e16()  argument
2857   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27);  in VSsseg6e16()
2860 void Riscv64Assembler::VSsseg6e32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg6e32()  argument
2863   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27);  in VSsseg6e32()
2866 void Riscv64Assembler::VSsseg6e64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg6e64()  argument
2869   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27);  in VSsseg6e64()
2872 void Riscv64Assembler::VSsseg7e8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg7e8()  argument
2875   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27);  in VSsseg7e8()
2878 void Riscv64Assembler::VSsseg7e16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg7e16()  argument
2881   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27);  in VSsseg7e16()
2884 void Riscv64Assembler::VSsseg7e32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg7e32()  argument
2887   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27);  in VSsseg7e32()
2890 void Riscv64Assembler::VSsseg7e64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg7e64()  argument
2893   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27);  in VSsseg7e64()
2896 void Riscv64Assembler::VSsseg8e8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg8e8()  argument
2899   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27);  in VSsseg8e8()
2902 void Riscv64Assembler::VSsseg8e16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg8e16()  argument
2905   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27);  in VSsseg8e16()
2908 void Riscv64Assembler::VSsseg8e32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg8e32()  argument
2911   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27);  in VSsseg8e32()
2914 void Riscv64Assembler::VSsseg8e64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg8e64()  argument
2917   EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27);  in VSsseg8e64()
2920 void Riscv64Assembler::VLuxseg2ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg2ei8()  argument
2924   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLuxseg2ei8()
2927 void Riscv64Assembler::VLuxseg2ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg2ei16()  argument
2931   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLuxseg2ei16()
2934 void Riscv64Assembler::VLuxseg2ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg2ei32()  argument
2938   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLuxseg2ei32()
2941 void Riscv64Assembler::VLuxseg2ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg2ei64()  argument
2945   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLuxseg2ei64()
2948 void Riscv64Assembler::VLuxseg3ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg3ei8()  argument
2952   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLuxseg3ei8()
2955 void Riscv64Assembler::VLuxseg3ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg3ei16()  argument
2959   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLuxseg3ei16()
2962 void Riscv64Assembler::VLuxseg3ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg3ei32()  argument
2966   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLuxseg3ei32()
2969 void Riscv64Assembler::VLuxseg3ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg3ei64()  argument
2973   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLuxseg3ei64()
2976 void Riscv64Assembler::VLuxseg4ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg4ei8()  argument
2980   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLuxseg4ei8()
2983 void Riscv64Assembler::VLuxseg4ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg4ei16()  argument
2987   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLuxseg4ei16()
2990 void Riscv64Assembler::VLuxseg4ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg4ei32()  argument
2994   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLuxseg4ei32()
2997 void Riscv64Assembler::VLuxseg4ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg4ei64()  argument
3001   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLuxseg4ei64()
3004 void Riscv64Assembler::VLuxseg5ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg5ei8()  argument
3008   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLuxseg5ei8()
3011 void Riscv64Assembler::VLuxseg5ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg5ei16()  argument
3015   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLuxseg5ei16()
3018 void Riscv64Assembler::VLuxseg5ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg5ei32()  argument
3022   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLuxseg5ei32()
3025 void Riscv64Assembler::VLuxseg5ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg5ei64()  argument
3029   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLuxseg5ei64()
3032 void Riscv64Assembler::VLuxseg6ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg6ei8()  argument
3036   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLuxseg6ei8()
3039 void Riscv64Assembler::VLuxseg6ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg6ei16()  argument
3043   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLuxseg6ei16()
3046 void Riscv64Assembler::VLuxseg6ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg6ei32()  argument
3050   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLuxseg6ei32()
3053 void Riscv64Assembler::VLuxseg6ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg6ei64()  argument
3057   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLuxseg6ei64()
3060 void Riscv64Assembler::VLuxseg7ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg7ei8()  argument
3064   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLuxseg7ei8()
3067 void Riscv64Assembler::VLuxseg7ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg7ei16()  argument
3071   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLuxseg7ei16()
3074 void Riscv64Assembler::VLuxseg7ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg7ei32()  argument
3078   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLuxseg7ei32()
3081 void Riscv64Assembler::VLuxseg7ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg7ei64()  argument
3085   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLuxseg7ei64()
3088 void Riscv64Assembler::VLuxseg8ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg8ei8()  argument
3092   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLuxseg8ei8()
3095 void Riscv64Assembler::VLuxseg8ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg8ei16()  argument
3099   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLuxseg8ei16()
3102 void Riscv64Assembler::VLuxseg8ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg8ei32()  argument
3106   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLuxseg8ei32()
3109 void Riscv64Assembler::VLuxseg8ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg8ei64()  argument
3113   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLuxseg8ei64()
3116 void Riscv64Assembler::VSuxseg2ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg2ei8()  argument
3119   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27);  in VSuxseg2ei8()
3122 void Riscv64Assembler::VSuxseg2ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg2ei16()  argument
3125   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27);  in VSuxseg2ei16()
3128 void Riscv64Assembler::VSuxseg2ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg2ei32()  argument
3131   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27);  in VSuxseg2ei32()
3134 void Riscv64Assembler::VSuxseg2ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg2ei64()  argument
3137   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27);  in VSuxseg2ei64()
3140 void Riscv64Assembler::VSuxseg3ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg3ei8()  argument
3143   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27);  in VSuxseg3ei8()
3146 void Riscv64Assembler::VSuxseg3ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg3ei16()  argument
3149   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27);  in VSuxseg3ei16()
3152 void Riscv64Assembler::VSuxseg3ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg3ei32()  argument
3155   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27);  in VSuxseg3ei32()
3158 void Riscv64Assembler::VSuxseg3ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg3ei64()  argument
3161   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27);  in VSuxseg3ei64()
3164 void Riscv64Assembler::VSuxseg4ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg4ei8()  argument
3167   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27);  in VSuxseg4ei8()
3170 void Riscv64Assembler::VSuxseg4ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg4ei16()  argument
3173   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27);  in VSuxseg4ei16()
3176 void Riscv64Assembler::VSuxseg4ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg4ei32()  argument
3179   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27);  in VSuxseg4ei32()
3182 void Riscv64Assembler::VSuxseg4ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg4ei64()  argument
3185   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27);  in VSuxseg4ei64()
3188 void Riscv64Assembler::VSuxseg5ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg5ei8()  argument
3191   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27);  in VSuxseg5ei8()
3194 void Riscv64Assembler::VSuxseg5ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg5ei16()  argument
3197   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27);  in VSuxseg5ei16()
3200 void Riscv64Assembler::VSuxseg5ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg5ei32()  argument
3203   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27);  in VSuxseg5ei32()
3206 void Riscv64Assembler::VSuxseg5ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg5ei64()  argument
3209   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27);  in VSuxseg5ei64()
3212 void Riscv64Assembler::VSuxseg6ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg6ei8()  argument
3215   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27);  in VSuxseg6ei8()
3218 void Riscv64Assembler::VSuxseg6ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg6ei16()  argument
3221   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27);  in VSuxseg6ei16()
3224 void Riscv64Assembler::VSuxseg6ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg6ei32()  argument
3227   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27);  in VSuxseg6ei32()
3230 void Riscv64Assembler::VSuxseg6ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg6ei64()  argument
3233   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27);  in VSuxseg6ei64()
3236 void Riscv64Assembler::VSuxseg7ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg7ei8()  argument
3239   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27);  in VSuxseg7ei8()
3242 void Riscv64Assembler::VSuxseg7ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg7ei16()  argument
3245   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27);  in VSuxseg7ei16()
3248 void Riscv64Assembler::VSuxseg7ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg7ei32()  argument
3251   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27);  in VSuxseg7ei32()
3254 void Riscv64Assembler::VSuxseg7ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg7ei64()  argument
3257   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27);  in VSuxseg7ei64()
3260 void Riscv64Assembler::VSuxseg8ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg8ei8()  argument
3263   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27);  in VSuxseg8ei8()
3266 void Riscv64Assembler::VSuxseg8ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg8ei16()  argument
3269   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27);  in VSuxseg8ei16()
3272 void Riscv64Assembler::VSuxseg8ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg8ei32()  argument
3275   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27);  in VSuxseg8ei32()
3278 void Riscv64Assembler::VSuxseg8ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg8ei64()  argument
3281   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27);  in VSuxseg8ei64()
3284 void Riscv64Assembler::VLoxseg2ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg2ei8()  argument
3288   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLoxseg2ei8()
3291 void Riscv64Assembler::VLoxseg2ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg2ei16()  argument
3295   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLoxseg2ei16()
3298 void Riscv64Assembler::VLoxseg2ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg2ei32()  argument
3302   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLoxseg2ei32()
3305 void Riscv64Assembler::VLoxseg2ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg2ei64()  argument
3309   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLoxseg2ei64()
3312 void Riscv64Assembler::VLoxseg3ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg3ei8()  argument
3316   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLoxseg3ei8()
3319 void Riscv64Assembler::VLoxseg3ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg3ei16()  argument
3323   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLoxseg3ei16()
3326 void Riscv64Assembler::VLoxseg3ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg3ei32()  argument
3330   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLoxseg3ei32()
3333 void Riscv64Assembler::VLoxseg3ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg3ei64()  argument
3337   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLoxseg3ei64()
3340 void Riscv64Assembler::VLoxseg4ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg4ei8()  argument
3344   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLoxseg4ei8()
3347 void Riscv64Assembler::VLoxseg4ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg4ei16()  argument
3351   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLoxseg4ei16()
3354 void Riscv64Assembler::VLoxseg4ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg4ei32()  argument
3358   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLoxseg4ei32()
3361 void Riscv64Assembler::VLoxseg4ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg4ei64()  argument
3365   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLoxseg4ei64()
3368 void Riscv64Assembler::VLoxseg5ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg5ei8()  argument
3372   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLoxseg5ei8()
3375 void Riscv64Assembler::VLoxseg5ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg5ei16()  argument
3379   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLoxseg5ei16()
3382 void Riscv64Assembler::VLoxseg5ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg5ei32()  argument
3386   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLoxseg5ei32()
3389 void Riscv64Assembler::VLoxseg5ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg5ei64()  argument
3393   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLoxseg5ei64()
3396 void Riscv64Assembler::VLoxseg6ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg6ei8()  argument
3400   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLoxseg6ei8()
3403 void Riscv64Assembler::VLoxseg6ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg6ei16()  argument
3407   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLoxseg6ei16()
3410 void Riscv64Assembler::VLoxseg6ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg6ei32()  argument
3414   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLoxseg6ei32()
3417 void Riscv64Assembler::VLoxseg6ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg6ei64()  argument
3421   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLoxseg6ei64()
3424 void Riscv64Assembler::VLoxseg7ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg7ei8()  argument
3428   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLoxseg7ei8()
3431 void Riscv64Assembler::VLoxseg7ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg7ei16()  argument
3435   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLoxseg7ei16()
3438 void Riscv64Assembler::VLoxseg7ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg7ei32()  argument
3442   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLoxseg7ei32()
3445 void Riscv64Assembler::VLoxseg7ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg7ei64()  argument
3449   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLoxseg7ei64()
3452 void Riscv64Assembler::VLoxseg8ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg8ei8()  argument
3456   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VLoxseg8ei8()
3459 void Riscv64Assembler::VLoxseg8ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg8ei16()  argument
3463   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VLoxseg8ei16()
3466 void Riscv64Assembler::VLoxseg8ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg8ei32()  argument
3470   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VLoxseg8ei32()
3473 void Riscv64Assembler::VLoxseg8ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg8ei64()  argument
3477   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VLoxseg8ei64()
3480 void Riscv64Assembler::VSoxseg2ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg2ei8()  argument
3483   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27);  in VSoxseg2ei8()
3486 void Riscv64Assembler::VSoxseg2ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg2ei16()  argument
3489   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27);  in VSoxseg2ei16()
3492 void Riscv64Assembler::VSoxseg2ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg2ei32()  argument
3495   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27);  in VSoxseg2ei32()
3498 void Riscv64Assembler::VSoxseg2ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg2ei64()  argument
3501   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27);  in VSoxseg2ei64()
3504 void Riscv64Assembler::VSoxseg3ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg3ei8()  argument
3507   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27);  in VSoxseg3ei8()
3510 void Riscv64Assembler::VSoxseg3ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg3ei16()  argument
3513   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27);  in VSoxseg3ei16()
3516 void Riscv64Assembler::VSoxseg3ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg3ei32()  argument
3519   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27);  in VSoxseg3ei32()
3522 void Riscv64Assembler::VSoxseg3ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg3ei64()  argument
3525   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27);  in VSoxseg3ei64()
3528 void Riscv64Assembler::VSoxseg4ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg4ei8()  argument
3531   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27);  in VSoxseg4ei8()
3534 void Riscv64Assembler::VSoxseg4ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg4ei16()  argument
3537   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27);  in VSoxseg4ei16()
3540 void Riscv64Assembler::VSoxseg4ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg4ei32()  argument
3543   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27);  in VSoxseg4ei32()
3546 void Riscv64Assembler::VSoxseg4ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg4ei64()  argument
3549   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27);  in VSoxseg4ei64()
3552 void Riscv64Assembler::VSoxseg5ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg5ei8()  argument
3555   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27);  in VSoxseg5ei8()
3558 void Riscv64Assembler::VSoxseg5ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg5ei16()  argument
3561   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27);  in VSoxseg5ei16()
3564 void Riscv64Assembler::VSoxseg5ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg5ei32()  argument
3567   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27);  in VSoxseg5ei32()
3570 void Riscv64Assembler::VSoxseg5ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg5ei64()  argument
3573   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27);  in VSoxseg5ei64()
3576 void Riscv64Assembler::VSoxseg6ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg6ei8()  argument
3579   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27);  in VSoxseg6ei8()
3582 void Riscv64Assembler::VSoxseg6ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg6ei16()  argument
3585   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27);  in VSoxseg6ei16()
3588 void Riscv64Assembler::VSoxseg6ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg6ei32()  argument
3591   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27);  in VSoxseg6ei32()
3594 void Riscv64Assembler::VSoxseg6ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg6ei64()  argument
3597   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27);  in VSoxseg6ei64()
3600 void Riscv64Assembler::VSoxseg7ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg7ei8()  argument
3603   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27);  in VSoxseg7ei8()
3606 void Riscv64Assembler::VSoxseg7ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg7ei16()  argument
3609   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27);  in VSoxseg7ei16()
3612 void Riscv64Assembler::VSoxseg7ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg7ei32()  argument
3615   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27);  in VSoxseg7ei32()
3618 void Riscv64Assembler::VSoxseg7ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg7ei64()  argument
3621   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27);  in VSoxseg7ei64()
3624 void Riscv64Assembler::VSoxseg8ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg8ei8()  argument
3627   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27);  in VSoxseg8ei8()
3630 void Riscv64Assembler::VSoxseg8ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg8ei16()  argument
3633   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27);  in VSoxseg8ei16()
3636 void Riscv64Assembler::VSoxseg8ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg8ei32()  argument
3639   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27);  in VSoxseg8ei32()
3642 void Riscv64Assembler::VSoxseg8ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg8ei64()  argument
3645   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27);  in VSoxseg8ei64()
3648 void Riscv64Assembler::VL1re8(VRegister vd, XRegister rs1) {  in VL1re8()  argument
3651   EmitR(funct7, 0b01000u, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VL1re8()
3654 void Riscv64Assembler::VL1re16(VRegister vd, XRegister rs1) {  in VL1re16()  argument
3657   EmitR(funct7, 0b01000u, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VL1re16()
3660 void Riscv64Assembler::VL1re32(VRegister vd, XRegister rs1) {  in VL1re32()  argument
3663   EmitR(funct7, 0b01000u, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VL1re32()
3666 void Riscv64Assembler::VL1re64(VRegister vd, XRegister rs1) {  in VL1re64()  argument
3669   EmitR(funct7, 0b01000u, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VL1re64()
3672 void Riscv64Assembler::VL2re8(VRegister vd, XRegister rs1) {  in VL2re8()  argument
3676   EmitR(funct7, 0b01000u, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VL2re8()
3679 void Riscv64Assembler::VL2re16(VRegister vd, XRegister rs1) {  in VL2re16()  argument
3683   EmitR(funct7, 0b01000u, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VL2re16()
3686 void Riscv64Assembler::VL2re32(VRegister vd, XRegister rs1) {  in VL2re32()  argument
3690   EmitR(funct7, 0b01000u, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VL2re32()
3693 void Riscv64Assembler::VL2re64(VRegister vd, XRegister rs1) {  in VL2re64()  argument
3697   EmitR(funct7, 0b01000u, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VL2re64()
3700 void Riscv64Assembler::VL4re8(VRegister vd, XRegister rs1) {  in VL4re8()  argument
3704   EmitR(funct7, 0b01000u, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VL4re8()
3707 void Riscv64Assembler::VL4re16(VRegister vd, XRegister rs1) {  in VL4re16()  argument
3711   EmitR(funct7, 0b01000u, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VL4re16()
3714 void Riscv64Assembler::VL4re32(VRegister vd, XRegister rs1) {  in VL4re32()  argument
3718   EmitR(funct7, 0b01000u, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VL4re32()
3721 void Riscv64Assembler::VL4re64(VRegister vd, XRegister rs1) {  in VL4re64()  argument
3725   EmitR(funct7, 0b01000u, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VL4re64()
3728 void Riscv64Assembler::VL8re8(VRegister vd, XRegister rs1) {  in VL8re8()  argument
3732   EmitR(funct7, 0b01000u, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7);  in VL8re8()
3735 void Riscv64Assembler::VL8re16(VRegister vd, XRegister rs1) {  in VL8re16()  argument
3739   EmitR(funct7, 0b01000u, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7);  in VL8re16()
3742 void Riscv64Assembler::VL8re32(VRegister vd, XRegister rs1) {  in VL8re32()  argument
3746   EmitR(funct7, 0b01000u, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7);  in VL8re32()
3749 void Riscv64Assembler::VL8re64(VRegister vd, XRegister rs1) {  in VL8re64()  argument
3753   EmitR(funct7, 0b01000u, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7);  in VL8re64()
3756 void Riscv64Assembler::VL1r(VRegister vd, XRegister rs1) { VL1re8(vd, rs1); }  in VL1r()  argument
3758 void Riscv64Assembler::VL2r(VRegister vd, XRegister rs1) { VL2re8(vd, rs1); }  in VL2r()  argument
3760 void Riscv64Assembler::VL4r(VRegister vd, XRegister rs1) { VL4re8(vd, rs1); }  in VL4r()  argument
3762 void Riscv64Assembler::VL8r(VRegister vd, XRegister rs1) { VL8re8(vd, rs1); }  in VL8r()  argument
3764 void Riscv64Assembler::VS1r(VRegister vs3, XRegister rs1) {  in VS1r()  argument
3767   EmitR(funct7, 0b01000u, rs1, enum_cast<uint32_t>(VectorWidth::kWholeR), vs3, 0x27);  in VS1r()
3770 void Riscv64Assembler::VS2r(VRegister vs3, XRegister rs1) {  in VS2r()  argument
3773   EmitR(funct7, 0b01000u, rs1, enum_cast<uint32_t>(VectorWidth::kWholeR), vs3, 0x27);  in VS2r()
3776 void Riscv64Assembler::VS4r(VRegister vs3, XRegister rs1) {  in VS4r()  argument
3779   EmitR(funct7, 0b01000u, rs1, enum_cast<uint32_t>(VectorWidth::kWholeR), vs3, 0x27);  in VS4r()
3782 void Riscv64Assembler::VS8r(VRegister vs3, XRegister rs1) {  in VS8r()  argument
3785   EmitR(funct7, 0b01000u, rs1, enum_cast<uint32_t>(VectorWidth::kWholeR), vs3, 0x27);  in VS8r()
3799 void Riscv64Assembler::VAdd_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VAdd_vx()  argument
3803   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VAdd_vx()
3820 void Riscv64Assembler::VSub_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VSub_vx()  argument
3824   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VSub_vx()
3827 void Riscv64Assembler::VRsub_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VRsub_vx()  argument
3831   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VRsub_vx()
3850 void Riscv64Assembler::VMinu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VMinu_vx()  argument
3854   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VMinu_vx()
3864 void Riscv64Assembler::VMin_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VMin_vx()  argument
3868   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VMin_vx()
3878 void Riscv64Assembler::VMaxu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VMaxu_vx()  argument
3882   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VMaxu_vx()
3892 void Riscv64Assembler::VMax_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VMax_vx()  argument
3896   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VMax_vx()
3906 void Riscv64Assembler::VAnd_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VAnd_vx()  argument
3910   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VAnd_vx()
3927 void Riscv64Assembler::VOr_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VOr_vx()  argument
3930   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VOr_vx()
3947 void Riscv64Assembler::VXor_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VXor_vx()  argument
3951   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VXor_vx()
3972 void Riscv64Assembler::VRgather_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VRgather_vx()  argument
3977   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VRgather_vx()
3988 void Riscv64Assembler::VSlideup_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VSlideup_vx()  argument
3993   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VSlideup_vx()
4013 void Riscv64Assembler::VSlidedown_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VSlidedown_vx()  argument
4018   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VSlidedown_vx()
4035 void Riscv64Assembler::VAdc_vxm(VRegister vd, VRegister vs2, XRegister rs1) {  in VAdc_vxm()  argument
4039   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VAdc_vxm()
4055 void Riscv64Assembler::VMadc_vxm(VRegister vd, VRegister vs2, XRegister rs1) {  in VMadc_vxm()  argument
4058   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VMadc_vxm()
4073 void Riscv64Assembler::VMadc_vx(VRegister vd, VRegister vs2, XRegister rs1) {  in VMadc_vx()  argument
4076   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VMadc_vx()
4092 void Riscv64Assembler::VSbc_vxm(VRegister vd, VRegister vs2, XRegister rs1) {  in VSbc_vxm()  argument
4096   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VSbc_vxm()
4105 void Riscv64Assembler::VMsbc_vxm(VRegister vd, VRegister vs2, XRegister rs1) {  in VMsbc_vxm()  argument
4108   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VMsbc_vxm()
4117 void Riscv64Assembler::VMsbc_vx(VRegister vd, VRegister vs2, XRegister rs1) {  in VMsbc_vx()  argument
4120   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VMsbc_vx()
4130 void Riscv64Assembler::VMerge_vxm(VRegister vd, VRegister vs2, XRegister rs1) {  in VMerge_vxm()  argument
4134   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VMerge_vxm()
4150 void Riscv64Assembler::VMv_vx(VRegister vd, XRegister rs1) {  in VMv_vx()  argument
4153   EmitR(funct7, V0, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VMv_vx()
4169 void Riscv64Assembler::VMseq_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VMseq_vx()  argument
4173   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VMseq_vx()
4190 void Riscv64Assembler::VMsne_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VMsne_vx()  argument
4194   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VMsne_vx()
4211 void Riscv64Assembler::VMsltu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VMsltu_vx()  argument
4215   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VMsltu_vx()
4230 void Riscv64Assembler::VMslt_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VMslt_vx()  argument
4234   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VMslt_vx()
4248 void Riscv64Assembler::VMsleu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VMsleu_vx()  argument
4252   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VMsleu_vx()
4278 void Riscv64Assembler::VMsle_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VMsle_vx()  argument
4282   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VMsle_vx()
4300 void Riscv64Assembler::VMsgtu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VMsgtu_vx()  argument
4304   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VMsgtu_vx()
4320 void Riscv64Assembler::VMsgt_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VMsgt_vx()  argument
4324   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VMsgt_vx()
4345 void Riscv64Assembler::VSaddu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VSaddu_vx()  argument
4349   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VSaddu_vx()
4366 void Riscv64Assembler::VSadd_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VSadd_vx()  argument
4370   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VSadd_vx()
4387 void Riscv64Assembler::VSsubu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VSsubu_vx()  argument
4391   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VSsubu_vx()
4401 void Riscv64Assembler::VSsub_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VSsub_vx()  argument
4405   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VSsub_vx()
4415 void Riscv64Assembler::VSll_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VSll_vx()  argument
4419   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VSll_vx()
4436 void Riscv64Assembler::VSmul_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VSmul_vx()  argument
4440   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VSmul_vx()
4484 void Riscv64Assembler::VSrl_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VSrl_vx()  argument
4488   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VSrl_vx()
4505 void Riscv64Assembler::VSra_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VSra_vx()  argument
4509   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VSra_vx()
4526 void Riscv64Assembler::VSsrl_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VSsrl_vx()  argument
4530   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VSsrl_vx()
4547 void Riscv64Assembler::VSsra_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VSsra_vx()  argument
4551   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VSsra_vx()
4568 void Riscv64Assembler::VNsrl_wx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VNsrl_wx()  argument
4572   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VNsrl_wx()
4594 void Riscv64Assembler::VNsra_wx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VNsra_wx()  argument
4598   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VNsra_wx()
4615 void Riscv64Assembler::VNclipu_wx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VNclipu_wx()  argument
4619   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VNclipu_wx()
4636 void Riscv64Assembler::VNclip_wx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VNclip_wx()  argument
4640   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPIVX), vd, 0x57);  in VNclip_wx()
4717 void Riscv64Assembler::VAaddu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VAaddu_vx()  argument
4721   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VAaddu_vx()
4731 void Riscv64Assembler::VAadd_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VAadd_vx()  argument
4735   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VAadd_vx()
4745 void Riscv64Assembler::VAsubu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VAsubu_vx()  argument
4749   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VAsubu_vx()
4759 void Riscv64Assembler::VAsub_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VAsub_vx()  argument
4763   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VAsub_vx()
4766 void Riscv64Assembler::VSlide1up_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VSlide1up_vx()  argument
4771   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VSlide1up_vx()
4774 void Riscv64Assembler::VSlide1down_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VSlide1down_vx()  argument
4778   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VSlide1down_vx()
4852 void Riscv64Assembler::VDivu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VDivu_vx()  argument
4856   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VDivu_vx()
4866 void Riscv64Assembler::VDiv_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VDiv_vx()  argument
4870   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VDiv_vx()
4880 void Riscv64Assembler::VRemu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VRemu_vx()  argument
4884   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VRemu_vx()
4894 void Riscv64Assembler::VRem_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VRem_vx()  argument
4898   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VRem_vx()
4908 void Riscv64Assembler::VMulhu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VMulhu_vx()  argument
4912   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VMulhu_vx()
4922 void Riscv64Assembler::VMul_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VMul_vx()  argument
4926   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VMul_vx()
4936 void Riscv64Assembler::VMulhsu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VMulhsu_vx()  argument
4940   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VMulhsu_vx()
4950 void Riscv64Assembler::VMulh_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VMulh_vx()  argument
4954   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VMulh_vx()
4964 void Riscv64Assembler::VMadd_vx(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VMadd_vx()  argument
4968   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VMadd_vx()
4978 void Riscv64Assembler::VNmsub_vx(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VNmsub_vx()  argument
4982   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VNmsub_vx()
4992 void Riscv64Assembler::VMacc_vx(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VMacc_vx()  argument
4996   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VMacc_vx()
5008 void Riscv64Assembler::VNmsac_vx(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VNmsac_vx()  argument
5012   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VNmsac_vx()
5024 void Riscv64Assembler::VWaddu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VWaddu_vx()  argument
5029   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VWaddu_vx()
5045 void Riscv64Assembler::VWadd_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VWadd_vx()  argument
5050   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VWadd_vx()
5066 void Riscv64Assembler::VWsubu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VWsubu_vx()  argument
5071   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VWsubu_vx()
5083 void Riscv64Assembler::VWsub_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VWsub_vx()  argument
5088   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VWsub_vx()
5099 void Riscv64Assembler::VWaddu_wx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VWaddu_wx()  argument
5103   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VWaddu_wx()
5114 void Riscv64Assembler::VWadd_wx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VWadd_wx()  argument
5118   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VWadd_wx()
5129 void Riscv64Assembler::VWsubu_wx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VWsubu_wx()  argument
5133   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VWsubu_wx()
5144 void Riscv64Assembler::VWsub_wx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VWsub_wx()  argument
5148   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VWsub_wx()
5160 void Riscv64Assembler::VWmulu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VWmulu_vx()  argument
5165   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VWmulu_vx()
5177 void Riscv64Assembler::VWmulsu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VWmulsu_vx()  argument
5182   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VWmulsu_vx()
5194 void Riscv64Assembler::VWmul_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VWmul_vx()  argument
5199   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VWmul_vx()
5211 void Riscv64Assembler::VWmaccu_vx(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VWmaccu_vx()  argument
5216   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VWmaccu_vx()
5228 void Riscv64Assembler::VWmacc_vx(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VWmacc_vx()  argument
5233   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VWmacc_vx()
5236 void Riscv64Assembler::VWmaccus_vx(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VWmaccus_vx()  argument
5241   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VWmaccus_vx()
5253 void Riscv64Assembler::VWmaccsu_vx(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VWmaccsu_vx()  argument
5258   EmitR(funct7, vs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VWmaccsu_vx()
5808 void Riscv64Assembler::VMv_s_x(VRegister vd, XRegister rs1) {  in VMv_s_x()  argument
5811   EmitR(funct7, 0b00000, rs1, enum_cast<uint32_t>(VAIEncoding::kOPMVX), vd, 0x57);  in VMv_s_x()
6311 void Riscv64Assembler::Loadb(XRegister rd, XRegister rs1, int32_t offset) {  in Loadb()  argument
6312   LoadFromOffset<&Riscv64Assembler::Lb>(rd, rs1, offset);  in Loadb()
6315 void Riscv64Assembler::Loadh(XRegister rd, XRegister rs1, int32_t offset) {  in Loadh()  argument
6316   LoadFromOffset<&Riscv64Assembler::Lh>(rd, rs1, offset);  in Loadh()
6319 void Riscv64Assembler::Loadw(XRegister rd, XRegister rs1, int32_t offset) {  in Loadw()  argument
6320   LoadFromOffset<&Riscv64Assembler::Lw>(rd, rs1, offset);  in Loadw()
6323 void Riscv64Assembler::Loadd(XRegister rd, XRegister rs1, int32_t offset) {  in Loadd()  argument
6324   LoadFromOffset<&Riscv64Assembler::Ld>(rd, rs1, offset);  in Loadd()
6327 void Riscv64Assembler::Loadbu(XRegister rd, XRegister rs1, int32_t offset) {  in Loadbu()  argument
6328   LoadFromOffset<&Riscv64Assembler::Lbu>(rd, rs1, offset);  in Loadbu()
6331 void Riscv64Assembler::Loadhu(XRegister rd, XRegister rs1, int32_t offset) {  in Loadhu()  argument
6332   LoadFromOffset<&Riscv64Assembler::Lhu>(rd, rs1, offset);  in Loadhu()
6335 void Riscv64Assembler::Loadwu(XRegister rd, XRegister rs1, int32_t offset) {  in Loadwu()  argument
6336   LoadFromOffset<&Riscv64Assembler::Lwu>(rd, rs1, offset);  in Loadwu()
6339 void Riscv64Assembler::Storeb(XRegister rs2, XRegister rs1, int32_t offset) {  in Storeb()  argument
6340   StoreToOffset<&Riscv64Assembler::Sb>(rs2, rs1, offset);  in Storeb()
6343 void Riscv64Assembler::Storeh(XRegister rs2, XRegister rs1, int32_t offset) {  in Storeh()  argument
6344   StoreToOffset<&Riscv64Assembler::Sh>(rs2, rs1, offset);  in Storeh()
6347 void Riscv64Assembler::Storew(XRegister rs2, XRegister rs1, int32_t offset) {  in Storew()  argument
6348   StoreToOffset<&Riscv64Assembler::Sw>(rs2, rs1, offset);  in Storew()
6351 void Riscv64Assembler::Stored(XRegister rs2, XRegister rs1, int32_t offset) {  in Stored()  argument
6352   StoreToOffset<&Riscv64Assembler::Sd>(rs2, rs1, offset);  in Stored()
6355 void Riscv64Assembler::FLoadw(FRegister rd, XRegister rs1, int32_t offset) {  in FLoadw()  argument
6356   FLoadFromOffset<&Riscv64Assembler::FLw>(rd, rs1, offset);  in FLoadw()
6359 void Riscv64Assembler::FLoadd(FRegister rd, XRegister rs1, int32_t offset) {  in FLoadd()  argument
6360   FLoadFromOffset<&Riscv64Assembler::FLd>(rd, rs1, offset);  in FLoadd()
6363 void Riscv64Assembler::FStorew(FRegister rs2, XRegister rs1, int32_t offset) {  in FStorew()  argument
6364   FStoreToOffset<&Riscv64Assembler::FSw>(rs2, rs1, offset);  in FStorew()
6367 void Riscv64Assembler::FStored(FRegister rs2, XRegister rs1, int32_t offset) {  in FStored()  argument
6368   FStoreToOffset<&Riscv64Assembler::FSd>(rs2, rs1, offset);  in FStored()
6383                   XRegister rs1,  in AddConstImpl()  argument
6390   DCHECK_IMPLIES(rd == rs1 || rd == SP, srs.AvailableXRegisters() != 0u);  in AddConstImpl()
6393     addi(rd, rs1, value);  in AddConstImpl()
6402   if (rd != rs1 && rd != SP) {  in AddConstImpl()
6407     addi(tmp, rs1, kPositiveValueSimpleAdjustment);  in AddConstImpl()
6410     addi(tmp, rs1, kNegativeValueSimpleAdjustment);  in AddConstImpl()
6413     add_large(rd, rs1, value, tmp);  in AddConstImpl()
6417 void Riscv64Assembler::AddConst32(XRegister rd, XRegister rs1, int32_t value) {  in AddConst32()  argument
6418   CHECK_EQ((1u << rs1) & available_scratch_core_registers_, 0u);  in AddConst32()
6420   auto addiw = [&](XRegister rd, XRegister rs1, int32_t value) { Addiw(rd, rs1, value); };  in AddConst32()  argument
6421   auto add_large = [&](XRegister rd, XRegister rs1, int32_t value, XRegister tmp) {  in AddConst32()  argument
6423     Addw(rd, rs1, tmp);  in AddConst32()
6425   AddConstImpl(this, rd, rs1, value, addiw, add_large);  in AddConst32()
6428 void Riscv64Assembler::AddConst64(XRegister rd, XRegister rs1, int64_t value) {  in AddConst64()  argument
6429   CHECK_EQ((1u << rs1) & available_scratch_core_registers_, 0u);  in AddConst64()
6431   auto addi = [&](XRegister rd, XRegister rs1, int32_t value) { Addi(rd, rs1, value); };  in AddConst64()  argument
6432   auto add_large = [&](XRegister rd, XRegister rs1, int64_t value, XRegister tmp) {  in AddConst64()  argument
6439     Add(rd, rs1, tmp);  in AddConst64()
6441   AddConstImpl(this, rd, rs1, value, addi, add_large);  in AddConst64()
7597 void Riscv64Assembler::LoadFromOffset(XRegister rd, XRegister rs1, int32_t offset) {  in LoadFromOffset()  argument
7598   CHECK_EQ((1u << rs1) & available_scratch_core_registers_, 0u);  in LoadFromOffset()
7602   if (rd != rs1) {  in LoadFromOffset()
7605   AdjustBaseAndOffset(rs1, offset, srs);  in LoadFromOffset()
7606   (this->*insn)(rd, rs1, offset);  in LoadFromOffset()
7610 void Riscv64Assembler::StoreToOffset(XRegister rs2, XRegister rs1, int32_t offset) {  in StoreToOffset()  argument
7611   CHECK_EQ((1u << rs1) & available_scratch_core_registers_, 0u);  in StoreToOffset()
7614   AdjustBaseAndOffset(rs1, offset, srs);  in StoreToOffset()
7615   (this->*insn)(rs2, rs1, offset);  in StoreToOffset()
7619 void Riscv64Assembler::FLoadFromOffset(FRegister rd, XRegister rs1, int32_t offset) {  in FLoadFromOffset()  argument
7620   CHECK_EQ((1u << rs1) & available_scratch_core_registers_, 0u);  in FLoadFromOffset()
7622   AdjustBaseAndOffset(rs1, offset, srs);  in FLoadFromOffset()
7623   (this->*insn)(rd, rs1, offset);  in FLoadFromOffset()
7627 void Riscv64Assembler::FStoreToOffset(FRegister rs2, XRegister rs1, int32_t offset) {  in FStoreToOffset()  argument
7628   CHECK_EQ((1u << rs1) & available_scratch_core_registers_, 0u);  in FStoreToOffset()
7630   AdjustBaseAndOffset(rs1, offset, srs);  in FStoreToOffset()
7631   (this->*insn)(rs2, rs1, offset);  in FStoreToOffset()