1297 void Riscv64Assembler::CSw(XRegister rs2_s, XRegister rs1_s, int32_t offset) {  in CSw()  argument
1299   EmitCM(0b110u, ExtractOffset52_6(offset), rs1_s, rs2_s, 0b00u);  in CSw()
1302 void Riscv64Assembler::CSd(XRegister rs2_s, XRegister rs1_s, int32_t offset) {  in CSd()  argument
1304   EmitCM(0b111u, ExtractOffset53_76(offset), rs1_s, rs2_s, 0b00u);  in CSd()
1307 void Riscv64Assembler::CFSd(FRegister rs2_s, XRegister rs1_s, int32_t offset) {  in CFSd()  argument
1310   EmitCM(0b101u, ExtractOffset53_76(offset), rs1_s, rs2_s, 0b00u);  in CFSd()
1416 void Riscv64Assembler::CAnd(XRegister rd_s, XRegister rs2_s) {  in CAnd()  argument
1418   EmitCAReg(0b100011u, rd_s, 0b11u, rs2_s, 0b01u);  in CAnd()
1421 void Riscv64Assembler::COr(XRegister rd_s, XRegister rs2_s) {  in COr()  argument
1423   EmitCAReg(0b100011u, rd_s, 0b10u, rs2_s, 0b01u);  in COr()
1426 void Riscv64Assembler::CXor(XRegister rd_s, XRegister rs2_s) {  in CXor()  argument
1428   EmitCAReg(0b100011u, rd_s, 0b01u, rs2_s, 0b01u);  in CXor()
1431 void Riscv64Assembler::CSub(XRegister rd_s, XRegister rs2_s) {  in CSub()  argument
1433   EmitCAReg(0b100011u, rd_s, 0b00u, rs2_s, 0b01u);  in CSub()
1436 void Riscv64Assembler::CAddw(XRegister rd_s, XRegister rs2_s) {  in CAddw()  argument
1438   EmitCAReg(0b100111u, rd_s, 0b01u, rs2_s, 0b01u);  in CAddw()
1441 void Riscv64Assembler::CSubw(XRegister rd_s, XRegister rs2_s) {  in CSubw()  argument
1443   EmitCAReg(0b100111u, rd_s, 0b00u, rs2_s, 0b01u);  in CSubw()
1467 void Riscv64Assembler::CSb(XRegister rs2_s, XRegister rs1_s, int32_t offset) {  in CSb()  argument
1469   EmitCAReg(0b100010u, rs1_s, EncodeOffset0_1(offset), rs2_s, 0b00u);  in CSb()
1472 void Riscv64Assembler::CSh(XRegister rs2_s, XRegister rs1_s, int32_t offset) {  in CSh()  argument
1476   EmitCAReg(0b100011u, rs1_s, BitFieldExtract<uint32_t>(offset, 1, 1), rs2_s, 0b00u);  in CSh()
1509 void Riscv64Assembler::CMul(XRegister rd_s, XRegister rs2_s) {  in CMul()  argument
1511   EmitCAReg(0b100111u, rd_s, 0b10u, rs2_s, 0b01u);  in CMul()