Lines Matching refs:vm
1752 void Riscv64Assembler::VLe8(VRegister vd, XRegister rs1, VM vm) { in VLe8() argument
1754 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLe8()
1755 const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kUnitStride, vm); in VLe8()
1759 void Riscv64Assembler::VLe16(VRegister vd, XRegister rs1, VM vm) { in VLe16() argument
1761 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLe16()
1762 const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kUnitStride, vm); in VLe16()
1766 void Riscv64Assembler::VLe32(VRegister vd, XRegister rs1, VM vm) { in VLe32() argument
1768 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLe32()
1769 const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kUnitStride, vm); in VLe32()
1773 void Riscv64Assembler::VLe64(VRegister vd, XRegister rs1, VM vm) { in VLe64() argument
1775 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLe64()
1776 const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kUnitStride, vm); in VLe64()
1780 void Riscv64Assembler::VSe8(VRegister vs3, XRegister rs1, VM vm) { in VSe8() argument
1782 const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kUnitStride, vm); in VSe8()
1786 void Riscv64Assembler::VSe16(VRegister vs3, XRegister rs1, VM vm) { in VSe16() argument
1788 const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kUnitStride, vm); in VSe16()
1792 void Riscv64Assembler::VSe32(VRegister vs3, XRegister rs1, VM vm) { in VSe32() argument
1794 const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kUnitStride, vm); in VSe32()
1798 void Riscv64Assembler::VSe64(VRegister vs3, XRegister rs1, VM vm) { in VSe64() argument
1800 const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kUnitStride, vm); in VSe64()
1840 void Riscv64Assembler::VLse8(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLse8() argument
1842 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLse8()
1843 const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kStrided, vm); in VLse8()
1847 void Riscv64Assembler::VLse16(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLse16() argument
1849 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLse16()
1850 const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kStrided, vm); in VLse16()
1854 void Riscv64Assembler::VLse32(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLse32() argument
1856 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLse32()
1857 const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kStrided, vm); in VLse32()
1861 void Riscv64Assembler::VLse64(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLse64() argument
1863 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLse64()
1864 const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kStrided, vm); in VLse64()
1868 void Riscv64Assembler::VSse8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSse8() argument
1870 const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kStrided, vm); in VSse8()
1874 void Riscv64Assembler::VSse16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSse16() argument
1876 const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kStrided, vm); in VSse16()
1880 void Riscv64Assembler::VSse32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSse32() argument
1882 const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kStrided, vm); in VSse32()
1886 void Riscv64Assembler::VSse64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSse64() argument
1888 const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kStrided, vm); in VSse64()
1892 void Riscv64Assembler::VLoxei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxei8() argument
1894 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLoxei8()
1895 const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kIndexedOrdered, vm); in VLoxei8()
1899 void Riscv64Assembler::VLoxei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxei16() argument
1901 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLoxei16()
1902 const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kIndexedOrdered, vm); in VLoxei16()
1906 void Riscv64Assembler::VLoxei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxei32() argument
1908 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLoxei32()
1909 const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kIndexedOrdered, vm); in VLoxei32()
1913 void Riscv64Assembler::VLoxei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxei64() argument
1915 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLoxei64()
1916 const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kIndexedOrdered, vm); in VLoxei64()
1920 void Riscv64Assembler::VLuxei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxei8() argument
1922 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLuxei8()
1923 const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kIndexedUnordered, vm); in VLuxei8()
1927 void Riscv64Assembler::VLuxei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxei16() argument
1929 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLuxei16()
1930 const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kIndexedUnordered, vm); in VLuxei16()
1934 void Riscv64Assembler::VLuxei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxei32() argument
1936 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLuxei32()
1937 const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kIndexedUnordered, vm); in VLuxei32()
1941 void Riscv64Assembler::VLuxei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxei64() argument
1943 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLuxei64()
1944 const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kIndexedUnordered, vm); in VLuxei64()
1948 void Riscv64Assembler::VSoxei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxei8() argument
1950 const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kIndexedOrdered, vm); in VSoxei8()
1954 void Riscv64Assembler::VSoxei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxei16() argument
1956 const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kIndexedOrdered, vm); in VSoxei16()
1960 void Riscv64Assembler::VSoxei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxei32() argument
1962 const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kIndexedOrdered, vm); in VSoxei32()
1966 void Riscv64Assembler::VSoxei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxei64() argument
1968 const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kIndexedOrdered, vm); in VSoxei64()
1972 void Riscv64Assembler::VSuxei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSuxei8() argument
1974 const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kIndexedUnordered, vm); in VSuxei8()
1978 void Riscv64Assembler::VSuxei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSuxei16() argument
1980 const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kIndexedUnordered, vm); in VSuxei16()
1984 void Riscv64Assembler::VSuxei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSuxei32() argument
1986 const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kIndexedUnordered, vm); in VSuxei32()
1990 void Riscv64Assembler::VSuxei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSuxei64() argument
1992 const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kIndexedUnordered, vm); in VSuxei64()
1996 void Riscv64Assembler::VLseg2e8(VRegister vd, XRegister rs1, VM vm) { in VLseg2e8() argument
1998 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg2e8()
1999 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kUnitStride, vm); in VLseg2e8()
2003 void Riscv64Assembler::VLseg2e16(VRegister vd, XRegister rs1, VM vm) { in VLseg2e16() argument
2005 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg2e16()
2006 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kUnitStride, vm); in VLseg2e16()
2010 void Riscv64Assembler::VLseg2e32(VRegister vd, XRegister rs1, VM vm) { in VLseg2e32() argument
2012 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg2e32()
2013 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kUnitStride, vm); in VLseg2e32()
2017 void Riscv64Assembler::VLseg2e64(VRegister vd, XRegister rs1, VM vm) { in VLseg2e64() argument
2019 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg2e64()
2020 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kUnitStride, vm); in VLseg2e64()
2024 void Riscv64Assembler::VLseg3e8(VRegister vd, XRegister rs1, VM vm) { in VLseg3e8() argument
2026 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg3e8()
2027 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kUnitStride, vm); in VLseg3e8()
2031 void Riscv64Assembler::VLseg3e16(VRegister vd, XRegister rs1, VM vm) { in VLseg3e16() argument
2033 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg3e16()
2034 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kUnitStride, vm); in VLseg3e16()
2038 void Riscv64Assembler::VLseg3e32(VRegister vd, XRegister rs1, VM vm) { in VLseg3e32() argument
2040 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg3e32()
2041 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kUnitStride, vm); in VLseg3e32()
2045 void Riscv64Assembler::VLseg3e64(VRegister vd, XRegister rs1, VM vm) { in VLseg3e64() argument
2047 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg3e64()
2048 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kUnitStride, vm); in VLseg3e64()
2052 void Riscv64Assembler::VLseg4e8(VRegister vd, XRegister rs1, VM vm) { in VLseg4e8() argument
2054 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg4e8()
2055 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kUnitStride, vm); in VLseg4e8()
2059 void Riscv64Assembler::VLseg4e16(VRegister vd, XRegister rs1, VM vm) { in VLseg4e16() argument
2061 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg4e16()
2062 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kUnitStride, vm); in VLseg4e16()
2066 void Riscv64Assembler::VLseg4e32(VRegister vd, XRegister rs1, VM vm) { in VLseg4e32() argument
2068 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg4e32()
2069 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kUnitStride, vm); in VLseg4e32()
2073 void Riscv64Assembler::VLseg4e64(VRegister vd, XRegister rs1, VM vm) { in VLseg4e64() argument
2075 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg4e64()
2076 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kUnitStride, vm); in VLseg4e64()
2080 void Riscv64Assembler::VLseg5e8(VRegister vd, XRegister rs1, VM vm) { in VLseg5e8() argument
2082 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg5e8()
2083 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kUnitStride, vm); in VLseg5e8()
2087 void Riscv64Assembler::VLseg5e16(VRegister vd, XRegister rs1, VM vm) { in VLseg5e16() argument
2089 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg5e16()
2090 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kUnitStride, vm); in VLseg5e16()
2094 void Riscv64Assembler::VLseg5e32(VRegister vd, XRegister rs1, VM vm) { in VLseg5e32() argument
2096 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg5e32()
2097 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kUnitStride, vm); in VLseg5e32()
2101 void Riscv64Assembler::VLseg5e64(VRegister vd, XRegister rs1, VM vm) { in VLseg5e64() argument
2103 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg5e64()
2104 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kUnitStride, vm); in VLseg5e64()
2108 void Riscv64Assembler::VLseg6e8(VRegister vd, XRegister rs1, VM vm) { in VLseg6e8() argument
2110 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg6e8()
2111 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kUnitStride, vm); in VLseg6e8()
2115 void Riscv64Assembler::VLseg6e16(VRegister vd, XRegister rs1, VM vm) { in VLseg6e16() argument
2117 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg6e16()
2118 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kUnitStride, vm); in VLseg6e16()
2122 void Riscv64Assembler::VLseg6e32(VRegister vd, XRegister rs1, VM vm) { in VLseg6e32() argument
2124 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg6e32()
2125 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kUnitStride, vm); in VLseg6e32()
2129 void Riscv64Assembler::VLseg6e64(VRegister vd, XRegister rs1, VM vm) { in VLseg6e64() argument
2131 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg6e64()
2132 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kUnitStride, vm); in VLseg6e64()
2136 void Riscv64Assembler::VLseg7e8(VRegister vd, XRegister rs1, VM vm) { in VLseg7e8() argument
2138 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg7e8()
2139 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kUnitStride, vm); in VLseg7e8()
2143 void Riscv64Assembler::VLseg7e16(VRegister vd, XRegister rs1, VM vm) { in VLseg7e16() argument
2145 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg7e16()
2146 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kUnitStride, vm); in VLseg7e16()
2150 void Riscv64Assembler::VLseg7e32(VRegister vd, XRegister rs1, VM vm) { in VLseg7e32() argument
2152 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg7e32()
2153 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kUnitStride, vm); in VLseg7e32()
2157 void Riscv64Assembler::VLseg7e64(VRegister vd, XRegister rs1, VM vm) { in VLseg7e64() argument
2159 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg7e64()
2160 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kUnitStride, vm); in VLseg7e64()
2164 void Riscv64Assembler::VLseg8e8(VRegister vd, XRegister rs1, VM vm) { in VLseg8e8() argument
2166 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg8e8()
2167 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kUnitStride, vm); in VLseg8e8()
2171 void Riscv64Assembler::VLseg8e16(VRegister vd, XRegister rs1, VM vm) { in VLseg8e16() argument
2173 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg8e16()
2174 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kUnitStride, vm); in VLseg8e16()
2178 void Riscv64Assembler::VLseg8e32(VRegister vd, XRegister rs1, VM vm) { in VLseg8e32() argument
2180 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg8e32()
2181 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kUnitStride, vm); in VLseg8e32()
2185 void Riscv64Assembler::VLseg8e64(VRegister vd, XRegister rs1, VM vm) { in VLseg8e64() argument
2187 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg8e64()
2188 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kUnitStride, vm); in VLseg8e64()
2192 void Riscv64Assembler::VSseg2e8(VRegister vs3, XRegister rs1, VM vm) { in VSseg2e8() argument
2194 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kUnitStride, vm); in VSseg2e8()
2198 void Riscv64Assembler::VSseg2e16(VRegister vs3, XRegister rs1, VM vm) { in VSseg2e16() argument
2200 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kUnitStride, vm); in VSseg2e16()
2204 void Riscv64Assembler::VSseg2e32(VRegister vs3, XRegister rs1, VM vm) { in VSseg2e32() argument
2206 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kUnitStride, vm); in VSseg2e32()
2210 void Riscv64Assembler::VSseg2e64(VRegister vs3, XRegister rs1, VM vm) { in VSseg2e64() argument
2212 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kUnitStride, vm); in VSseg2e64()
2216 void Riscv64Assembler::VSseg3e8(VRegister vs3, XRegister rs1, VM vm) { in VSseg3e8() argument
2218 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kUnitStride, vm); in VSseg3e8()
2222 void Riscv64Assembler::VSseg3e16(VRegister vs3, XRegister rs1, VM vm) { in VSseg3e16() argument
2224 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kUnitStride, vm); in VSseg3e16()
2228 void Riscv64Assembler::VSseg3e32(VRegister vs3, XRegister rs1, VM vm) { in VSseg3e32() argument
2230 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kUnitStride, vm); in VSseg3e32()
2234 void Riscv64Assembler::VSseg3e64(VRegister vs3, XRegister rs1, VM vm) { in VSseg3e64() argument
2236 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kUnitStride, vm); in VSseg3e64()
2240 void Riscv64Assembler::VSseg4e8(VRegister vs3, XRegister rs1, VM vm) { in VSseg4e8() argument
2242 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kUnitStride, vm); in VSseg4e8()
2246 void Riscv64Assembler::VSseg4e16(VRegister vs3, XRegister rs1, VM vm) { in VSseg4e16() argument
2248 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kUnitStride, vm); in VSseg4e16()
2252 void Riscv64Assembler::VSseg4e32(VRegister vs3, XRegister rs1, VM vm) { in VSseg4e32() argument
2254 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kUnitStride, vm); in VSseg4e32()
2258 void Riscv64Assembler::VSseg4e64(VRegister vs3, XRegister rs1, VM vm) { in VSseg4e64() argument
2260 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kUnitStride, vm); in VSseg4e64()
2264 void Riscv64Assembler::VSseg5e8(VRegister vs3, XRegister rs1, VM vm) { in VSseg5e8() argument
2266 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kUnitStride, vm); in VSseg5e8()
2270 void Riscv64Assembler::VSseg5e16(VRegister vs3, XRegister rs1, VM vm) { in VSseg5e16() argument
2272 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kUnitStride, vm); in VSseg5e16()
2276 void Riscv64Assembler::VSseg5e32(VRegister vs3, XRegister rs1, VM vm) { in VSseg5e32() argument
2278 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kUnitStride, vm); in VSseg5e32()
2282 void Riscv64Assembler::VSseg5e64(VRegister vs3, XRegister rs1, VM vm) { in VSseg5e64() argument
2284 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kUnitStride, vm); in VSseg5e64()
2288 void Riscv64Assembler::VSseg6e8(VRegister vs3, XRegister rs1, VM vm) { in VSseg6e8() argument
2290 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kUnitStride, vm); in VSseg6e8()
2294 void Riscv64Assembler::VSseg6e16(VRegister vs3, XRegister rs1, VM vm) { in VSseg6e16() argument
2296 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kUnitStride, vm); in VSseg6e16()
2300 void Riscv64Assembler::VSseg6e32(VRegister vs3, XRegister rs1, VM vm) { in VSseg6e32() argument
2302 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kUnitStride, vm); in VSseg6e32()
2306 void Riscv64Assembler::VSseg6e64(VRegister vs3, XRegister rs1, VM vm) { in VSseg6e64() argument
2308 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kUnitStride, vm); in VSseg6e64()
2312 void Riscv64Assembler::VSseg7e8(VRegister vs3, XRegister rs1, VM vm) { in VSseg7e8() argument
2314 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kUnitStride, vm); in VSseg7e8()
2318 void Riscv64Assembler::VSseg7e16(VRegister vs3, XRegister rs1, VM vm) { in VSseg7e16() argument
2320 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kUnitStride, vm); in VSseg7e16()
2324 void Riscv64Assembler::VSseg7e32(VRegister vs3, XRegister rs1, VM vm) { in VSseg7e32() argument
2326 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kUnitStride, vm); in VSseg7e32()
2330 void Riscv64Assembler::VSseg7e64(VRegister vs3, XRegister rs1, VM vm) { in VSseg7e64() argument
2332 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kUnitStride, vm); in VSseg7e64()
2336 void Riscv64Assembler::VSseg8e8(VRegister vs3, XRegister rs1, VM vm) { in VSseg8e8() argument
2338 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kUnitStride, vm); in VSseg8e8()
2342 void Riscv64Assembler::VSseg8e16(VRegister vs3, XRegister rs1, VM vm) { in VSseg8e16() argument
2344 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kUnitStride, vm); in VSseg8e16()
2348 void Riscv64Assembler::VSseg8e32(VRegister vs3, XRegister rs1, VM vm) { in VSseg8e32() argument
2350 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kUnitStride, vm); in VSseg8e32()
2354 void Riscv64Assembler::VSseg8e64(VRegister vs3, XRegister rs1, VM vm) { in VSseg8e64() argument
2356 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kUnitStride, vm); in VSseg8e64()
2360 void Riscv64Assembler::VLseg2e8ff(VRegister vd, XRegister rs1, VM vm) { in VLseg2e8ff() argument
2362 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg2e8ff()
2363 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kUnitStride, vm); in VLseg2e8ff()
2367 void Riscv64Assembler::VLseg2e16ff(VRegister vd, XRegister rs1, VM vm) { in VLseg2e16ff() argument
2369 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg2e16ff()
2370 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kUnitStride, vm); in VLseg2e16ff()
2374 void Riscv64Assembler::VLseg2e32ff(VRegister vd, XRegister rs1, VM vm) { in VLseg2e32ff() argument
2376 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg2e32ff()
2377 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kUnitStride, vm); in VLseg2e32ff()
2381 void Riscv64Assembler::VLseg2e64ff(VRegister vd, XRegister rs1, VM vm) { in VLseg2e64ff() argument
2383 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg2e64ff()
2384 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kUnitStride, vm); in VLseg2e64ff()
2388 void Riscv64Assembler::VLseg3e8ff(VRegister vd, XRegister rs1, VM vm) { in VLseg3e8ff() argument
2390 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg3e8ff()
2391 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kUnitStride, vm); in VLseg3e8ff()
2395 void Riscv64Assembler::VLseg3e16ff(VRegister vd, XRegister rs1, VM vm) { in VLseg3e16ff() argument
2397 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg3e16ff()
2398 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kUnitStride, vm); in VLseg3e16ff()
2402 void Riscv64Assembler::VLseg3e32ff(VRegister vd, XRegister rs1, VM vm) { in VLseg3e32ff() argument
2404 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg3e32ff()
2405 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kUnitStride, vm); in VLseg3e32ff()
2409 void Riscv64Assembler::VLseg3e64ff(VRegister vd, XRegister rs1, VM vm) { in VLseg3e64ff() argument
2411 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg3e64ff()
2412 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kUnitStride, vm); in VLseg3e64ff()
2416 void Riscv64Assembler::VLseg4e8ff(VRegister vd, XRegister rs1, VM vm) { in VLseg4e8ff() argument
2418 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg4e8ff()
2419 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kUnitStride, vm); in VLseg4e8ff()
2423 void Riscv64Assembler::VLseg4e16ff(VRegister vd, XRegister rs1, VM vm) { in VLseg4e16ff() argument
2425 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg4e16ff()
2426 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kUnitStride, vm); in VLseg4e16ff()
2430 void Riscv64Assembler::VLseg4e32ff(VRegister vd, XRegister rs1, VM vm) { in VLseg4e32ff() argument
2432 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg4e32ff()
2433 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kUnitStride, vm); in VLseg4e32ff()
2437 void Riscv64Assembler::VLseg4e64ff(VRegister vd, XRegister rs1, VM vm) { in VLseg4e64ff() argument
2439 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg4e64ff()
2440 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kUnitStride, vm); in VLseg4e64ff()
2444 void Riscv64Assembler::VLseg5e8ff(VRegister vd, XRegister rs1, VM vm) { in VLseg5e8ff() argument
2446 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg5e8ff()
2447 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kUnitStride, vm); in VLseg5e8ff()
2451 void Riscv64Assembler::VLseg5e16ff(VRegister vd, XRegister rs1, VM vm) { in VLseg5e16ff() argument
2453 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg5e16ff()
2454 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kUnitStride, vm); in VLseg5e16ff()
2458 void Riscv64Assembler::VLseg5e32ff(VRegister vd, XRegister rs1, VM vm) { in VLseg5e32ff() argument
2460 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg5e32ff()
2461 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kUnitStride, vm); in VLseg5e32ff()
2465 void Riscv64Assembler::VLseg5e64ff(VRegister vd, XRegister rs1, VM vm) { in VLseg5e64ff() argument
2467 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg5e64ff()
2468 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kUnitStride, vm); in VLseg5e64ff()
2472 void Riscv64Assembler::VLseg6e8ff(VRegister vd, XRegister rs1, VM vm) { in VLseg6e8ff() argument
2474 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg6e8ff()
2475 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kUnitStride, vm); in VLseg6e8ff()
2479 void Riscv64Assembler::VLseg6e16ff(VRegister vd, XRegister rs1, VM vm) { in VLseg6e16ff() argument
2481 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg6e16ff()
2482 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kUnitStride, vm); in VLseg6e16ff()
2486 void Riscv64Assembler::VLseg6e32ff(VRegister vd, XRegister rs1, VM vm) { in VLseg6e32ff() argument
2488 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg6e32ff()
2489 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kUnitStride, vm); in VLseg6e32ff()
2493 void Riscv64Assembler::VLseg6e64ff(VRegister vd, XRegister rs1, VM vm) { in VLseg6e64ff() argument
2495 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg6e64ff()
2496 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kUnitStride, vm); in VLseg6e64ff()
2500 void Riscv64Assembler::VLseg7e8ff(VRegister vd, XRegister rs1, VM vm) { in VLseg7e8ff() argument
2502 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg7e8ff()
2503 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kUnitStride, vm); in VLseg7e8ff()
2507 void Riscv64Assembler::VLseg7e16ff(VRegister vd, XRegister rs1, VM vm) { in VLseg7e16ff() argument
2509 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg7e16ff()
2510 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kUnitStride, vm); in VLseg7e16ff()
2514 void Riscv64Assembler::VLseg7e32ff(VRegister vd, XRegister rs1, VM vm) { in VLseg7e32ff() argument
2516 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg7e32ff()
2517 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kUnitStride, vm); in VLseg7e32ff()
2521 void Riscv64Assembler::VLseg7e64ff(VRegister vd, XRegister rs1, VM vm) { in VLseg7e64ff() argument
2523 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg7e64ff()
2524 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kUnitStride, vm); in VLseg7e64ff()
2528 void Riscv64Assembler::VLseg8e8ff(VRegister vd, XRegister rs1, VM vm) { in VLseg8e8ff() argument
2530 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg8e8ff()
2531 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kUnitStride, vm); in VLseg8e8ff()
2535 void Riscv64Assembler::VLseg8e16ff(VRegister vd, XRegister rs1, VM vm) { in VLseg8e16ff() argument
2537 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg8e16ff()
2538 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kUnitStride, vm); in VLseg8e16ff()
2542 void Riscv64Assembler::VLseg8e32ff(VRegister vd, XRegister rs1, VM vm) { in VLseg8e32ff() argument
2544 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg8e32ff()
2545 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kUnitStride, vm); in VLseg8e32ff()
2549 void Riscv64Assembler::VLseg8e64ff(VRegister vd, XRegister rs1, VM vm) { in VLseg8e64ff() argument
2551 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLseg8e64ff()
2552 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kUnitStride, vm); in VLseg8e64ff()
2556 void Riscv64Assembler::VLsseg2e8(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg2e8() argument
2558 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLsseg2e8()
2559 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kStrided, vm); in VLsseg2e8()
2563 void Riscv64Assembler::VLsseg2e16(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg2e16() argument
2565 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLsseg2e16()
2566 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kStrided, vm); in VLsseg2e16()
2570 void Riscv64Assembler::VLsseg2e32(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg2e32() argument
2572 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLsseg2e32()
2573 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kStrided, vm); in VLsseg2e32()
2577 void Riscv64Assembler::VLsseg2e64(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg2e64() argument
2579 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLsseg2e64()
2580 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kStrided, vm); in VLsseg2e64()
2584 void Riscv64Assembler::VLsseg3e8(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg3e8() argument
2586 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLsseg3e8()
2587 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kStrided, vm); in VLsseg3e8()
2591 void Riscv64Assembler::VLsseg3e16(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg3e16() argument
2593 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLsseg3e16()
2594 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kStrided, vm); in VLsseg3e16()
2598 void Riscv64Assembler::VLsseg3e32(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg3e32() argument
2600 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLsseg3e32()
2601 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kStrided, vm); in VLsseg3e32()
2605 void Riscv64Assembler::VLsseg3e64(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg3e64() argument
2607 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLsseg3e64()
2608 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kStrided, vm); in VLsseg3e64()
2612 void Riscv64Assembler::VLsseg4e8(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg4e8() argument
2614 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLsseg4e8()
2615 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kStrided, vm); in VLsseg4e8()
2619 void Riscv64Assembler::VLsseg4e16(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg4e16() argument
2621 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLsseg4e16()
2622 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kStrided, vm); in VLsseg4e16()
2626 void Riscv64Assembler::VLsseg4e32(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg4e32() argument
2628 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLsseg4e32()
2629 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kStrided, vm); in VLsseg4e32()
2633 void Riscv64Assembler::VLsseg4e64(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg4e64() argument
2635 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLsseg4e64()
2636 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kStrided, vm); in VLsseg4e64()
2640 void Riscv64Assembler::VLsseg5e8(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg5e8() argument
2642 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLsseg5e8()
2643 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kStrided, vm); in VLsseg5e8()
2647 void Riscv64Assembler::VLsseg5e16(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg5e16() argument
2649 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLsseg5e16()
2650 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kStrided, vm); in VLsseg5e16()
2654 void Riscv64Assembler::VLsseg5e32(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg5e32() argument
2656 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLsseg5e32()
2657 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kStrided, vm); in VLsseg5e32()
2661 void Riscv64Assembler::VLsseg5e64(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg5e64() argument
2663 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLsseg5e64()
2664 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kStrided, vm); in VLsseg5e64()
2668 void Riscv64Assembler::VLsseg6e8(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg6e8() argument
2670 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLsseg6e8()
2671 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kStrided, vm); in VLsseg6e8()
2675 void Riscv64Assembler::VLsseg6e16(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg6e16() argument
2677 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLsseg6e16()
2678 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kStrided, vm); in VLsseg6e16()
2682 void Riscv64Assembler::VLsseg6e32(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg6e32() argument
2684 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLsseg6e32()
2685 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kStrided, vm); in VLsseg6e32()
2689 void Riscv64Assembler::VLsseg6e64(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg6e64() argument
2691 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLsseg6e64()
2692 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kStrided, vm); in VLsseg6e64()
2696 void Riscv64Assembler::VLsseg7e8(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg7e8() argument
2698 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLsseg7e8()
2699 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kStrided, vm); in VLsseg7e8()
2703 void Riscv64Assembler::VLsseg7e16(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg7e16() argument
2705 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLsseg7e16()
2706 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kStrided, vm); in VLsseg7e16()
2710 void Riscv64Assembler::VLsseg7e32(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg7e32() argument
2712 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLsseg7e32()
2713 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kStrided, vm); in VLsseg7e32()
2717 void Riscv64Assembler::VLsseg7e64(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg7e64() argument
2719 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLsseg7e64()
2720 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kStrided, vm); in VLsseg7e64()
2724 void Riscv64Assembler::VLsseg8e8(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg8e8() argument
2726 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLsseg8e8()
2727 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kStrided, vm); in VLsseg8e8()
2731 void Riscv64Assembler::VLsseg8e16(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg8e16() argument
2733 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLsseg8e16()
2734 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kStrided, vm); in VLsseg8e16()
2738 void Riscv64Assembler::VLsseg8e32(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg8e32() argument
2740 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLsseg8e32()
2741 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kStrided, vm); in VLsseg8e32()
2745 void Riscv64Assembler::VLsseg8e64(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg8e64() argument
2747 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLsseg8e64()
2748 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kStrided, vm); in VLsseg8e64()
2752 void Riscv64Assembler::VSsseg2e8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg2e8() argument
2754 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kStrided, vm); in VSsseg2e8()
2758 void Riscv64Assembler::VSsseg2e16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg2e16() argument
2760 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kStrided, vm); in VSsseg2e16()
2764 void Riscv64Assembler::VSsseg2e32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg2e32() argument
2766 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kStrided, vm); in VSsseg2e32()
2770 void Riscv64Assembler::VSsseg2e64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg2e64() argument
2772 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kStrided, vm); in VSsseg2e64()
2776 void Riscv64Assembler::VSsseg3e8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg3e8() argument
2778 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kStrided, vm); in VSsseg3e8()
2782 void Riscv64Assembler::VSsseg3e16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg3e16() argument
2784 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kStrided, vm); in VSsseg3e16()
2788 void Riscv64Assembler::VSsseg3e32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg3e32() argument
2790 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kStrided, vm); in VSsseg3e32()
2794 void Riscv64Assembler::VSsseg3e64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg3e64() argument
2796 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kStrided, vm); in VSsseg3e64()
2800 void Riscv64Assembler::VSsseg4e8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg4e8() argument
2802 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kStrided, vm); in VSsseg4e8()
2806 void Riscv64Assembler::VSsseg4e16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg4e16() argument
2808 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kStrided, vm); in VSsseg4e16()
2812 void Riscv64Assembler::VSsseg4e32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg4e32() argument
2814 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kStrided, vm); in VSsseg4e32()
2818 void Riscv64Assembler::VSsseg4e64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg4e64() argument
2820 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kStrided, vm); in VSsseg4e64()
2824 void Riscv64Assembler::VSsseg5e8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg5e8() argument
2826 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kStrided, vm); in VSsseg5e8()
2830 void Riscv64Assembler::VSsseg5e16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg5e16() argument
2832 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kStrided, vm); in VSsseg5e16()
2836 void Riscv64Assembler::VSsseg5e32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg5e32() argument
2838 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kStrided, vm); in VSsseg5e32()
2842 void Riscv64Assembler::VSsseg5e64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg5e64() argument
2844 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kStrided, vm); in VSsseg5e64()
2848 void Riscv64Assembler::VSsseg6e8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg6e8() argument
2850 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kStrided, vm); in VSsseg6e8()
2854 void Riscv64Assembler::VSsseg6e16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg6e16() argument
2856 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kStrided, vm); in VSsseg6e16()
2860 void Riscv64Assembler::VSsseg6e32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg6e32() argument
2862 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kStrided, vm); in VSsseg6e32()
2866 void Riscv64Assembler::VSsseg6e64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg6e64() argument
2868 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kStrided, vm); in VSsseg6e64()
2872 void Riscv64Assembler::VSsseg7e8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg7e8() argument
2874 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kStrided, vm); in VSsseg7e8()
2878 void Riscv64Assembler::VSsseg7e16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg7e16() argument
2880 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kStrided, vm); in VSsseg7e16()
2884 void Riscv64Assembler::VSsseg7e32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg7e32() argument
2886 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kStrided, vm); in VSsseg7e32()
2890 void Riscv64Assembler::VSsseg7e64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg7e64() argument
2892 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kStrided, vm); in VSsseg7e64()
2896 void Riscv64Assembler::VSsseg8e8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg8e8() argument
2898 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kStrided, vm); in VSsseg8e8()
2902 void Riscv64Assembler::VSsseg8e16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg8e16() argument
2904 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kStrided, vm); in VSsseg8e16()
2908 void Riscv64Assembler::VSsseg8e32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg8e32() argument
2910 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kStrided, vm); in VSsseg8e32()
2914 void Riscv64Assembler::VSsseg8e64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg8e64() argument
2916 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kStrided, vm); in VSsseg8e64()
2920 void Riscv64Assembler::VLuxseg2ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxseg2ei8() argument
2922 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLuxseg2ei8()
2923 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kIndexedUnordered, vm); in VLuxseg2ei8()
2927 void Riscv64Assembler::VLuxseg2ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxseg2ei16() argument
2929 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLuxseg2ei16()
2930 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kIndexedUnordered, vm); in VLuxseg2ei16()
2934 void Riscv64Assembler::VLuxseg2ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxseg2ei32() argument
2936 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLuxseg2ei32()
2937 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kIndexedUnordered, vm); in VLuxseg2ei32()
2941 void Riscv64Assembler::VLuxseg2ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxseg2ei64() argument
2943 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLuxseg2ei64()
2944 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kIndexedUnordered, vm); in VLuxseg2ei64()
2948 void Riscv64Assembler::VLuxseg3ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxseg3ei8() argument
2950 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLuxseg3ei8()
2951 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kIndexedUnordered, vm); in VLuxseg3ei8()
2955 void Riscv64Assembler::VLuxseg3ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxseg3ei16() argument
2957 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLuxseg3ei16()
2958 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kIndexedUnordered, vm); in VLuxseg3ei16()
2962 void Riscv64Assembler::VLuxseg3ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxseg3ei32() argument
2964 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLuxseg3ei32()
2965 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kIndexedUnordered, vm); in VLuxseg3ei32()
2969 void Riscv64Assembler::VLuxseg3ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxseg3ei64() argument
2971 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLuxseg3ei64()
2972 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kIndexedUnordered, vm); in VLuxseg3ei64()
2976 void Riscv64Assembler::VLuxseg4ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxseg4ei8() argument
2978 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLuxseg4ei8()
2979 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kIndexedUnordered, vm); in VLuxseg4ei8()
2983 void Riscv64Assembler::VLuxseg4ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxseg4ei16() argument
2985 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLuxseg4ei16()
2986 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kIndexedUnordered, vm); in VLuxseg4ei16()
2990 void Riscv64Assembler::VLuxseg4ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxseg4ei32() argument
2992 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLuxseg4ei32()
2993 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kIndexedUnordered, vm); in VLuxseg4ei32()
2997 void Riscv64Assembler::VLuxseg4ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxseg4ei64() argument
2999 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLuxseg4ei64()
3000 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kIndexedUnordered, vm); in VLuxseg4ei64()
3004 void Riscv64Assembler::VLuxseg5ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxseg5ei8() argument
3006 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLuxseg5ei8()
3007 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kIndexedUnordered, vm); in VLuxseg5ei8()
3011 void Riscv64Assembler::VLuxseg5ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxseg5ei16() argument
3013 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLuxseg5ei16()
3014 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kIndexedUnordered, vm); in VLuxseg5ei16()
3018 void Riscv64Assembler::VLuxseg5ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxseg5ei32() argument
3020 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLuxseg5ei32()
3021 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kIndexedUnordered, vm); in VLuxseg5ei32()
3025 void Riscv64Assembler::VLuxseg5ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxseg5ei64() argument
3027 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLuxseg5ei64()
3028 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kIndexedUnordered, vm); in VLuxseg5ei64()
3032 void Riscv64Assembler::VLuxseg6ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxseg6ei8() argument
3034 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLuxseg6ei8()
3035 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kIndexedUnordered, vm); in VLuxseg6ei8()
3039 void Riscv64Assembler::VLuxseg6ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxseg6ei16() argument
3041 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLuxseg6ei16()
3042 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kIndexedUnordered, vm); in VLuxseg6ei16()
3046 void Riscv64Assembler::VLuxseg6ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxseg6ei32() argument
3048 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLuxseg6ei32()
3049 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kIndexedUnordered, vm); in VLuxseg6ei32()
3053 void Riscv64Assembler::VLuxseg6ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxseg6ei64() argument
3055 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLuxseg6ei64()
3056 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kIndexedUnordered, vm); in VLuxseg6ei64()
3060 void Riscv64Assembler::VLuxseg7ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxseg7ei8() argument
3062 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLuxseg7ei8()
3063 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kIndexedUnordered, vm); in VLuxseg7ei8()
3067 void Riscv64Assembler::VLuxseg7ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxseg7ei16() argument
3069 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLuxseg7ei16()
3070 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kIndexedUnordered, vm); in VLuxseg7ei16()
3074 void Riscv64Assembler::VLuxseg7ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxseg7ei32() argument
3076 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLuxseg7ei32()
3077 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kIndexedUnordered, vm); in VLuxseg7ei32()
3081 void Riscv64Assembler::VLuxseg7ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxseg7ei64() argument
3083 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLuxseg7ei64()
3084 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kIndexedUnordered, vm); in VLuxseg7ei64()
3088 void Riscv64Assembler::VLuxseg8ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxseg8ei8() argument
3090 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLuxseg8ei8()
3091 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kIndexedUnordered, vm); in VLuxseg8ei8()
3095 void Riscv64Assembler::VLuxseg8ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxseg8ei16() argument
3097 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLuxseg8ei16()
3098 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kIndexedUnordered, vm); in VLuxseg8ei16()
3102 void Riscv64Assembler::VLuxseg8ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxseg8ei32() argument
3104 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLuxseg8ei32()
3105 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kIndexedUnordered, vm); in VLuxseg8ei32()
3109 void Riscv64Assembler::VLuxseg8ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxseg8ei64() argument
3111 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLuxseg8ei64()
3112 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kIndexedUnordered, vm); in VLuxseg8ei64()
3116 void Riscv64Assembler::VSuxseg2ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSuxseg2ei8() argument
3118 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kIndexedUnordered, vm); in VSuxseg2ei8()
3122 void Riscv64Assembler::VSuxseg2ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSuxseg2ei16() argument
3124 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kIndexedUnordered, vm); in VSuxseg2ei16()
3128 void Riscv64Assembler::VSuxseg2ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSuxseg2ei32() argument
3130 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kIndexedUnordered, vm); in VSuxseg2ei32()
3134 void Riscv64Assembler::VSuxseg2ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSuxseg2ei64() argument
3136 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kIndexedUnordered, vm); in VSuxseg2ei64()
3140 void Riscv64Assembler::VSuxseg3ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSuxseg3ei8() argument
3142 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kIndexedUnordered, vm); in VSuxseg3ei8()
3146 void Riscv64Assembler::VSuxseg3ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSuxseg3ei16() argument
3148 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kIndexedUnordered, vm); in VSuxseg3ei16()
3152 void Riscv64Assembler::VSuxseg3ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSuxseg3ei32() argument
3154 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kIndexedUnordered, vm); in VSuxseg3ei32()
3158 void Riscv64Assembler::VSuxseg3ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSuxseg3ei64() argument
3160 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kIndexedUnordered, vm); in VSuxseg3ei64()
3164 void Riscv64Assembler::VSuxseg4ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSuxseg4ei8() argument
3166 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kIndexedUnordered, vm); in VSuxseg4ei8()
3170 void Riscv64Assembler::VSuxseg4ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSuxseg4ei16() argument
3172 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kIndexedUnordered, vm); in VSuxseg4ei16()
3176 void Riscv64Assembler::VSuxseg4ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSuxseg4ei32() argument
3178 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kIndexedUnordered, vm); in VSuxseg4ei32()
3182 void Riscv64Assembler::VSuxseg4ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSuxseg4ei64() argument
3184 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kIndexedUnordered, vm); in VSuxseg4ei64()
3188 void Riscv64Assembler::VSuxseg5ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSuxseg5ei8() argument
3190 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kIndexedUnordered, vm); in VSuxseg5ei8()
3194 void Riscv64Assembler::VSuxseg5ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSuxseg5ei16() argument
3196 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kIndexedUnordered, vm); in VSuxseg5ei16()
3200 void Riscv64Assembler::VSuxseg5ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSuxseg5ei32() argument
3202 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kIndexedUnordered, vm); in VSuxseg5ei32()
3206 void Riscv64Assembler::VSuxseg5ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSuxseg5ei64() argument
3208 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kIndexedUnordered, vm); in VSuxseg5ei64()
3212 void Riscv64Assembler::VSuxseg6ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSuxseg6ei8() argument
3214 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kIndexedUnordered, vm); in VSuxseg6ei8()
3218 void Riscv64Assembler::VSuxseg6ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSuxseg6ei16() argument
3220 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kIndexedUnordered, vm); in VSuxseg6ei16()
3224 void Riscv64Assembler::VSuxseg6ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSuxseg6ei32() argument
3226 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kIndexedUnordered, vm); in VSuxseg6ei32()
3230 void Riscv64Assembler::VSuxseg6ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSuxseg6ei64() argument
3232 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kIndexedUnordered, vm); in VSuxseg6ei64()
3236 void Riscv64Assembler::VSuxseg7ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSuxseg7ei8() argument
3238 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kIndexedUnordered, vm); in VSuxseg7ei8()
3242 void Riscv64Assembler::VSuxseg7ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSuxseg7ei16() argument
3244 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kIndexedUnordered, vm); in VSuxseg7ei16()
3248 void Riscv64Assembler::VSuxseg7ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSuxseg7ei32() argument
3250 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kIndexedUnordered, vm); in VSuxseg7ei32()
3254 void Riscv64Assembler::VSuxseg7ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSuxseg7ei64() argument
3256 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kIndexedUnordered, vm); in VSuxseg7ei64()
3260 void Riscv64Assembler::VSuxseg8ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSuxseg8ei8() argument
3262 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kIndexedUnordered, vm); in VSuxseg8ei8()
3266 void Riscv64Assembler::VSuxseg8ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSuxseg8ei16() argument
3268 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kIndexedUnordered, vm); in VSuxseg8ei16()
3272 void Riscv64Assembler::VSuxseg8ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSuxseg8ei32() argument
3274 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kIndexedUnordered, vm); in VSuxseg8ei32()
3278 void Riscv64Assembler::VSuxseg8ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSuxseg8ei64() argument
3280 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kIndexedUnordered, vm); in VSuxseg8ei64()
3284 void Riscv64Assembler::VLoxseg2ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxseg2ei8() argument
3286 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLoxseg2ei8()
3287 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kIndexedOrdered, vm); in VLoxseg2ei8()
3291 void Riscv64Assembler::VLoxseg2ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxseg2ei16() argument
3293 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLoxseg2ei16()
3294 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kIndexedOrdered, vm); in VLoxseg2ei16()
3298 void Riscv64Assembler::VLoxseg2ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxseg2ei32() argument
3300 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLoxseg2ei32()
3301 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kIndexedOrdered, vm); in VLoxseg2ei32()
3305 void Riscv64Assembler::VLoxseg2ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxseg2ei64() argument
3307 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLoxseg2ei64()
3308 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kIndexedOrdered, vm); in VLoxseg2ei64()
3312 void Riscv64Assembler::VLoxseg3ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxseg3ei8() argument
3314 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLoxseg3ei8()
3315 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kIndexedOrdered, vm); in VLoxseg3ei8()
3319 void Riscv64Assembler::VLoxseg3ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxseg3ei16() argument
3321 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLoxseg3ei16()
3322 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kIndexedOrdered, vm); in VLoxseg3ei16()
3326 void Riscv64Assembler::VLoxseg3ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxseg3ei32() argument
3328 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLoxseg3ei32()
3329 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kIndexedOrdered, vm); in VLoxseg3ei32()
3333 void Riscv64Assembler::VLoxseg3ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxseg3ei64() argument
3335 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLoxseg3ei64()
3336 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kIndexedOrdered, vm); in VLoxseg3ei64()
3340 void Riscv64Assembler::VLoxseg4ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxseg4ei8() argument
3342 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLoxseg4ei8()
3343 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kIndexedOrdered, vm); in VLoxseg4ei8()
3347 void Riscv64Assembler::VLoxseg4ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxseg4ei16() argument
3349 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLoxseg4ei16()
3350 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kIndexedOrdered, vm); in VLoxseg4ei16()
3354 void Riscv64Assembler::VLoxseg4ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxseg4ei32() argument
3356 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLoxseg4ei32()
3357 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kIndexedOrdered, vm); in VLoxseg4ei32()
3361 void Riscv64Assembler::VLoxseg4ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxseg4ei64() argument
3363 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLoxseg4ei64()
3364 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kIndexedOrdered, vm); in VLoxseg4ei64()
3368 void Riscv64Assembler::VLoxseg5ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxseg5ei8() argument
3370 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLoxseg5ei8()
3371 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kIndexedOrdered, vm); in VLoxseg5ei8()
3375 void Riscv64Assembler::VLoxseg5ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxseg5ei16() argument
3377 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLoxseg5ei16()
3378 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kIndexedOrdered, vm); in VLoxseg5ei16()
3382 void Riscv64Assembler::VLoxseg5ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxseg5ei32() argument
3384 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLoxseg5ei32()
3385 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kIndexedOrdered, vm); in VLoxseg5ei32()
3389 void Riscv64Assembler::VLoxseg5ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxseg5ei64() argument
3391 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLoxseg5ei64()
3392 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kIndexedOrdered, vm); in VLoxseg5ei64()
3396 void Riscv64Assembler::VLoxseg6ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxseg6ei8() argument
3398 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLoxseg6ei8()
3399 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kIndexedOrdered, vm); in VLoxseg6ei8()
3403 void Riscv64Assembler::VLoxseg6ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxseg6ei16() argument
3405 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLoxseg6ei16()
3406 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kIndexedOrdered, vm); in VLoxseg6ei16()
3410 void Riscv64Assembler::VLoxseg6ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxseg6ei32() argument
3412 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLoxseg6ei32()
3413 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kIndexedOrdered, vm); in VLoxseg6ei32()
3417 void Riscv64Assembler::VLoxseg6ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxseg6ei64() argument
3419 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLoxseg6ei64()
3420 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kIndexedOrdered, vm); in VLoxseg6ei64()
3424 void Riscv64Assembler::VLoxseg7ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxseg7ei8() argument
3426 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLoxseg7ei8()
3427 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kIndexedOrdered, vm); in VLoxseg7ei8()
3431 void Riscv64Assembler::VLoxseg7ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxseg7ei16() argument
3433 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLoxseg7ei16()
3434 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kIndexedOrdered, vm); in VLoxseg7ei16()
3438 void Riscv64Assembler::VLoxseg7ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxseg7ei32() argument
3440 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLoxseg7ei32()
3441 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kIndexedOrdered, vm); in VLoxseg7ei32()
3445 void Riscv64Assembler::VLoxseg7ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxseg7ei64() argument
3447 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLoxseg7ei64()
3448 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kIndexedOrdered, vm); in VLoxseg7ei64()
3452 void Riscv64Assembler::VLoxseg8ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxseg8ei8() argument
3454 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLoxseg8ei8()
3455 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kIndexedOrdered, vm); in VLoxseg8ei8()
3459 void Riscv64Assembler::VLoxseg8ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxseg8ei16() argument
3461 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLoxseg8ei16()
3462 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kIndexedOrdered, vm); in VLoxseg8ei16()
3466 void Riscv64Assembler::VLoxseg8ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxseg8ei32() argument
3468 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLoxseg8ei32()
3469 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kIndexedOrdered, vm); in VLoxseg8ei32()
3473 void Riscv64Assembler::VLoxseg8ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxseg8ei64() argument
3475 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VLoxseg8ei64()
3476 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kIndexedOrdered, vm); in VLoxseg8ei64()
3480 void Riscv64Assembler::VSoxseg2ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxseg2ei8() argument
3482 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kIndexedOrdered, vm); in VSoxseg2ei8()
3486 void Riscv64Assembler::VSoxseg2ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxseg2ei16() argument
3488 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kIndexedOrdered, vm); in VSoxseg2ei16()
3492 void Riscv64Assembler::VSoxseg2ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxseg2ei32() argument
3494 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kIndexedOrdered, vm); in VSoxseg2ei32()
3498 void Riscv64Assembler::VSoxseg2ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxseg2ei64() argument
3500 const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kIndexedOrdered, vm); in VSoxseg2ei64()
3504 void Riscv64Assembler::VSoxseg3ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxseg3ei8() argument
3506 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kIndexedOrdered, vm); in VSoxseg3ei8()
3510 void Riscv64Assembler::VSoxseg3ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxseg3ei16() argument
3512 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kIndexedOrdered, vm); in VSoxseg3ei16()
3516 void Riscv64Assembler::VSoxseg3ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxseg3ei32() argument
3518 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kIndexedOrdered, vm); in VSoxseg3ei32()
3522 void Riscv64Assembler::VSoxseg3ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxseg3ei64() argument
3524 const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kIndexedOrdered, vm); in VSoxseg3ei64()
3528 void Riscv64Assembler::VSoxseg4ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxseg4ei8() argument
3530 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kIndexedOrdered, vm); in VSoxseg4ei8()
3534 void Riscv64Assembler::VSoxseg4ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxseg4ei16() argument
3536 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kIndexedOrdered, vm); in VSoxseg4ei16()
3540 void Riscv64Assembler::VSoxseg4ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxseg4ei32() argument
3542 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kIndexedOrdered, vm); in VSoxseg4ei32()
3546 void Riscv64Assembler::VSoxseg4ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxseg4ei64() argument
3548 const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kIndexedOrdered, vm); in VSoxseg4ei64()
3552 void Riscv64Assembler::VSoxseg5ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxseg5ei8() argument
3554 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kIndexedOrdered, vm); in VSoxseg5ei8()
3558 void Riscv64Assembler::VSoxseg5ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxseg5ei16() argument
3560 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kIndexedOrdered, vm); in VSoxseg5ei16()
3564 void Riscv64Assembler::VSoxseg5ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxseg5ei32() argument
3566 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kIndexedOrdered, vm); in VSoxseg5ei32()
3570 void Riscv64Assembler::VSoxseg5ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxseg5ei64() argument
3572 const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kIndexedOrdered, vm); in VSoxseg5ei64()
3576 void Riscv64Assembler::VSoxseg6ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxseg6ei8() argument
3578 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kIndexedOrdered, vm); in VSoxseg6ei8()
3582 void Riscv64Assembler::VSoxseg6ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxseg6ei16() argument
3584 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kIndexedOrdered, vm); in VSoxseg6ei16()
3588 void Riscv64Assembler::VSoxseg6ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxseg6ei32() argument
3590 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kIndexedOrdered, vm); in VSoxseg6ei32()
3594 void Riscv64Assembler::VSoxseg6ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxseg6ei64() argument
3596 const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kIndexedOrdered, vm); in VSoxseg6ei64()
3600 void Riscv64Assembler::VSoxseg7ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxseg7ei8() argument
3602 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kIndexedOrdered, vm); in VSoxseg7ei8()
3606 void Riscv64Assembler::VSoxseg7ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxseg7ei16() argument
3608 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kIndexedOrdered, vm); in VSoxseg7ei16()
3612 void Riscv64Assembler::VSoxseg7ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxseg7ei32() argument
3614 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kIndexedOrdered, vm); in VSoxseg7ei32()
3618 void Riscv64Assembler::VSoxseg7ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxseg7ei64() argument
3620 const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kIndexedOrdered, vm); in VSoxseg7ei64()
3624 void Riscv64Assembler::VSoxseg8ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxseg8ei8() argument
3626 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kIndexedOrdered, vm); in VSoxseg8ei8()
3630 void Riscv64Assembler::VSoxseg8ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxseg8ei16() argument
3632 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kIndexedOrdered, vm); in VSoxseg8ei16()
3636 void Riscv64Assembler::VSoxseg8ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxseg8ei32() argument
3638 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kIndexedOrdered, vm); in VSoxseg8ei32()
3642 void Riscv64Assembler::VSoxseg8ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxseg8ei64() argument
3644 const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kIndexedOrdered, vm); in VSoxseg8ei64()
3792 void Riscv64Assembler::VAdd_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VAdd_vv() argument
3794 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VAdd_vv()
3795 const uint32_t funct7 = EncodeRVVF7(0b000000, vm); in VAdd_vv()
3799 void Riscv64Assembler::VAdd_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VAdd_vx() argument
3801 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VAdd_vx()
3802 const uint32_t funct7 = EncodeRVVF7(0b000000, vm); in VAdd_vx()
3806 void Riscv64Assembler::VAdd_vi(VRegister vd, VRegister vs2, int32_t imm5, VM vm) { in VAdd_vi() argument
3808 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VAdd_vi()
3809 const uint32_t funct7 = EncodeRVVF7(0b000000, vm); in VAdd_vi()
3813 void Riscv64Assembler::VSub_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VSub_vv() argument
3815 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSub_vv()
3816 const uint32_t funct7 = EncodeRVVF7(0b000010, vm); in VSub_vv()
3820 void Riscv64Assembler::VSub_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VSub_vx() argument
3822 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSub_vx()
3823 const uint32_t funct7 = EncodeRVVF7(0b000010, vm); in VSub_vx()
3827 void Riscv64Assembler::VRsub_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VRsub_vx() argument
3829 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VRsub_vx()
3830 const uint32_t funct7 = EncodeRVVF7(0b000011, vm); in VRsub_vx()
3834 void Riscv64Assembler::VRsub_vi(VRegister vd, VRegister vs2, int32_t imm5, VM vm) { in VRsub_vi() argument
3836 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VRsub_vi()
3837 const uint32_t funct7 = EncodeRVVF7(0b000011, vm); in VRsub_vi()
3843 void Riscv64Assembler::VMinu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VMinu_vv() argument
3845 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMinu_vv()
3846 const uint32_t funct7 = EncodeRVVF7(0b000100, vm); in VMinu_vv()
3850 void Riscv64Assembler::VMinu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VMinu_vx() argument
3852 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMinu_vx()
3853 const uint32_t funct7 = EncodeRVVF7(0b000100, vm); in VMinu_vx()
3857 void Riscv64Assembler::VMin_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VMin_vv() argument
3859 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMin_vv()
3860 const uint32_t funct7 = EncodeRVVF7(0b000101, vm); in VMin_vv()
3864 void Riscv64Assembler::VMin_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VMin_vx() argument
3866 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMin_vx()
3867 const uint32_t funct7 = EncodeRVVF7(0b000101, vm); in VMin_vx()
3871 void Riscv64Assembler::VMaxu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VMaxu_vv() argument
3873 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMaxu_vv()
3874 const uint32_t funct7 = EncodeRVVF7(0b000110, vm); in VMaxu_vv()
3878 void Riscv64Assembler::VMaxu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VMaxu_vx() argument
3880 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMaxu_vx()
3881 const uint32_t funct7 = EncodeRVVF7(0b000110, vm); in VMaxu_vx()
3885 void Riscv64Assembler::VMax_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VMax_vv() argument
3887 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMax_vv()
3888 const uint32_t funct7 = EncodeRVVF7(0b000111, vm); in VMax_vv()
3892 void Riscv64Assembler::VMax_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VMax_vx() argument
3894 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMax_vx()
3895 const uint32_t funct7 = EncodeRVVF7(0b000111, vm); in VMax_vx()
3899 void Riscv64Assembler::VAnd_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VAnd_vv() argument
3901 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VAnd_vv()
3902 const uint32_t funct7 = EncodeRVVF7(0b001001, vm); in VAnd_vv()
3906 void Riscv64Assembler::VAnd_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VAnd_vx() argument
3908 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VAnd_vx()
3909 const uint32_t funct7 = EncodeRVVF7(0b001001, vm); in VAnd_vx()
3913 void Riscv64Assembler::VAnd_vi(VRegister vd, VRegister vs2, int32_t imm5, VM vm) { in VAnd_vi() argument
3915 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VAnd_vi()
3916 const uint32_t funct7 = EncodeRVVF7(0b001001, vm); in VAnd_vi()
3920 void Riscv64Assembler::VOr_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VOr_vv() argument
3922 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VOr_vv()
3923 const uint32_t funct7 = EncodeRVVF7(0b001010, vm); in VOr_vv()
3927 void Riscv64Assembler::VOr_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VOr_vx() argument
3929 const uint32_t funct7 = EncodeRVVF7(0b001010, vm); in VOr_vx()
3933 void Riscv64Assembler::VOr_vi(VRegister vd, VRegister vs2, int32_t imm5, VM vm) { in VOr_vi() argument
3935 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VOr_vi()
3936 const uint32_t funct7 = EncodeRVVF7(0b001010, vm); in VOr_vi()
3940 void Riscv64Assembler::VXor_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VXor_vv() argument
3942 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VXor_vv()
3943 const uint32_t funct7 = EncodeRVVF7(0b001011, vm); in VXor_vv()
3947 void Riscv64Assembler::VXor_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VXor_vx() argument
3949 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VXor_vx()
3950 const uint32_t funct7 = EncodeRVVF7(0b001011, vm); in VXor_vx()
3954 void Riscv64Assembler::VXor_vi(VRegister vd, VRegister vs2, int32_t imm5, VM vm) { in VXor_vi() argument
3956 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VXor_vi()
3957 const uint32_t funct7 = EncodeRVVF7(0b001011, vm); in VXor_vi()
3961 void Riscv64Assembler::VNot_v(VRegister vd, VRegister vs2, VM vm) { VXor_vi(vd, vs2, -1, vm); } in VNot_v() argument
3963 void Riscv64Assembler::VRgather_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VRgather_vv() argument
3965 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VRgather_vv()
3968 const uint32_t funct7 = EncodeRVVF7(0b001100, vm); in VRgather_vv()
3972 void Riscv64Assembler::VRgather_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VRgather_vx() argument
3974 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VRgather_vx()
3976 const uint32_t funct7 = EncodeRVVF7(0b001100, vm); in VRgather_vx()
3980 void Riscv64Assembler::VRgather_vi(VRegister vd, VRegister vs2, uint32_t uimm5, VM vm) { in VRgather_vi() argument
3982 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VRgather_vi()
3984 const uint32_t funct7 = EncodeRVVF7(0b001100, vm); in VRgather_vi()
3988 void Riscv64Assembler::VSlideup_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VSlideup_vx() argument
3990 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSlideup_vx()
3992 const uint32_t funct7 = EncodeRVVF7(0b001110, vm); in VSlideup_vx()
3996 void Riscv64Assembler::VSlideup_vi(VRegister vd, VRegister vs2, uint32_t uimm5, VM vm) { in VSlideup_vi() argument
3998 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSlideup_vi()
4000 const uint32_t funct7 = EncodeRVVF7(0b001110, vm); in VSlideup_vi()
4004 void Riscv64Assembler::VRgatherei16_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VRgatherei16_vv() argument
4006 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VRgatherei16_vv()
4009 const uint32_t funct7 = EncodeRVVF7(0b001110, vm); in VRgatherei16_vv()
4013 void Riscv64Assembler::VSlidedown_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VSlidedown_vx() argument
4015 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSlidedown_vx()
4017 const uint32_t funct7 = EncodeRVVF7(0b001111, vm); in VSlidedown_vx()
4021 void Riscv64Assembler::VSlidedown_vi(VRegister vd, VRegister vs2, uint32_t uimm5, VM vm) { in VSlidedown_vi() argument
4023 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSlidedown_vi()
4024 const uint32_t funct7 = EncodeRVVF7(0b001111, vm); in VSlidedown_vi()
4162 void Riscv64Assembler::VMseq_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VMseq_vv() argument
4164 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMseq_vv()
4165 const uint32_t funct7 = EncodeRVVF7(0b011000, vm); in VMseq_vv()
4169 void Riscv64Assembler::VMseq_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VMseq_vx() argument
4171 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMseq_vx()
4172 const uint32_t funct7 = EncodeRVVF7(0b011000, vm); in VMseq_vx()
4176 void Riscv64Assembler::VMseq_vi(VRegister vd, VRegister vs2, int32_t imm5, VM vm) { in VMseq_vi() argument
4178 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMseq_vi()
4179 const uint32_t funct7 = EncodeRVVF7(0b011000, vm); in VMseq_vi()
4183 void Riscv64Assembler::VMsne_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VMsne_vv() argument
4185 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMsne_vv()
4186 const uint32_t funct7 = EncodeRVVF7(0b011001, vm); in VMsne_vv()
4190 void Riscv64Assembler::VMsne_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VMsne_vx() argument
4192 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMsne_vx()
4193 const uint32_t funct7 = EncodeRVVF7(0b011001, vm); in VMsne_vx()
4197 void Riscv64Assembler::VMsne_vi(VRegister vd, VRegister vs2, int32_t imm5, VM vm) { in VMsne_vi() argument
4199 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMsne_vi()
4200 const uint32_t funct7 = EncodeRVVF7(0b011001, vm); in VMsne_vi()
4204 void Riscv64Assembler::VMsltu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VMsltu_vv() argument
4206 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMsltu_vv()
4207 const uint32_t funct7 = EncodeRVVF7(0b011010, vm); in VMsltu_vv()
4211 void Riscv64Assembler::VMsltu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VMsltu_vx() argument
4213 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMsltu_vx()
4214 const uint32_t funct7 = EncodeRVVF7(0b011010, vm); in VMsltu_vx()
4218 void Riscv64Assembler::VMsgtu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VMsgtu_vv() argument
4220 VMsltu_vv(vd, vs1, vs2, vm); in VMsgtu_vv()
4223 void Riscv64Assembler::VMslt_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VMslt_vv() argument
4225 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMslt_vv()
4226 const uint32_t funct7 = EncodeRVVF7(0b011011, vm); in VMslt_vv()
4230 void Riscv64Assembler::VMslt_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VMslt_vx() argument
4232 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMslt_vx()
4233 const uint32_t funct7 = EncodeRVVF7(0b011011, vm); in VMslt_vx()
4237 void Riscv64Assembler::VMsgt_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VMsgt_vv() argument
4238 VMslt_vv(vd, vs1, vs2, vm); in VMsgt_vv()
4241 void Riscv64Assembler::VMsleu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VMsleu_vv() argument
4243 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMsleu_vv()
4244 const uint32_t funct7 = EncodeRVVF7(0b011100, vm); in VMsleu_vv()
4248 void Riscv64Assembler::VMsleu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VMsleu_vx() argument
4250 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMsleu_vx()
4251 const uint32_t funct7 = EncodeRVVF7(0b011100, vm); in VMsleu_vx()
4255 void Riscv64Assembler::VMsleu_vi(VRegister vd, VRegister vs2, int32_t imm5, VM vm) { in VMsleu_vi() argument
4257 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMsleu_vi()
4258 const uint32_t funct7 = EncodeRVVF7(0b011100, vm); in VMsleu_vi()
4262 void Riscv64Assembler::VMsgeu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VMsgeu_vv() argument
4263 VMsleu_vv(vd, vs1, vs2, vm); in VMsgeu_vv()
4266 void Riscv64Assembler::VMsltu_vi(VRegister vd, VRegister vs2, int32_t aimm5, VM vm) { in VMsltu_vi() argument
4268 VMsleu_vi(vd, vs2, aimm5 - 1, vm); in VMsltu_vi()
4271 void Riscv64Assembler::VMsle_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VMsle_vv() argument
4273 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMsle_vv()
4274 const uint32_t funct7 = EncodeRVVF7(0b011101, vm); in VMsle_vv()
4278 void Riscv64Assembler::VMsle_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VMsle_vx() argument
4280 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMsle_vx()
4281 const uint32_t funct7 = EncodeRVVF7(0b011101, vm); in VMsle_vx()
4285 void Riscv64Assembler::VMsle_vi(VRegister vd, VRegister vs2, int32_t imm5, VM vm) { in VMsle_vi() argument
4287 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMsle_vi()
4288 const uint32_t funct7 = EncodeRVVF7(0b011101, vm); in VMsle_vi()
4292 void Riscv64Assembler::VMsge_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VMsge_vv() argument
4293 VMsle_vv(vd, vs1, vs2, vm); in VMsge_vv()
4296 void Riscv64Assembler::VMslt_vi(VRegister vd, VRegister vs2, int32_t aimm5, VM vm) { in VMslt_vi() argument
4297 VMsle_vi(vd, vs2, aimm5 - 1, vm); in VMslt_vi()
4300 void Riscv64Assembler::VMsgtu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VMsgtu_vx() argument
4302 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMsgtu_vx()
4303 const uint32_t funct7 = EncodeRVVF7(0b011110, vm); in VMsgtu_vx()
4307 void Riscv64Assembler::VMsgtu_vi(VRegister vd, VRegister vs2, int32_t imm5, VM vm) { in VMsgtu_vi() argument
4309 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMsgtu_vi()
4310 const uint32_t funct7 = EncodeRVVF7(0b011110, vm); in VMsgtu_vi()
4314 void Riscv64Assembler::VMsgeu_vi(VRegister vd, VRegister vs2, int32_t aimm5, VM vm) { in VMsgeu_vi() argument
4317 VMsgtu_vi(vd, vs2, aimm5 - 1, vm); in VMsgeu_vi()
4320 void Riscv64Assembler::VMsgt_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VMsgt_vx() argument
4322 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMsgt_vx()
4323 const uint32_t funct7 = EncodeRVVF7(0b011111, vm); in VMsgt_vx()
4327 void Riscv64Assembler::VMsgt_vi(VRegister vd, VRegister vs2, int32_t imm5, VM vm) { in VMsgt_vi() argument
4329 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMsgt_vi()
4330 const uint32_t funct7 = EncodeRVVF7(0b011111, vm); in VMsgt_vi()
4334 void Riscv64Assembler::VMsge_vi(VRegister vd, VRegister vs2, int32_t aimm5, VM vm) { in VMsge_vi() argument
4335 VMsgt_vi(vd, vs2, aimm5 - 1, vm); in VMsge_vi()
4338 void Riscv64Assembler::VSaddu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VSaddu_vv() argument
4340 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSaddu_vv()
4341 const uint32_t funct7 = EncodeRVVF7(0b100000, vm); in VSaddu_vv()
4345 void Riscv64Assembler::VSaddu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VSaddu_vx() argument
4347 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSaddu_vx()
4348 const uint32_t funct7 = EncodeRVVF7(0b100000, vm); in VSaddu_vx()
4352 void Riscv64Assembler::VSaddu_vi(VRegister vd, VRegister vs2, int32_t imm5, VM vm) { in VSaddu_vi() argument
4354 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSaddu_vi()
4355 const uint32_t funct7 = EncodeRVVF7(0b100000, vm); in VSaddu_vi()
4359 void Riscv64Assembler::VSadd_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VSadd_vv() argument
4361 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSadd_vv()
4362 const uint32_t funct7 = EncodeRVVF7(0b100001, vm); in VSadd_vv()
4366 void Riscv64Assembler::VSadd_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VSadd_vx() argument
4368 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSadd_vx()
4369 const uint32_t funct7 = EncodeRVVF7(0b100001, vm); in VSadd_vx()
4373 void Riscv64Assembler::VSadd_vi(VRegister vd, VRegister vs2, int32_t imm5, VM vm) { in VSadd_vi() argument
4375 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSadd_vi()
4376 const uint32_t funct7 = EncodeRVVF7(0b100001, vm); in VSadd_vi()
4380 void Riscv64Assembler::VSsubu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VSsubu_vv() argument
4382 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSsubu_vv()
4383 const uint32_t funct7 = EncodeRVVF7(0b100010, vm); in VSsubu_vv()
4387 void Riscv64Assembler::VSsubu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VSsubu_vx() argument
4389 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSsubu_vx()
4390 const uint32_t funct7 = EncodeRVVF7(0b100010, vm); in VSsubu_vx()
4394 void Riscv64Assembler::VSsub_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VSsub_vv() argument
4396 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSsub_vv()
4397 const uint32_t funct7 = EncodeRVVF7(0b100011, vm); in VSsub_vv()
4401 void Riscv64Assembler::VSsub_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VSsub_vx() argument
4403 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSsub_vx()
4404 const uint32_t funct7 = EncodeRVVF7(0b100011, vm); in VSsub_vx()
4408 void Riscv64Assembler::VSll_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VSll_vv() argument
4410 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSll_vv()
4411 const uint32_t funct7 = EncodeRVVF7(0b100101, vm); in VSll_vv()
4415 void Riscv64Assembler::VSll_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VSll_vx() argument
4417 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSll_vx()
4418 const uint32_t funct7 = EncodeRVVF7(0b100101, vm); in VSll_vx()
4422 void Riscv64Assembler::VSll_vi(VRegister vd, VRegister vs2, uint32_t uimm5, VM vm) { in VSll_vi() argument
4424 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSll_vi()
4425 const uint32_t funct7 = EncodeRVVF7(0b100101, vm); in VSll_vi()
4429 void Riscv64Assembler::VSmul_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VSmul_vv() argument
4431 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSmul_vv()
4432 const uint32_t funct7 = EncodeRVVF7(0b100111, vm); in VSmul_vv()
4436 void Riscv64Assembler::VSmul_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VSmul_vx() argument
4438 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSmul_vx()
4439 const uint32_t funct7 = EncodeRVVF7(0b100111, vm); in VSmul_vx()
4477 void Riscv64Assembler::VSrl_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VSrl_vv() argument
4479 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSrl_vv()
4480 const uint32_t funct7 = EncodeRVVF7(0b101000, vm); in VSrl_vv()
4484 void Riscv64Assembler::VSrl_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VSrl_vx() argument
4486 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSrl_vx()
4487 const uint32_t funct7 = EncodeRVVF7(0b101000, vm); in VSrl_vx()
4491 void Riscv64Assembler::VSrl_vi(VRegister vd, VRegister vs2, uint32_t uimm5, VM vm) { in VSrl_vi() argument
4493 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSrl_vi()
4494 const uint32_t funct7 = EncodeRVVF7(0b101000, vm); in VSrl_vi()
4498 void Riscv64Assembler::VSra_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VSra_vv() argument
4500 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSra_vv()
4501 const uint32_t funct7 = EncodeRVVF7(0b101001, vm); in VSra_vv()
4505 void Riscv64Assembler::VSra_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VSra_vx() argument
4507 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSra_vx()
4508 const uint32_t funct7 = EncodeRVVF7(0b101001, vm); in VSra_vx()
4512 void Riscv64Assembler::VSra_vi(VRegister vd, VRegister vs2, uint32_t uimm5, VM vm) { in VSra_vi() argument
4514 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSra_vi()
4515 const uint32_t funct7 = EncodeRVVF7(0b101001, vm); in VSra_vi()
4519 void Riscv64Assembler::VSsrl_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VSsrl_vv() argument
4521 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSsrl_vv()
4522 const uint32_t funct7 = EncodeRVVF7(0b101010, vm); in VSsrl_vv()
4526 void Riscv64Assembler::VSsrl_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VSsrl_vx() argument
4528 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSsrl_vx()
4529 const uint32_t funct7 = EncodeRVVF7(0b101010, vm); in VSsrl_vx()
4533 void Riscv64Assembler::VSsrl_vi(VRegister vd, VRegister vs2, uint32_t uimm5, VM vm) { in VSsrl_vi() argument
4535 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSsrl_vi()
4536 const uint32_t funct7 = EncodeRVVF7(0b101010, vm); in VSsrl_vi()
4540 void Riscv64Assembler::VSsra_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VSsra_vv() argument
4542 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSsra_vv()
4543 const uint32_t funct7 = EncodeRVVF7(0b101011, vm); in VSsra_vv()
4547 void Riscv64Assembler::VSsra_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VSsra_vx() argument
4549 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSsra_vx()
4550 const uint32_t funct7 = EncodeRVVF7(0b101011, vm); in VSsra_vx()
4554 void Riscv64Assembler::VSsra_vi(VRegister vd, VRegister vs2, uint32_t uimm5, VM vm) { in VSsra_vi() argument
4556 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSsra_vi()
4557 const uint32_t funct7 = EncodeRVVF7(0b101011, vm); in VSsra_vi()
4561 void Riscv64Assembler::VNsrl_wv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VNsrl_wv() argument
4563 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VNsrl_wv()
4564 const uint32_t funct7 = EncodeRVVF7(0b101100, vm); in VNsrl_wv()
4568 void Riscv64Assembler::VNsrl_wx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VNsrl_wx() argument
4570 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VNsrl_wx()
4571 const uint32_t funct7 = EncodeRVVF7(0b101100, vm); in VNsrl_wx()
4575 void Riscv64Assembler::VNsrl_wi(VRegister vd, VRegister vs2, uint32_t uimm5, VM vm) { in VNsrl_wi() argument
4577 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VNsrl_wi()
4578 const uint32_t funct7 = EncodeRVVF7(0b101100, vm); in VNsrl_wi()
4582 void Riscv64Assembler::VNcvt_x_x_w(VRegister vd, VRegister vs2, VM vm) { in VNcvt_x_x_w() argument
4584 VNsrl_wx(vd, vs2, Zero, vm); in VNcvt_x_x_w()
4587 void Riscv64Assembler::VNsra_wv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VNsra_wv() argument
4589 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VNsra_wv()
4590 const uint32_t funct7 = EncodeRVVF7(0b101101, vm); in VNsra_wv()
4594 void Riscv64Assembler::VNsra_wx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VNsra_wx() argument
4596 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VNsra_wx()
4597 const uint32_t funct7 = EncodeRVVF7(0b101101, vm); in VNsra_wx()
4601 void Riscv64Assembler::VNsra_wi(VRegister vd, VRegister vs2, uint32_t uimm5, VM vm) { in VNsra_wi() argument
4603 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VNsra_wi()
4604 const uint32_t funct7 = EncodeRVVF7(0b101101, vm); in VNsra_wi()
4608 void Riscv64Assembler::VNclipu_wv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VNclipu_wv() argument
4610 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VNclipu_wv()
4611 const uint32_t funct7 = EncodeRVVF7(0b101110, vm); in VNclipu_wv()
4615 void Riscv64Assembler::VNclipu_wx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VNclipu_wx() argument
4617 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VNclipu_wx()
4618 const uint32_t funct7 = EncodeRVVF7(0b101110, vm); in VNclipu_wx()
4622 void Riscv64Assembler::VNclipu_wi(VRegister vd, VRegister vs2, uint32_t uimm5, VM vm) { in VNclipu_wi() argument
4624 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VNclipu_wi()
4625 const uint32_t funct7 = EncodeRVVF7(0b101110, vm); in VNclipu_wi()
4629 void Riscv64Assembler::VNclip_wv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VNclip_wv() argument
4631 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VNclip_wv()
4632 const uint32_t funct7 = EncodeRVVF7(0b101111, vm); in VNclip_wv()
4636 void Riscv64Assembler::VNclip_wx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VNclip_wx() argument
4638 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VNclip_wx()
4639 const uint32_t funct7 = EncodeRVVF7(0b101111, vm); in VNclip_wx()
4643 void Riscv64Assembler::VNclip_wi(VRegister vd, VRegister vs2, uint32_t uimm5, VM vm) { in VNclip_wi() argument
4645 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VNclip_wi()
4646 const uint32_t funct7 = EncodeRVVF7(0b101111, vm); in VNclip_wi()
4650 void Riscv64Assembler::VWredsumu_vs(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VWredsumu_vs() argument
4652 const uint32_t funct7 = EncodeRVVF7(0b110000, vm); in VWredsumu_vs()
4656 void Riscv64Assembler::VWredsum_vs(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VWredsum_vs() argument
4658 const uint32_t funct7 = EncodeRVVF7(0b110001, vm); in VWredsum_vs()
4662 void Riscv64Assembler::VRedsum_vs(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VRedsum_vs() argument
4664 const uint32_t funct7 = EncodeRVVF7(0b000000, vm); in VRedsum_vs()
4668 void Riscv64Assembler::VRedand_vs(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VRedand_vs() argument
4670 const uint32_t funct7 = EncodeRVVF7(0b000001, vm); in VRedand_vs()
4674 void Riscv64Assembler::VRedor_vs(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VRedor_vs() argument
4676 const uint32_t funct7 = EncodeRVVF7(0b000010, vm); in VRedor_vs()
4680 void Riscv64Assembler::VRedxor_vs(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VRedxor_vs() argument
4682 const uint32_t funct7 = EncodeRVVF7(0b000011, vm); in VRedxor_vs()
4686 void Riscv64Assembler::VRedminu_vs(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VRedminu_vs() argument
4688 const uint32_t funct7 = EncodeRVVF7(0b000100, vm); in VRedminu_vs()
4692 void Riscv64Assembler::VRedmin_vs(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VRedmin_vs() argument
4694 const uint32_t funct7 = EncodeRVVF7(0b000101, vm); in VRedmin_vs()
4698 void Riscv64Assembler::VRedmaxu_vs(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VRedmaxu_vs() argument
4700 const uint32_t funct7 = EncodeRVVF7(0b000110, vm); in VRedmaxu_vs()
4704 void Riscv64Assembler::VRedmax_vs(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VRedmax_vs() argument
4706 const uint32_t funct7 = EncodeRVVF7(0b000111, vm); in VRedmax_vs()
4710 void Riscv64Assembler::VAaddu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VAaddu_vv() argument
4712 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VAaddu_vv()
4713 const uint32_t funct7 = EncodeRVVF7(0b001000, vm); in VAaddu_vv()
4717 void Riscv64Assembler::VAaddu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VAaddu_vx() argument
4719 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VAaddu_vx()
4720 const uint32_t funct7 = EncodeRVVF7(0b001000, vm); in VAaddu_vx()
4724 void Riscv64Assembler::VAadd_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VAadd_vv() argument
4726 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VAadd_vv()
4727 const uint32_t funct7 = EncodeRVVF7(0b001001, vm); in VAadd_vv()
4731 void Riscv64Assembler::VAadd_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VAadd_vx() argument
4733 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VAadd_vx()
4734 const uint32_t funct7 = EncodeRVVF7(0b001001, vm); in VAadd_vx()
4738 void Riscv64Assembler::VAsubu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VAsubu_vv() argument
4740 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VAsubu_vv()
4741 const uint32_t funct7 = EncodeRVVF7(0b001010, vm); in VAsubu_vv()
4745 void Riscv64Assembler::VAsubu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VAsubu_vx() argument
4747 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VAsubu_vx()
4748 const uint32_t funct7 = EncodeRVVF7(0b001010, vm); in VAsubu_vx()
4752 void Riscv64Assembler::VAsub_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VAsub_vv() argument
4754 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VAsub_vv()
4755 const uint32_t funct7 = EncodeRVVF7(0b001011, vm); in VAsub_vv()
4759 void Riscv64Assembler::VAsub_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VAsub_vx() argument
4761 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VAsub_vx()
4762 const uint32_t funct7 = EncodeRVVF7(0b001011, vm); in VAsub_vx()
4766 void Riscv64Assembler::VSlide1up_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VSlide1up_vx() argument
4768 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSlide1up_vx()
4770 const uint32_t funct7 = EncodeRVVF7(0b001110, vm); in VSlide1up_vx()
4774 void Riscv64Assembler::VSlide1down_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VSlide1down_vx() argument
4776 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSlide1down_vx()
4777 const uint32_t funct7 = EncodeRVVF7(0b001111, vm); in VSlide1down_vx()
4845 void Riscv64Assembler::VDivu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VDivu_vv() argument
4847 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VDivu_vv()
4848 const uint32_t funct7 = EncodeRVVF7(0b100000, vm); in VDivu_vv()
4852 void Riscv64Assembler::VDivu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VDivu_vx() argument
4854 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VDivu_vx()
4855 const uint32_t funct7 = EncodeRVVF7(0b100000, vm); in VDivu_vx()
4859 void Riscv64Assembler::VDiv_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VDiv_vv() argument
4861 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VDiv_vv()
4862 const uint32_t funct7 = EncodeRVVF7(0b100001, vm); in VDiv_vv()
4866 void Riscv64Assembler::VDiv_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VDiv_vx() argument
4868 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VDiv_vx()
4869 const uint32_t funct7 = EncodeRVVF7(0b100001, vm); in VDiv_vx()
4873 void Riscv64Assembler::VRemu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VRemu_vv() argument
4875 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VRemu_vv()
4876 const uint32_t funct7 = EncodeRVVF7(0b100010, vm); in VRemu_vv()
4880 void Riscv64Assembler::VRemu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VRemu_vx() argument
4882 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VRemu_vx()
4883 const uint32_t funct7 = EncodeRVVF7(0b100010, vm); in VRemu_vx()
4887 void Riscv64Assembler::VRem_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VRem_vv() argument
4889 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VRem_vv()
4890 const uint32_t funct7 = EncodeRVVF7(0b100011, vm); in VRem_vv()
4894 void Riscv64Assembler::VRem_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VRem_vx() argument
4896 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VRem_vx()
4897 const uint32_t funct7 = EncodeRVVF7(0b100011, vm); in VRem_vx()
4901 void Riscv64Assembler::VMulhu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VMulhu_vv() argument
4903 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMulhu_vv()
4904 const uint32_t funct7 = EncodeRVVF7(0b100100, vm); in VMulhu_vv()
4908 void Riscv64Assembler::VMulhu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VMulhu_vx() argument
4910 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMulhu_vx()
4911 const uint32_t funct7 = EncodeRVVF7(0b100100, vm); in VMulhu_vx()
4915 void Riscv64Assembler::VMul_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VMul_vv() argument
4917 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMul_vv()
4918 const uint32_t funct7 = EncodeRVVF7(0b100101, vm); in VMul_vv()
4922 void Riscv64Assembler::VMul_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VMul_vx() argument
4924 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMul_vx()
4925 const uint32_t funct7 = EncodeRVVF7(0b100101, vm); in VMul_vx()
4929 void Riscv64Assembler::VMulhsu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VMulhsu_vv() argument
4931 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMulhsu_vv()
4932 const uint32_t funct7 = EncodeRVVF7(0b100110, vm); in VMulhsu_vv()
4936 void Riscv64Assembler::VMulhsu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VMulhsu_vx() argument
4938 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMulhsu_vx()
4939 const uint32_t funct7 = EncodeRVVF7(0b100110, vm); in VMulhsu_vx()
4943 void Riscv64Assembler::VMulh_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VMulh_vv() argument
4945 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMulh_vv()
4946 const uint32_t funct7 = EncodeRVVF7(0b100111, vm); in VMulh_vv()
4950 void Riscv64Assembler::VMulh_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VMulh_vx() argument
4952 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMulh_vx()
4953 const uint32_t funct7 = EncodeRVVF7(0b100111, vm); in VMulh_vx()
4957 void Riscv64Assembler::VMadd_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) { in VMadd_vv() argument
4959 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMadd_vv()
4960 const uint32_t funct7 = EncodeRVVF7(0b101001, vm); in VMadd_vv()
4964 void Riscv64Assembler::VMadd_vx(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VMadd_vx() argument
4966 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMadd_vx()
4967 const uint32_t funct7 = EncodeRVVF7(0b101001, vm); in VMadd_vx()
4971 void Riscv64Assembler::VNmsub_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) { in VNmsub_vv() argument
4973 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VNmsub_vv()
4974 const uint32_t funct7 = EncodeRVVF7(0b101011, vm); in VNmsub_vv()
4978 void Riscv64Assembler::VNmsub_vx(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VNmsub_vx() argument
4980 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VNmsub_vx()
4981 const uint32_t funct7 = EncodeRVVF7(0b101011, vm); in VNmsub_vx()
4985 void Riscv64Assembler::VMacc_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) { in VMacc_vv() argument
4987 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMacc_vv()
4988 const uint32_t funct7 = EncodeRVVF7(0b101101, vm); in VMacc_vv()
4992 void Riscv64Assembler::VMacc_vx(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VMacc_vx() argument
4994 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMacc_vx()
4995 const uint32_t funct7 = EncodeRVVF7(0b101101, vm); in VMacc_vx()
4999 void Riscv64Assembler::VNmsac_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) { in VNmsac_vv() argument
5001 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VNmsac_vv()
5004 const uint32_t funct7 = EncodeRVVF7(0b101111, vm); in VNmsac_vv()
5008 void Riscv64Assembler::VNmsac_vx(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VNmsac_vx() argument
5010 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VNmsac_vx()
5011 const uint32_t funct7 = EncodeRVVF7(0b101111, vm); in VNmsac_vx()
5015 void Riscv64Assembler::VWaddu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VWaddu_vv() argument
5017 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VWaddu_vv()
5020 const uint32_t funct7 = EncodeRVVF7(0b110000, vm); in VWaddu_vv()
5024 void Riscv64Assembler::VWaddu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VWaddu_vx() argument
5026 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VWaddu_vx()
5028 const uint32_t funct7 = EncodeRVVF7(0b110000, vm); in VWaddu_vx()
5032 void Riscv64Assembler::VWcvtu_x_x_v(VRegister vd, VRegister vs, VM vm) { in VWcvtu_x_x_v() argument
5033 VWaddu_vx(vd, vs, Zero, vm); in VWcvtu_x_x_v()
5036 void Riscv64Assembler::VWadd_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VWadd_vv() argument
5038 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VWadd_vv()
5041 const uint32_t funct7 = EncodeRVVF7(0b110001, vm); in VWadd_vv()
5045 void Riscv64Assembler::VWadd_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VWadd_vx() argument
5047 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VWadd_vx()
5049 const uint32_t funct7 = EncodeRVVF7(0b110001, vm); in VWadd_vx()
5053 void Riscv64Assembler::VWcvt_x_x_v(VRegister vd, VRegister vs, VM vm) { in VWcvt_x_x_v() argument
5054 VWadd_vx(vd, vs, Zero, vm); in VWcvt_x_x_v()
5057 void Riscv64Assembler::VWsubu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VWsubu_vv() argument
5059 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VWsubu_vv()
5062 const uint32_t funct7 = EncodeRVVF7(0b110010, vm); in VWsubu_vv()
5066 void Riscv64Assembler::VWsubu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VWsubu_vx() argument
5068 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VWsubu_vx()
5070 const uint32_t funct7 = EncodeRVVF7(0b110010, vm); in VWsubu_vx()
5074 void Riscv64Assembler::VWsub_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VWsub_vv() argument
5076 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VWsub_vv()
5079 const uint32_t funct7 = EncodeRVVF7(0b110011, vm); in VWsub_vv()
5083 void Riscv64Assembler::VWsub_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VWsub_vx() argument
5085 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VWsub_vx()
5087 const uint32_t funct7 = EncodeRVVF7(0b110011, vm); in VWsub_vx()
5091 void Riscv64Assembler::VWaddu_wv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VWaddu_wv() argument
5093 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VWaddu_wv()
5095 const uint32_t funct7 = EncodeRVVF7(0b110100, vm); in VWaddu_wv()
5099 void Riscv64Assembler::VWaddu_wx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VWaddu_wx() argument
5101 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VWaddu_wx()
5102 const uint32_t funct7 = EncodeRVVF7(0b110100, vm); in VWaddu_wx()
5106 void Riscv64Assembler::VWadd_wv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VWadd_wv() argument
5108 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VWadd_wv()
5110 const uint32_t funct7 = EncodeRVVF7(0b110101, vm); in VWadd_wv()
5114 void Riscv64Assembler::VWadd_wx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VWadd_wx() argument
5116 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VWadd_wx()
5117 const uint32_t funct7 = EncodeRVVF7(0b110101, vm); in VWadd_wx()
5121 void Riscv64Assembler::VWsubu_wv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VWsubu_wv() argument
5123 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VWsubu_wv()
5125 const uint32_t funct7 = EncodeRVVF7(0b110110, vm); in VWsubu_wv()
5129 void Riscv64Assembler::VWsubu_wx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VWsubu_wx() argument
5131 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VWsubu_wx()
5132 const uint32_t funct7 = EncodeRVVF7(0b110110, vm); in VWsubu_wx()
5136 void Riscv64Assembler::VWsub_wv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VWsub_wv() argument
5138 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VWsub_wv()
5140 const uint32_t funct7 = EncodeRVVF7(0b110111, vm); in VWsub_wv()
5144 void Riscv64Assembler::VWsub_wx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VWsub_wx() argument
5146 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VWsub_wx()
5147 const uint32_t funct7 = EncodeRVVF7(0b110111, vm); in VWsub_wx()
5151 void Riscv64Assembler::VWmulu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VWmulu_vv() argument
5153 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VWmulu_vv()
5156 const uint32_t funct7 = EncodeRVVF7(0b111000, vm); in VWmulu_vv()
5160 void Riscv64Assembler::VWmulu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VWmulu_vx() argument
5162 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VWmulu_vx()
5164 const uint32_t funct7 = EncodeRVVF7(0b111000, vm); in VWmulu_vx()
5168 void Riscv64Assembler::VWmulsu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VWmulsu_vv() argument
5170 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VWmulsu_vv()
5173 const uint32_t funct7 = EncodeRVVF7(0b111010, vm); in VWmulsu_vv()
5177 void Riscv64Assembler::VWmulsu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VWmulsu_vx() argument
5179 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VWmulsu_vx()
5181 const uint32_t funct7 = EncodeRVVF7(0b111010, vm); in VWmulsu_vx()
5185 void Riscv64Assembler::VWmul_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VWmul_vv() argument
5187 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VWmul_vv()
5190 const uint32_t funct7 = EncodeRVVF7(0b111011, vm); in VWmul_vv()
5194 void Riscv64Assembler::VWmul_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) { in VWmul_vx() argument
5196 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VWmul_vx()
5198 const uint32_t funct7 = EncodeRVVF7(0b111011, vm); in VWmul_vx()
5202 void Riscv64Assembler::VWmaccu_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) { in VWmaccu_vv() argument
5204 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VWmaccu_vv()
5207 const uint32_t funct7 = EncodeRVVF7(0b111100, vm); in VWmaccu_vv()
5211 void Riscv64Assembler::VWmaccu_vx(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VWmaccu_vx() argument
5213 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VWmaccu_vx()
5215 const uint32_t funct7 = EncodeRVVF7(0b111100, vm); in VWmaccu_vx()
5219 void Riscv64Assembler::VWmacc_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) { in VWmacc_vv() argument
5221 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VWmacc_vv()
5224 const uint32_t funct7 = EncodeRVVF7(0b111101, vm); in VWmacc_vv()
5228 void Riscv64Assembler::VWmacc_vx(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VWmacc_vx() argument
5230 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VWmacc_vx()
5232 const uint32_t funct7 = EncodeRVVF7(0b111101, vm); in VWmacc_vx()
5236 void Riscv64Assembler::VWmaccus_vx(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VWmaccus_vx() argument
5238 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VWmaccus_vx()
5240 const uint32_t funct7 = EncodeRVVF7(0b111110, vm); in VWmaccus_vx()
5244 void Riscv64Assembler::VWmaccsu_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) { in VWmaccsu_vv() argument
5246 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VWmaccsu_vv()
5249 const uint32_t funct7 = EncodeRVVF7(0b111111, vm); in VWmaccsu_vv()
5253 void Riscv64Assembler::VWmaccsu_vx(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VWmaccsu_vx() argument
5255 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VWmaccsu_vx()
5257 const uint32_t funct7 = EncodeRVVF7(0b111111, vm); in VWmaccsu_vx()
5261 void Riscv64Assembler::VFadd_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VFadd_vv() argument
5263 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFadd_vv()
5264 const uint32_t funct7 = EncodeRVVF7(0b000000, vm); in VFadd_vv()
5268 void Riscv64Assembler::VFadd_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) { in VFadd_vf() argument
5270 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFadd_vf()
5271 const uint32_t funct7 = EncodeRVVF7(0b000000, vm); in VFadd_vf()
5275 void Riscv64Assembler::VFredusum_vs(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VFredusum_vs() argument
5277 const uint32_t funct7 = EncodeRVVF7(0b000001, vm); in VFredusum_vs()
5281 void Riscv64Assembler::VFsub_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VFsub_vv() argument
5283 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFsub_vv()
5284 const uint32_t funct7 = EncodeRVVF7(0b000010, vm); in VFsub_vv()
5288 void Riscv64Assembler::VFsub_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) { in VFsub_vf() argument
5290 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFsub_vf()
5291 const uint32_t funct7 = EncodeRVVF7(0b000010, vm); in VFsub_vf()
5295 void Riscv64Assembler::VFredosum_vs(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VFredosum_vs() argument
5297 const uint32_t funct7 = EncodeRVVF7(0b000011, vm); in VFredosum_vs()
5301 void Riscv64Assembler::VFmin_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VFmin_vv() argument
5303 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFmin_vv()
5304 const uint32_t funct7 = EncodeRVVF7(0b000100, vm); in VFmin_vv()
5308 void Riscv64Assembler::VFmin_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) { in VFmin_vf() argument
5310 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFmin_vf()
5311 const uint32_t funct7 = EncodeRVVF7(0b000100, vm); in VFmin_vf()
5315 void Riscv64Assembler::VFredmin_vs(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VFredmin_vs() argument
5317 const uint32_t funct7 = EncodeRVVF7(0b000101, vm); in VFredmin_vs()
5321 void Riscv64Assembler::VFmax_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VFmax_vv() argument
5323 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFmax_vv()
5324 const uint32_t funct7 = EncodeRVVF7(0b000110, vm); in VFmax_vv()
5328 void Riscv64Assembler::VFmax_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) { in VFmax_vf() argument
5330 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFmax_vf()
5331 const uint32_t funct7 = EncodeRVVF7(0b000110, vm); in VFmax_vf()
5335 void Riscv64Assembler::VFredmax_vs(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VFredmax_vs() argument
5337 const uint32_t funct7 = EncodeRVVF7(0b000111, vm); in VFredmax_vs()
5341 void Riscv64Assembler::VFsgnj_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VFsgnj_vv() argument
5343 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFsgnj_vv()
5344 const uint32_t funct7 = EncodeRVVF7(0b001000, vm); in VFsgnj_vv()
5348 void Riscv64Assembler::VFsgnj_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) { in VFsgnj_vf() argument
5350 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFsgnj_vf()
5351 const uint32_t funct7 = EncodeRVVF7(0b001000, vm); in VFsgnj_vf()
5355 void Riscv64Assembler::VFsgnjn_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VFsgnjn_vv() argument
5357 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFsgnjn_vv()
5358 const uint32_t funct7 = EncodeRVVF7(0b001001, vm); in VFsgnjn_vv()
5362 void Riscv64Assembler::VFsgnjn_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) { in VFsgnjn_vf() argument
5364 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFsgnjn_vf()
5365 const uint32_t funct7 = EncodeRVVF7(0b001001, vm); in VFsgnjn_vf()
5371 void Riscv64Assembler::VFsgnjx_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VFsgnjx_vv() argument
5373 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFsgnjx_vv()
5374 const uint32_t funct7 = EncodeRVVF7(0b001010, vm); in VFsgnjx_vv()
5378 void Riscv64Assembler::VFsgnjx_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) { in VFsgnjx_vf() argument
5380 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFsgnjx_vf()
5381 const uint32_t funct7 = EncodeRVVF7(0b001010, vm); in VFsgnjx_vf()
5387 void Riscv64Assembler::VFslide1up_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) { in VFslide1up_vf() argument
5389 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFslide1up_vf()
5391 const uint32_t funct7 = EncodeRVVF7(0b001110, vm); in VFslide1up_vf()
5395 void Riscv64Assembler::VFslide1down_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) { in VFslide1down_vf() argument
5397 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFslide1down_vf()
5398 const uint32_t funct7 = EncodeRVVF7(0b001111, vm); in VFslide1down_vf()
5415 void Riscv64Assembler::VMfeq_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VMfeq_vv() argument
5417 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMfeq_vv()
5418 const uint32_t funct7 = EncodeRVVF7(0b011000, vm); in VMfeq_vv()
5422 void Riscv64Assembler::VMfeq_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) { in VMfeq_vf() argument
5424 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMfeq_vf()
5425 const uint32_t funct7 = EncodeRVVF7(0b011000, vm); in VMfeq_vf()
5429 void Riscv64Assembler::VMfle_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VMfle_vv() argument
5431 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMfle_vv()
5432 const uint32_t funct7 = EncodeRVVF7(0b011001, vm); in VMfle_vv()
5436 void Riscv64Assembler::VMfle_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) { in VMfle_vf() argument
5438 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMfle_vf()
5439 const uint32_t funct7 = EncodeRVVF7(0b011001, vm); in VMfle_vf()
5443 void Riscv64Assembler::VMfge_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VMfge_vv() argument
5444 VMfle_vv(vd, vs1, vs2, vm); in VMfge_vv()
5447 void Riscv64Assembler::VMflt_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VMflt_vv() argument
5449 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMflt_vv()
5450 const uint32_t funct7 = EncodeRVVF7(0b011011, vm); in VMflt_vv()
5454 void Riscv64Assembler::VMflt_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) { in VMflt_vf() argument
5456 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMflt_vf()
5457 const uint32_t funct7 = EncodeRVVF7(0b011011, vm); in VMflt_vf()
5461 void Riscv64Assembler::VMfgt_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VMfgt_vv() argument
5462 VMflt_vv(vd, vs1, vs2, vm); in VMfgt_vv()
5465 void Riscv64Assembler::VMfne_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VMfne_vv() argument
5467 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMfne_vv()
5468 const uint32_t funct7 = EncodeRVVF7(0b011100, vm); in VMfne_vv()
5472 void Riscv64Assembler::VMfne_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) { in VMfne_vf() argument
5474 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMfne_vf()
5475 const uint32_t funct7 = EncodeRVVF7(0b011100, vm); in VMfne_vf()
5479 void Riscv64Assembler::VMfgt_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) { in VMfgt_vf() argument
5481 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMfgt_vf()
5482 const uint32_t funct7 = EncodeRVVF7(0b011101, vm); in VMfgt_vf()
5486 void Riscv64Assembler::VMfge_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) { in VMfge_vf() argument
5488 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMfge_vf()
5489 const uint32_t funct7 = EncodeRVVF7(0b011111, vm); in VMfge_vf()
5493 void Riscv64Assembler::VFdiv_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VFdiv_vv() argument
5495 const uint32_t funct7 = EncodeRVVF7(0b100000, vm); in VFdiv_vv()
5499 void Riscv64Assembler::VFdiv_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) { in VFdiv_vf() argument
5501 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFdiv_vf()
5502 const uint32_t funct7 = EncodeRVVF7(0b100000, vm); in VFdiv_vf()
5506 void Riscv64Assembler::VFrdiv_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) { in VFrdiv_vf() argument
5508 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFrdiv_vf()
5509 const uint32_t funct7 = EncodeRVVF7(0b100001, vm); in VFrdiv_vf()
5513 void Riscv64Assembler::VFmul_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VFmul_vv() argument
5515 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFmul_vv()
5516 const uint32_t funct7 = EncodeRVVF7(0b100100, vm); in VFmul_vv()
5520 void Riscv64Assembler::VFmul_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) { in VFmul_vf() argument
5522 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFmul_vf()
5523 const uint32_t funct7 = EncodeRVVF7(0b100100, vm); in VFmul_vf()
5527 void Riscv64Assembler::VFrsub_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) { in VFrsub_vf() argument
5529 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFrsub_vf()
5530 const uint32_t funct7 = EncodeRVVF7(0b100111, vm); in VFrsub_vf()
5534 void Riscv64Assembler::VFmadd_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) { in VFmadd_vv() argument
5536 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFmadd_vv()
5537 const uint32_t funct7 = EncodeRVVF7(0b101000, vm); in VFmadd_vv()
5541 void Riscv64Assembler::VFmadd_vf(VRegister vd, FRegister fs1, VRegister vs2, VM vm) { in VFmadd_vf() argument
5543 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFmadd_vf()
5544 const uint32_t funct7 = EncodeRVVF7(0b101000, vm); in VFmadd_vf()
5548 void Riscv64Assembler::VFnmadd_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) { in VFnmadd_vv() argument
5550 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFnmadd_vv()
5551 const uint32_t funct7 = EncodeRVVF7(0b101001, vm); in VFnmadd_vv()
5555 void Riscv64Assembler::VFnmadd_vf(VRegister vd, FRegister fs1, VRegister vs2, VM vm) { in VFnmadd_vf() argument
5557 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFnmadd_vf()
5558 const uint32_t funct7 = EncodeRVVF7(0b101001, vm); in VFnmadd_vf()
5562 void Riscv64Assembler::VFmsub_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) { in VFmsub_vv() argument
5564 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFmsub_vv()
5565 const uint32_t funct7 = EncodeRVVF7(0b101010, vm); in VFmsub_vv()
5569 void Riscv64Assembler::VFmsub_vf(VRegister vd, FRegister fs1, VRegister vs2, VM vm) { in VFmsub_vf() argument
5571 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFmsub_vf()
5572 const uint32_t funct7 = EncodeRVVF7(0b101010, vm); in VFmsub_vf()
5576 void Riscv64Assembler::VFnmsub_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) { in VFnmsub_vv() argument
5578 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFnmsub_vv()
5579 const uint32_t funct7 = EncodeRVVF7(0b101011, vm); in VFnmsub_vv()
5583 void Riscv64Assembler::VFnmsub_vf(VRegister vd, FRegister fs1, VRegister vs2, VM vm) { in VFnmsub_vf() argument
5585 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFnmsub_vf()
5586 const uint32_t funct7 = EncodeRVVF7(0b101011, vm); in VFnmsub_vf()
5590 void Riscv64Assembler::VFmacc_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) { in VFmacc_vv() argument
5592 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFmacc_vv()
5593 const uint32_t funct7 = EncodeRVVF7(0b101100, vm); in VFmacc_vv()
5597 void Riscv64Assembler::VFmacc_vf(VRegister vd, FRegister fs1, VRegister vs2, VM vm) { in VFmacc_vf() argument
5599 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFmacc_vf()
5600 const uint32_t funct7 = EncodeRVVF7(0b101100, vm); in VFmacc_vf()
5604 void Riscv64Assembler::VFnmacc_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) { in VFnmacc_vv() argument
5606 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFnmacc_vv()
5607 const uint32_t funct7 = EncodeRVVF7(0b101101, vm); in VFnmacc_vv()
5611 void Riscv64Assembler::VFnmacc_vf(VRegister vd, FRegister fs1, VRegister vs2, VM vm) { in VFnmacc_vf() argument
5613 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFnmacc_vf()
5614 const uint32_t funct7 = EncodeRVVF7(0b101101, vm); in VFnmacc_vf()
5618 void Riscv64Assembler::VFmsac_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) { in VFmsac_vv() argument
5620 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFmsac_vv()
5621 const uint32_t funct7 = EncodeRVVF7(0b101110, vm); in VFmsac_vv()
5625 void Riscv64Assembler::VFmsac_vf(VRegister vd, FRegister fs1, VRegister vs2, VM vm) { in VFmsac_vf() argument
5627 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFmsac_vf()
5628 const uint32_t funct7 = EncodeRVVF7(0b101110, vm); in VFmsac_vf()
5632 void Riscv64Assembler::VFnmsac_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) { in VFnmsac_vv() argument
5634 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFnmsac_vv()
5635 const uint32_t funct7 = EncodeRVVF7(0b101111, vm); in VFnmsac_vv()
5639 void Riscv64Assembler::VFnmsac_vf(VRegister vd, FRegister fs1, VRegister vs2, VM vm) { in VFnmsac_vf() argument
5641 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFnmsac_vf()
5642 const uint32_t funct7 = EncodeRVVF7(0b101111, vm); in VFnmsac_vf()
5646 void Riscv64Assembler::VFwadd_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VFwadd_vv() argument
5648 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFwadd_vv()
5651 const uint32_t funct7 = EncodeRVVF7(0b110000, vm); in VFwadd_vv()
5655 void Riscv64Assembler::VFwadd_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) { in VFwadd_vf() argument
5657 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFwadd_vf()
5659 const uint32_t funct7 = EncodeRVVF7(0b110000, vm); in VFwadd_vf()
5663 void Riscv64Assembler::VFwredusum_vs(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VFwredusum_vs() argument
5665 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFwredusum_vs()
5666 const uint32_t funct7 = EncodeRVVF7(0b110001, vm); in VFwredusum_vs()
5670 void Riscv64Assembler::VFwsub_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VFwsub_vv() argument
5672 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFwsub_vv()
5675 const uint32_t funct7 = EncodeRVVF7(0b110010, vm); in VFwsub_vv()
5679 void Riscv64Assembler::VFwsub_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) { in VFwsub_vf() argument
5681 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFwsub_vf()
5683 const uint32_t funct7 = EncodeRVVF7(0b110010, vm); in VFwsub_vf()
5687 void Riscv64Assembler::VFwredosum_vs(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VFwredosum_vs() argument
5689 const uint32_t funct7 = EncodeRVVF7(0b110011, vm); in VFwredosum_vs()
5693 void Riscv64Assembler::VFwadd_wv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VFwadd_wv() argument
5695 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFwadd_wv()
5697 const uint32_t funct7 = EncodeRVVF7(0b110100, vm); in VFwadd_wv()
5701 void Riscv64Assembler::VFwadd_wf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) { in VFwadd_wf() argument
5703 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFwadd_wf()
5704 const uint32_t funct7 = EncodeRVVF7(0b110100, vm); in VFwadd_wf()
5708 void Riscv64Assembler::VFwsub_wv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VFwsub_wv() argument
5710 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFwsub_wv()
5712 const uint32_t funct7 = EncodeRVVF7(0b110110, vm); in VFwsub_wv()
5716 void Riscv64Assembler::VFwsub_wf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) { in VFwsub_wf() argument
5718 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFwsub_wf()
5719 const uint32_t funct7 = EncodeRVVF7(0b110110, vm); in VFwsub_wf()
5723 void Riscv64Assembler::VFwmul_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VFwmul_vv() argument
5725 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFwmul_vv()
5728 const uint32_t funct7 = EncodeRVVF7(0b111000, vm); in VFwmul_vv()
5732 void Riscv64Assembler::VFwmul_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) { in VFwmul_vf() argument
5734 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFwmul_vf()
5736 const uint32_t funct7 = EncodeRVVF7(0b111000, vm); in VFwmul_vf()
5740 void Riscv64Assembler::VFwmacc_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) { in VFwmacc_vv() argument
5742 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFwmacc_vv()
5745 const uint32_t funct7 = EncodeRVVF7(0b111100, vm); in VFwmacc_vv()
5749 void Riscv64Assembler::VFwmacc_vf(VRegister vd, FRegister fs1, VRegister vs2, VM vm) { in VFwmacc_vf() argument
5751 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFwmacc_vf()
5753 const uint32_t funct7 = EncodeRVVF7(0b111100, vm); in VFwmacc_vf()
5757 void Riscv64Assembler::VFwnmacc_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) { in VFwnmacc_vv() argument
5759 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFwnmacc_vv()
5762 const uint32_t funct7 = EncodeRVVF7(0b111101, vm); in VFwnmacc_vv()
5766 void Riscv64Assembler::VFwnmacc_vf(VRegister vd, FRegister fs1, VRegister vs2, VM vm) { in VFwnmacc_vf() argument
5768 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFwnmacc_vf()
5770 const uint32_t funct7 = EncodeRVVF7(0b111101, vm); in VFwnmacc_vf()
5774 void Riscv64Assembler::VFwmsac_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) { in VFwmsac_vv() argument
5776 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFwmsac_vv()
5779 const uint32_t funct7 = EncodeRVVF7(0b111110, vm); in VFwmsac_vv()
5783 void Riscv64Assembler::VFwmsac_vf(VRegister vd, FRegister fs1, VRegister vs2, VM vm) { in VFwmsac_vf() argument
5785 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFwmsac_vf()
5787 const uint32_t funct7 = EncodeRVVF7(0b111110, vm); in VFwmsac_vf()
5791 void Riscv64Assembler::VFwnmsac_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) { in VFwnmsac_vv() argument
5793 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFwnmsac_vv()
5796 const uint32_t funct7 = EncodeRVVF7(0b111111, vm); in VFwnmsac_vv()
5800 void Riscv64Assembler::VFwnmsac_vf(VRegister vd, FRegister fs1, VRegister vs2, VM vm) { in VFwnmsac_vf() argument
5802 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFwnmsac_vf()
5804 const uint32_t funct7 = EncodeRVVF7(0b111111, vm); in VFwnmsac_vf()
5820 void Riscv64Assembler::VCpop_m(XRegister rd, VRegister vs2, VM vm) { in VCpop_m() argument
5822 const uint32_t funct7 = EncodeRVVF7(0b010000, vm); in VCpop_m()
5826 void Riscv64Assembler::VFirst_m(XRegister rd, VRegister vs2, VM vm) { in VFirst_m() argument
5828 const uint32_t funct7 = EncodeRVVF7(0b010000, vm); in VFirst_m()
5832 void Riscv64Assembler::VZext_vf8(VRegister vd, VRegister vs2, VM vm) { in VZext_vf8() argument
5834 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VZext_vf8()
5835 const uint32_t funct7 = EncodeRVVF7(0b010010, vm); in VZext_vf8()
5839 void Riscv64Assembler::VSext_vf8(VRegister vd, VRegister vs2, VM vm) { in VSext_vf8() argument
5841 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSext_vf8()
5842 const uint32_t funct7 = EncodeRVVF7(0b010010, vm); in VSext_vf8()
5846 void Riscv64Assembler::VZext_vf4(VRegister vd, VRegister vs2, VM vm) { in VZext_vf4() argument
5848 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VZext_vf4()
5849 const uint32_t funct7 = EncodeRVVF7(0b010010, vm); in VZext_vf4()
5853 void Riscv64Assembler::VSext_vf4(VRegister vd, VRegister vs2, VM vm) { in VSext_vf4() argument
5855 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSext_vf4()
5856 const uint32_t funct7 = EncodeRVVF7(0b010010, vm); in VSext_vf4()
5860 void Riscv64Assembler::VZext_vf2(VRegister vd, VRegister vs2, VM vm) { in VZext_vf2() argument
5862 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VZext_vf2()
5863 const uint32_t funct7 = EncodeRVVF7(0b010010, vm); in VZext_vf2()
5867 void Riscv64Assembler::VSext_vf2(VRegister vd, VRegister vs2, VM vm) { in VSext_vf2() argument
5869 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VSext_vf2()
5870 const uint32_t funct7 = EncodeRVVF7(0b010010, vm); in VSext_vf2()
5886 void Riscv64Assembler::VFcvt_xu_f_v(VRegister vd, VRegister vs2, VM vm) { in VFcvt_xu_f_v() argument
5888 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFcvt_xu_f_v()
5889 const uint32_t funct7 = EncodeRVVF7(0b010010, vm); in VFcvt_xu_f_v()
5893 void Riscv64Assembler::VFcvt_x_f_v(VRegister vd, VRegister vs2, VM vm) { in VFcvt_x_f_v() argument
5895 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFcvt_x_f_v()
5896 const uint32_t funct7 = EncodeRVVF7(0b010010, vm); in VFcvt_x_f_v()
5900 void Riscv64Assembler::VFcvt_f_xu_v(VRegister vd, VRegister vs2, VM vm) { in VFcvt_f_xu_v() argument
5902 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFcvt_f_xu_v()
5903 const uint32_t funct7 = EncodeRVVF7(0b010010, vm); in VFcvt_f_xu_v()
5907 void Riscv64Assembler::VFcvt_f_x_v(VRegister vd, VRegister vs2, VM vm) { in VFcvt_f_x_v() argument
5909 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFcvt_f_x_v()
5910 const uint32_t funct7 = EncodeRVVF7(0b010010, vm); in VFcvt_f_x_v()
5914 void Riscv64Assembler::VFcvt_rtz_xu_f_v(VRegister vd, VRegister vs2, VM vm) { in VFcvt_rtz_xu_f_v() argument
5916 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFcvt_rtz_xu_f_v()
5917 const uint32_t funct7 = EncodeRVVF7(0b010010, vm); in VFcvt_rtz_xu_f_v()
5921 void Riscv64Assembler::VFcvt_rtz_x_f_v(VRegister vd, VRegister vs2, VM vm) { in VFcvt_rtz_x_f_v() argument
5923 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFcvt_rtz_x_f_v()
5924 const uint32_t funct7 = EncodeRVVF7(0b010010, vm); in VFcvt_rtz_x_f_v()
5928 void Riscv64Assembler::VFwcvt_xu_f_v(VRegister vd, VRegister vs2, VM vm) { in VFwcvt_xu_f_v() argument
5930 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFwcvt_xu_f_v()
5932 const uint32_t funct7 = EncodeRVVF7(0b010010, vm); in VFwcvt_xu_f_v()
5936 void Riscv64Assembler::VFwcvt_x_f_v(VRegister vd, VRegister vs2, VM vm) { in VFwcvt_x_f_v() argument
5938 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFwcvt_x_f_v()
5940 const uint32_t funct7 = EncodeRVVF7(0b010010, vm); in VFwcvt_x_f_v()
5944 void Riscv64Assembler::VFwcvt_f_xu_v(VRegister vd, VRegister vs2, VM vm) { in VFwcvt_f_xu_v() argument
5946 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFwcvt_f_xu_v()
5948 const uint32_t funct7 = EncodeRVVF7(0b010010, vm); in VFwcvt_f_xu_v()
5952 void Riscv64Assembler::VFwcvt_f_x_v(VRegister vd, VRegister vs2, VM vm) { in VFwcvt_f_x_v() argument
5954 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFwcvt_f_x_v()
5956 const uint32_t funct7 = EncodeRVVF7(0b010010, vm); in VFwcvt_f_x_v()
5960 void Riscv64Assembler::VFwcvt_f_f_v(VRegister vd, VRegister vs2, VM vm) { in VFwcvt_f_f_v() argument
5962 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFwcvt_f_f_v()
5964 const uint32_t funct7 = EncodeRVVF7(0b010010, vm); in VFwcvt_f_f_v()
5968 void Riscv64Assembler::VFwcvt_rtz_xu_f_v(VRegister vd, VRegister vs2, VM vm) { in VFwcvt_rtz_xu_f_v() argument
5970 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFwcvt_rtz_xu_f_v()
5972 const uint32_t funct7 = EncodeRVVF7(0b010010, vm); in VFwcvt_rtz_xu_f_v()
5976 void Riscv64Assembler::VFwcvt_rtz_x_f_v(VRegister vd, VRegister vs2, VM vm) { in VFwcvt_rtz_x_f_v() argument
5978 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFwcvt_rtz_x_f_v()
5980 const uint32_t funct7 = EncodeRVVF7(0b010010, vm); in VFwcvt_rtz_x_f_v()
5984 void Riscv64Assembler::VFncvt_xu_f_w(VRegister vd, VRegister vs2, VM vm) { in VFncvt_xu_f_w() argument
5986 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFncvt_xu_f_w()
5987 const uint32_t funct7 = EncodeRVVF7(0b010010, vm); in VFncvt_xu_f_w()
5991 void Riscv64Assembler::VFncvt_x_f_w(VRegister vd, VRegister vs2, VM vm) { in VFncvt_x_f_w() argument
5993 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFncvt_x_f_w()
5994 const uint32_t funct7 = EncodeRVVF7(0b010010, vm); in VFncvt_x_f_w()
5998 void Riscv64Assembler::VFncvt_f_xu_w(VRegister vd, VRegister vs2, VM vm) { in VFncvt_f_xu_w() argument
6000 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFncvt_f_xu_w()
6001 const uint32_t funct7 = EncodeRVVF7(0b010010, vm); in VFncvt_f_xu_w()
6005 void Riscv64Assembler::VFncvt_f_x_w(VRegister vd, VRegister vs2, VM vm) { in VFncvt_f_x_w() argument
6007 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFncvt_f_x_w()
6008 const uint32_t funct7 = EncodeRVVF7(0b010010, vm); in VFncvt_f_x_w()
6012 void Riscv64Assembler::VFncvt_f_f_w(VRegister vd, VRegister vs2, VM vm) { in VFncvt_f_f_w() argument
6014 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFncvt_f_f_w()
6015 const uint32_t funct7 = EncodeRVVF7(0b010010, vm); in VFncvt_f_f_w()
6019 void Riscv64Assembler::VFncvt_rod_f_f_w(VRegister vd, VRegister vs2, VM vm) { in VFncvt_rod_f_f_w() argument
6021 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFncvt_rod_f_f_w()
6022 const uint32_t funct7 = EncodeRVVF7(0b010010, vm); in VFncvt_rod_f_f_w()
6026 void Riscv64Assembler::VFncvt_rtz_xu_f_w(VRegister vd, VRegister vs2, VM vm) { in VFncvt_rtz_xu_f_w() argument
6028 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFncvt_rtz_xu_f_w()
6029 const uint32_t funct7 = EncodeRVVF7(0b010010, vm); in VFncvt_rtz_xu_f_w()
6033 void Riscv64Assembler::VFncvt_rtz_x_f_w(VRegister vd, VRegister vs2, VM vm) { in VFncvt_rtz_x_f_w() argument
6035 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFncvt_rtz_x_f_w()
6036 const uint32_t funct7 = EncodeRVVF7(0b010010, vm); in VFncvt_rtz_x_f_w()
6040 void Riscv64Assembler::VFsqrt_v(VRegister vd, VRegister vs2, VM vm) { in VFsqrt_v() argument
6042 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFsqrt_v()
6043 const uint32_t funct7 = EncodeRVVF7(0b010011, vm); in VFsqrt_v()
6047 void Riscv64Assembler::VFrsqrt7_v(VRegister vd, VRegister vs2, VM vm) { in VFrsqrt7_v() argument
6049 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFrsqrt7_v()
6050 const uint32_t funct7 = EncodeRVVF7(0b010011, vm); in VFrsqrt7_v()
6054 void Riscv64Assembler::VFrec7_v(VRegister vd, VRegister vs2, VM vm) { in VFrec7_v() argument
6056 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFrec7_v()
6057 const uint32_t funct7 = EncodeRVVF7(0b010011, vm); in VFrec7_v()
6061 void Riscv64Assembler::VFclass_v(VRegister vd, VRegister vs2, VM vm) { in VFclass_v() argument
6063 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VFclass_v()
6064 const uint32_t funct7 = EncodeRVVF7(0b010011, vm); in VFclass_v()
6068 void Riscv64Assembler::VMsbf_m(VRegister vd, VRegister vs2, VM vm) { in VMsbf_m() argument
6070 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMsbf_m()
6072 const uint32_t funct7 = EncodeRVVF7(0b010100, vm); in VMsbf_m()
6076 void Riscv64Assembler::VMsof_m(VRegister vd, VRegister vs2, VM vm) { in VMsof_m() argument
6078 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMsof_m()
6080 const uint32_t funct7 = EncodeRVVF7(0b010100, vm); in VMsof_m()
6084 void Riscv64Assembler::VMsif_m(VRegister vd, VRegister vs2, VM vm) { in VMsif_m() argument
6086 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VMsif_m()
6088 const uint32_t funct7 = EncodeRVVF7(0b010100, vm); in VMsif_m()
6092 void Riscv64Assembler::VIota_m(VRegister vd, VRegister vs2, VM vm) { in VIota_m() argument
6094 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VIota_m()
6096 const uint32_t funct7 = EncodeRVVF7(0b010100, vm); in VIota_m()
6100 void Riscv64Assembler::VId_v(VRegister vd, VM vm) { in VId_v() argument
6102 DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0); in VId_v()
6103 const uint32_t funct7 = EncodeRVVF7(0b010100, vm); in VId_v()