Lines Matching refs:t5

452     SAVE_GPR t5,  8*57  // x30
541     RESTORE_GPR t5,  (8*57)  // x30
760     LUI_VALUE t5, LOCK_WORD_GC_STATE_MASK_SHIFTED  // Prepare mask for testing non-gc bits.
765     or      t6, t5, t3                // Test the non-gc bits.
766     beq     t6, t5, 2f                // Check if unlocked.
769         t5, 0xffffffff ^ (LOCK_WORD_STATE_MASK_SHIFTED | LOCK_WORD_THIN_LOCK_OWNER_MASK_SHIFTED)
770     or      t6, t5, t4
771     bne     t6, t5, \slow_lock
774     LUI_VALUE t5, LOCK_WORD_THIN_LOCK_COUNT_MASK_SHIFTED  // Test the new thin lock count.
775     and     t5, t4, t5
776     beqz    t5, \slow_lock            // Zero as the new count indicates overflow, go slow path.
801     LUI_VALUE t5, LOCK_WORD_GC_STATE_MASK_SHIFTED  // Prepare mask for testing non-gc bits.
806     or      t6, t5, t4                // Test the non-gc bits.
807     beq     t6, t5, 2f                // Simply locked by this thread?
810         t5, 0xffffffff ^ (LOCK_WORD_STATE_MASK_SHIFTED | LOCK_WORD_THIN_LOCK_OWNER_MASK_SHIFTED)
811     or      t6, t5, t4
812     bne     t6, t5, \slow_unlock