165         return Int64(arg1) + Int64(arg2);  in Op()
167         return Int64(arg1) - Int64(arg2);  in Op()
169         return Int64(arg1) & Int64(arg2);  in Op()
171         return Int64(arg1) | Int64(arg2);  in Op()
173         return Int64(arg1) ^ Int64(arg2);  in Op()
175         return Int64(arg1) << Int64(arg2);  in Op()
177         return UInt64(arg1) >> Int64(arg2);  in Op()
179         return Int64(arg1) >> Int64(arg2);  in Op()
181         return Int64(arg1) < Int64(arg2) ? 1 : 0;  in Op()
185         return Int64(arg1) * Int64(arg2);  in Op()
187         return NarrowTopHalf(Widen(Int64(arg1)) * Widen(Int64(arg2)));  in Op()
189         return NarrowTopHalf(Widen(Int64(arg1)) * BitCastToSigned(Widen(UInt64(arg2))));  in Op()
193         return Int64(arg1) & (~Int64(arg2));  in Op()
195         return Int64(arg1) | (~Int64(arg2));  in Op()
197         return ~(Int64(arg1) ^ Int64(arg2));  in Op()
1151               intrinsics::BitMaskToSimdMask<ElementType>(Int64{MaskType{register_mask}});
3068     Register element = Int64{SIMD128Register{state_->cpu.v[src1]}.Get<ElementType>(0)};  in OpVectorVmvxs()
3402     if constexpr (sizeof(ElementType) < sizeof(Int64) &&  in OpVectorWidenv()
3424     if constexpr (sizeof(ElementType) < sizeof(Int64) &&  in OpVectorWidenvv()
3445     if constexpr (sizeof(ElementType) < sizeof(Int64) &&  in OpVectorWidenvvw()
3466     if constexpr (sizeof(ElementType) < sizeof(Int64) &&  in OpVectorWidenwv()
3486     if constexpr (sizeof(ElementType) < sizeof(Int64) &&  in OpVectorWidenwx()
3506     if constexpr (sizeof(ElementType) < sizeof(Int64) &&  in OpVectorWidenvx()
3526     if constexpr (sizeof(ElementType) < sizeof(Int64) &&  in OpVectorWidenvxw()
3668     if constexpr (sizeof(TargetElementType) < sizeof(Int64) &&  in OpVectorNarroww()
3689     if constexpr (sizeof(ElementType) < sizeof(Int64) &&  in OpVectorNarrowwx()
3710     if constexpr (sizeof(ElementType) < sizeof(Int64) &&  in OpVectorNarrowwv()