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"  #  $  %  &  '  (  )  *  +  ,  -  .  /  0  1  2  3   4   5   6 ! 7 ! 8 ! 9 " : " ; " < # = # > # ? $ @ $ A $ B % C % D % E & F & G & H ' I ' J ' K ( L ( M ( N ) O ) P ) Q * R * S * T + U + V + W , X , Y , Z - [ - \ - ] . ^ . _ . ` / a / b / c 0 d 0 e 0 f 1 g 1 h 1 i 2 j 2 k 2 l 3 m 3 n 3 o 4 p 4 q 4 r 5 s 5 t 5 u 6 v 6 w 6 x 7 y 7 z 7 { 8 | 8 } 8 ~ 9  9  9  :  :  :  ;  ;  ;  <  <  <  =  =  =  >  >  >  ?  ?  ?  @  @  @  A  A  A  B  B  B  C  C  C  D  D  D  E  E  E  F  F  F  G  G  G  H  H  H  I  I  I  J  J  J  K  K  K  L  L  L  M  M  M  N  N  N  O  O  O  P  P  P  Q  Q  Q  R  R  R  S  S  S  T  T  T  U  U  U  V  V  V  W  W  W  X  X  X  Y  Y  Y  Z  Z  Z  [  [  [  \  \  \  ]  ]  ]  ^  ^  ^  _  _  _  `  `  `  a  a  a  b  b  b  c  c  c  d  d  d  e  e  e  f  f  f  g  g  g  h  h  h  i  i  i  j  j  j  k  k  k  l  l  l  m  m  m  n  n  n  o ! o " o # p $ p % p & q ' q ( q ) r * r + r , s - s . s / t 0 t 1 t 2 u 3 u 4 u 5 v 6 v 7 v 8 w 9 w : w ; x < x = x > y ? y @ y A z B z C z D { E { F { G | H | I | J } K } L } M ~ N ~ O ~ P  Q  R  S  T  U  V  W  X  Y  Z  [  \  ]  ^  _  `  a  b  c  d  e  f  g  h  i  j  k  l  m  n  o  p  q  r  s  t  u  v  w  x  y  z  {  |  }  ~                                                                                                                                                                                                                                                                                                                                      !  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"  #  $  %  &  '  (  )  *  +  ,  -  .  /  0  1  2  3   4   5   6 ! 7 ! 8 ! 9 " : " ; " < # = # > # ? $ @ $ A $ B % C % D % E & F & G & H ' I ' J ' K ( L ( M ( N ) O ) P ) Q * R * S * T + U + V + W , X , Y , Z - [ - \ - ] . ^ . _ . ` / a / b / c 0 d 0 e 0 f 1 g 1 h 1 i 2 j 2 k 2 l 3 m 3 n 3 o 4 p 4 q 4 r 5 s 5 t 5 u 6 v 6 w 6 x 7 y 7 z 7 { 8 | 8 } 8 ~ 9  9  9  :  :  :  ;  ;  ;  <  <  <  =  =  =  >  >  >  ?  ?  ?  @  @  @  A  A  A  B  B  B  C  C  C  D  D  D  E  E  E  F  F  F  G  G  G  H  H  H  I  I  I  J  J  J  K  K  K  L  L  L  M  M  M  N  N  N  O  O  O  P  P  P  Q  Q  Q  R  R  R  S  S  S  T  T  T  U  U  U  V  V  V  W  W  W  X  X  X  Y  Y  Y  Z  Z  Z  [  [  [  \  \  \  ]  ]  ]  ^  ^  ^  _  _  _  `  `  `  a  a  a  b  b  b  c  c  c  d  d  d  e  e  e  f  f  f  g  g  g  h  h  h  i  i  i  j  j  j  k  k  k  l  l  l  m  m  m  n  n  n  o ! o " o # p $ p % p & q ' q ( q ) r * r + r , s - s . s / t 0 t 1 t 2 u 3 u 4 u 5 v 6 v 7 v 8 w 9 w : w ; x < x = x > y ? y @ y A z B z C z D { E { F { G | H | I | J } K } L } M ~ N ~ O ~ P  Q  R  S  T  U  V  W  X  Y  Z  [  \  ]  ^  _  `  a  b  c  d  e  f  g  h  i  j  k  l  m  n  o  p  q  r  s  t  u  v  w  x  y  z  {  |  }  ~                                                                                                                                                                                                                                                                                                                                      !  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"  #  $  %  &  '  (  )  *  +  ,  -  .  /  0  1  2  3   4   5   6 ! 7 ! 8 ! 9 " : " ; " < # = # > # ? $ @ $ A $ B % C % D % E & F & G & H ' I ' J ' K ( L ( M ( N ) O ) P ) Q * R * S * T + U + V + W , X , Y , Z - [ - \ - ] . ^ . _ . ` / a / b / c 0 d 0 e 0 f 1 g 1 h 1 i 2 j 2 k 2 l 3 m 3 n 3 o 4 p 4 q 4 r 5 s 5 t 5 u 6 v 6 w 6 x 7 y 7 z 7 { 8 | 8 } 8 ~ 9  9  9  :  :  :  ;  ;  ;  <  <  <  =  =  =  >  >  >  ?  ?  ?  @  @  @  A  A  A  B  B  B  C  C  C  D  D  D  E  E  E  F  F  F  G  G  G  H  H  H  I  I  I  J  J  J  K  K  K  L  L  L  M  M  M  N  N  N  O  O  O  P  P  P  Q  Q  Q  R  R  R  S  S  S  T  T  T  U  U  U  V  V  V  W  W  W  X  X  X  Y  Y  Y  Z  Z  Z  [  [  [  \  \  \  ]  ]  ]  ^  ^  ^  _  _  _  `  `  `  a  a  a  b  b  b  c  c  c  d  d  d  e  e  e  f  f  f  g  g  g  h  h  h  i  i  i  j  j  j  k  k  k  l  l  l  m  m  m  n  n  n  o ! o " o # p $ p % p & q ' q ( q ) r * r + r , s - s . s / t 0 t 1 t 2 u 3 u 4 u 5 v 6 v 7 v 8 w 9 w : w ; x < x = x > y ? y @ y A z B z C z D { E { F { G | H | I | J } K } L } M ~ N ~ O ~ P  Q  R  S  T  U  V  W  X  Y  Z  [  \  ]  ^  _  `  a  b  c  d  e  f  g  h  i  j  k  l  m  n  o  p  q  r  s  t  u  v  w  x  y  z  {  |  }  ~                                                                                                                                                                                                                                                                                                                                      !  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"  #  $  %  &  '  (  )  *  +  ,  -  .  /  0  1  2  3   4   5   6 ! 7 ! 8 ! 9 " : " ; " < # = # > # ? $ @ $ A $ B % C % D % E & F & G & H ' I ' J ' K ( L ( M ( N ) O ) P ) Q * R * S * T + U + V + W , X , Y , Z - [ - \ - ] . ^ . _ . ` / a / b / c 0 d 0 e 0 f 1 g 1 h 1 i 2 j 2 k 2 l 3 m 3 n 3 o 4 p 4 q 4 r 5 s 5 t 5 u 6 v 6 w 6 x 7 y 7 z 7 { 8 | 8 } 8 ~ 9  9  9  :  :  :  ;  ;  ;  <  <  <  =  =  =  >  >  >  ?  ?  ?  @  @  @  A  A  A  B  B  B  C  C  C  D  D  D  E  E  E  F  F  F  G  G  G  H  H  H  I  I  I  J  J  J  K  K  K  L  L  L  M  M  M  N  N  N  O  O  O  P  P  P  Q  Q  Q  R  R  R  S  S  S  T  T  T  U  U  U  V  V  V  W  W  W  X  X  X  Y  Y  Y  Z  Z  Z  [  [  [  \  \  \  ]  ]  ]  ^  ^  ^  _  _  _  `  `  `  a  a  a  b  b  b  c  c  c  d  d  d  e  e  e  f  f  f  g  g  g  h  h  h  i  i  i  j  j  j  k  k  k  l  l  l  m  m  m  n  n  n  o ! o " o # p $ p % p & q ' q ( q ) r * r + r , s - s . s / t 0 t 1 t 2 u 3 u 4 u 5 v 6 v 7 v 8 w 9 w : w ; x < x = x > y ? y @ y A z B z C z D { E { F { G | H | I | J } K } L } M ~ N ~ O ~ P  Q  R  S  T  U  V  W  X  Y  Z  [  \  ]  ^  _  `  a  b  c  d  e  f  g  h  i  j  k  l  m  n  o  p  q  r  s  t  u  v  w  x  y  z  {  |  }  ~                                                                                                                                                                                                                                                                                                                                      !  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"  #  $  %  &  '  (  )  *  +  ,  -  .  /  0  1  2  3  4  5  6 ! 7 ! 8 ! 9 " : " ; " < # = # > # ? $ @ $ A $ B % C % D % E & F & G & H ' I ' J ' K ( L ( M ( N ) O ) P ) Q * R * S * T + U + V + W , X , Y , Z - [ - \ - ] . ^ . _ . ` / a / b / c 0 d 0 e 0 f 1 g 1 h 1 i 2 j 2 k 2 l 3 m 3 n 3 o 4 p 4 q 4 r 5 s 5 t 5 u 6 v 6 w 6 x 7 y 7 z 7 { 8 | 8 } 8 ~ 9  9  9  :  :  :  ;  ;  ;  <  <  <  =  =  =  >  >  >  ?  ?  ?  @  @  @  A  A  A  B  B  B  C  C  C  D  D  D  E  E  E  F  F  F  G  G  G  H  H  H  I  I  I  J  J  J  K  K  K  L  L  L  M  M  M  N  N  N  O  O  O  P  P  P  Q  Q  Q  R  R  R  S  S  S  T  T  T  U  U  U  V  V  V  W  W  W  X  X  X  Y  Y  Y  Z  Z  Z  [  [  [  \  \  \  ]  ]  ]  ^  ^  ^  _  _  _  `  `  `  a  a  a  b  b  b  c  c  c  d  d  d  e  e  e  f  f  f  g  g  g  h  h  h  i  i  i  j  j  j  k  k  k  l  l  l  m  m  m  n  n  n  o ! o " o # p $ p % p & q ' q ( q ) r * r + r , s - s . s / t 0 t 1 t 2 u 3 u 4 u 5 v 6 v 7 v 8 w 9 w : w ; x < x = x > y ? y @ y A z B z C z D { E { F { G | H | I | J } K } L } M ~ N ~ O ~ P  Q  R  S  T  U  V  W  X  Y  Z  [  \  ]  ^  _  `  a  b  c  d  e  f  g  h  i  j  k  l  m  n  o  p  q  r  s  t  u  v  w  x  y  z  {  |  }  ~                                                                                                                                                                                                                                                                                                                                      !  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"  #  $  %  &  '  (  )  *  +  ,  -  .  /  0  1  2  3  4  5  6 ! 7 ! 8 ! 9 " : " ; " < # = # > # ? $ @ $ A $ B % C % D % E & F & G & H ' I ' J ' K ( L ( M ( N ) O ) P ) Q * R * S * T + U + V + W , X , Y , Z - [ - \ - ] . ^ . _ . ` / a / b / c 0 d 0 e 0 f 1 g 1 h 1 i 2 j 2 k 2 l 3 m 3 n 3 o 4 p 4 q 4 r 5 s 5 t 5 u 6 v 6 w 6 x 7 y 7 z 7 { 8 | 8 } 8 ~ 9  9  9  :  :  :  ;  ;  ;  <  <  <  =  =  =  >  >  >  ?  ?  ?  @  @  @  A  A  A  B  B  B  C  C  C  D  D  D  E  E  E  F  F  F  G  G  G  H  H  H  I  I  I  J  J  J  K  K  K  L  L  L  M  M  M  N  N  N  O  O  O  P  P  P  Q  Q  Q  R  R  R  S  S  S  T  T  T  U  U  U  V  V  V  W  W  W  X  X  X  Y  Y  Y  Z  Z  Z  [  [  [  \  \  \  ]  ]  ]  ^  ^  ^  _  _  _  `  `  `  a  a  a  b  b  b  c  c  c  d  d  d  e  e  e  f  f  f  g  g  g  h  h  h  i  i  i  j  j  j  k  k  k  l  l  l  m  m  m  n  n  n  o ! o " o # p $ p % p & q ' q ( q ) r * r + r , s - s . s / t 0 t 1 t 2 u 3 u 4 u 5 v 6 v 7 v 8 w 9 w : w ; x < x = x > y ? y @ y A z B z C z D { E { F { G | H | I | J } K } L } M ~ N ~ O ~ P  Q  R  S  T  U  V  W  X  Y  Z  [  \  ]  ^  _  `  a  b  c  d  e  f  g  h  i  j  k  l  m  n  o  p  q  r  s  t  u  v  w  x  y  z  {  |  }  ~                                                                                                                                                                                                                                                                                                                                      !  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X / Y / Z / [ 0 \ 0 ] 0 ^ 1 _ 1 ` 1 a 2 b 2 c 2 d 3 e 3 f 3 g 4 h 4 i 4 j 5 k 5 l 5 m 6 n 6 o 6 p 7 q 7 r 7 s 8 t 8 u 8 v 9 w 9 x 9 y : z : { : | ; } ; ~ ;  < < < = = = > > > ? ? ? @ @ @ A A A B B B C C C D D D E E E F F F G G G H H H I I I J J J K K K L L L M M M N N N O O O P P P Q Q Q R R R S S S T T T U U U V V V W W W X X X Y Y Y Z Z Z [ [ [ \ \ \ ] ] ] ^ ^ ^ _ _ _ ` ` ` a a a b b b c c c d d d e e e f f f ! g ! g ! g ! h ! h ! h ! i ! i ! i ! j ! j ! j ! k ! k ! k ! l ! l ! l ! m ! m ! m ! n ! n ! n ! o ! o ! o ! p ! p ! p ! q ! q ! q !! r "! r #! r $! s %! s &! s '! t (! t )! t *! u +! u ,! u -! v .! v /! v 0! w 1! w 2! w 3! x 4! x 5! x 6! y 7! y 8! y 9! z :! z ;! z ! { ?! | @! | A! | B! } C! } D! } E! ~ F! ~ G! ~ H!  I!  J!  K!  L!  M!  N!  O!  P!  Q!  R!  S!  T!  U!  V!  W!  X!  Y!  Z!  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" # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~                                                                                                                                                                         ! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~                                                                                                                                                                         ! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~                                                                                                                                                                         ! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~                                                                                                                                                                         ! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~                                                                                                                                                                         ! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~                                                                   /   prpr@AAD@-@-X  / /j  C ` q ++IIDX jE U"0Pi0n~@BP{ N  Xh0W@'U"(5 x? h nZ22)p *           y5 x- $ y5 ) $ (u5 ) $O > >                     pd-g3dpd-embedded_g3d@pd-dpubpd-dpuf0pd-dpuf1pd-g2d@pd-gdcpd-gsepd-mcsc@pd-mfc@pd-rgbppd-tnrpd-aoc pd-aur`pd-bwpd-ehpd-yuvppd-hsi0pd-hsi1pd-ispfe0pd-tpuIO3pll mux change time out, '%s' 3%s 3%s %s: error on PA2VA conversion. seq:save, pd_id:%d. aborting init... 3%s %s: error on PA2VA conversion. seq:enable, cluster_id:%d. aborting init... G3D_CONFIGURATIONPLL_CON2_PLL_G3DQCH_CON_RSTNSYNC_CLK_G3D_DD_QCHDBG_NFO_QCH_CON_GPC_G3D_QCHDBG_NFO_QCH_CON_SLH_AXI_MI_P_DPUB_QCHQCH_CON_LH_AXI_SI_D1_DPUF0_QCHDPUF1_CONFIGURATIONDBG_NFO_QCH_CON_PPMU_D1_DPUF1_QCHQCH_CON_SYSMMU_S0_PMMU0_G2D_QCHQCH_CON_QE_D0_GDC0_QCHDBG_NFO_QCH_CON_LH_AST_MI_ID_GDC1_LME_QCHDBG_NFO_QCH_CON_QE_D0_GDC1_QCHDBG_NFO_QCH_CON_SYSMMU_S0_PMMU1_GDC_QCH_S0QCH_CON_SYSMMU_S0_GSE_QCH_S0QCH_CON_MCSC_QCHQCH_CON_QE_D3_MCSC_QCHPLL_CON0_MUX_CLKCMU_MFC_MFC_USERDBG_NFO_QCH_CON_SLH_AXI_MI_P_MFC_QCHQCH_CON_LH_AXI_SI_D4_RGBP_QCHQCH_CON_SYSMMU_S0_PMMU0_RGBP_QCH_S0QCH_CON_SYSMMU_S1_PMMU3_RGBP_QCH_S0DBG_NFO_QCH_CON_QE_D4_MCFP_QCHDBG_NFO_QCH_CON_SSMT_D2_MCFP_QCHQCH_CON_QE_D6_TNR_QCHQCH_CON_SSMT_D0_TNR_QCHDBG_NFO_QCH_CON_LH_AST_SI_L_OTF_TNR_GSE_QCHDBG_NFO_QCH_CON_QE_D2_TNR_QCHDBG_NFO_QCH_CON_SSMT_D6_TNR_QCHDBG_NFO_QCH_CON_LH_AST_SI_L_OTF_YUVP_TNR_QCHDBG_NFO_QCH_CON_SYSMMU_S0_PMMU0_YUVP_QCH_S0DMYQCH_CON_ADD_AUR_QCHDMYQCH_CON_AUR_QCHQCH_CON_LH_ACEL_SI_D1_AUR_QCHDBG_NFO_QCH_CON_GPC_AUR_QCHQCH_CON_PPMU_D2_ISPFE_QCHDBG_NFO_QCH_CON_LH_AXI_SI_IP_ISPFE_QCHQCH_CON_GPC_TPU_QCHQCH_CON_SYSMMU_S0_PMMU1_TPU_QCHDBG_NFO_QCH_CON_ADD_APBIF_TPU_QCHTPU_HCHGEN_CLKMUX_LPMQCH_CON_NOCL0_CMU_NOCL0_QCHDBG_NFO_QCH_CON_LH_AST_MI_G_NOCL1B_QCHDBG_NFO_QCH_CON_LH_AXI_SI_P_MIF3_CD_QCHCLK_CON_DIV_DIV_CLK_NOCL1A_NOCPQCH_CON_LH_AST_SI_G_NOCL1A_QCHQCH_CON_LH_TAXI_SI_D1_NOCL1A_NOCL0_QCHQCH_CON_PPC_BW_D_CYCLE_QCHQCH_CON_LH_AST_SI_G_NOCL1B_CD_QCHQCH_CON_TREX_P_NOCL1B_QCHDBG_NFO_QCH_CON_LH_TAXI_MI_P_NOCL0_NOCL1B_QCHDBG_NFO_QCH_CON_LH_AXI_MI_D0_ISPFE_QCHDBG_NFO_QCH_CON_LH_AXI_MI_D3_ISPFE_QCHPLL_LOCKTIME_PLL_USBQCH_CON_I3C3_HSI0_QCH_PCLKQCH_CON_USI4_HSI0_QCHDBG_NFO_DMYQCH_CON_I3C3_HSI0_QCH_SCLKDBG_NFO_QCH_CON_SLH_AXI_MI_LG_ETR_HSI0_QCHDBG_NFO_QCH_CON_SSMT_HSI1_QCHDBG_NFO_QCH_CON_SYSREG_HSI1_QCHCPUCL1_CLKDIVSTEP_CON_LIGHTEXT_REGULATOR_MIF_DURATIONPLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USERQCH_CON_SLH_AXI_SI_LP_ALIVE_CPUCL0_QCHDBG_NFO_QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCHDBG_NFO_QCH_CON_LH_AXI_SI_LP_AOC_ALIVE_CU_QCHDBG_NFO_QCH_CON_MAILBOX_AP_AOCA32_QCHDBG_NFO_QCH_CON_MAILBOX_AP_AURMCUNS0_QCHQCH_CON_WDT_CLUSTER0_QCHQCH_CON_LH_AXI_MI_P_HSI2_CU_QCHQCH_CON_PCIE_GEN3A_1_QCH_APBQCH_CON_SYSMMU_S0_HSI2_QCHQCH_CON_D_TZPC_PERIC0_QCHQCH_CON_I3C1_QCH_PCLKDBG_NFO_DMYQCH_CON_I3C1_QCH_SCLKDBG_NFO_DMYQCH_CON_I3C6_QCH_SCLKDBG_NFO_QCH_CON_SYSREG_PERIC1_QCHCLKOUT_CON_BLK_CPUCL0_CMU_CPUCL0_CLKOUT0CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT0PLL_CPUCL0MUX_CLKCMU_HSI0_NOC_USERMUX_CLKCMU_NOCL2AB_NOC_USERCLKCMU_GDC_LMECLKCMU_RGBP_MCFPDIV_CLK_CLUSTER0_PERIPHCLKDIV_CLK_CPUCL2_CMUREFDIV_CLK_PERIC1_USI0_USIDIV_CLK_RGBP_NOCPGOUT_BLK_AOC_UID_D_TZPC_AOC_IPCLKPORT_PCLKCLK_BLK_AOC_UID_RSTNSYNC_SR_CLK_AOC_NOC_IPCLKPORT_CLKGOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLKGOUT_BLK_APM_UID_RTC_IPCLKPORT_PCLKGOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLKCLK_BLK_APM_UID_LH_AXI_MI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLKCLK_BLK_APM_UID_MAILBOX_AOC_AURCORE2_IPCLKPORT_PCLKGOUT_BLK_BW_UID_UASC_BW_IPCLKPORT_PCLKGATE_CLKCMU_CIS_CLK7CLKCMU_NOCL1A_BOOSTGATE_CLKCMU_CPUCL2_SWITCHGATE_CLKCMU_AUR_NOCCLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_PCLK_LH_IPCLKPORT_CLKCLK_BLK_CPUCL0_UID_PPMU_CPUCL0_D3_IPCLKPORT_PCLKCLK_BLK_CPUCL0_UID_LH_ACEL_SI_D3_CPUCL0_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_NPRESET_IPCLKPORT_CLKCLK_BLK_CPUCL0_UID_LH_ACEL_MI_D1_NOCL0_CPUCL0_IPCLKPORT_I_CLKGOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPUFGOUT_BLK_DPUF1_UID_SYSMMU_S0_PMMU0_DPUF1_IPCLKPORT_CLKCLK_BLK_DPUF1_UID_PPMU_D1_DPUF1_IPCLKPORT_PCLKCLK_BLK_DPUF1_UID_BLK_DPUF1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLKCLK_BLK_EH_UID_RSTNSYNC_SR_CLK_EH_NOCP_IPCLKPORT_CLKCLK_BLK_G3D_UID_SSMT_G3D0_IPCLKPORT_ACLKCLK_BLK_G3D_UID_SYSMMU_S0_PMMU2_G3D_IPCLKPORT_CLKGOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC1_IPCLKPORT_CLKCLK_BLK_GDC_UID_SSMT_D2_GDC0_IPCLKPORT_ACLKGOUT_BLK_GSACORE_UID_WDT_GSACORE_IPCLKPORT_PCLKGOUT_BLK_GSACTRL_UID_MAILBOX_GSA2NONTZ_IPCLKPORT_PCLKCLK_BLK_GSACTRL_UID_SSMT_GSACTRL_IPCLKPORT_PCLKGOUT_BLK_GSE_UID_PPMU_D0_GSE_IPCLKPORT_PCLKGOUT_BLK_GSE_UID_PPMU_D2_GSE_IPCLKPORT_PCLKCLK_BLK_HSI0_UID_USI0_HSI0_IPCLKPORT_IPCLKCLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_I3C_IPCLKPORT_CLKGOUT_BLK_HSI1_UID_PCIE_GEN3_0_IPCLKPORT_PCIE_PHY_TOP_INST_0_PHY_UDBG_I_APB_PCLKCLK_BLK_HSI2_UID_PCIE_GEN3A_1_IPCLKPORT_PCIE_SUB_CTRL_A_G3X1_PHY_REFCLK_INCLK_BLK_HSI2_UID_PCIE_GEN3A_1_IPCLKPORT_PCIE_PHY_TOP_X1_INST_0_SF_PCIEPHY_X1_QCH_TM_WRAPPER_INST_0_I_APB_PCLKGOUT_BLK_ISPFE_UID_SSMT_D0_ISPFE_IPCLKPORT_ACLKCLK_BLK_ISPFE_UID_SYSMMU_S2_ISPFE_IPCLKPORT_CLKCLK_BLK_ISPFE_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS7GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLKGOUT_BLK_MIF_UID_LH_AXI_MI_P_MIF_CU_IPCLKPORT_I_CLKGOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLKGOUT_BLK_MISC_UID_SYSMMU_S0_PMMU0_MISC_IPCLKPORT_CLKGOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLKCLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_SLC2_ACLK_IPCLKPORT_CLKGOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLKGOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_IPCLKPORT_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out, '%s'6cmu_top_base : 0x%x ----------------------------------------------------- activeecho id > dvfs_domain 3%s %s: error on PA2VA conversion. seq:disable, core_id:%d. aborting init... pmucal_rae_waitCLK_CON_DIV_DIV_CLK_G3D_L2_GLBDBG_NFO_QCH_CON_SSMT_G3D3_QCHDBG_NFO_QCH_CON_SYSMMU_S0_PMMU3_G3D_QCH_S0G3D_CLKDIVSTEP_VDROOP_FLTQCH_CON_D_TZPC_DPUF0_QCHQCH_CON_DPUF1_CMU_DPUF1_QCHQCH_CON_LH_AST_MI_ID_LME_GDC1_QCHQCH_CON_LH_AST_SI_ID_GDC0_GDC1_QCHDBG_NFO_QCH_CON_LH_AXI_SI_D1_GDC_QCHDBG_NFO_QCH_CON_LME_QCH_CLKQCH_CON_SYSREG_GSE_QCHQCH_CON_GPC_MCSC_QCHQCH_CON_LH_AST_MI_L_OTF_TNR_MCSC_QCHQCH_CON_SSMT_D5_MCSC_QCHQCH_CON_SYSMMU_S0_PMMU1_MCSC_QCH_S0PLL_CON0_MUX_CLKCMU_RGBP_MCFP_USERQCH_CON_QE_D3_RGBP_QCHQCH_CON_QE_D5_MCFP_QCHDBG_NFO_QCH_CON_LH_AXI_SI_D1_RGBP_QCHDBG_NFO_QCH_CON_LH_AXI_SI_D5_RGBP_QCHDBG_NFO_QCH_CON_QE_D10_MCFP_QCHDBG_NFO_QCH_CON_SSMT_D3_MCFP_QCHQCH_CON_LH_AST_MI_L_OTF_YUVP_TNR_QCHQCH_CON_QE_D10_TNRA_QCHQCH_CON_QE_D2_TNR_QCHDBG_NFO_QCH_CON_GTNR_MERGE_QCH_00DBG_NFO_QCH_CON_SYSMMU_S2_PMMU0_TNR_QCH_S0QCH_CON_LH_AXI_SI_D_YUVP_QCHDBG_NFO_QCH_CON_GPC_YUVP_QCHDBG_NFO_QCH_CON_QE_D1_YUVP_QCHDBG_NFO_QCH_CON_SLH_AXI_MI_P_YUVP_QCHCLK_CON_DIV_DIV_CLK_AUR_NOCPCLK_CON_MUX_MUX_CLK_AUR_AURQCH_CON_SSMT_D0_AUR_QCHDBG_NFO_QCH_CON_BAAW_AUR_QCHDBG_NFO_QCH_CON_SLH_AXI_MI_P_AUR_QCHDBG_NFO_QCH_CON_LH_AXI_MI_IP_BW_QCHQCH_CON_D_TZPC_ISPFE_QCHQCH_CON_QE_D0_ISPFE_QCHDBG_NFO_QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CD_QCHQCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CD_QCHDBG_NFO_QCH_CON_GPC_TPU_QCHDBG_NFO_QCH_CON_LH_AXI_SI_P_TPU_CU_QCHCLK_CON_MUX_MUX_CLK_NOCL0_NOCQCH_CON_LH_AST_MI_G_NOCL1A_QCHQCH_CON_PPC_NOCL1A_M3_EVENT_QCHQCH_CON_SYSREG_NOCL0_QCHDBG_NFO_QCH_CON_SLH_AXI_SI_P_MISC_QCHQCH_CON_SLH_AXI_SI_P_AUR_QCHQCH_CON_SLH_AXI_SI_P_G3D_QCHQCH_CON_LH_AST_MI_G_NOCL1B_CD_QCHQCH_CON_LH_AXI_MI_P_HSI0_CD_QCHQCH_CON_LH_AXI_SI_G_CSSYS_CU_QCHDBG_NFO_QCH_CON_LH_AXI_MI_P_GSA_CD_QCHDBG_NFO_QCH_CON_SLH_AXI_MI_G_CSSYS_QCHCLK_CON_DIV_DIV_CLK_NOCL2AA_NOCPQCH_CON_TREX_D_NOCL2AA_QCHQCH_CON_LH_ACEL_MI_D_MISC_QCHQCH_CON_LH_AXI_MI_D2_GDC_QCHQCH_CON_TREX_P_NOCL2AB_QCHPLL_CON6_PLL_USBQCH_CON_LH_AXI_SI_LD_HSI0_AOC_QCHDMYQCH_CON_I3C3_HSI0_QCH_SCLKDBG_NFO_QCH_CON_LH_AXI_SI_LP_AOC_HSI0_CU_QCHDBG_NFO_QCH_CON_SSMT_HSI0_QCHDBG_NFO_QCH_CON_SYSMMU_S0_HSI0_QCH_S0DBG_NFO_QCH_CON_PCIE_GEN3_0_QCH_AXIDBG_NFO_QCH_CON_SYSMMU_S0_HSI1_QCH_S0blkpwr_rgbpblkpwr_nocl1bPWRMGMT_BUNDLE_PwrMgmtMode2CLK_CON_DIV_DIV_CLK_APM_NOCPLL_CON0_MUX_CLKCMU_PERIC0_NOC_USERPLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USERQCH_CON_APBIF_PMU_ALIVE_QCHQCH_CON_LH_AXI_MI_LP_AOC_ALIVE_CU_QCHQCH_CON_PMU_INTR_GEN_QCHDBG_NFO_QCH_CON_APM_I3C_PMIC_QCH_PDBG_NFO_QCH_CON_TRTC_QCHQCH_CON_MCT_V41_QCHQCH_CON_SYSMMU_S0_PMMU0_MISC_QCHQCH_CON_WDT_CLUSTER1_QCHDBG_NFO_QCH_CON_DIT_QCHDBG_NFO_QCH_CON_QE_DIT_QCHQCH_CON_QE_UFS_EMBD_HSI2_QCHDMYQCH_CON_I3C1_QCH_SCLKQCH_CON_I3C3_QCH_PCLKDBG_NFO_QCH_CON_I3C5_QCH_PCLKQCH_CON_GPC_PERIC1_QCHQCH_CON_USI0_USI_QCHQCH_CON_USI9_USI_QCHPLL_AURMUX_CLKCMU_PERIC0_NOCMUX_CLKCMU_CIS_CLK4MUX_CLKCMU_HSI0_USB20_USERMUX_CLKCMU_PERIC0_USI2_USI_USERMUX_CLKCMU_RGBP_RGBP_USERCLKCMU_MISC_NOCDIV_CLK_GSACTRL_NOCPDIV_CLK_HSI0_USI1DIV_CLK_NOCL1B_NOCPDIV_CLK_PERIC0_USI6_USIDIV_CLK_PERIC0_I3CDIV_CLK_PERIC1_USI12_USIDIV_CLK_TPU_NOCPDIV_CLK_CPUCL1_CPUGOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_PCLKGOUT_BLK_APM_UID_SSMT_LP_ALIVE_CPUCL0_IPCLKPORT_PCLKGOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLKCLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLKCLK_BLK_APM_UID_GPC_APM_CUSTOM_IPCLKPORT_PCLKCLK_BLK_AUR_UID_RSTNSYNC_SR_CLK_AUR_NOCD_IPCLKPORT_CLKCLKCMU_NOCL1B_BOOSTGATE_CLKCMU_RGBP_MCFPCLK_BLK_CPUCL0_UID_LH_AXI_MI_G_CSSYS_CD_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_LH_ATB_SI_T_SLC_CU_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_PPMU_CPUCL0_D0_IPCLKPORT_PCLKCLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_PCLK_IPCLKPORT_CLKGOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_OSCCLK_IPCLKPORT_CLKCLK_BLK_EH_UID_SLH_AXI_MI_P_EH_IPCLKPORT_I_CLKCLK_BLK_EH_UID_PPC_EH_EVENT_IPCLKPORT_PCLKGOUT_BLK_G2D_UID_GPC_G2D_IPCLKPORT_PCLKCLK_BLK_G3D_UID_PPCFW_G3D0_IPCLKPORT_PCLKCLK_BLK_G3D_UID_SSMT_G3D0_IPCLKPORT_PCLKGOUT_BLK_GDC_UID_SLH_AXI_MI_P_GDC_IPCLKPORT_I_CLKCLK_BLK_GDC_UID_PPMU_D2_GDC1_IPCLKPORT_ACLKCLK_BLK_GDC_UID_PPMU_D4_GDC0_IPCLKPORT_PCLKCLK_BLK_GDC_UID_SSMT_D2_GDC0_IPCLKPORT_PCLKCLK_BLK_GDC_UID_QE_D0_GDC1_IPCLKPORT_PCLKGOUT_BLK_GSACORE_UID_LH_AST_MI_I_CA32_GIC_IPCLKPORT_I_CLKGOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLKCLK_BLK_HSI0_UID_USI2_HSI0_IPCLKPORT_PCLKCLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_USI3_IPCLKPORT_CLKCLK_BLK_HSI0_UID_USI4_HSI0_IPCLKPORT_IPCLKGOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLKCLK_BLK_HSI2_UID_SLH_AXI_MI_P_HSI2_IPCLKPORT_I_CLKGOUT_BLK_ISPFE_UID_SYSMMU_S0_PMMU1_ISPFE_IPCLKPORT_CLKCLK_BLK_ISPFE_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS2CLK_BLK_ISPFE_UID_BLK_ISPFE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLKCLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCD_IPCLKPORT_CLKGOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_PCLKCLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCD_IPCLKPORT_CLKCLK_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLKGOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_ACLKGOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_ACLKGOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLKCLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLKGOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLKGOUT_BLK_NOCL0_UID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LK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLKGOUT_BLK_MISC_UID_LH_AXI_MI_P_MISC_GIC_CU_IPCLKPORT_I_CLKCLK_BLK_MISC_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLKCLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_PCLKCLK_BLK_MISC_UID_PDMA1_IPCLKPORT_ACLKCLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1A_CU_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2AB_CU_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_PPMU_NOCL0_IOC1_IPCLKPORT_ACLKGOUT_BLK_NOCL1A_UID_PPC_NOCL2AA_S1_EVENT_IPCLKPORT_ACLKGOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI1_CD_IPCLKPORT_I_CLKCLK_BLK_NOCL2AA_UID_NOCL2AA_CMU_NOCL2AA_IPCLKPORT_PCLKCLK_BLK_NOCL2AA_UID_BLK_NOCL2AA_FRC_OTP_DESERIAL_IPCLKPORT_I_CLKCLK_BLK_NOCL2AB_UID_LH_ACEL_MI_D2_G2D_IPCLKPORT_I_CLKCLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLKGOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLKCLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_PCLKCLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_IPCLKCLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLKGOUT_BLK_RGBP_UID_RSTNSYNC_CLK_RGBP_NOCP_IPCLKPORT_CLKCLK_BLK_RGBP_UID_PPMU_D0_MCFP_IPCLKPORT_ACLKCLK_BLK_RGBP_UID_QE_D4_MCFP_IPCLKPORT_PCLKCLK_BLK_RGBP_UID_BLK_RGBP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLKGOUT_BLK_TNR_UID_SYSMMU_S1_PMMU1_TNR_IPCLKPORT_CLKCLK_BLK_TNR_UID_QE_D9_TNR_IPCLKPORT_ACLKCLK_BLK_TNR_UID_QE_D2_TNR_IPCLKPORT_PCLKCLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_OSCCLK_IPCLKPORT_CLKCLK_BLK_TPU_UID_RSTNSYNC_SR_CLK_TPU_TPUCTL_DBG_IPCLKPORT_CLKGOUT_BLK_YUVP_UID_SYSMMU_S0_PMMU0_YUVP_IPCLKPORT_CLKPLL_SHARED0_D3MAILBOX_AP_AURMCUNS0_QCHCLUSTER0_QCH_PDBGCLKLH_AXI_MI_P_CPUCL0_CU_QCHLH_AXI_SI_IP_CPUCL2_QCHPPC_INSTRRET_CLUSTER0_1_QCHGPC_DPUF1_QCHGDC_CMU_GDC_QCHQE_D2_GDC1_QCHSSMT_D2_GDC1_QCHSLH_AXI_MI_P_GSA_QCHQE_D1_GSE_QCHPPMU_D1_MCSC_QCHQE_D0_MCSC_QCHSSMT_SC_QCHLH_ATB_SI_T_SLC_QCHLH_AXI_SI_P_MIF3_CD_QCHLH_TAXI_MI_D1_NOCL1A_NOCL0_QCHLH_AST_MI_G_NOCL1A_CD_QCHPPC_G3D_D3_EVENT_QCHPPC_TPU_D0_CYCLE_QCHLH_AXI_SI_P_PERIC0_CU_QCHGPIO_PERIC1_QCHPPMU_D1_RGBP_QCHLH_AXI_SI_D1_TNR_QCHPPMU_D0_TNR_QCHSSMT_D2_TNR_QCHSSMT_D4_TNR_QCHCTRL_OPTION_CMU_AURCTRL_OPTION_CMU_CPUCL2VCLK_MUX_CLKCMU_PERIC0_IPVCLK_BLK_NOCL0VCLK_BLK_BWVCLK_IP_APBIF_INTCOMB_VGPIO2APVCLK_IP_LH_AXI_SI_LG_SCAN2DRAM_CDVCLK_IP_MAILBOX_AP_AURMCUNS4VCLK_IP_MAILBOX_AOC_AURMCUVCLK_IP_MAILBOX_APM_AURMCUVCLK_IP_D_TZPC_BWVCLK_IP_GRAY2BIN_TSVALUEBVCLK_IP_SYSMMU_S0_PMMU0_EHVCLK_IP_G2DVCLK_IP_D_TZPC_G2DVCLK_IP_SYSMMU_S0_G3DVCLK_IP_SYSMMU_S0_PMMU0_G3DVCLK_IP_SSMT_D0_GDC1VCLK_IP_SSMT_D4_GDC1VCLK_IP_LH_AXI_SI_ID_GME_GSAVCLK_IP_AD_APB_INTMEM_GSACTRLVCLK_IP_D_TZPC_GSEVCLK_IP_SLH_AXI_MI_P_GSEVCLK_IP_XIU_D1_GSEVCLK_IP_XIU_D2_HSI0VCLK_IP_UASC_PCIE_GEN3A_DBI_1VCLK_IP_PPMU_D3_ISPFEVCLK_IP_QE_D3_MCSCVCLK_IP_PPMU_D6_MCSCVCLK_IP_SYSREG_MFCVCLK_IP_MFCVCLK_IP_XIU_D_MFCVCLK_IP_D_TZPC_MIFVCLK_IP_QE_PDMA1VCLK_IP_LH_AXI_SI_P_MIF2_CDVCLK_IP_LH_AST_MI_G_NOCL1B_CDVCLK_IP_LH_AXI_MI_D5_RGBPVCLK_IP_SLH_AXI_SI_P_DPUF0VCLK_IP_LH_TAXI_SI_D1_NOCL2AB_NOCL1AVCLK_IP_LH_AST_MI_G_NOCL2AB_CDVCLK_IP_SYSMMU_S0_PMMU0_RGBPVCLK_IP_SYSMMU_S1_PMMU0_RGBPVCLK_IP_SSMT_D5_MCFPVCLK_IP_SSMT_D9_TNRCPUCL2INTCAMGEN3un-support pll type %7d - CMU_TOP GATE info 3%s %s: error on PA2VA conversion. seq:save, mode_id:%d. aborting init... pmucal_cpu_cluster_enable3%s %s: error on PA2VA conversion. seq:status, core_id:%d. aborting init... CLK_CON_DIV_DIV_CLK_G3D_TOPDBG_NFO_QCH_CON_LH_AXI_SI_P_G3D_CU_QCHDBG_NFO_QCH_CON_SSMT_G3D0_QCHDBG_NFO_QCH_CON_SYSMMU_S0_PMMU0_G3D_QCH_S0QCH_CON_DPUB_QCH_ALV_DSIM1DBG_NFO_QCH_CON_DPUB_QCHQCH_CON_SSMT_D0_DPUF0_QCHDBG_NFO_QCH_CON_DPUF1_CMU_DPUF1_QCHDBG_NFO_QCH_CON_SSMT_D0_DPUF1_QCHQCH_CON_D_TZPC_G2D_QCHQCH_CON_GPC_G2D_QCHQCH_CON_LH_AST_MI_ID_JPEG_G2D0_QCHQCH_CON_LH_AST_SI_ID_JPEG_G2D0_QCHQCH_CON_SSMT_D1_G2D_QCHDBG_NFO_QCH_CON_LH_AST_SI_ID_G2D1_JPEG_QCHQCH_CON_LH_AST_MI_ID_GDC1_LME_QCHQCH_CON_SSMT_D0_GDC1_QCHDBG_NFO_QCH_CON_GPC_GDC_QCHDBG_NFO_QCH_CON_LH_AST_MI_ID_LME_GDC1_QCHQCH_CON_LH_AST_MI_L_OTF_YUVP_GSE_QCHQCH_CON_MCSC_CMU_MCSC_QCHQCH_CON_PPMU_D4_MCSC_QCHDBG_NFO_QCH_CON_LH_AST_MI_L_OTF_YUVP_MCSC_QCHDBG_NFO_QCH_CON_LH_AXI_SI_D1_MCSC_QCHDBG_NFO_QCH_CON_SSMT_D4_MCSC_QCHQCH_CON_SSMT_D0_MFC_QCHQCH_CON_PPMU_D1_RGBP_QCHQCH_CON_PPMU_D2_RGBP_QCHQCH_CON_QE_D6_RGBP_QCHDBG_NFO_QCH_CON_QE_D2_RGBP_QCHQCH_CON_GTNR_MERGE_QCH_00QCH_CON_SYSMMU_S1_PMMU0_TNR_QCH_S0DBG_NFO_QCH_CON_D_TZPC_YUVP_QCHQCH_CON_LH_AXI_MI_P_AUR_CU_QCHDBG_NFO_DMYQCH_CON_ADD_AUR_QCHDBG_NFO_QCH_CON_BW_CMU_BW_QCHDBG_NFO_QCH_CON_SLH_AXI_MI_P_EH_QCHDBG_NFO_QCH_CON_SYSMMU_S0_EH_QCHPLL_CON0_MUX_CLKCMU_ISPFE_NOC_USERQCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6QCH_CON_SYSMMU_S1_PMMU0_ISPFE_QCH_S0DBG_NFO_QCH_CON_PPMU_D2_ISPFE_QCHPLL_CON0_MUX_CLKCMU_TPU_TPUCTL_USERQCH_CON_LH_ACEL_SI_D0_TPU_QCHQCH_CON_SYSREG_TPU_QCHQCH_CON_LH_AXI_SI_P_MISC_CD_QCHDBG_NFO_QCH_CON_D_TZPC_NOCL0_QCHDBG_NFO_QCH_CON_LH_AXI_MI_P_MIF1_CD_QCHDBG_NFO_DMYQCH_CON_SLC_CH3_QCHDBG_NFO_QCH_CON_NOCL0_CMU_NOCL0_QCHDBG_NFO_QCH_CON_PPMU_NOCL0_S1_QCHQCH_CON_LH_TAXI_MI_D0_NOCL2AA_NOCL1A_QCHQCH_CON_PPC_G3DMMU_D_EVENT_QCHDBG_NFO_QCH_CON_LH_ACEL_MI_D0_TPU_QCHDBG_NFO_QCH_CON_LH_TAXI_SI_D0_NOCL1A_NOCL0_QCHDBG_NFO_QCH_CON_PPC_NOCL2AB_S0_CYCLE_QCHDBG_NFO_QCH_CON_PPMU_NOCL1A_M2_QCHCLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_LHNOCL2AA_CONFIGURATIONQCH_CON_LH_AXI_MI_D3_RGBP_QCHQCH_CON_SLH_AXI_SI_P_MFC_QCHQCH_CON_SYSREG_NOCL2AA_QCHDBG_NFO_QCH_CON_LH_AXI_MI_D0_DPUF0_QCHDBG_NFO_QCH_CON_LH_AXI_MI_D0_TNR_QCHCLK_CON_DIV_DIV_CLK_HSI0_I3CQCH_CON_LH_AXI_SI_P_HSI0_CU_QCHQCH_CON_SYSMMU_S0_PMMU0_HSI0_QCH_S0DBG_NFO_QCH_CON_LH_AXI_SI_LD_HSI0_AOC_QCHDBG_NFO_QCH_CON_LH_AXI_MI_P_HSI1_CU_QCHDBG_NFO_QCH_CON_PCIE_GEN3_0_QCH_DBIDBG_NFO_QCH_CON_PCIE_GEN3_0_QCH_UDBGblkpwr_mcscblkpwr_hsi1CPUCL1_HCHGEN_CLKMUX_CPUBUS_COMPONENT_DRCG_EN_INTQCH_CON_MAILBOX_AP_AURCORE0_QCHDBG_NFO_QCH_CON_SYSMMU_S0_PMMU0_ALIVE_QCHQCH_CON_LH_ACEL_SI_D_MISC_QCHQCH_CON_QE_PDMA1_QCHQCH_CON_RTIC_QCHQCH_CON_SC_QCHDBG_NFO_QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_QCHDBG_NFO_QCH_CON_LH_AXI_SI_ID_SC_QCHDBG_NFO_QCH_CON_MCT_QCHQCH_CON_HSI2_CMU_HSI2_QCHQCH_CON_PCIE_GEN3B_1_QCH_PCS_APBQCH_CON_UFS_EMBD_QCHDBG_NFO_QCH_CON_PCIE_GEN3A_1_QCH_DBGQCH_CON_I3C6_QCH_PCLKQCH_CON_USI3_USI_QCHCLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0MISC_CMU_MISC_CONTROLLER_OPTIONCPUCL0_HCHGEN_CLKMUX_CMUREFPLL_G3DMUX_CLKCMU_G3D_NOCDMUX_CLKCMU_AUR_AURCTLMUX_CLKCMU_HSI0_DPOSCMUX_CLK_S2D_COREMUX_CLKCMU_G2D_JPEG_USERMUX_CLKCMU_HSI0_DPGTC_USERMUX_CLKCMU_HSI0_TCXO_USERMUX_CLKCMU_MFC_MFC_USERMUX_CLKCMU_TPU_TPU_USERDIV_CLK_AUR_AURCTL_LHDIV_CLK_AUR_NOCP_LHCLKCMU_G3D_GLBCLKCMU_EH_NOCDIV_CLK_G3D_TOPDIV_CLK_GSACORE_NOCPDIV_CLK_NOCL1A_NOCPCLK_BLK_APM_UID_MAILBOX_APM_AUR_IPCLKPORT_PCLKCLK_BLK_APM_UID_MAILBOX_AP_AURMCUNS1_IPCLKPORT_PCLKCLK_BLK_AUR_UID_SLH_AXI_MI_P_AUR_IPCLKPORT_I_CLKGATE_CLKCMU_G2D_G2DGATE_CLKCMU_PERIC1_NOCGATE_CLKCMU_GDC_LMEGATE_CLKCMU_NOCL2AB_NOCCLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_PPMU_CPUCL0_D0_IPCLKPORT_ACLKGOUT_BLK_DPUF1_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKMGOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_ACLKCLK_BLK_G2D_UID_XIU_D_G2D_IPCLKPORT_ACLKGOUT_BLK_G3D_UID_GPC_G3D_IPCLKPORT_PCLKCLK_BLK_G3D_UID_LH_AXI_MI_IP_G3D_IPCLKPORT_I_CLKCLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3DCORE_TOP_IPCLKPORT_CLKGOUT_BLK_GDC_UID_SSMT_D0_GDC1_IPCLKPORT_ACLKGOUT_BLK_GDC_UID_SYSMMU_S0_GDC_IPCLKPORT_CLKCLK_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC0_IPCLKPORT_CLKCLK_BLK_GDC_UID_BLK_GDC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLKGOUT_BLK_GSACORE_UID_LH_AST_SI_I_CA32_GIC_IPCLKPORT_I_CLKCLK_BLK_GSACORE_UID_GPIO_GSACORE1_IPCLKPORT_PCLKGOUT_BLK_GSE_UID_LH_AST_MI_L_OTF_TNR_GSE_IPCLKPORT_I_CLKCLK_BLK_GSE_UID_AXI_US_128TO256_QE_D2_GSE_IPCLKPORT_MAINCLKGATE_CLK_HSI0_USI2CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USB32DRD_SUSPEND_CLK_26GATE_CLK_HSI1_ALTCLK_BLK_HSI2_UID_LH_AXI_MI_LP_CPUCL0_HSI2_IPCLKPORT_I_CLKCLK_BLK_ISPFE_UID_ISPFE_CMU_ISPFE_IPCLKPORT_PCLKGOUT_BLK_ISPFE_UID_SSMT_D0_ISPFE_IPCLKPORT_PCLKCLK_BLK_ISPFE_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS3CLK_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_ACLKGOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_PCLKGOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLKGOUT_BLK_NOCL0_UID_PPC_CPUCL0_D2_EVENT_IPCLKPORT_ACLKCLK_BLK_NOCL0_UID_PPC_NOCL0_IO1_EVENT_IPCLKPORT_PCLKGOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLKGOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_PCLKGOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_PCLKGOUT_BLK_NOCL1A_UID_PPC_TPU_D0_CYCLE_IPCLKPORT_PCLKGOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_PCLKGOUT_BLK_NOCL2AA_UID_LH_AXI_MI_D1_ISPFE_IPCLKPORT_I_CLKGOUT_BLK_NOCL2AA_UID_LH_AXI_MI_D2_RGBP_IPCLKPORT_I_CLKCLK_BLK_NOCL2AB_UID_PPMU_NOCL2AB_M0_IPCLKPORT_PCLKCLK_BLK_NOCL2AB_UID_SLH_AXI_SI_P_G2D_IPCLKPORT_I_CLKCLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_PCLKCLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_SCLKCLK_BLK_RGBP_UID_SSMT_D2_RGBP_IPCLKPORT_ACLKCLK_BLK_RGBP_UID_QE_D2_RGBP_IPCLKPORT_ACLKCLK_BLK_RGBP_UID_QE_D4_RGBP_IPCLKPORT_PCLKCLK_BLK_RGBP_UID_LH_AST_SI_L_OTF_RGBP_YUVP_IPCLKPORT_I_CLKCLK_BLK_RGBP_UID_XIU_D4_RGBP_IPCLKPORT_ACLKGOUT_BLK_TNR_UID_QE_D10_TNRA_IPCLKPORT_PCLKCLK_BLK_TNR_UID_QE_D2_TNR_IPCLKPORT_ACLKCLK_BLK_TPU_UID_PPMU_D1_TPU_IPCLKPORT_ACLKCLK_BLK_YUVP_UID_SSMT_D1_YUVP_IPCLKPORT_ACLKCLK_BLK_YUVP_UID_SSMT_D4_YUVP_IPCLKPORT_ACLKOSCCLK_GDCPLL_SHARED1_D2LH_AXI_MI_LP_ALIVE_CPUCL0_CD_QCHLH_AXI_MI_P_ALIVE_CU_QCHMAILBOX_AP_AURMCUNS1_QCHSS_DBGCORE_QCH_GREBELH_AXI_MI_P_AUR_CU_QCHLH_AXI_MI_G_CSSYS_CD_QCHCMU_CPUCL1_CMUREF_QCHLH_ACEL_SI_LD_EH_CPUCL0_QCHLH_AXI_SI_P_EH_CU_QCHLH_AST_SI_ID_JPEG_G2D0_QCHGDC0_QCH_CLKLH_AST_MI_ID_GDC1_GDC0_QCHSSMT_D0_GDC1_QCHSSMT_D_LME_QCHINTMEM_GSACORE_QCHQE_SC_GSACORE_QCHSLH_AXI_MI_LG_ETR_HSI0_QCHUSB32DRD_QCH_USBDPPHY_CTRLPCIE_GEN3_0_QCH_AXISLH_AXI_MI_P_HSI1_QCHSSMT_D5_MCSC_QCHLH_AXI_SI_P_MIF_CU_QCHLH_AST_SI_G_NOCL2AB_CU_QCHLH_AXI_SI_P_PERIC1_CD_QCHPPMU_NOCL0_S2_QCHLH_ACEL_MI_D2_G3D_QCHPPC_G3DMMU_D_EVENT_QCHPPC_NOCL2AA_S1_EVENT_QCHPPMU_NOCL1A_M1_QCHPPMU_NOCL1A_M3_QCHLH_ACEL_MI_D_HSI0_QCHLH_AXI_MI_D0_MCSC_QCHSLH_AXI_SI_P_GSE_QCHUSI14_USI_QCHUSI4_USI_QCHQE_D5_MCFP_QCHPPMU_D9_TNR_QCHSYSMMU_S2_PMMU0_TNR_QCH_S0SYSREG_TNR_QCHSSMT_D1_TPU_QCHSYSREG_TPU_QCHVCLK_MUX_NOCL2AA_CMUREFVCLK_DIV_CLK_APM_USI0_USIVCLK_DIV_CLK_SLC3_DCLKVCLK_DIV_CLK_PERIC1_I3CVCLK_BLK_APMVCLK_BLK_CPUCL2VCLK_BLK_G2DVCLK_IP_LH_AXI_MI_LD_HSI0_AOCVCLK_IP_LH_AXI_SI_P_AOC_CUVCLK_IP_RTCVCLK_IP_MAILBOX_AP_AURCORE2VCLK_IP_LH_AXI_SI_P_ALIVE_CUVCLK_IP_MAILBOX_AOC_AURCORE1VCLK_IP_APBIF_GPIO_CUSTOM_ALIVEVCLK_IP_SSMT_BWVCLK_IP_GPC_BWVCLK_IP_LH_ATB_MI_LT_GSA_CPUCL0_CUVCLK_IP_LH_ATB_MI_T_SLC_CUVCLK_IP_AD_APB_DECON_MAINVCLK_IP_SLH_AXI_MI_P_DPUF0VCLK_IP_LH_AXI_SI_D1_DPUF0VCLK_IP_SYSMMU_S0_PMMU0_DPUF0VCLK_IP_SLH_AXI_MI_P_G3DVCLK_IP_PPCFW_G3D1VCLK_IP_LH_ACEL_SI_D1_G3DVCLK_IP_PPMU_D4_GDC0VCLK_IP_LH_AXI_MI_IP_AXI2APB0_GSACTRLVCLK_IP_LH_AXI_MI_IP_ISPFEVCLK_IP_MCSCVCLK_IP_SYSMMU_S0_PMMU0_MISCVCLK_IP_PPMU_NOCL0_ALIVE_PVCLK_IP_PPC_CPUCL0_D0_CYCLEVCLK_IP_PPC_CPUCL0_D0_EVENTVCLK_IP_SLH_AXI_SI_P_PERIC1VCLK_IP_LH_ATB_SI_T_SLC_CDVCLK_IP_NOCL0_CMU_NOCL0VCLK_IP_GPC_NOCL1AVCLK_IP_TREX_P_NOCL1AVCLK_IP_LH_AST_SI_G_NOCL1B_CDVCLK_IP_PPMU_NOCL2AA_M0VCLK_IP_LH_TAXI_SI_D1_NOCL2AA_NOCL1AVCLK_IP_LH_AXI_MI_D0_GDCVCLK_IP_LH_AXI_MI_D2_TNRVCLK_IP_LH_ACEL_MI_D2_G2DVCLK_IP_I3C5VCLK_IP_SYSMMU_S1_PMMU4_RGBPVCLK_IP_LH_AST_SI_L_OTF_RGBP_YUVPVCLK_IP_XIU_D1_RGBPVCLK_IP_SYSMMU_S1_PMMU1_TNRVCLK_IP_PPMU_D0_TPUexynos-acpm-dvfsacpm_dvfs_probemargin_lit_write_filera_set_valuedvfs_domain3%s %s: error on PA2VA conversion. seq:erlywkup, mode_id:%d. aborting init... 3%s %s: error on PA2VA conversion. seq:on, pd_id:%d. aborting init... CLUSTER0_CPU0_STATUSPLL_CON3_PLL_G3DPLL_CON0_PLL_G3DQCH_CON_LH_ACEL_SI_D2_G3D_QCHQCH_CON_SLH_AXI_MI_P_G3D_QCHQCH_CON_UASC_G3D_QCHDBG_NFO_QCH_CON_LH_AXI_MI_IP_G3D_QCHDBG_NFO_QCH_CON_PPCFW_G3D1_QCHG3D_CLKDIVSTEPDBG_NFO_QCH_CON_GPC_DPUF0_QCHCLK_CON_DIV_DIV_CLK_DPUF1_NOCPDBG_NFO_QCH_CON_SYSMMU_S0_PMMU1_DPUF1_QCH_S0QCH_CON_G2D_QCHQCH_CON_PPMU_D4_GDC0_QCHQCH_CON_SSMT_D2_GDC1_QCHDBG_NFO_QCH_CON_LH_AST_MI_ID_GDC0_GDC1_QCHDBG_NFO_QCH_CON_PPMU_D_LME_QCHQCH_CON_QE_D4_MCSC_QCHDBG_NFO_QCH_CON_PPMU_D1_MFC_QCHQCH_CON_PPMU_D5_MCFP_QCHQCH_CON_QE_D4_MCFP_QCHQCH_CON_RGBP_QCH_VOTF0DBG_NFO_QCH_CON_SSMT_D1_RGBP_QCHDBG_NFO_QCH_CON_SSMT_D5_MCFP_QCHDBG_NFO_QCH_CON_SYSMMU_S1_RGBP_QCH_S0QCH_CON_LH_AXI_SI_D3_TNR_QCHDBG_NFO_QCH_CON_TNR_CMU_TNR_QCHQCH_CON_SYSREG_AUR_QCHAUR_CLKDIVSTEPDBG_NFO_QCH_CON_SYSREG_BW_QCHDBG_NFO_QCH_CON_EH_CMU_EH_QCHDBG_NFO_QCH_CON_SSMT_EH_QCHQCH_CON_SYSMMU_S0_ISPFE_QCH_S0DBG_NFO_QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS8DBG_NFO_QCH_CON_SYSMMU_S1_ISPFE_QCH_S0CLK_CON_MUX_MUX_CLK_TPU_TPUCTRL_LPMPLL_CON0_MUX_CLKCMU_TPU_NOC_USERDMYQCH_CON_ADD_TPU_QCHDBG_NFO_DMYQCH_CON_TPU_QCHDBG_NFO_QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_QCHDBG_NFO_QCH_CON_LH_AXI_MI_P_TPU_CU_QCHDBG_NFO_QCH_CON_SLH_AXI_MI_P_TPU_QCHPLL_CON5_PLL_NOCL0DMYQCH_CON_SLC_CH2_QCHQCH_CON_LH_AXI_MI_P_MIF0_CD_QCHQCH_CON_PPC_CPUCL0_D1_EVENT_QCHDBG_NFO_QCH_CON_LH_TAXI_MI_D3_NOCL1A_NOCL0_QCHDBG_NFO_QCH_CON_PPC_CPUCL0_D0_CYCLE_QCHDBG_NFO_QCH_CON_PPC_NOCL1B_M0_EVENT_QCHQCH_CON_LH_TAXI_MI_D1_NOCL2AB_NOCL1A_QCHQCH_CON_PPMU_NOCL1A_M1_QCHDBG_NFO_QCH_CON_LH_ACEL_MI_D0_AUR_QCHDBG_NFO_QCH_CON_LH_AST_SI_G_NOCL1A_CD_QCHDBG_NFO_QCH_CON_LH_TAXI_SI_D2_NOCL1A_NOCL0_QCHDBG_NFO_QCH_CON_PPC_G3D_D3_EVENT_QCHDBG_NFO_QCH_CON_PPC_TPU_D0_EVENT_QCHNOCL1A_CMU_NOCL1A_CONTROLLER_OPTIONQCH_CON_GPC_NOCL1B_QCHQCH_CON_LH_ACEL_MI_D_HSI1_QCHDBG_NFO_QCH_CON_GPC_NOCL1B_QCHDBG_NFO_QCH_CON_SYSREG_NOCL1B_QCHCLK_CON_DIV_DIV_CLK_NOCL2AA_NOCD_LHQCH_CON_LH_AXI_MI_D0_ISPFE_QCHDBG_NFO_QCH_CON_LH_AXI_MI_D4_RGBP_QCHQCH_CON_PPMU_NOCL2AB_M0_QCHHSI0_CONFIGURATIONQCH_CON_I3C2_HSI0_QCH_PCLKQCH_CON_USB32DRD_QCH_SUBCTLDBG_NFO_QCH_CON_LH_AXI_SI_P_HSI0_CU_QCHQCH_CON_LH_AXI_MI_LP_AOC_HSI1_CU_QCHDBG_NFO_QCH_CON_LH_AXI_SI_LP_CPUCL0_HSI1_CU_QCHCPUCL1_CLKDIVSTEP_SMPL_FLTCPUCL0_SHORTSTOP_DBGEARLY_WAKEUP_ISPFE_CTRLPLL_CON0_MUX_CLKCMU_PERIC0_I3C_USERPLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USERQCH_CON_APM_DMA_QCHQCH_CON_LH_AXI_MI_P_ALIVE_CU_QCHQCH_CON_MAILBOX_APM_SWD_QCHQCH_CON_RSTNSYNC_CLK_APM_GREBE_QCHDBG_NFO_QCH_CON_GREBEINTEGRATION_QCH_DBGDBG_NFO_QCH_CON_PMU_QCHDMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6QCH_CON_SSMT_DIT_QCHDBG_NFO_QCH_CON_RTIC_QCHDBG_NFO_QCH_CON_SC_QCHDBG_NFO_QCH_CON_SSMT_HSI2_QCHDBG_NFO_QCH_CON_I3C2_QCH_PCLKDBG_NFO_QCH_CON_LH_AXI_MI_P_PERIC0_CU_QCHCPUCL0_CMU_CPUCL0_CONTROLLER_OPTIONMUX_CLKCMU_CIS_CLK0MUX_CLKCMU_TOP_BOOST_OPTION1MUX_CPUCL0_CMUREFMUX_CLK_G3D_L2_GLBMUX_CLK_G3DCORE_STACKS_USERMUX_CLKCMU_HSI2_NOC_USERMUX_CLKCMU_NOCL1B_NOC_USERDIV_CLK_APM_NOC_LHDIV_CLK_HSI2_NOC_LHDIV_CLK_ISPFE_NOCPDIV_CLK_NOCL0_NOCP_LHDIV_CLK_PERIC1_USI13_USIDIV_CLK_TNR_NOCPDIV_CLK_TPU_TPUCTLCLK_BLK_AOC_UID_AOC_CMU_AOC_IPCLKPORT_PCLKCLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_CD_IPCLKPORT_I_CLKCLK_BLK_APM_UID_LH_AXI_MI_P_ALIVE_CU_IPCLKPORT_I_CLKCLK_BLK_APM_UID_SYSMMU_S0_ALIVE_IPCLKPORT_CLKCLK_BLK_AUR_UID_UASC_P0_AUR_IPCLKPORT_ACLKCLK_BLK_AUR_UID_DAPAPBAP_AUR_IPCLKPORT_DAPCLKCLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_CU_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_LH_AXI_MI_ID_PPU_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_S2MPU_S0_PMMU0_CPUCL0_IPCLKPORT_CLKGATE_CLK_CLUSTER2_CORE8CLKGOUT_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECONGOUT_BLK_DPUB_UID_GPC_DPUB_IPCLKPORT_PCLKGOUT_BLK_DPUF0_UID_LH_AXI_SI_D1_DPUF0_IPCLKPORT_I_CLKGOUT_BLK_DPUF0_UID_SYSMMU_S0_PMMU0_DPUF0_IPCLKPORT_CLKGOUT_BLK_G2D_UID_SYSMMU_S0_PMMU0_G2D_IPCLKPORT_CLKCLK_BLK_G3D_UID_PPMU_G3D_D1_IPCLKPORT_ACLKCLK_BLK_G3D_UID_SSMT_G3D1_IPCLKPORT_PCLKCLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_G3DCORE_NOCD_IPCLKPORT_CLKGOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_PCLKGOUT_BLK_GSACORE_UID_LH_AST_SI_I_GIC_CA32_IPCLKPORT_I_CLKGOUT_BLK_GSACTRL_UID_SYSREG_GSACTRL_IPCLKPORT_PCLKGOUT_BLK_GSACTRL_UID_DAP_GSACTRL_IPCLKPORT_DAPCLKGOUT_BLK_GSACTRL_UID_AD_APB_INTMEM_GSACTRL_IPCLKPORT_PCLKMGOUT_BLK_HSI0_UID_LH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLKCLK_BLK_HSI0_UID_USI1_HSI0_IPCLKPORT_PCLKCLK_BLK_HSI2_UID_SYSMMU_S0_PMMU0_HSI2_IPCLKPORT_CLKCLK_BLK_ISPFE_UID_SSMT_D3_ISPFE_IPCLKPORT_PCLKGOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLKGOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLKGOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLKGOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_PCLKGOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLKCLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_PCLKCLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_CU_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF3_CD_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_LH_AXI_MI_P_MISC_GIC_CD_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_LH_IPCLKPORT_CLKGOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLKGOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_ACLKGOUT_BLK_NOCL1A_UID_PPC_TPU_D0_EVENT_IPCLKPORT_ACLKCLK_BLK_NOCL1A_UID_PPMU_NOCL1A_M0_IPCLKPORT_PCLKCLK_BLK_NOCL2AB_UID_LH_TAXI_MI_P_NOCL0_NOCL2AB_IPCLKPORT_I_CLKGOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLKCLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_PCLKCLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLKCLK_BLK_PERIC1_UID_PWM_IPCLKPORT_I_PCLK_S0GOUT_BLK_RGBP_UID_LH_AXI_SI_D1_RGBP_IPCLKPORT_I_CLKCLK_BLK_RGBP_UID_PPMU_D1_RGBP_IPCLKPORT_ACLKGOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_PCLKGOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_ACLKCLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_ACLKCLK_BLK_TNR_UID_PPMU_D9_TNR_IPCLKPORT_PCLKCLK_BLK_TNR_UID_QE_D10_TNRA_IPCLKPORT_ACLKCLK_BLK_TNR_UID_QE_D3_TNR_IPCLKPORT_ACLKGOUT_BLK_TPU_UID_LH_AXI_MI_P_TPU_CU_IPCLKPORT_I_CLKGOUT_BLK_TPU_UID_SYSREG_TPU_IPCLKPORT_PCLKCLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CLKCLK_BLK_YUVP_UID_XIU_D1_YUVP_IPCLKPORT_ACLKPLL_ALVOSCCLK_NOCL1ADIV_CLK_MIF_NOCDGPC_AOC_QCHMAILBOX_AOC_AURCORE1_QCHMAILBOX_APM_AURMCU_QCHDFTMUX_CMU_QCH_CIS_CLK4CLUSTER0_QCH_COMPLEX0DPUB_CMU_DPUB_QCHLH_AXI_MI_LD1_DPUF1_DPUF0_QCHLH_AXI_MI_IP_G3D_QCHSYSMMU_S0_PMMU3_G3D_QCH_S0GSACORE_CMU_GSACORE_QCHQE_DMA_GSACORE_QCHUGME_QCHPMU_GSA_QCHLH_AXI_SI_D_GSE_QCHSSMT_D2_GSE_QCHSYSREG_GSE_QCHPCIE_GEN3A_1_QCH_AXIQE_UFS_EMBD_HSI2_QCHPPMU_D1_MFC_QCHMCT_SUB_QCHOTP_CON_TOP_QCHSSMT_SPDMA0_QCHPPC_CPUCL0_D2_EVENT_QCHPPC_NOCL1A_M3_EVENT_QCHPPC_NOCL1B_M0_EVENT_QCHSLC_CB_TOP_QCHLH_ACEL_MI_D0_G3D_QCHPPC_BW_D_CYCLE_QCHUSI2_USI_QCHMCFP_QCH_CLKPPMU_D5_MCFP_QCHSSMT_D0_RGBP_QCHGTNR_ALIGN_QCH_MSALH_AST_SI_L_OTF_YUVP_GSE_QCHCTRL_OPTION_CMU_MCSCCTRL_OPTION_CMU_MFCVCLK_VDD_INTVCLK_CLKCMU_DPUB_DSIMVCLK_DIV_CLK_PERIC1_USI11_USIVCLK_DIV_CLK_PERIC1_USI12_USIVCLK_BLK_PERIC1VCLK_IP_AOC_SYSCTRL_APBVCLK_IP_WDT_APMVCLK_IP_D_TZPC_APMVCLK_IP_MAILBOX_APM_SWDVCLK_IP_AUR_CMU_AURVCLK_IP_SYSMMU_S0_PMMU0_AURVCLK_IP_LH_ATB_SI_LT_AUR_CPUCL0VCLK_IP_UASC_BWVCLK_IP_XIU_D_BWVCLK_IP_SYSREG_CPUCL0VCLK_IP_LH_AXI_SI_IG_HSI0VCLK_IP_LH_AST_SI_L_ICC_CLUSTER0_GIC_CDVCLK_IP_SLH_AXI_SI_LG_ETR_HSI0VCLK_IP_XIU_P0_CPUCL0VCLK_IP_DPUBVCLK_IP_LH_AXI_SI_D0_DPUF0VCLK_IP_SSMT_D0_DPUF0VCLK_IP_AS_APB_JPEGVCLK_IP_SSMT_G3D1VCLK_IP_LH_AXI_SI_D1_GDCVCLK_IP_BAAW_GSACOREVCLK_IP_LH_AXI_SI_IP_AXI2APB2_GSACOREVCLK_IP_MAILBOX_GSA2TZVCLK_IP_ISPFEVCLK_IP_SYSMMU_S1_ISPFEVCLK_IP_LH_AST_MI_L_OTF_TNR_MCSCVCLK_IP_QE_D4_MCSCVCLK_IP_PPMU_D5_MCSCVCLK_IP_MISC_CMU_MISCVCLK_IP_LH_AXI_MI_P_ALIVE_CDVCLK_IP_LH_AXI_MI_P_MISC_CDVCLK_IP_LH_TAXI_SI_P_NOCL0_NOCL2ABVCLK_IP_LH_AXI_SI_P_HSI1_CDVCLK_IP_SYSREG_NOCL1BVCLK_IP_LH_AXI_MI_P_AOC_CDVCLK_IP_TREX_D_NOCL2ABVCLK_IP_SYSREG_PERIC0VCLK_IP_AD_APB_RGBPVCLK_IP_PPMU_D5_TNRVCLK_IP_SSMT_D10_TNRAVCLK_IP_QE_D2_TNRVCLK_IP_GPC_TPUVCLK_IP_LH_ATB_SI_LT1_TPU_CPUCL0_CDVCLK_IP_PPMU_D0_YUVPCPUCL0TNRzuma_cal_data_initmargin_int_write_filemargin_dsu_write_fileDOUT4ECT DVFS not found vclk_num_rates3%s %s: error on PA2VA conversion. seq:disable, cluster_id:%d. aborting init... PLL_CON0_MUX_CLK_G3DCORE_TOP_USERQCH_CON_ADD_APBIF_G3D_QCHQCH_CON_PPMU_G3D_D1_QCHDBG_NFO_QCH_CON_PPCFW_G3D0_QCHdelayQCH_CON_DPUB_QCH_ALV_DSIM0DBG_NFO_QCH_CON_PPMU_D2_G2D_QCHQCH_CON_SYSMMU_S0_PMMU1_GDC_QCH_S0DBG_NFO_QCH_CON_GDC1_QCH_CLKQCH_CON_QE_D0_GSE_QCHQCH_CON_SSMT_D6_MCSC_QCHDBG_NFO_QCH_CON_PPMU_D2_MCSC_QCHCLK_CON_DIV_DIV_CLK_RGBP_NOCPQCH_CON_QE_D11_MCFP_QCHDBG_NFO_QCH_CON_QE_D4_RGBP_QCHDBG_NFO_QCH_CON_SSMT_D2_RGBP_QCHQCH_CON_LH_AXI_SI_D1_TNR_QCHDBG_NFO_QCH_CON_GTNR_ALIGN_QCH_MSADBG_NFO_QCH_CON_QE_D6_TNR_QCHQCH_CON_D_TZPC_YUVP_QCHQCH_CON_QE_D4_YUVP_QCHQCH_CON_SSMT_D1_YUVP_QCHDBG_NFO_QCH_CON_LH_AST_SI_L_OTF_YUVP_MCSC_QCHDBG_NFO_QCH_CON_PPMU_D0_YUVP_QCHPLL_CON6_PLL_AURDBG_NFO_QCH_CON_SYSMMU_S0_PMMU1_AUR_QCH_S0BW_STATUSQCH_CON_LH_AXI_MI_IP_BW_QCHQCH_CON_SSMT_BW_QCHQCH_CON_LH_AXI_SI_D1_ISPFE_QCHQCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0CLK_CON_DIV_CLK_TPU_ADD_CH_CLKCLK_CON_DIV_DIV_CLK_SLC1_DCLKQCH_CON_LH_ACEL_SI_D0_NOCL0_CPUCL0_QCHQCH_CON_LH_AXI_SI_P_MIF3_CD_QCHQCH_CON_PPC_NOCL1B_M0_EVENT_QCHQCH_CON_PPMU_NOCL0_ALIVE_P_QCHDBG_NFO_QCH_CON_LH_AST_SI_G_NOCL2AA_CU_QCHDBG_NFO_QCH_CON_LH_ATB_SI_T_SLC_QCHDBG_NFO_QCH_CON_LH_AXI_MI_P_ALIVE_CD_QCHQCH_CON_LH_AST_SI_G_NOCL1A_CD_QCHQCH_CON_LH_AXI_MI_P_AUR_CD_QCHDBG_NFO_QCH_CON_LH_AXI_MI_D_BW_QCHDBG_NFO_QCH_CON_PPC_NOCL2AB_S1_EVENT_QCHQCH_CON_SLH_AXI_MI_G_CSSYS_QCHDBG_NFO_QCH_CON_PPC_AOC_EVENT_QCHNOCL2AB_CONFIGURATIONQCH_CON_LH_AXI_MI_D0_MCSC_QCHDBG_NFO_QCH_CON_NOCL2AB_CMU_NOCL2AB_QCHQCH_CON_SYSREG_HSI0_QCHQCH_CON_USB32DRD_QCH_EUSBCTLDBG_NFO_QCH_CON_SYSMMU_S0_PMMU0_HSI0_QCH_S0PLL_CON0_MUX_CLKCMU_HSI1_NOC_USERQCH_CON_LH_AXI_SI_LP_AOC_HSI1_CU_QCHQCH_CON_SLH_AXI_MI_LP_AOC_HSI1_QCHQCH_CON_UASC_PCIE_GEN3A_DBI_0_QCHQCH_CON_UASC_PCIE_GEN3A_SLV_0_QCHDBG_NFO_QCH_CON_LH_ACEL_SI_D_HSI1_QCHDBG_NFO_QCH_CON_LH_AXI_MI_LP_CPUCL0_HSI1_CU_QCHblkpwr_nocl2aaWAKEUP_INT_ENCLK_CON_DIV_DIV_CLK_PERIC1_NOCP_LHPLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USERPLL_CON0_MUX_CLKCMU_PERIC1_NOC_USERQCH_CON_MAILBOX_AOC_AURCORE2_QCHQCH_CON_MAILBOX_TPU_AURMCU_QCHDBG_NFO_QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CD_QCHDBG_NFO_QCH_CON_MAILBOX_APM_TPU_QCHDMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3QCH_CON_PPMU_MISC_QCHDBG_NFO_QCH_CON_SSMT_DIT_QCHDBG_NFO_QCH_CON_WDT_CLUSTER1_QCHDBG_NFO_QCH_CON_D_TZPC_HSI2_QCHDBG_NFO_QCH_CON_PCIE_GEN3A_1_QCH_UDBGQCH_CON_USI14_USI_QCHQCH_CON_USI12_USI_QCHMUX_CLKCMU_HSI0_DPGTCMUX_CLK_HSI0_NOCMUX_CLK_HSI0_USB20_REFMUX_CLKCMU_EH_NOC_USERMUX_CLKCMU_HSI0_PERI_USERMUX_CLKCMU_PERIC1_USI11_USI_USERDIV_CLK_APM_USI0_UARTDIV_CLK_APM_USI1_UARTCLKCMU_TPU_TPUCTLCLKCMU_AUR_NOCGOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_ACLKGOUT_BLK_AOC_UID_XIU_DP_AOC_IPCLKPORT_ACLKCLK_BLK_AOC_UID_SLH_AXI_SI_LP_AOC_HSI0_IPCLKPORT_I_CLKCLK_BLK_AOC_UID_PPMU_PCIE_IPCLKPORT_ACLKCLK_BLK_AOC_UID_LH_AXI_MI_LP_AOC_HSI1_CD_IPCLKPORT_I_CLKCLK_BLK_APM_UID_MAILBOX_AP_AURMCUTZ_IPCLKPORT_PCLKCLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLKCLK_BLK_BW_UID_TREX_D_BW_IPCLKPORT_ACLKGOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_STM_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_SLH_AXI_SI_LG_ETR_HSI0_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_CPUCL0_CON_IPCLKPORT_I_PERIPHCLKCLK_BLK_CPUCL0_UID_LH_AXI_SI_IP_CPUCL1_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_PCLK_IPCLKPORT_CLKCLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLKGATE_CLK_CLUSTER1_CORE4CLKGOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCD_IPCLKPORT_CLKCLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM1GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_NOCP_IPCLKPORT_CLKCLK_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_SRAMCCLK_BLK_EH_UID_RSTNSYNC_SR_CLK_EH_NOCD_IPCLKPORT_CLKCLK_BLK_EH_UID_PPC_EH_CYCLE_IPCLKPORT_PCLKCLK_BLK_G2D_UID_RSTNSYNC_SR_CLK_G2D_NOCP_IPCLKPORT_CLKGOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_PCLKCLK_BLK_G3D_UID_PPCFW_G3D1_IPCLKPORT_ACLKCLK_BLK_G3D_UID_LH_ACEL_SI_D2_G3D_IPCLKPORT_I_CLKCLK_BLK_GDC_UID_QE_D2_GDC1_IPCLKPORT_PCLKCLK_BLK_GDC_UID_QE_D0_GDC1_IPCLKPORT_ACLKCLK_BLK_GDC_UID_GDC0_IPCLKPORT_CLKGOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_ACLKGOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_I_PCLKCLK_BLK_GSACORE_UID_RSTNSYNC_SR_CLK_GSACORE_NOCD_IPCLKPORT_CLKGOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCD_IPCLKPORT_CLKGOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_OSCCLK_IPCLKPORT_CLKCLK_BLK_GSACTRL_UID_SYSMMU_S0_PMMU0_GSA_ZM_IPCLKPORT_CLKCLK_BLK_GSE_UID_GSE_IPCLKPORT_CLK_VOTFGOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLKCLK_BLK_HSI0_UID_SLH_AXI_MI_LG_ETR_HSI0_IPCLKPORT_I_CLKCLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_USI2_IPCLKPORT_CLKGOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLKCLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN3A_0_IPCLKPORT_PCLKCLK_BLK_HSI1_UID_XIU_D1_HSI1_IPCLKPORT_ACLKGOUT_BLK_HSI2_UID_PCIE_IA_GEN3B_1_IPCLKPORT_I_CLKCLK_BLK_HSI2_UID_PCIE_GEN3B_1_IPCLKPORT_PCIE_QUADRA_G3X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UGCLK_BLK_HSI2_UID_LH_AXI_MI_LP_CPUCL0_HSI2_CU_IPCLKPORT_I_CLKCLK_BLK_HSI2_UID_RSTNSYNC_SR_HCI_SW_RST_PULSE_IPCLKPORT_CLKGOUT_BLK_ISPFE_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2GOUT_BLK_ISPFE_UID_XIU_D0_ISPFE_IPCLKPORT_ACLKCLK_BLK_ISPFE_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS0CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLKCLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_PCLKGOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLKGOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLKGOUT_BLK_MISC_UID_XIU_D0_MISC_IPCLKPORT_ACLKCLK_BLK_MISC_UID_RSTNSYNC_SR_CLK_MISC_NOCP_LH_IPCLKPORT_CLKGOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_PCLKGOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_PCLKCLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2AA_CU_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLKCLK_BLK_NOCL0_UID_LH_AXI_MI_P_CPUCL0_NOCL0_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_LD_SLC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_PPC_NOCL0_IO0_CYCLE_IPCLKPORT_ACLKCLK_BLK_NOCL0_UID_PPC_NOCL0_IO0_EVENT_IPCLKPORT_PCLKCLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_SLC2_DCLK_IPCLKPORT_CLKGOUT_BLK_NOCL1A_UID_GPC_NOCL1A_IPCLKPORT_PCLKCLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLKCLK_BLK_NOCL1A_UID_PPC_BW_D_EVENT_IPCLKPORT_ACLKGOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI0_CD_IPCLKPORT_I_CLKGOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_ACLK_P_NOCL1BGOUT_BLK_NOCL2AA_UID_LH_AXI_MI_D1_MFC_IPCLKPORT_I_CLKCLK_BLK_NOCL2AA_UID_LH_AST_SI_G_NOCL2AA_IPCLKPORT_I_CLKCLK_BLK_NOCL2AB_UID_LH_AST_MI_G_NOCL2AB_CD_IPCLKPORT_I_CLKCLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_SCLKCLK_BLK_RGBP_UID_SYSMMU_S0_RGBP_IPCLKPORT_CLKCLK_BLK_RGBP_UID_SSMT_D4_MCFP_IPCLKPORT_ACLKCLK_BLK_RGBP_UID_QE_D4_MCFP_IPCLKPORT_ACLKCLK_BLK_S2D_UID_RSTNSYNC_SR_CLK_S2D_CORE_LH_IPCLKPORT_CLKGOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLKGOUT_BLK_TNR_UID_LH_AXI_SI_D3_TNR_IPCLKPORT_I_CLKGOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLKCLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_ACLKCLK_BLK_TNR_UID_XIU_D11_TNR_IPCLKPORT_ACLKCLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_PCLKTCXO_HSI1_HSI0LH_AXI_SI_LP_AOC_ALIVE_CD_QCHLH_AXI_SI_LP_ALIVE_CPUCL0_CD_QCHMAILBOX_APM_AP_QCHMAILBOX_AP_AOCA32_QCHMAILBOX_AP_AURCORE1_QCHPMU_INTR_GEN_QCHSYSMMU_S0_BW_QCHCLUSTER0_QCH_GICLH_AXI_MI_LG_ETR_HSI0_CD_QCHCPUCL1_QCH_CORE5CLKCMU_CPUCL2_SHORTSTOP_QCHPPMU_D0_DPUF0_QCHPPMU_D1_DPUF0_QCHLH_AXI_SI_IP_EH_QCHADD_G3D_QCHSSMT_G3D0_QCHLH_AXI_SI_D0_GDC_QCHLH_AST_SI_I_GIC_CA32_QCHLH_ATB_SI_LT_GSA_CPUCL0_QCHSYSMMU_S0_GSE_QCH_S0UASC_PCIE_GEN3B_SLV_1_QCHSSMT_D2_ISPFE_QCHLH_AST_SI_L_IRI_GIC_CLUSTER0_QCHSLH_AXI_MI_P_MISC_QCHSSMT_SPDMA1_QCHLH_AXI_SI_P_MISC_CD_QCHSFR_APBIF_CMU_TOPC_QCHTREX_P_NOCL1A_QCHSLH_AXI_SI_P_GSA_QCHSLH_AXI_SI_P_HSI0_QCHLH_AXI_MI_D2_RGBP_QCHUSI1_USI_QCHSYSMMU_S1_PMMU1_RGBP_QCH_S0QE_D5_TNR_QCHQE_D6_TNR_QCHSYSMMU_S0_TNR_QCH_S0LH_ATB_SI_LT1_TPU_CPUCL0_CD_QCHPPMU_D0_YUVP_QCHSSMT_D4_YUVP_QCHVCLK_MUX_CPUCL1_CMUREFVCLK_DIV_CLK_APM_I3C_PMICVCLK_DIV_CLK_PERIC0_USI14_USIVCLK_DIV_CLK_PERIC1_USI0_USIVCLK_BLK_DPUF1VCLK_IP_XIU_P_AOCVCLK_IP_SSMT_LP_ALIVE_CPUCL0VCLK_IP_MAILBOX_AP_AOCF1VCLK_IP_MAILBOX_AP_AURMCUNS0VCLK_IP_MAILBOX_AOC_AURCORE0VCLK_IP_MAILBOX_AP_AURMCUNS1VCLK_IP_PPC_INSTRRUN_CLUSTER0_0VCLK_IP_PPC_INSTRRET_CLUSTER0_1VCLK_IP_LH_ACEL_MI_D1_NOCL0_CPUCL0VCLK_IP_ADD2_APBIF_CPUCL2VCLK_IP_XIU_D0_DPUF0VCLK_IP_SYSMMU_S0_PMMU0_DPUF1VCLK_IP_GPC_G3DVCLK_IP_DAPAHBAP_GPUVCLK_IP_SYSMMU_S0_PMMU0_GDCVCLK_IP_LH_AST_SI_ID_GDC1_GDC0VCLK_IP_DMA_GSACOREVCLK_IP_LH_ATB_SI_LT_GSA_CPUCL0VCLK_IP_LH_AXI_MI_IP_AXI2APB2_GSACOREVCLK_IP_AD_APB_INTMEM_GSACOREVCLK_IP_MAILBOX_GSA2NONTZVCLK_IP_INTMEM_GSACTRLVCLK_IP_SLH_AXI_MI_LP_AOC_HSI0VCLK_IP_LH_AXI_MI_LP_AOC_HSI0_CUVCLK_IP_LH_ACEL_SI_D_HSI1VCLK_IP_SYSMMU_S0_PMMU0_HSI2VCLK_IP_QE_D1_ISPFEVCLK_IP_QE_D5_MCSCVCLK_IP_SSMT_D5_MCSCVCLK_IP_SYSMMU_S0_PMMU1_MFCVCLK_IP_LH_AXI_MI_P_MIF_CUVCLK_IP_OTP_CON_BIRAVCLK_IP_D_TZPC_MISCVCLK_IP_LH_ACEL_MI_D1_CPUCL0VCLK_IP_TREX_D_NOCL1AVCLK_IP_SLH_AXI_MI_D_G3DMMUVCLK_IP_PPMU_NOCL1A_M1VCLK_IP_LH_ACEL_MI_D_HSI0VCLK_IP_USI10_USIVCLK_IP_RGBP_CMU_RGBPVCLK_IP_QE_D9_MCFPVCLK_IP_SYSMMU_S1_PMMU0_TNRVCLK_IP_SYSMMU_S0_PMMU1_TNRVCLK_IP_SYSMMU_S0_TNRVCLK_IP_SSMT_D11_TNRAVCLK_IP_SYSMMU_S2_TNRmargin_intcam_write_filera_set_enable3cannot found vclk node %x 3%s pd index(%d) is out of supported range (0~%d). PLL_LOCKTIME_REG_PLL_G3D_L2CLK_CON_DIV_DIV_CLK_G3D_NOCPQCH_CON_PPCFW_G3D1_QCHDBG_NFO_DMYQCH_CON_ADM_DAP_G_GPU_QCHG3D_SHORTSTOPEMBEDDED_G3D_OUTQCH_CON_DPUB_QCHQCH_CON_SYSREG_DPUB_QCHDBG_NFO_QCH_CON_SYSREG_DPUB_QCHCLK_CON_DIV_DIV_CLK_DPUF0_NOCPQCH_CON_SYSREG_DPUF0_QCHDBG_NFO_QCH_CON_LH_AXI_SI_LD0_DPUF1_DPUF0_QCHDBG_NFO_QCH_CON_SYSMMU_S0_PMMU0_DPUF1_QCH_S0DBG_NFO_QCH_CON_PPMU_D4_GDC0_QCHQCH_CON_PPMU_D0_GSE_QCHDBG_NFO_QCH_CON_SSMT_D2_GSE_QCHCLK_CON_DIV_DIV_CLK_MFC_NOCPQCH_CON_PPMU_D2_MCFP_QCHQCH_CON_SSMT_D0_RGBP_QCHQCH_CON_SYSREG_RGBP_QCHDBG_NFO_QCH_CON_PPMU_D2_RGBP_QCHDBG_NFO_QCH_CON_QE_D5_RGBP_QCHDBG_NFO_QCH_CON_QE_D6_MCFP_QCHQCH_CON_GPC_TNR_QCHQCH_CON_PPMU_D4_TNR_QCHQCH_CON_SYSMMU_S1_PMMU1_TNR_QCH_S0DBG_NFO_QCH_CON_PPMU_D2_TNR_QCHDBG_NFO_QCH_CON_QE_D8_TNR_QCHDBG_NFO_QCH_CON_QE_D9_TNR_QCHPLL_CON0_MUX_CLKCMU_YUVP_NOC_USERPLL_CON7_PLL_AURQCH_CON_PPMU_D1_AUR_QCHDBG_NFO_QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_QCHDBG_NFO_QCH_CON_SYSMMU_S0_PMMU0_AUR_QCH_S0AUR_CMU_AUR_CONTROLLER_OPTIONQCH_CON_SYSMMU_S0_EH_QCHQCH_CON_LH_AXI_SI_D2_ISPFE_QCHQCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS9QCH_CON_SYSMMU_S1_ISPFE_QCH_S0DBG_NFO_QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS10DBG_NFO_QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3CLK_CON_DIV_DIV_CLK_TPU_TPUCTL_DBGDMYQCH_CON_TPU_QCHQCH_CON_LH_AXI_SI_P_MIF2_CD_QCHQCH_CON_LH_TAXI_SI_P_NOCL0_NOCL1A_QCHQCH_CON_PPMU_NOCL0_IOC1_QCHQCH_CON_LH_AXI_MI_P_EH_CD_QCHDBG_NFO_DMYQCH_CON_SLC_CH_TOP_QCHDBG_NFO_QCH_CON_PPMU_NOCL0_ALIVE_P_QCHBUS_COMPONENT0_DRCG_ENDBG_NFO_QCH_CON_SLH_AXI_SI_P_AUR_QCHQCH_CON_LH_TAXI_SI_D_NOCL1B_NOCL0_QCHQCH_CON_PPC_AOC_EVENT_QCHDBG_NFO_QCH_CON_LH_AST_SI_G_NOCL1B_QCHQCH_CON_SLH_AXI_SI_P_RGBP_QCHDBG_NFO_QCH_CON_LH_AST_SI_G_NOCL2AA_CD_QCHDBG_NFO_QCH_CON_LH_AXI_MI_D0_MFC_QCHDBG_NFO_QCH_CON_SLH_AXI_SI_P_DPUF0_QCHDBG_NFO_QCH_CON_D_TZPC_NOCL2AB_QCHQCH_CON_PPMU_HSI0_QCHDBG_NFO_DMYQCH_CON_I3C2_HSI0_QCH_SCLKDBG_NFO_QCH_CON_HSI0_CMU_HSI0_QCHDBG_NFO_QCH_CON_LH_AXI_MI_P_HSI0_CU_QCHDBG_NFO_QCH_CON_PCIE_GEN3_0_QCH_APBDBG_NFO_QCH_CON_SLH_AXI_MI_P_HSI1_QCHCPUCL0_CLKDIVSTEP_SMPL_FLTCPUCL0_CLKDIVSTEPCPUCL2_CLKDIVSTEP_OCP_FLTCPUCL2_CLKDIVSTEP_CON_LIGHTMIF_SHORTSTOPDBG_NFO_QCH_CON_APM_CMU_APM_QCHDBG_NFO_QCH_CON_GREBEINTEGRATION_QCH_GREBEDBG_NFO_QCH_CON_MAILBOX_AP_AURMCUTZ_QCHQCH_CON_MCT_QCHDBG_NFO_QCH_CON_LH_ACEL_SI_D_MISC_QCHDBG_NFO_QCH_CON_PCIE_IA_GEN3B_1_QCHQCH_CON_USI6_USI_QCHMUX_CLKCMU_PERIC1_IPMUX_CLKCMU_CMU_BOOSTMUX_CLK_HSI0_USI4MUX_CLKCMU_CPUCL0_DSU_SWITCH_USERCLKMUX_MIF_DDRPHY2XMUX_CLKCMU_PERIC1_NOC_USERCLKCMU_NOCL1B_NOCDIV_CLK_GSACORE_NOCDIV_CLK_HSI0_USI3DIV_CLK_SLC_DCLKGOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_PCLKGOUT_BLK_AOC_UID_SYSREG_AOC_IPCLKPORT_PCLKCLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_SCLKCLK_BLK_AUR_UID_GPC_AUR_IPCLKPORT_PCLKCLK_BLK_BW_UID_RSTNSYNC_SR_CLK_BW_NOCP_IPCLKPORT_CLKGATE_CLKCMU_G3D_SWITCHCLKCMU_CPUCL0_BOOSTCLKCMU_NOCL2AA_BOOSTGATE_CLKCMU_TNR_ALIGNGOUT_BLK_CPUCL0_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKMCLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLKCLK_BLK_DPUF1_UID_SSMT_D0_DPUF1_IPCLKPORT_ACLKGOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_PCLKCLK_BLK_G2D_UID_LH_AST_MI_ID_G2D1_JPEG_IPCLKPORT_I_CLKCLK_BLK_GDC_UID_RSTNSYNC_SR_CLK_GDC_GDC0_IPCLKPORT_CLKGOUT_BLK_GSACORE_UID_SC_GSACORE_IPCLKPORT_I_PCLKCLK_BLK_GSACORE_UID_AD_APB_INTMEM_GSACORE_IPCLKPORT_PCLKMCLK_BLK_GSACORE_UID_RSTNSYNC_SR_CLK_GSACORE_SC_IPCLKPORT_CLKGATE_CLK_GSACTRL2CORE_SCGOUT_BLK_GSE_UID_QE_D1_GSE_IPCLKPORT_PCLKGOUT_BLK_GSE_UID_SSMT_D0_GSE_IPCLKPORT_ACLKGOUT_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_CTRL_PCLKGOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLKGOUT_BLK_HSI2_UID_LH_AXI_MI_P_HSI2_CU_IPCLKPORT_I_CLKGOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLKGOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKINCLK_BLK_HSI2_UID_GPIO_HSI2UFS_IPCLKPORT_PCLKCLK_BLK_HSI2_UID_PCIE_GEN3B_1_IPCLKPORT_PCIE_SUB_CTRL_A_G3X1_PHY_REFCLK_INCLK_BLK_HSI2_UID_PCIE_GEN3B_1_IPCLKPORT_PCIE_QUADRA_G3X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UGGOUT_BLK_ISPFE_UID_RSTNSYNC_CLK_ISPFE_NOCD_IPCLKPORT_CLKGOUT_BLK_ISPFE_UID_SYSMMU_S0_ISPFE_IPCLKPORT_CLKGOUT_BLK_ISPFE_UID_QE_D2_ISPFE_IPCLKPORT_PCLKGOUT_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_PCLKGOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_IPCLKPORT_CLKGOUT_BLK_MISC_UID_SSMT_SC_IPCLKPORT_ACLKCLK_BLK_MISC_UID_SPDMA1_IPCLKPORT_ACLKGOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_ACLKGOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_ACLKGOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_DCLKCLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC1_CD_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_LH_ACEL_MI_D3_CPUCL0_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_LH_TAXI_SI_P_NOCL0_NOCL1A_IPCLKPORT_I_CLKGOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_ACLKGOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_ACLKCLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_PCLKCLK_BLK_NOCL1A_UID_LH_ACEL_MI_D1_AUR_IPCLKPORT_I_CLKCLK_BLK_NOCL1A_UID_LH_TAXI_MI_D0_NOCL2AB_NOCL1A_IPCLKPORT_I_CLKCLK_BLK_NOCL1A_UID_PPC_NOCL2AB_S0_CYCLE_IPCLKPORT_PCLKGOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLKCLK_BLK_NOCL2AB_UID_LH_AXI_MI_D_GSE_IPCLKPORT_I_CLKGOUT_BLK_PERIC0_UID_LH_AXI_MI_P_PERIC0_CU_IPCLKPORT_I_CLKCLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_IPCLKCLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_PCLKCLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLKGOUT_BLK_PERIC1_UID_LH_AXI_MI_P_PERIC1_CU_IPCLKPORT_I_CLKGOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLKCLK_BLK_RGBP_UID_QE_D5_RGBP_IPCLKPORT_PCLKCLK_BLK_RGBP_UID_QE_D10_MCFP_IPCLKPORT_PCLKGOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLKGOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_PCLKCLK_BLK_TNR_UID_SYSMMU_S2_TNR_IPCLKPORT_CLKGOUT_BLK_YUVP_UID_QE_D0_YUVP_IPCLKPORT_ACLKLH_AXI_MI_LD_HSI0_AOC_QCHAPBIF_GPIO_FAR_ALIVE_QCHMAILBOX_AOC_AURCORE2_QCHLH_AXI_SI_IP_BW_QCHDFTMUX_CMU_QCH_CIS_CLK6CLUSTER0_QCH_CORE3CMU_CPUCL0_CMUREF_QCHLH_AXI_SI_IG_STM_QCHPPC_INSTRRET_CLUSTER0_0_QCHSLH_AXI_MI_P_EH_QCHSLH_AXI_SI_D_G3DMMU_QCHSYSMMU_S0_PMMU0_G3D_QCH_S0UASC_G3D_QCHLH_AXI_SI_D1_GDC_QCHLH_AST_MI_I_GIC_CA32_QCHSSMT_GSACTRL_QCHI3C3_HSI0_QCH_SCLKSSMT_HSI0_QCHPCIE_GEN3A_1_QCH_UDBGSSMT_PCIE_IA_GEN3B_1_QCHMIPI_PHY_LINK_WRAP_QCH_CSIS1SYSMMU_S2_ISPFE_QCH_S0SSMT_D2_MCSC_QCHQCH_ADAPTER_PPC_DEBUG_QCHLH_AST_MI_L_ICC_CLUSTER0_GIC_QCHOTP_CON_BIRA_QCHQE_PDMA0_QCHLH_AST_SI_G_NOCL1A_CU_QCHLH_TAXI_SI_P_NOCL0_NOCL2AA_QCHPPMU_NOCL0_DP_QCHPPMU_NOCL0_S3_QCHSLH_AXI_SI_P_CPUCL0_QCHLH_AXI_SI_P_G3D_CD_QCHLH_TAXI_SI_D2_NOCL1A_NOCL0_QCHPPC_G3D_D1_EVENT_QCHLH_TAXI_SI_D_NOCL1B_NOCL0_QCHLH_AST_SI_G_NOCL2AB_CD_QCHI3C5_QCH_PCLKGPC_PERIC1_QCHI3C0_QCH_SCLKQE_D9_TNR_QCHSYSMMU_S0_PMMU0_TNR_QCH_S0TPU_QCHTPU_CMU_TPU_QCHSYSMMU_S0_PMMU0_YUVP_QCH_S0CTRL_OPTION_CMU_AOCCTRL_OPTION_CMU_G2DCTRL_OPTION_CMU_GDCVCLK_VDD_CPUCL0VCLK_MUX_CLKCMU_CIS_CLK0VCLK_BLK_AURVCLK_IP_PPMU_USBVCLK_IP_SLH_AXI_SI_LP_AOC_HSI1VCLK_IP_APM_I3C_PMICVCLK_IP_LH_AXI_MI_P_ALIVE_CUVCLK_IP_AS_APB_SYSMMU_S1_NS_AURVCLK_IP_SYSMMU_S0_PMMU1_AURVCLK_IP_GPC_CPUCL0VCLK_IP_LH_AXI_SI_G_CSSYS_CDVCLK_IP_LH_ATB_MI_T_BDUVCLK_IP_S2MPU_S0_PMMU0_CPUCL0VCLK_IP_APB_ASYNC_P_PCSMVCLK_IP_LH_AXI_MI_IP_CPUCL1VCLK_IP_SYSMMU_S0_PMMU1_DPUF1VCLK_IP_QE_EHVCLK_IP_SYSMMU_S0_PMMU0_G2DVCLK_IP_PPMU_G3D_D0VCLK_IP_PPMU_G3D_D1VCLK_IP_LH_AST_SI_ID_LME_GDC1VCLK_IP_SYSMMU_S0_PMMU1_GDCVCLK_IP_SYSREG_HSI1VCLK_IP_SSMT_PCIE_IA_GEN3A_0VCLK_IP_SSMT_D0_ISPFEVCLK_IP_SSMT_D2_ISPFEVCLK_IP_UASC_ISPFEVCLK_IP_QE_D0_MCSCVCLK_IP_QE_D2_MCSCVCLK_IP_PPMU_D1_MFCVCLK_IP_PPC_NOCL1B_M0_EVENTVCLK_IP_SLH_AXI_SI_P_MISC_GICVCLK_IP_LH_AXI_SI_P_MIF3_CDVCLK_IP_PPMU_NOCL0_S3VCLK_IP_LH_AXI_SI_P_G3D_CDVCLK_IP_LH_TAXI_MI_D0_NOCL2AA_NOCL1AVCLK_IP_LH_ACEL_MI_D_HSI1VCLK_IP_LH_TAXI_SI_D_NOCL1B_NOCL0VCLK_IP_LH_AST_SI_G_NOCL2AAVCLK_IP_SLH_AXI_SI_P_ISPFEVCLK_IP_D_TZPC_PERIC0VCLK_IP_USI3_USIVCLK_IP_I3C4VCLK_IP_SYSREG_RGBPVCLK_IP_PPMU_D2_RGBPVCLK_IP_SYSMMU_S1_RGBPVCLK_IP_ASYNC_APB_INT_TPUVCLK_IP_ADD_TPUmargin_g3dl2_write_fileminmax_idx%s is off. %s %s: error on handling enter sequence. (mode : %d)%s %s: error on handling disable sequence. (pd: %s)3%s[0x%x] = 0x%x 3%s %s: error on handling enable sequence. (cpu : %d) G3D_STATUSPLL_CON0_MUX_CLKCMU_G3D_NOCD_USERDMYQCH_CON_ADD_G3D_QCHQCH_CON_PPCFW_G3D0_QCHDBG_NFO_QCH_CON_LH_ACEL_SI_D0_G3D_QCHG3D_CLKDIVSTEP_OCP_FLTDBG_NFO_QCH_CON_DPUB_QCH_OSC_DSIM0QCH_CON_PPMU_D0_DPUF0_QCHQCH_CON_SYSMMU_S0_DPUF0_QCH_S0QCH_CON_SLH_AXI_MI_P_DPUF1_QCHPLL_CON0_MUX_CLKCMU_G2D_G2D_USERQCH_CON_GDC1_QCH_CLKQCH_CON_LH_AXI_SI_D2_GDC_QCHQCH_CON_QE_D1_MCSC_QCHDBG_NFO_QCH_CON_QE_D0_MCSC_QCHQCH_CON_SYSMMU_S0_PMMU0_MFC_QCHDBG_NFO_QCH_CON_MFC_QCHDBG_NFO_QCH_CON_PPMU_D0_MFC_QCHRGBP_CONFIGURATIONQCH_CON_LH_AXI_SI_D1_RGBP_QCHQCH_CON_SSMT_D3_MCFP_QCHDBG_NFO_QCH_CON_PPMU_D5_MCFP_QCHDBG_NFO_QCH_CON_SYSMMU_S1_PMMU4_RGBP_QCH_S0QCH_CON_PPMU_D5_TNR_QCHQCH_CON_PPMU_D6_TNR_QCHQCH_CON_SSMT_D2_TNR_QCHDBG_NFO_QCH_CON_SYSMMU_S0_PMMU0_TNR_QCH_S0QCH_CON_YUVP_CMU_YUVP_QCHPLL_CON4_PLL_AURCLK_CON_DIV_DIV_CLK_BW_NOCPPLL_CON0_MUX_CLKCMU_BW_NOC_USERDMYQCH_CON_BW_QCHQCH_CON_LH_ACEL_SI_LD_EH_CPUCL0_QCHISPFE_STATUSQCH_CON_GPC_ISPFE_QCHDBG_NFO_QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2DBG_NFO_QCH_CON_SSMT_D1_ISPFE_QCHPLL_CON4_PLL_TPUQCH_CON_SLH_AXI_MI_P_TPU_QCHQCH_CON_LH_AXI_MI_P_PERIC0_CD_QCHQCH_CON_PPC_NOCL0_IO0_EVENT_QCHDBG_NFO_QCH_CON_LH_ACEL_MI_D3_CPUCL0_QCHDBG_NFO_QCH_CON_LH_AXI_MI_P_MIF3_CD_QCHDBG_NFO_QCH_CON_LH_AXI_SI_P_MIF0_CD_QCHDBG_NFO_QCH_CON_PPMU_NOCL0_DP_QCHQCH_CON_GPC_NOCL1A_QCHQCH_CON_PPC_AUR_D0_EVENT_QCHDBG_NFO_QCH_CON_PPC_AUR_D0_CYCLE_QCHDBG_NFO_QCH_CON_PPC_TPU_D0_CYCLE_QCHDBG_NFO_QCH_CON_SYSREG_NOCL1A_QCHQCH_CON_LH_AXI_SI_P_HSI1_CD_QCHDBG_NFO_QCH_CON_LH_AXI_MI_G_CSSYS_CU_QCHDBG_NFO_QCH_CON_LH_AXI_MI_D2_RGBP_QCHQCH_CON_LH_AXI_MI_D0_TNR_QCHDBG_NFO_QCH_CON_LH_TAXI_SI_D0_NOCL2AB_NOCL1A_QCHPLL_CON1_PLL_USBQCH_CON_GPC_HSI1_QCHQCH_CON_HSI1_CMU_HSI1_QCHQCH_CON_LH_AXI_MI_LP_CPUCL0_HSI1_CU_QCHblkpwr_yuvpMIF_HCHGEN_CLKMUX_CMUREFEARLY_WAKEUP_GSE_DESTQCH_CON_MAILBOX_APM_AURMCU_QCHQCH_CON_MAILBOX_AP_AURMCUNS1_QCHQCH_CON_MAILBOX_AP_AURMCUTZ_QCHQCH_CON_MAILBOX_AP_DBGCORE_QCHDBG_NFO_QCH_CON_APBIF_GPIO_ALIVE_QCHDBG_NFO_QCH_CON_SYSREG_APM_QCHDBG_NFO_QCH_CON_WDT_APM_QCHDMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5QCH_CON_PCIE_GEN3A_1_QCH_DBGQCH_CON_QE_MMC_CARD_HSI2_QCHQCH_CON_SLH_AXI_MI_P_HSI2_QCHDBG_NFO_QCH_CON_PCIE_GEN3B_1_QCH_DBGQCH_CON_SLH_AXI_MI_P_PERIC0_QCHQCH_CON_SLH_AXI_MI_P_PERIC1_QCHDBG_NFO_QCH_CON_GPC_PERIC1_QCHPLL_SHARED0_D1MUX_CLKCMU_APM_FUNCSRCMUX_CLK_AUR_AURMUX_CLKCMU_HSI2_UFS_EMBDMUX_CLKCMU_TNR_ALIGNMUX_CLK_CPUCL2_CPUMUX_CLK_G3D_STACKSMUX_CLK_NOCL0_NOC_OPTION1MUX_CLKCMU_AUR_AURCTL_USERMUX_CLKCMU_HSI0_USPDPDBG_USERMUX_CLKCMU_PERIC0_USI5_USI_USERCLKCMU_ISPFE_NOCCLKCMU_CPUCL0_CPU_SWITCHDIV_CLK_DPUF1_NOCPCLK_TPU_ADD_CH_CLKDIV_CLK_TPU_TPUCLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_IPCLKPORT_I_CLKGOUT_BLK_APM_UID_SSMT_LP_ALIVE_CPUCL0_IPCLKPORT_ACLKGOUT_BLK_APM_UID_RSTNSYNC_SR_CLK_APM_USI1_UART_INT_IPCLKPORT_CLKCLK_BLK_APM_UID_LH_AXI_SI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLKCLK_BLK_BW_UID_BLK_BW_FRC_OTP_DESERIAL_IPCLKPORT_I_CLKCLKCMU_CPUCL1_BOOSTGATE_CLKCMU_G3D_TRACECLK_BLK_CPUCL0_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_PPMU_CPUCL0_D1_IPCLKPORT_PCLKCLK_BLK_CPUCL0_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLKCLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_MAIN_IPCLKPORT_CLKCLK_BLK_CPUCL0_UID_GRAY2BIN_CNTVALUEB_IPCLKPORT_CLKCLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLKGOUT_BLK_DPUF0_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKMGOUT_BLK_DPUF1_UID_D_TZPC_DPUF1_IPCLKPORT_PCLKGOUT_BLK_EH_UID_GPC_EH_IPCLKPORT_PCLKGOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_ACLKGOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLKCLK_BLK_G2D_UID_LH_AST_SI_ID_G2D0_JPEG_IPCLKPORT_I_CLKCLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLKGOUT_BLK_GDC_UID_SSMT_D_LME_IPCLKPORT_ACLKCLK_BLK_GDC_UID_PPMU_D0_GDC0_IPCLKPORT_ACLKCLK_BLK_GSACORE_UID_GSACORE_CMU_GSACORE_IPCLKPORT_PCLKCLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLKGATE_CLK_GSA_FUNCGOUT_BLK_HSI0_UID_XIU_D2_HSI0_IPCLKPORT_ACLKCLK_BLK_HSI0_UID_I3C2_HSI0_IPCLKPORT_I_SCLKGOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_ACLKGOUT_BLK_HSI2_UID_UASC_PCIE_GEN3A_DBI_1_IPCLKPORT_PCLKCLK_BLK_HSI2_UID_BLK_HSI2_FRC_OTP_DESERIAL_IPCLKPORT_I_CLKGOUT_BLK_ISPFE_UID_SYSMMU_S1_PMMU0_ISPFE_IPCLKPORT_CLKGOUT_BLK_ISPFE_UID_QE_D1_ISPFE_IPCLKPORT_PCLKCLK_BLK_ISPFE_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS4CLK_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKMCLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCP_IPCLKPORT_CLKGOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLKGOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLKGOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLKCLK_BLK_MISC_UID_RSTNSYNC_SR_CLK_MISC_NOCD_IPCLKPORT_CLKCLK_BLK_MISC_UID_RSTNSYNC_SR_CLK_MISC_OSCCLK_IPCLKPORT_CLKGOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLKGOUT_BLK_NOCL0_UID_PPC_CPUCL0_D2_EVENT_IPCLKPORT_PCLKGOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_PCLKCLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC0_CD_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_LH_ATB_MI_T_BDU_CD_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_PPMU_NOCL0_DP_IPCLKPORT_ACLKCLK_BLK_NOCL0_UID_PPMU_NOCL0_S1_IPCLKPORT_ACLKCLK_BLK_NOCL0_UID_PPC_NOCL0_IO0_CYCLE_IPCLKPORT_PCLKCLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_SLC3_DCLK_IPCLKPORT_CLKGOUT_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLKCLK_BLK_NOCL1A_UID_LH_AXI_SI_P_AUR_CD_IPCLKPORT_I_CLKCLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_PCLKCLK_BLK_NOCL1A_UID_LH_AXI_MI_P_TPU_CD_IPCLKPORT_I_CLKCLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLKGOUT_BLK_NOCL2AA_UID_LH_AXI_MI_D3_RGBP_IPCLKPORT_I_CLKCLK_BLK_NOCL2AB_UID_TREX_P_NOCL2AB_IPCLKPORT_PCLKCLK_BLK_NOCL2AB_UID_SLH_AXI_SI_P_GSE_IPCLKPORT_I_CLKCLK_BLK_NOCL2AB_UID_RSTNSYNC_SR_CLK_NOCL2AB_NOCP_IPCLKPORT_CLKGOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLKGOUT_BLK_RGBP_UID_AD_APB_RGBP_IPCLKPORT_PCLKMCLK_BLK_RGBP_UID_SSMT_D3_MCFP_IPCLKPORT_ACLKCLK_BLK_RGBP_UID_QE_D3_RGBP_IPCLKPORT_ACLKCLK_BLK_RGBP_UID_QE_D6_MCFP_IPCLKPORT_PCLKGOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLKGOUT_BLK_TNR_UID_GPC_TNR_IPCLKPORT_PCLKCLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_PCLKCLK_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_PCLKCLK_BLK_TNR_UID_GTNR_ALIGN_IPCLKPORT_ACLKCLK_BLK_TPU_UID_TPU_CMU_TPU_IPCLKPORT_PCLKCLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCD_IPCLKPORT_CLKOSCCLK_EHOSCCLK_GSACOREOSCCLK_HSI2AOC_SYSCTRL_APB_QCHSLH_AXI_SI_LP_AOC_HSI0_QCHAPM_I3C_PMIC_QCH_PINTMEM_QCHMAILBOX_AP_AURMCUNS2_QCHS2MPU_S0_CPUCL0_QCH_S0SLH_AXI_SI_LG_ETR_HSI0_QCHSSMT_CPUCL0_QCHSYSMMU_S0_DPUF0_QCH_S0EH_CMU_EH_QCHPPCFW_G3D1_QCHSSMT_G3D1_QCHGDC0_QCH_C2CLKGDC1_QCH_CLKLH_AST_MI_ID_LME_GDC1_QCHLH_AST_SI_ID_GDC1_LME_QCHSYSMMU_S0_PMMU1_GDC_QCH_S0LH_AXI_MI_P_HSI0_CU_QCHSLH_AXI_MI_P_HSI0_QCHUASC_HSI0_LINK_QCHPCIE_GEN3A_1_QCH_APBSSMT_D0_ISPFE_QCHQE_D5_MCSC_QCHSYSMMU_S0_MCSC_QCH_S0SYSMMU_S0_PMMU0_MFC_QCHMCT_QCHPDMA0_QCHLH_AST_MI_G_NOCL2AA_QCHPPC_NOCL1A_M0_EVENT_QCHPPC_TPU_D0_EVENT_QCHLH_AXI_SI_P_HSI1_CD_QCHSLH_AXI_SI_P_HSI1_QCHLH_AXI_MI_D3_ISPFE_QCHLH_AXI_MI_D6_RGBP_QCHLH_ACEL_MI_D2_G2D_QCHLH_AXI_MI_P_PERIC0_CU_QCHUSI3_USI_QCHUSI10_USI_QCHUSI13_USI_QCHUSI15_USI_QCHLH_AXI_SI_D6_RGBP_QCHQE_D10_MCFP_QCHSLH_AXI_MI_P_RGBP_QCHSSMT_D1_TNR_QCHSSMT_D3_TNR_QCHVCLK_CLKCMU_HSI0_USB32DRDVCLK_DIV_CLK_PERIC0_USI5_USIVCLK_IP_XIU_DP_AOCVCLK_IP_LH_AXI_MI_LP_AOC_HSI0_CDVCLK_IP_LH_AXI_MI_LD_HSI1_AOCVCLK_IP_SLH_AXI_SI_LG_SCAN2DRAMVCLK_IP_SSMT_P_AURVCLK_IP_LH_AXI_SI_D_BWVCLK_IP_APB_ASYNC_P_CSSYS_0VCLK_IP_XIU_DP_CSSYSVCLK_IP_LH_AXI_MI_G_CSSYS_CDVCLK_IP_LH_ATB_SI_LT1_TPU_CPUCL0_CUVCLK_IP_PPMU_CPUCL0_D0VCLK_IP_XIU_P2_CPUCL0VCLK_IP_LH_AXI_MI_IP_CPUCL2VCLK_IP_DPUB_CMU_DPUBVCLK_IP_LH_AXI_MI_LD0_DPUF1_DPUF0VCLK_IP_BLK_DPUF0_FRC_OTP_DESERIALVCLK_IP_LH_AXI_SI_LD1_DPUF1_DPUF0VCLK_IP_GPC_EHVCLK_IP_LH_AST_MI_ID_JPEG_G2D1VCLK_IP_LH_AST_MI_ID_LME_GDC1VCLK_IP_GPIO_GSACORE1VCLK_IP_SYSREG_HSI0VCLK_IP_I3C2_HSI0VCLK_IP_SSMT_HSI2VCLK_IP_SSMT_D0_MCSCVCLK_IP_D_TZPC_MFCVCLK_IP_LH_AST_SI_L_IRI_GIC_CLUSTER0_CDVCLK_IP_SLH_AXI_MI_P_MISCVCLK_IP_LH_AXI_MI_P_CPUCL0_CDVCLK_IP_LH_ACEL_MI_D1_G3DVCLK_IP_SLH_AXI_SI_P_AURVCLK_IP_TREX_P_NOCL1BVCLK_IP_I3C1VCLK_IP_LH_AXI_SI_P_PERIC0_CUVCLK_IP_USI13_USIVCLK_IP_I3C0VCLK_IP_PPMU_D3_TNRVCLK_IP_QE_D8_TNRVCLK_CLKOUT06%s : req %d KHz %d margin_mif_write_fileCLKCMU3Un-support PLL type vclk3%s %s: error on handling disable sequence. (cpu : %d) pmucal_cpu_cluster_disableEMBEDDED_G3D_CONFIGURATIONDBG_NFO_QCH_CON_LH_AXI_SI_D1_DPUF0_QCHDBG_NFO_QCH_CON_D_TZPC_DPUF1_QCHG2D_STATUSQCH_CON_LH_ACEL_SI_D2_G2D_QCHQCH_CON_LH_AST_SI_ID_G2D1_JPEG_QCHDBG_NFO_QCH_CON_PPMU_D1_G2D_QCHDBG_NFO_QCH_CON_LH_AST_SI_ID_LME_GDC1_QCHQCH_CON_PPMU_D1_MCSC_QCHDBG_NFO_QCH_CON_SSMT_D1_MCSC_QCHDBG_NFO_QCH_CON_SSMT_D3_MCSC_QCHQCH_CON_LH_AXI_SI_D0_MFC_QCHDBG_NFO_QCH_CON_D_TZPC_MFC_QCHQCH_CON_SSMT_D0_MCFP_QCHQCH_CON_SYSMMU_S1_PMMU2_RGBP_QCH_S0DBG_NFO_QCH_CON_QE_D6_RGBP_QCHDBG_NFO_QCH_CON_SSMT_D0_MCFP_QCHDBG_NFO_QCH_CON_SYSMMU_S0_PMMU1_RGBP_QCH_S0DBG_NFO_QCH_CON_SYSMMU_S0_RGBP_QCH_S0QCH_CON_GTNR_MERGE_QCH_01QCH_CON_LH_AST_SI_L_OTF_TNR_GSE_QCHQCH_CON_PPMU_D0_TNR_QCHQCH_CON_SSMT_D11_TNRA_QCHDBG_NFO_QCH_CON_LH_AXI_SI_D1_TNR_QCHDBG_NFO_QCH_CON_LH_AXI_SI_D3_TNR_QCHDBG_NFO_QCH_CON_PPMU_D5_TNR_QCHDBG_NFO_QCH_CON_SSMT_D2_TNR_QCHDBG_NFO_QCH_CON_SSMT_D8_TNR_QCHQCH_CON_QE_D0_YUVP_QCHQCH_CON_SYSMMU_S0_PMMU0_YUVP_QCH_S0DBG_NFO_QCH_CON_SSMT_D0_YUVP_QCHAOC_CONFIGURATIONPLL_LOCKTIME_PLL_AURDBG_NFO_QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CD_QCHDBG_NFO_QCH_CON_SSMT_D0_AUR_QCHQCH_CON_LH_AXI_MI_IP_EH_QCHQCH_CON_PPC_EH_CYCLE_QCHQCH_CON_PPMU_EH_QCHDBG_NFO_QCH_CON_LH_AXI_SI_IP_EH_QCHDBG_NFO_QCH_CON_QE_EH_QCHQCH_CON_LH_AXI_SI_D3_ISPFE_QCHDBG_NFO_QCH_CON_PPMU_D1_ISPFE_QCHTPU_CLKDIVSTEP_VDROOP_FLTPLL_CON6_PLL_NOCL0QCH_CON_BDU_QCHQCH_CON_LH_AST_SI_G_NOCL2AB_CU_QCHQCH_CON_LH_ATB_MI_T_BDU_CD_QCHQCH_CON_LH_TAXI_MI_D2_NOCL1A_NOCL0_QCHQCH_CON_PPC_CPUCL0_D0_EVENT_QCHQCH_CON_SFR_APBIF_CMU_TOPC_QCHDBG_NFO_DMYQCH_CON_PPC_DBG_CC_QCHDBG_NFO_QCH_CON_LH_AST_MI_G_NOCL1A_CU_QCHDBG_NFO_QCH_CON_LH_AST_MI_G_NOCL2AA_QCHDBG_NFO_QCH_CON_LH_AXI_MI_P_CPUCL0_CD_QCHDBG_NFO_QCH_CON_SLH_AXI_SI_P_PERIC1_QCHQCH_CON_LH_AST_MI_G_NOCL1A_CD_QCHQCH_CON_PPC_G3D_D0_EVENT_QCHQCH_CON_PPMU_NOCL1A_M3_QCHDBG_NFO_QCH_CON_PPC_NOCL2AB_S0_EVENT_QCHDBG_NFO_QCH_CON_LH_AST_SI_G_NOCL1B_CD_QCHDBG_NFO_QCH_CON_TREX_P_NOCL1B_QCHQCH_CON_LH_AST_SI_G_NOCL2AB_CD_QCHQCH_CON_LH_AXI_MI_D2_TNR_QCHQCH_CON_NOCL2AB_CMU_NOCL2AB_QCHDBG_NFO_QCH_CON_LH_AXI_MI_D0_G2D_QCHPLL_CON4_PLL_USBHSI0_CMU_HSI0_CONTROLLER_OPTIONCLK_CON_DIV_DIV_CLK_HSI1_NOC_LHQCH_CON_SLH_AXI_MI_P_HSI1_QCHDBG_NFO_QCH_CON_SYSMMU_S0_PMMU0_HSI1_QCH_S0CPUCL0_HCHGEN_CLKMUX_CPUCPUCL2_HCHGEN_CLKMUX_CPUCPUCL2_CLKDIVSTEPPLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USERQCH_CON_MAILBOX_AOC_AURCORE0_QCHDBG_NFO_QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCHQCH_CON_SSMT_SC_QCHQCH_CON_TMU_SUB_QCHDBG_NFO_QCH_CON_SPDMA1_QCHDBG_NFO_QCH_CON_SSMT_RTIC_QCHQCH_CON_PERIC0_CMU_PERIC0_QCHDBG_NFO_QCH_CON_D_TZPC_PERIC0_QCHDBG_NFO_QCH_CON_USI13_USI_QCHMUX_CLKCMU_YUVP_NOCMUX_CLKCMU_G3D_GLBMUX_CLK_HSI0_USI2MUX_CLK_NOCL1B_NOC_OPTION1MUX_CLKCMU_CPUCL2_SWITCH_USERMUX_CLKCMU_GDC_LME_USERMUX_CLKCMU_GDC_GDC1_USERMUX_CLKCMU_PERIC0_USI1_USI_USERCLKCMU_CPUCL0_DSU_SWITCHCLKCMU_CIS_CLK5DIV_CLK_PERIC1_USI15_USICLK_BLK_AOC_UID_LH_AXI_SI_LP_AOC_ALIVE_CD_IPCLKPORT_I_CLKGOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLKGOUT_BLK_APM_UID_SSMT_D_ALIVE_IPCLKPORT_PCLKCLK_BLK_AUR_UID_SSMT_P_AUR_IPCLKPORT_ACLKGOUT_BLK_BW_UID_GPC_BW_IPCLKPORT_PCLKCLK_BLK_BW_UID_SYSMMU_S0_BW_IPCLKPORT_CLKGATE_CLKCMU_PERIC0_IPGOUT_BLK_CPUCL0_UID_XIU_DP_CSSYS_IPCLKPORT_ACLKCLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_AXI_DS_128TO32_P_PCIE_CLUSTER0_IPCLKPORT_MAINCLKCLK_BLK_CPUCL0_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_ACLKCLK_BLK_CPUCL0_UID_XIU_P2_CPUCL0_IPCLKPORT_ACLKGOUT_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLKCLK_BLK_EH_UID_LH_AXI_SI_P_EH_CU_IPCLKPORT_I_CLKCLK_BLK_EH_UID_PPC_EH_CYCLE_IPCLKPORT_ACLKCLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLKCLK_BLK_G3D_UID_LH_ATB_SI_LT_G3D_CPUCL0_IPCLKPORT_I_CLKCLK_BLK_G3D_UID_SLH_AXI_SI_D_G3DMMU_IPCLKPORT_I_CLKGOUT_BLK_GDC_UID_D_TZPC_GDC_IPCLKPORT_PCLKCLK_BLK_GSACTRL_UID_RSTNSYNC_SR_CLK_GSACTRL_NOCP_IPCLKPORT_CLKGOUT_BLK_GSE_UID_SYSMMU_S0_GSE_IPCLKPORT_CLKGOUT_BLK_GSE_UID_QE_D0_GSE_IPCLKPORT_PCLKGOUT_BLK_GSE_UID_XIU_D1_GSE_IPCLKPORT_ACLKCLK_BLK_GSE_UID_BLK_GSE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLKCLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_EUSB_IPCLKPORT_CLKGOUT_BLK_HSI1_UID_GPC_HSI1_IPCLKPORT_PCLKCLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_NOC_IPCLKPORT_CLKGOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPROGOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLKGOUT_BLK_HSI2_UID_PCIE_GEN3A_1_IPCLKPORT_PCIE_PHY_TOP_X1_INST_0_PHY_UDBG_I_APB_PCLKCLK_BLK_HSI2_UID_RSTNSYNC_SR_CLK_HSI2_NOC_LH_IPCLKPORT_CLKCLK_BLK_MCSC_UID_PPMU_D6_MCSC_IPCLKPORT_PCLKCLK_BLK_MCSC_UID_SSMT_D4_MCSC_IPCLKPORT_PCLKCLK_BLK_MCSC_UID_SSMT_D6_MCSC_IPCLKPORT_ACLKCLK_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLKGOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLKCLK_BLK_MFC_UID_RSTNSYNC_SR_CLK_MFC_NOCD_IPCLKPORT_CLKGOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLKGOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2AGOUT_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLKCLK_BLK_MISC_UID_RSTNSYNC_SR_CLK_MISC_SC_IPCLKPORT_CLKGOUT_BLK_NOCL0_UID_SYSREG_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RIC1_OSCCLK_IPCLKPORT_CLKCLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_IPCLKGOUT_BLK_RGBP_UID_RGBP_IPCLKPORT_CLKGOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCP_IPCLKPORT_CLKCLK_BLK_TPU_UID_DAPAPBAP_TPU_IPCLKPORT_DAPCLKCLK_BLK_YUVP_UID_QE_D4_YUVP_IPCLKPORT_ACLKOSCCLK_DPUBOSCCLK_ISPFEOSCCLK_FRC_NOCL2AAOSCCLK_YUVPPLL_SHARED0_D2APBIF_GPIO_CUSTOM_ALIVE_QCHGPC_APM_CUSTOM_QCHSS_DBGCORE_QCH_DBGTRTC_QCHSSMT_D1_AUR_QCHSYSMMU_S0_PMMU0_BW_QCHCPUCL0_CMU_CPUCL0_QCHLH_ATB_MI_LT1_TPU_CPUCL0_CU_QCHLH_AXI_SI_LP_CPUCL0_HSI2_QCHADD1_APBIF_CPUCL1_QCHCPUCL1_QCH_CORE7CLKPPMU_EH_QCHLH_AST_SI_ID_G2D1_JPEG_QCHPPMU_D1_G2D_QCHPPMU_D2_G2D_QCHLH_AST_MI_L_OTF_TNR_GSE_QCHD_TZPC_HSI1_QCHPCIE_IA_GEN3B_1_QCHQE_PCIE_GEN3A_HSI2_QCHUFS_EMBD_QCHSYSMMU_S0_ISPFE_QCH_S0SYSMMU_S1_PMMU0_ISPFE_QCH_S0LH_AXI_SI_D0_MCSC_QCHGPC_MISC_QCHLH_TAXI_MI_D0_NOCL2AA_NOCL1A_QCHPPC_AOC_CYCLE_QCHLH_ACEL_MI_D_HSI2_QCHLH_AST_SI_G_NOCL2AA_QCHSLH_AXI_SI_P_MCSC_QCHI3C3_QCH_SCLKUSI9_USI_QCHLH_AST_MI_I_RGBP_MCFP_QCHQE_D9_MCFP_QCHPPMU_D11_TNRA_QCH_S0SYSMMU_S1_TNR_QCH_S0CTRL_OPTION_CMU_NOCL2AAVCLK_BLK_MCSCVCLK_IP_PPMU_PCIEVCLK_IP_GREBEINTEGRATIONVCLK_IP_LH_AXI_MI_LP_AOC_ALIVE_CUVCLK_IP_LH_AST_MI_L_ICC_CLUSTER0_GIC_CDVCLK_IP_LH_AXI_SI_LP_CPUCL0_HSI2_CDVCLK_IP_SSMT_D1_DPUF0VCLK_IP_G2D_CMU_G2DVCLK_IP_SSMT_D2_G2DVCLK_IP_LH_AST_SI_ID_JPEG_G2D0VCLK_IP_SYSMMU_S0_PMMU2_G3DVCLK_IP_PPMU_D2_GDC1VCLK_IP_LH_AXI_SI_LD_HSI1_AOCVCLK_IP_SSMT_D3_ISPFEVCLK_IP_LH_AXI_SI_IP_ISPFEVCLK_IP_SSMT_D4_MCSCVCLK_IP_LH_AXI_SI_D0_MFCVCLK_IP_SYSMMU_S0_PMMU0_MFCVCLK_IP_PPC_DEBUGVCLK_IP_SPDMA0VCLK_IP_GPC_NOCL0VCLK_IP_PPC_NOCL1A_M2_EVENTVCLK_IP_MPACE_ASB_D3_MIFVCLK_IP_SLC_CH_TOPVCLK_IP_GRAY2BIN_ATB_TSVALUEVCLK_IP_LH_AXI_SI_P_MISC_GIC_CDVCLK_IP_LH_AXI_MI_P_MIF3_CDVCLK_IP_PPC_NOCL1B_M0_CYCLEVCLK_IP_SLC_CH3VCLK_IP_LD_SLC3_FRC_OTP_DESERIALVCLK_IP_PPC_NOCL2AA_S1_EVENTVCLK_IP_LH_ACEL_MI_D1_AURVCLK_IP_D_TZPC_NOCL1BVCLK_IP_LH_AXI_MI_P_HSI0_CDVCLK_IP_LH_AXI_MI_D1_GDCVCLK_IP_LH_AXI_MI_D0_TNRVCLK_IP_XIU_D3_TNRVCLK_IP_SYSMMU_S0_PMMU0_TPUclk_infoCLK_NODE_INFO: echo "clk_name" > clk_info BLK_CMU_INFO: echo blk_hwacg #cmu_blk_id > clk_info TOP_CMU_INFO: echo hwacg > clk_info pmucal_system_enter%s there is no sequence element for pd(%d) power-on.3%s core index(%d) is out of supported range (0~%d). 3%s there is no sequence element for core(%d) power-off. PLL_LOCKTIME_REG_PLL_G3DPLL_CON4_PLL_G3DPLL_CON3_PLL_G3D_L2DBG_NFO_QCH_CON_PPMU_G3D_D2_QCHDBG_NFO_QCH_CON_SSMT_G3D2_QCHDPUF0_STATUSDBG_NFO_QCH_CON_LH_AXI_SI_D0_DPUF0_QCHDBG_NFO_QCH_CON_SYSMMU_S0_PMMU0_DPUF0_QCH_S0QCH_CON_D_TZPC_DPUF1_QCHQCH_CON_PPMU_D2_G2D_QCHQCH_CON_SYSMMU_S0_PMMU2_G2D_QCHDBG_NFO_QCH_CON_PPMU_D2_GDC0_QCHDBG_NFO_QCH_CON_SSMT_D0_GDC0_QCHQCH_CON_GSE_QCH_GSE_VOTFDBG_NFO_QCH_CON_QE_D1_MCSC_QCHQCH_CON_D_TZPC_MFC_QCHQCH_CON_SYSREG_MFC_QCHMFC_CMU_MFC_CONTROLLER_OPTIONRGBP_STATUSQCH_CON_MCFP_QCH_CLKQCH_CON_QE_D9_MCFP_QCHQCH_CON_RGBP_CMU_RGBP_QCHDBG_NFO_QCH_CON_LH_AST_MI_I_RGBP_MCFP_QCHDBG_NFO_QCH_CON_QE_D9_MCFP_QCHDBG_NFO_QCH_CON_SYSREG_RGBP_QCHQCH_CON_PPMU_D2_TNR_QCHQCH_CON_SYSMMU_S0_TNR_QCH_S0DBG_NFO_QCH_CON_LH_AST_MI_L_OTF_YUVP_TNR_QCHDBG_NFO_QCH_CON_PPMU_D9_TNR_QCHDBG_NFO_QCH_CON_SLH_AXI_MI_P_TNR_QCHDBG_NFO_QCH_CON_SYSMMU_S1_TNR_QCH_S0QCH_CON_PPMU_D1_YUVP_QCHDBG_NFO_QCH_CON_QE_D4_YUVP_QCHDBG_NFO_QCH_CON_YUVP_QCH_VOTF0QCH_CON_SSMT_D1_AUR_QCHQCH_CON_UASC_P1_AUR_QCHQCH_CON_QE_D1_ISPFE_QCHQCH_CON_QE_D2_ISPFE_QCHPLL_CON8_PLL_NOCL0QCH_CON_LH_AST_SI_G_NOCL1B_CU_QCHDMYQCH_CON_SLC_CH3_QCHQCH_CON_LH_TAXI_MI_D3_NOCL1A_NOCL0_QCHQCH_CON_LH_AXI_SI_P_EH_CD_QCHDBG_NFO_QCH_CON_BDU_QCHDBG_NFO_QCH_CON_LH_AST_MI_G_NOCL2AA_CU_QCHDBG_NFO_QCH_CON_LH_ATB_SI_T_BDU_QCHDBG_NFO_QCH_CON_LH_AXI_SI_P_MIF1_CD_QCHDBG_NFO_QCH_CON_PPC_CPUCL0_D2_EVENT_QCHDBG_NFO_QCH_CON_PPMU_NOCL0_IOC0_QCHDBG_NFO_QCH_CON_TREX_D_NOCL0_QCHQCH_CON_LH_AXI_SI_P_TPU_CD_QCHQCH_CON_PPC_AUR_D0_CYCLE_QCHQCH_CON_PPC_G3D_D2_EVENT_QCHDBG_NFO_QCH_CON_LH_TAXI_MI_P_NOCL0_NOCL1A_QCHDBG_NFO_QCH_CON_PPC_G3D_D0_EVENT_QCHQCH_CON_LH_TAXI_MI_P_NOCL0_NOCL1B_QCHDBG_NFO_QCH_CON_SLH_AXI_SI_P_HSI1_QCHQCH_CON_LH_AXI_MI_D0_DPUF0_QCHQCH_CON_LH_AXI_SI_P_HSI2_CD_QCHQCH_CON_SLH_AXI_SI_P_DPUF0_QCHQCH_CON_SLH_AXI_SI_P_HSI2_QCHDBG_NFO_QCH_CON_LH_AXI_MI_D2_ISPFE_QCHDBG_NFO_QCH_CON_LH_AXI_MI_P_HSI2_CD_QCHNOCL2AA_CMU_NOCL2AA_CONTROLLER_OPTIONDBG_NFO_QCH_CON_GPC_NOCL2AB_QCHDBG_NFO_QCH_CON_SLH_AXI_SI_P_TNR_QCHCLK_CON_DIV_DIV_CLK_HSI0_USI2CLK_CON_MUX_MUX_CLK_HSI0_RTCCLKPLL_CON0_MUX_CLKCMU_HSI0_USB32DRD_USERDMYQCH_CON_I3C2_HSI0_QCH_SCLKQCH_CON_LH_AXI_MI_LG_ETR_HSI0_CU_QCHDBG_NFO_QCH_CON_UASC_PCIE_GEN3A_DBI_0_QCHblkpwr_dpubblkpwr_mfcblkpwr_nocl1aEXT_REGULATOR_CPUCL2_DURATIONEXT_REGULATOR_G3D_DURATIONCLK_CON_DIV_DIV_CLK_APM_NOC_LHCLK_CON_DIV_DIV_CLK_PERIC0_USI2_USICLK_CON_DIV_DIV_CLK_PERIC0_USI6_USIQCH_CON_GREBEINTEGRATION_QCH_DBGDBG_NFO_QCH_CON_APM_USI0_USI_QCHDBG_NFO_QCH_CON_MAILBOX_AP_AURMCUNS2_QCHDBG_NFO_QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCHDBG_NFO_QCH_CON_LH_AXI_MI_P_MISC_GIC_CU_QCHDBG_NFO_QCH_CON_MMC_CARD_QCHDBG_NFO_QCH_CON_SSMT_PCIE_IA_GEN3A_1_QCHDBG_NFO_QCH_CON_PCIE_GEN3B_1_QCH_PCS_APBDMYQCH_CON_I3C3_QCH_SCLKDBG_NFO_DMYQCH_CON_I3C2_QCH_SCLKDBG_NFO_QCH_CON_USI0_UART_QCHDBG_NFO_QCH_CON_USI1_USI_QCHCPUCL1_CMU_CPUCL1_CONTROLLER_OPTIONMUX_CLKCMU_MISC_NOCMUX_CLKCMU_DPUB_NOCMUX_CLKCMU_EH_NOCMUX_CLKCMU_CMU_BOOST_OPTION1MUX_CLK_HSI0_USI0MUX_CLK_HSI0_RTCCLKMUX_CLKCMU_GSE_NOC_USERCLKCMU_G2D_G2DCLKCMU_CIS_CLK1CLKCMU_NOCL1A_NOCPLL_SHARED0_DIV5CLKCMU_AUR_AURCTLDIV_CLK_PERIC0_USI14_USICLK_BLK_AOC_UID_SLH_AXI_MI_P_AOC_IPCLKPORT_I_CLKGOUT_BLK_APM_UID_XIU_DP_ALIVE_IPCLKPORT_ACLKGOUT_BLK_APM_UID_TRTC_IPCLKPORT_PCLKGOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLKGOUT_BLK_APM_UID_LH_AXI_MI_IG_SWD_IPCLKPORT_I_CLKCLK_BLK_APM_UID_LH_AXI_MI_LP_AOC_ALIVE_CU_IPCLKPORT_I_CLKCLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_ACLKCLK_BLK_AUR_UID_ADD_APBIF_AUR_IPCLKPORT_PCLKCLK_BLK_AUR_UID_LH_AXI_SI_P_AUR_CU_IPCLKPORT_I_CLKGOUT_BLK_BW_UID_PPMU_BW_IPCLKPORT_ACLKGOUT_BLK_BW_UID_SYSREG_BW_IPCLKPORT_PCLKGATE_CLKCMU_HSI1_NOCGATE_CLKCMU_GSE_NOCCLKCMU_NOCL0_BOOSTGATE_CLKCMU_G3D_GLBGATE_CLKCMU_MISC_SCGOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PERIPHCLK_IPCLKPORT_CLKCLK_BLK_CPUCL0_UID_PPMU_CPUCL0_D2_IPCLKPORT_PCLKCLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PPUCLKCLK_BLK_CPUCL0_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLKCLK_BLK_CPUCL0_UID_LH_ACEL_SI_D2_CPUCL0_IPCLKPORT_I_CLKGATE_CLK_CLUSTER0_PCLKCLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CLUSTER0_ACLK_NON_MAIN_IPCLKPORT_CLKCLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCD_IPCLKPORT_CLKCLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM0GOUT_BLK_DPUF0_UID_PPMU_D0_DPUF0_IPCLKPORT_ACLKGOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DPUFCLK_BLK_DPUF0_UID_SSMT_D0_DPUF0_IPCLKPORT_PCLKGOUT_BLK_EH_UID_LH_AXI_MI_P_EH_CU_IPCLKPORT_I_CLKGOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_PCLKGOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_IPCLKPORT_CLKCLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLKGOUT_BLK_G2D_UID_SLH_AXI_MI_P_G2D_IPCLKPORT_I_CLKCLK_BLK_G3D_UID_SSMT_G3D3_IPCLKPORT_PCLKGOUT_BLK_GDC_UID_QE_D0_GDC0_IPCLKPORT_ACLKCLK_BLK_GDC_UID_PPMU_D2_GDC1_IPCLKPORT_PCLKCLK_BLK_GDC_UID_LH_AST_SI_ID_GDC1_GDC0_IPCLKPORT_I_CLKGOUT_BLK_GSE_UID_AD_APB_GSE_IPCLKPORT_PCLKMGOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLKCLK_BLK_HSI0_UID_SYSMMU_S0_HSI0_IPCLKPORT_CLKCLK_BLK_HSI0_UID_AD_APB_EUSBPHY_HSI0_IPCLKPORT_PCLKMGOUT_BLK_HSI1_UID_PCIE_GEN3_0_IPCLKPORT_PCIE_PHY_TOP_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLKGOUT_BLK_HSI1_UID_UASC_PCIE_GEN3A_SLV_0_IPCLKPORT_ACLKCLK_BLK_HSI1_UID_SYSMMU_S0_HSI1_IPCLKPORT_CLKCLK_BLK_HSI1_UID_LH_AXI_MI_LP_CPUCL0_HSI1_IPCLKPORT_I_CLKCLK_BLK_HSI1_UID_LH_AXI_SI_LD_HSI1_AOC_IPCLKPORT_I_CLKGOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLKGOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLKGOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLKGOUT_BLK_HSI2_UID_UASC_PCIE_GEN3B_DBI_1_IPCLKPORT_ACLKGOUT_BLK_ISPFE_UID_RSTNSYNC_SR_CLK_ISPFE_NOCD_IPCLKPORT_CLKCLK_BLK_ISPFE_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS11CLK_BLK_ISPFE_UID_RSTNSYNC_CLK_ISPFE_NOCD_IPTOP_IPCLKPORT_CLKGOUT_BLK_MCSC_UID_SYSMMU_S0_MCSC_IPCLKPORT_CLKGOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLKCLK_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_ACLKCLK_BLK_MCSC_UID_BLK_MCSC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLKGOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_ACLKCLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLKGOUT_BLK_MIF_UID_GEN_WREN_SECURE_IPCLKPORT_PCLKCLK_BLK_MIF_UID_LH_AXI_SI_P_MIF_CU_IPCLKPORT_I_CLKGOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLKCLK_BLK_MISC_UID_SLH_AXI_MI_P_MISC_GIC_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_CD_IPCLKPORT_I_CLKCLK_BLK_NOCL1A_UID_LH_AST_MI_G_NOCL1A_CD_IPCLKPORT_I_CLKCLK_BLK_NOCL1A_UID_PPMU_NOCL1A_M3_IPCLKPORT_ACLKGOUT_BLK_NOCL2AA_UID_LH_AXI_MI_D0_ISPFE_IPCLKPORT_I_CLKCLK_BLK_NOCL2AA_UID_RSTNSYNC_SR_CLK_NOCL2AA_NOCP_LH_IPCLKPORT_CLKGOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLKCLK_BLK_PERIC0_UID_LH_AXI_SI_P_PERIC0_CU_IPCLKPORT_I_CLKCLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLKCLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLKCLK_BLK_RGBP_UID_SSMT_D0_RGBP_IPCLKPORT_ACLKCLK_BLK_RGBP_UID_QE_D0_RGBP_IPCLKPORT_PCLKCLK_BLK_RGBP_UID_PPMU_D2_RGBP_IPCLKPORT_ACLKCLK_BLK_RGBP_UID_SYSMMU_S1_PMMU2_RGBP_IPCLKPORT_CLKGOUT_BLK_TNR_UID_SYSMMU_S1_PMMU2_TNR_IPCLKPORT_CLKGOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_ACLKCLK_BLK_TNR_UID_GTNR_MERGE_IPCLKPORT_ACLKCLK_BLK_TPU_UID_TPU_IPCLKPORT_APB_PCLKCLK_BLK_TPU_UID_SYSMMU_S0_TPU_IPCLKPORT_CLKGOUT_BLK_YUVP_UID_GPC_YUVP_IPCLKPORT_PCLKOSCCLK_CPUCL0LH_AXI_MI_LD_HSI1_AOC_QCHSYSREG_AOC_QCHD_TZPC_APM_QCHMAILBOX_AP_AURMCUTZ_QCHUASC_BW_QCHDFTMUX_CMU_QCH_CIS_CLK2GPC_CPUCL0_QCHLH_ATB_SI_LT0_TPU_CPUCL0_CU_QCHLH_AXI_MI_IG_HSI0_QCHCPUCL1_QCH_CORE6CLKSYSMMU_S0_PMMU1_DPUF0_QCH_S0ADM_DAP_G_GPU_QCHGPC_G3D_QCHPUF_GSACORE_QCHGSE_QCH_GSEPCIE_GEN3B_1_QCH_UDBGSYSMMU_S0_PMMU0_HSI2_QCHLH_AXI_MI_IP_ISPFE_QCHMIPI_PHY_LINK_WRAP_QCH_CSIS8PPMU_D2_MCSC_QCHGIC_QCHMISC_CMU_MISC_QCHPPC_CPUCL0_D3_EVENT_QCHPPC_G3D_D2_EVENT_QCHLH_AST_SI_G_NOCL1B_CD_QCHLH_AXI_MI_P_HSI0_CD_QCHLH_AXI_MI_D2_ISPFE_QCHTREX_D_NOCL2AA_QCHLH_AXI_MI_D0_G2D_QCHPPMU_NOCL2AB_M0_QCHLH_AXI_SI_D1_RGBP_QCHLH_AXI_SI_D4_RGBP_QCHSSMT_D11_TNRA_QCHLH_ATB_MI_LT0_TPU_CPUCL0_CD_QCHCTRL_OPTION_CMU_GSECTRL_OPTION_CMU_HSI2CTRL_OPTION_CMU_RGBPVCLK_MUX_CLK_HSI0_USB20_REFVCLK_MUX_MIF_CMUREFVCLK_DIV_CLK_GSACORE_UARTVCLK_BLK_S2DVCLK_IP_APBIF_GPIO_ALIVEVCLK_IP_APM_USI0_UARTVCLK_IP_CPUCL0_CMU_CPUCL0VCLK_IP_D_TZPC_CPUCL0VCLK_IP_LH_ATB_MI_LT_AUR_CPUCL0VCLK_IP_LH_AXI_SI_ID_PPUVCLK_IP_LH_ATB_MI_LT_G3D_CPUCL0VCLK_IP_DPUF0_CMU_DPUF0VCLK_IP_SYSMMU_S0_DPUF0VCLK_IP_SSMT_D1_DPUF1VCLK_IP_PPMU_EHVCLK_IP_LH_AXI_SI_D_GSAVCLK_IP_DP_LINKVCLK_IP_ETR_MIUVCLK_IP_SLH_AXI_MI_LG_ETR_HSI0VCLK_IP_PPMU_D3_MCSCVCLK_IP_SLH_AXI_SI_P_MIF2VCLK_IP_LH_AXI_MI_P_MIF1_CDVCLK_IP_LH_AXI_MI_P_PERIC0_CDVCLK_IP_LH_TAXI_MI_D2_NOCL1A_NOCL0VCLK_IP_LH_TAXI_MI_D3_NOCL1A_NOCL0VCLK_IP_PPMU_NOCL0_DPVCLK_IP_PPC_G3D_D1_EVENTVCLK_IP_PPC_BW_D_EVENTVCLK_IP_TREX_D_NOCL1BVCLK_IP_TREX_D_NOCL2AAVCLK_IP_TREX_P_NOCL2AAVCLK_IP_LH_AXI_MI_D0_G2DVCLK_IP_AD_APB_MCFPVCLK_IP_LH_AXI_SI_D5_RGBPVCLK_IP_PPMU_D10_TNRA3fixed pll enable time out, '%s' 6cmu_top_mux_dbg_offset : 0x%x vclk_rate%s %s: error on handling enable sequence. (pd_id : %d)3%s %s: there is no cpu/cluster list. aborting init... PLL_CON5_PLL_G3D_L2PLL_CON1_PLL_G3D_L2DBG_NFO_QCH_CON_G3D_CMU_G3D_QCHDBG_NFO_QCH_CON_PPMU_G3D_D1_QCHDPUB_CMU_DPUB_CONTROLLER_OPTIONDBG_NFO_QCH_CON_PPMU_D1_DPUF0_QCHQCH_CON_JPEG_QCHCLK_CON_DIV_DIV_CLK_GDC_NOCPQCH_CON_GPC_GDC_QCHQCH_CON_LH_AXI_MI_LD_RGBP_GDC_QCHDBG_NFO_QCH_CON_SYSREG_GDC_QCHDBG_NFO_QCH_CON_GPC_GSE_QCHDBG_NFO_QCH_CON_PPMU_D6_MCSC_QCHQCH_CON_GPC_MFC_QCHQCH_CON_MFC_QCHDBG_NFO_QCH_CON_SYSMMU_S0_PMMU1_MFC_QCHQCH_CON_LH_AXI_SI_LD_RGBP_GDC_QCHQCH_CON_QE_D4_RGBP_QCHQCH_CON_RGBP_QCHDBG_NFO_QCH_CON_SYSMMU_S1_PMMU0_RGBP_QCH_S0QCH_CON_PPMU_D8_TNR_QCHQCH_CON_QE_D5_TNR_QCHQCH_CON_SSMT_D9_TNR_QCHDBG_NFO_QCH_CON_LH_AXI_SI_D4_TNR_QCHDBG_NFO_QCH_CON_QE_D10_TNRA_QCHDBG_NFO_QCH_CON_SSMT_D3_TNR_QCHQCH_CON_LH_AST_SI_L_OTF_YUVP_GSE_QCHQCH_CON_YUVP_QCH_VOTF0PLL_CON3_PLL_AURDBG_NFO_QCH_CON_SYSMMU_S0_AUR_QCH_S0QCH_CON_BW_CMU_BW_QCHQCH_CON_D_TZPC_BW_QCHQCH_CON_SLH_AXI_MI_P_BW_QCHQCH_CON_TREX_D_BW_QCHDBG_NFO_QCH_CON_LH_AXI_MI_P_EH_CU_QCHQCH_CON_ISPFE_CMU_ISPFE_QCHQCH_CON_SSMT_D0_ISPFE_QCHDBG_NFO_QCH_CON_D_TZPC_ISPFE_QCHCLK_CON_MUX_MUX_CLK_TPU_NOC_LPMDBG_NFO_DMYQCH_CON_ADD_TPU_QCHTPU_CLKDIVSTEP_OCP_FLTCLK_CON_MUX_MUX_NOCL0_CMUREFQCH_CON_LH_ACEL_MI_D3_CPUCL0_QCHQCH_CON_LH_AST_MI_G_NOCL1A_CU_QCHQCH_CON_LH_AST_SI_G_NOCL1A_CU_QCHQCH_CON_LH_AXI_SI_P_MIF0_CD_QCHQCH_CON_LH_TAXI_SI_P_NOCL0_NOCL1B_QCHQCH_CON_PPMU_NOCL0_CPUCL0_P_QCHQCH_CON_PPC_NOCL0_IO0_CYCLE_QCHDBG_NFO_QCH_CON_LH_TAXI_SI_P_NOCL0_NOCL1B_QCHQCH_CON_LH_ACEL_MI_D1_G3D_QCHQCH_CON_LH_TAXI_SI_D2_NOCL1A_NOCL0_QCHQCH_CON_LH_TAXI_SI_D3_NOCL1A_NOCL0_QCHDBG_NFO_QCH_CON_LH_AXI_MI_P_TPU_CD_QCHDBG_NFO_QCH_CON_PPC_AUR_D1_EVENT_QCHDBG_NFO_QCH_CON_D_TZPC_NOCL1B_QCHDBG_NFO_QCH_CON_LH_ACEL_MI_D_HSI0_QCHDBG_NFO_QCH_CON_LH_AST_MI_G_NOCL1B_CD_QCHDBG_NFO_QCH_CON_SLH_AXI_SI_P_ISPFE_QCHQCH_CON_LH_AXI_MI_D0_G2D_QCHDBG_NFO_QCH_CON_LH_ACEL_MI_D2_G2D_QCHDBG_NFO_QCH_CON_LH_AST_MI_G_NOCL2AB_CD_QCHPLL_CON3_PLL_USBQCH_CON_DP_LINK_QCH_GTC_CLKDBG_NFO_QCH_CON_DP_LINK_QCH_PCLKCLK_CON_MUX_MUX_CLK_HSI1_NOCQCH_CON_PPMU_HSI1_QCHDBG_NFO_QCH_CON_LH_AXI_SI_LP_AOC_HSI1_CU_QCHDBG_NFO_QCH_CON_PCIE_GEN3_0_QCH_PCS_APBblkpwr_tnrEXT_REGULATOR_TPU_DURATIONWAKEUP2_INT_ENCLK_CON_DIV_DIV_CLK_PERIC1_USI0_USICLK_CON_DIV_DIV_CLK_PERIC1_USI13_USIQCH_CON_APBIF_INTCOMB_VGPIO2APM_QCHQCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CD_QCHDBG_NFO_QCH_CON_MAILBOX_APM_AOC_QCHQCH_CON_GIC_QCHQCH_CON_OTP_CON_BIRA_QCHQCH_CON_SSMT_PDMA1_QCHDBG_NFO_QCH_CON_GIC_QCHDBG_NFO_QCH_CON_LH_AXI_SI_P_MISC_GIC_CU_QCHDMYQCH_CON_PCIE_GEN3A_1_QCH_REFQCH_CON_LH_AXI_MI_LP_CPUCL0_HSI2_CU_QCHQCH_CON_SYSREG_HSI2_QCHDMYQCH_CON_I3C6_QCH_SCLKDBG_NFO_QCH_CON_GPC_PERIC0_QCHDBG_NFO_QCH_CON_I3C6_QCH_PCLKQCH_CON_LH_AXI_SI_P_PERIC1_CU_QCHGRP2_INTR_BID_CLEARMUX_CLKCMU_NOCL2AA_NOCMUX_CLKCMU_GDC_GDC0MUX_CLKCMU_TPU_TPUMUX_CLKCMU_RGBP_MCFPMUX_CLKCMU_HSI0_PERIMUX_CLKCMU_G3D_SWITCH_USERMUX_CLKCMU_HSI2_MMC_CARD_USERMUX_CLKCMU_PERIC1_USI15_USI_USERDIV_CLK_APM_NOCCLKCMU_PERIC1_IPCLKCMU_TNR_ALIGNDIV_CLK_CPUCL0_DBG_NOC_LHDIV_CLK_ISPFE_DCPHYDIV_CLK_PERIC0_NOCP_LHCLK_BLK_AOC_UID_PPMU_PCIE_IPCLKPORT_PCLKGOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLKGOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLKCLK_BLK_AUR_UID_UASC_P0_AUR_IPCLKPORT_PCLKGATE_CLKCMU_DPUF0_NOCGATE_CLKCMU_TPU_NOCGATE_CLKCMU_GDC_GDC0GATE_CLKCMU_AUR_AURCTLCLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_NOC_LH_IPCLKPORT_CLKCLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLKGOUT_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLKCLK_BLK_DPUF1_UID_SYSMMU_S0_PMMU1_DPUF1_IPCLKPORT_CLKGOUT_BLK_EH_UID_LH_ACEL_SI_LD_EH_CPUCL0_IPCLKPORT_I_CLKGOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_ACLKCLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLKCLK_BLK_G3D_UID_RSTNSYNC_CLK_G3DCORE_TOP_IPCLKPORT_CLKCLK_BLK_G3D_UID_SSMT_G3D1_IPCLKPORT_ACLKGOUT_BLK_GDC_UID_SSMT_D_LME_IPCLKPORT_PCLKGOUT_BLK_GDC_UID_QE_D2_GDC0_IPCLKPORT_ACLKCLK_BLK_GDC_UID_XIU_D1_GDC_IPCLKPORT_ACLKCLK_BLK_GDC_UID_SSMT_D4_GDC1_IPCLKPORT_PCLKCLK_BLK_GDC_UID_RSTNSYNC_SR_CLK_GDC_LME_IPCLKPORT_CLKCLK_BLK_GSACORE_UID_LH_AXI_SI_ID_SC_GSACORE_IPCLKPORT_I_CLKCLK_BLK_GSACTRL_UID_LH_AXI_MI_ID_GME_GSA_IPCLKPORT_I_CLKCLK_BLK_GSACTRL_UID_LH_AXI_SI_D_GSA_IPCLKPORT_I_CLKGOUT_BLK_HSI2_UID_PCIE_GEN3A_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_G3X1_INST_0_I_DRIVER_APB_CLKCLK_BLK_ISPFE_UID_LH_AXI_MI_IP_ISPFE_IPCLKPORT_I_CLKCLK_BLK_ISPFE_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS1GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLKGOUT_BLK_MCSC_UID_QE_D6_MCSC_IPCLKPORT_PCLKCLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_ACLKCLK_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_ACLKGOUT_BLK_MFC_UID_LH_AXI_SI_D1_MFC_IPCLKPORT_I_CLKGOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLKGOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLKCLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLKCLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLKCLK_BLK_NOCL0_UID_PPC_NOCL0_IO1_EVENT_IPCLKPORT_ACLKGOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLKCLK_BLK_NOCL1A_UID_PPC_G3DMMU_D_EVENT_IPCLKPORT_PCLKCLK_BLK_NOCL1A_UID_PPC_BW_D_CYCLE_IPCLKPORT_ACLKGOUT_BLK_NOCL2AA_UID_LH_AXI_SI_P_HSI2_CD_IPCLKPORT_I_CLKCLK_BLK_NOCL2AA_UID_SLH_AXI_SI_P_DPUB_IPCLKPORT_I_CLKCLK_BLK_NOCL2AA_UID_LH_TAXI_SI_D0_NOCL2AA_NOCL1A_IPCLKPORT_I_CLKCLK_BLK_NOCL2AB_UID_LH_AXI_MI_D4_TNR_IPCLKPORT_I_CLKGOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLKCLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_SCLKCLK_BLK_RGBP_UID_SYSMMU_S1_PMMU1_RGBP_IPCLKPORT_CLKCLK_BLK_RGBP_UID_RSTNSYNC_CLK_RGBP_MCFP_IPCLKPORT_CLKGOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLKCLK_BLK_TNR_UID_RSTNSYNC_SR_CLK_TNR_MERGE_IPCLKPORT_CLKCLK_BLK_TNR_UID_SYSMMU_S0_PMMU1_TNR_IPCLKPORT_CLKCLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_PCLKCLK_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_PCLKCLK_BLK_TNR_UID_RSTNSYNC_CLK_TNR_ALIGN_IPCLKPORT_CLKCLK_BLK_TPU_UID_TPU_IPCLKPORT_AXI_CLKGOUT_BLK_TPU_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLKCLK_BLK_TPU_UID_XIU_D_TPU_IPCLKPORT_ACLKGOUT_BLK_YUVP_UID_SSMT_D0_YUVP_IPCLKPORT_PCLKI_CLK_AOC_NOCOSCCLK_DPUF1OSCCLK_HSI1PLL_SHARED0_D4CLK_MIF_NOCD_S2DSLH_AXI_SI_LP_AOC_HSI1_QCHSYSMMU_S0_PMMU_AOC_QCH_S0GPC_APM_QCHSSMT_D_ALIVE_QCHAUR_QCHLH_ATB_MI_LT1_TPU_CPUCL0_QCHLH_ATB_SI_IT1_BOOKER_QCHLH_AXI_SI_LP_ALIVE_CPUCL0_CU_QCHS2MPU_S0_PMMU0_CPUCL0_QCHADD2_APBIF_CPUCL2_QCHSSMT_D0_DPUF1_QCHSYSMMU_S0_DPUF1_QCH_S0QE_EH_QCHLH_AXI_SI_P_G3D_CU_QCHD_TZPC_GDC_QCHSLH_AXI_MI_P_GDC_QCHDP_LINK_QCH_GTC_CLKLH_ACEL_SI_D_HSI0_QCHPCIE_GEN3_0_QCH_PCS_APBPCIE_GEN3B_1_QCH_PMA_APBGPC_MCSC_QCHD_TZPC_MFC_QCHSYSMMU_S0_MFC_QCHLH_AXI_SI_P_MISC_CU_QCHLH_AXI_SI_P_MISC_GIC_CU_QCHSPDMA0_QCHSYSMMU_S0_MISC_QCHLH_ACEL_MI_D2_CPUCL0_QCHLH_AST_MI_G_NOCL2AB_CU_QCHLH_AXI_MI_P_CPUCL0_CD_QCHLH_AXI_SI_P_MISC_GIC_CD_QCHPPC_NOCL0_IO0_CYCLE_QCHLH_ACEL_MI_D1_AUR_QCHLH_AST_SI_G_NOCL1A_CD_QCHPPC_BW_D_EVENT_QCHLH_TAXI_MI_P_NOCL0_NOCL2AA_QCHLH_AST_SI_G_NOCL2AB_QCHLH_AXI_MI_D4_TNR_QCHLH_TAXI_SI_D0_NOCL2AB_NOCL1A_QCHD_TZPC_PERIC0_QCHSYSMMU_S1_PMMU0_RGBP_QCH_S0SYSREG_RGBP_QCHADD_APBIF_TPU_QCHCTRL_OPTION_CMU_CPUCL0VCLK_BLK_CPUCL0VCLK_BLK_NOCL2ABVCLK_IP_UASC_AOCVCLK_IP_APM_USI1_UART_INTVCLK_IP_D_TZPC_APM_CUSTOMVCLK_IP_APM_DMAVCLK_IP_LH_ACEL_SI_D2_CPUCL0VCLK_IP_APB_ASYNC_P_SYSMMUVCLK_IP_LH_ATB_SI_IT1_BOOKERVCLK_IP_SYSREG_DPUBVCLK_IP_BLK_DPUB_FRC_OTP_DESERIALVCLK_IP_XIU_D_DPUF1VCLK_IP_LH_ACEL_SI_LD_EH_CPUCL0VCLK_IP_JPEGVCLK_IP_ADD_APBIF_G3DVCLK_IP_CA32_GSACOREVCLK_IP_QE_SC_GSACOREVCLK_IP_SYSMMU_S0_GSA_ZMVCLK_IP_GPC_GSEVCLK_IP_XIU_D1_HSI1VCLK_IP_XIU_P_HSI2VCLK_IP_UFS_EMBDVCLK_IP_UASC_PCIE_GEN3B_DBI_1VCLK_IP_AS_APB_PCIEPHY_0_HSI2VCLK_IP_QE_D3_ISPFEVCLK_IP_GPC_MCSCVCLK_IP_BLK_MIF_FRC_OTP_DESERIALVCLK_IP_QE_RTICVCLK_IP_LH_AXI_MI_P_MISC_GIC_CUVCLK_IP_PPC_NOCL1A_M1_EVENTVCLK_IP_MPACE_ASB_D0_MIFVCLK_IP_PPC_CPUCL0_D1_EVENTVCLK_IP_LH_ACEL_SI_D1_NOCL0_CPUCL0VCLK_IP_BLK_NOCL0_FRC_OTP_DESERIALVCLK_IP_LD_SLC1_FRC_OTP_DESERIALVCLK_IP_PPC_TPU_D0_CYCLEVCLK_IP_SLH_AXI_SI_P_TPUVCLK_IP_LH_AXI_MI_D_ALIVEVCLK_IP_LH_AXI_MI_D1_DPUF0VCLK_IP_LH_AXI_MI_D4_TNRVCLK_IP_LH_AXI_SI_P_PERIC1_CUVCLK_IP_SSMT_D2_RGBPVCLK_IP_LH_AST_SI_L_OTF_TNR_MCSCVCLK_IP_QE_D5_TNRVCLK_IP_SSMT_D0_YUVP - CMU_TOP MUX info 6%s, tcxo_req: %d 3%s there is no sequence element for pd(%d) status. 3%s %s: there is no such PA in p2v_list (idx:%d) QCH_CON_LH_AXI_SI_IP_G3D_QCHQCH_CON_PPMU_G3D_D2_QCHDBG_NFO_QCH_CON_RSTNSYNC_CLK_G3D_DD_QCHDBG_NFO_QCH_CON_SLH_AXI_MI_P_G3D_QCHCLK_CON_DIV_DIV_CLK_DPUB_NOCPDBG_NFO_QCH_CON_DPUB_QCH_OSC_DSIM1QCH_CON_GPC_DPUF0_QCHDBG_NFO_QCH_CON_DPUF0_QCH_SRAMCDBG_NFO_QCH_CON_LH_AXI_MI_LD1_DPUF1_DPUF0_QCHQCH_CON_SSMT_D1_DPUF1_QCHDBG_NFO_QCH_CON_LH_AXI_SI_D0_G2D_QCHDBG_NFO_QCH_CON_SYSMMU_S0_PMMU0_G2D_QCHDBG_NFO_QCH_CON_SYSMMU_S0_PMMU1_G2D_QCHQCH_CON_PPMU_D2_GDC0_QCHDBG_NFO_QCH_CON_LH_AST_SI_ID_GDC1_GDC0_QCHDBG_NFO_QCH_CON_QE_D4_GDC0_QCHQCH_CON_GSE_QCH_GSEQCH_CON_QE_D1_GSE_QCHDBG_NFO_QCH_CON_PPMU_D2_GSE_QCHDBG_NFO_QCH_CON_QE_D6_MCSC_QCHMFC_STATUSDBG_NFO_QCH_CON_LH_AXI_SI_D0_MFC_QCHDBG_NFO_QCH_CON_SYSREG_MFC_QCHQCH_CON_LH_AXI_SI_D5_RGBP_QCHQCH_CON_QE_D0_RGBP_QCHQCH_CON_QE_D5_RGBP_QCHDBG_NFO_QCH_CON_QE_D7_MCFP_QCHQCH_CON_SSMT_D6_TNR_QCHDBG_NFO_QCH_CON_GTNR_MERGE_QCH_01DBG_NFO_QCH_CON_SSMT_D9_TNR_QCHQCH_CON_LH_AST_MI_L_OTF_RGBP_YUVP_QCHQCH_CON_LH_AST_SI_L_OTF_YUVP_MCSC_QCHQCH_CON_SYSMMU_S0_YUVP_QCH_S0PLL_CON1_PLL_AURDBG_NFO_QCH_CON_UASC_P1_AUR_QCHEH_CONFIGURATIONQCH_CON_LH_AXI_SI_IP_EH_QCHDBG_NFO_QCH_CON_LH_AXI_SI_P_EH_CU_QCHDBG_NFO_QCH_CON_PPMU_D1_TPU_QCHDBG_NFO_QCH_CON_SSMT_D1_TPU_QCHDBG_NFO_QCH_CON_SYSMMU_S0_TPU_QCHTPU_CLKDIVSTEP_CON_HEAVYPLL_CON0_MUX_CLKCMU_NOCL0_NOC_USERQCH_CON_LH_ACEL_MI_D2_CPUCL0_QCHQCH_CON_LH_ATB_SI_T_SLC_CD_QCHDBG_NFO_QCH_CON_LH_TAXI_MI_D_NOCL1B_NOCL0_QCHDBG_NFO_QCH_CON_PPC_CPUCL0_D1_EVENT_QCHDBG_NFO_QCH_CON_SLH_AXI_SI_P_MIF2_QCHPLL_CON0_MUX_CLKCMU_NOCL1A_NOC_USERQCH_CON_LH_ACEL_MI_D2_G3D_QCHQCH_CON_PPC_NOCL2AB_S0_EVENT_QCHQCH_CON_SLH_AXI_SI_P_TPU_QCHDBG_NFO_QCH_CON_PPC_G3D_D0_CYCLE_QCHDBG_NFO_QCH_CON_PPMU_NOCL1A_M3_QCHDBG_NFO_QCH_CON_LH_AXI_MI_D_AOC_QCHDBG_NFO_QCH_CON_LH_TAXI_SI_D0_NOCL2AA_NOCL1A_QCHNOCL2AB_STATUSQCH_CON_LH_AXI_MI_D1_MCSC_QCHQCH_CON_SLH_AXI_SI_P_G2D_QCHPLL_CON8_PLL_USBPLL_CON0_MUX_CLKCMU_HSI0_TCXO_USERQCH_CON_LH_AXI_SI_LG_ETR_HSI0_CU_QCHDBG_NFO_QCH_CON_USI3_HSI0_QCHDBG_NFO_QCH_CON_USI4_HSI0_QCHQCH_CON_PCIE_GEN3_0_QCH_APBQCH_CON_SYSREG_HSI1_QCHCPUCL1_CLKDIVSTEP_OCP_FLTGRP1_INTR_BID_CLEARCLK_CON_DIV_DIV_CLK_APM_I3C_PMICQCH_CON_APBIF_GPIO_CUSTOM_ALIVE_QCHQCH_CON_MAILBOX_APM_TPU_QCHQCH_CON_MAILBOX_AP_AURCORE1_QCHQCH_CON_PMU_QCHQCH_CON_ROM_CRC32_HOST_QCHDBG_NFO_QCH_CON_APBIF_GPIO_CUSTOM_ALIVE_QCHDBG_NFO_QCH_CON_MAILBOX_AP_AURMCUNS4_QCHDMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4QCH_CON_QE_DIT_QCHQCH_CON_SLH_AXI_MI_P_MISC_QCHQCH_CON_SPDMA0_QCHQCH_CON_SSMT_SPDMA1_QCHDBG_NFO_QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_QCHQCH_CON_LH_AXI_MI_LP_CPUCL0_HSI2_QCHQCH_CON_PPMU_HSI2_QCHQCH_CON_UASC_PCIE_GEN3B_DBI_1_QCHDBG_NFO_QCH_CON_SYSREG_HSI2_QCHDBG_NFO_DMYQCH_CON_I3C4_QCH_SCLKQCH_CON_USI10_USI_QCHDBG_NFO_QCH_CON_LH_AXI_SI_P_PERIC1_CU_QCHMUX_CLKCMU_CPUCL1_SWITCHMUX_CLKCMU_TPU_TPUCTLMUX_CLKCMU_RGBP_MCFP_USERDIV_CLK_APM_I3C_PMICDIV_CLK_AUR_NOCPCLKCMU_HSI2_MMC_CARDDIV_CLK_CLUSTER0_PPUCLKDIV_CLK_CLUSTER0_ACLK_NON_MAIN_LHDIV_CLK_GSACORE_NOCDCLK_HSI1_ALTDIV_CLK_CPUCL0_DSUCLK_BLK_AOC_UID_SLH_AXI_SI_LP_AOC_HSI1_IPCLKPORT_I_CLKCLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_DBGCORE_IPCLKPORT_CLKCLK_BLK_APM_UID_APM_DMA_IPCLKPORT_PCLKCLK_BLK_AUR_UID_RSTNSYNC_SR_CLK_AUR_AURCTL_LH_IPCLKPORT_CLKCLK_BLK_AUR_UID_XIU_D_AUR_IPCLKPORT_ACLKCLK_BLK_AUR_UID_BLK_AUR_FRC_OTP_DESERIAL_IPCLKPORT_I_CLKGATE_CLKCMU_RGBP_RGBPGATE_CLKCMU_HSI2_UFS_EMBDGATE_CLKCMU_CPUCL0_BCI_SWITCHGOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBGGOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_HSI0_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_LH_AXI_MI_P_CPUCL0_CU_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLKCLK_BLK_CPUCL0_UID_APB_ASYNC_P_CSSYS_1_IPCLKPORT_PCLKMCLK_BLK_CPUCL0_UID_CPUCL0_QOS_IPCLKPORT_ACLKCLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_NON_MAIN_IPCLKPORT_CLKCLK_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKMCLK_BLK_DPUB_UID_BLK_DPUB_FRC_OTP_DESERIAL_IPCLKPORT_I_CLKCLK_BLK_DPUF0_UID_DPUF0_CMU_DPUF0_IPCLKPORT_PCLKGOUT_BLK_EH_UID_SYSREG_EH_IPCLKPORT_PCLKGOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLKCLK_BLK_G2D_UID_RSTNSYNC_SR_CLK_G2D_NOCD_JPEG_IPCLKPORT_CLKCLK_BLK_G2D_UID_LH_AST_SI_ID_JPEG_G2D1_IPCLKPORT_I_CLKCLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUPCLK_BLK_G3D_UID_SYSMMU_S0_PMMU3_G3D_IPCLKPORT_CLKCLK_BLK_GDC_UID_PPMU_D2_GDC0_IPCLKPORT_PCLKCLK_BLK_GDC_UID_PPMU_D4_GDC0_IPCLKPORT_ACLKCLK_BLK_GDC_UID_SSMT_D2_GDC1_IPCLKPORT_ACLKCLK_BLK_GDC_UID_QE_D4_GDC1_IPCLKPORT_PCLKGOUT_BLK_GSACORE_UID_LH_AXI_SI_IP_GSA_IPCLKPORT_I_CLKGOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_I_CLKGOUT_BLK_GSACORE_UID_AD_APB_DMA_GSACORE_NS_IPCLKPORT_PCLKMCLK_BLK_GSACTRL_UID_GSACTRL_CMU_GSACTRL_IPCLKPORT_PCLKGOUT_BLK_GSACTRL_UID_PMU_GSA_IPCLKPORT_PCLKGOUT_BLK_GSE_UID_PPMU_D0_GSE_IPCLKPORT_ACLKGOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLKGOUT_BLK_HSI0_UID_SSMT_HSI0_IPCLKPORT_ACLKGOUT_BLK_HSI1_UID_PCIE_IA_GEN3A_0_IPCLKPORT_I_CLKCLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN3A_0_IPCLKPORT_ACLKGOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLKGOUT_BLK_HSI2_UID_PCIE_GEN3A_1_IPCLKPORT_PCIE_QUADRA_G3X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UGGOUT_BLK_HSI2_UID_QE_PCIE_GEN3B_HSI2_IPCLKPORT_PCLKGOUT_BLK_ISPFE_UID_SSMT_D1_ISPFE_IPCLKPORT_A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cmucal type %x MOUT%s %s: error on handling restore sequence. (pd_id : %d)3%s %s: error on PA2VA conversion. seq:enable, core_id:%d. aborting init... 3%s %s:timed out during wait. reg:%s (value:0x%x, seq_idx = %d) PLL_CON0_MUX_CLK_G3DCORE_TRACE_USERQCH_CON_LH_AXI_SI_P_G3D_CU_QCHMEMCLKDBG_NFO_QCH_CON_PPMU_D0_DPUF0_QCHDBG_NFO_QCH_CON_SYSREG_DPUF0_QCHQCH_CON_G2D_CMU_G2D_QCHQCH_CON_LH_AST_MI_ID_JPEG_G2D1_QCHDBG_NFO_QCH_CON_LH_AST_SI_ID_JPEG_G2D1_QCHDBG_NFO_QCH_CON_SLH_AXI_MI_P_G2D_QCHQCH_CON_D_TZPC_GDC_QCHDBG_NFO_QCH_CON_LH_AXI_SI_D0_GDC_QCHBUS_COMPONENT_DRCG_EN1DBG_NFO_QCH_CON_SLH_AXI_MI_P_GSE_QCHQCH_CON_SYSMMU_S1_RGBP_QCH_S0DBG_NFO_QCH_CON_RGBP_QCHQCH_CON_LH_AST_SI_L_OTF_TNR_MCSC_QCHDBG_NFO_QCH_CON_PPMU_D0_TNR_QCHQCH_CON_SSMT_D0_YUVP_QCHDBG_NFO_QCH_CON_SLH_AXI_MI_P_BW_QCHCLK_CON_DIV_DIV_CLK_ISPFE_NOCPDBG_NFO_QCH_CON_LH_AXI_MI_IP_ISPFE_QCHDBG_NFO_QCH_CON_LH_AXI_SI_D3_ISPFE_QCHDBG_NFO_QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6DBG_NFO_QCH_CON_SSMT_D2_ISPFE_QCHPLL_CON3_PLL_NOCL0QCH_CON_LH_TAXI_SI_P_NOCL0_NOCL2AA_QCHQCH_CON_PPC_CPUCL0_D3_EVENT_QCHQCH_CON_PPC_NOCL1B_M0_CYCLE_QCHDBG_NFO_QCH_CON_LH_AXI_SI_P_MISC_CD_QCHCLK_CON_DIV_DIV_CLK_NOCL1A_NOCD_LHDBG_NFO_QCH_CON_LH_ACEL_MI_D1_TPU_QCHDBG_NFO_QCH_CON_PPC_BW_D_CYCLE_QCHQCH_CON_LH_AXI_SI_P_GSA_CD_QCHQCH_CON_LH_AXI_MI_D5_RGBP_QCHDBG_NFO_QCH_CON_PPMU_NOCL2AA_M0_QCHDBG_NFO_QCH_CON_PPMU_NOCL2AA_M1_QCHDBG_NFO_QCH_CON_SYSREG_NOCL2AA_QCHCLK_CON_DIV_DIV_CLK_NOCL2AB_NOCD_LHQCH_CON_LH_TAXI_SI_D0_NOCL2AB_NOCL1A_QCHDBG_NFO_QCH_CON_LH_AST_SI_G_NOCL2AB_QCHDBG_NFO_QCH_CON_LH_AXI_MI_D1_MCSC_QCHDBG_NFO_QCH_CON_LH_AXI_MI_D2_TNR_QCHQCH_CON_LH_AXI_MI_LP_AOC_HSI0_CU_QCHQCH_CON_USI1_HSI0_QCHDBG_NFO_QCH_CON_GPC_HSI0_QCHDBG_NFO_QCH_CON_USB32DRD_QCH_USBDPPHY_CTRLDBG_NFO_QCH_CON_GPIO_HSI1_QCHblkpwr_gdcCMU_HCHGEN_CLKMUXEXT_REGULATOR_CPUCL1_DURATIONCLK_CON_MUX_MUX_CLKCMU_APM_FUNCQCH_CON_MAILBOX_APM_AUR_QCHQCH_CON_WDT_APM_QCHDBG_NFO_DMYQCH_CON_APM_I3C_PMIC_QCH_SDBG_NFO_QCH_CON_LH_AXI_SI_LP_ALIVE_CPUCL0_CD_QCHDBG_NFO_QCH_CON_MAILBOX_AOC_AURCORE2_QCHDBG_NFO_QCH_CON_MAILBOX_AP_AOCF1_QCHQCH_CON_QE_RTIC_QCHDBG_NFO_QCH_CON_LH_AXI_MI_P_MISC_CU_QCHQCH_CON_PCIE_GEN3A_1_QCH_PMA_APBQCH_CON_SSMT_PCIE_IA_GEN3A_1_QCHDBG_NFO_QCH_CON_PCIE_GEN3A_1_QCH_AXIDBG_NFO_QCH_CON_PCIE_GEN3A_1_QCH_PCS_APBDMYQCH_CON_I3C0_QCH_SCLKQCH_CON_PWM_QCHPLL_SHARED3_D1PLL_USBMUX_CLKCMU_HSI2_PCIEMUX_CLKCMU_NOCL1A_NOCMUX_CLK_G3DCORE_COREGROUP_USERMUX_CLKCMU_HSI2_PCIE_USERMUX_CLKCMU_NOCL1A_NOC_USERMUX_CLKCMU_PERIC1_I3C_USERMUX_CLK_TPU_TPU_LPMDIV_CLK_AOC_TRACE_LHCLKCMU_PERIC0_IPDIV_CLK_HSI1_NOCPGATE_CLKCMU_APM_FUNCGOUT_BLK_APM_UID_SYSMMU_S0_PMMU0_ALIVE_IPCLKPORT_CLKGOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLKCLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLKCLK_BLK_APM_UID_APBIF_GPIO_CUSTOM_ALIVE_IPCLKPORT_PCLKCLK_BLK_APM_UID_MAILBOX_AP_AURMCUNS4_IPCLKPORT_PCLKGATE_CLKCMU_HSI0_NOCCLK_BLK_CPUCL0_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_LH_AXI_SI_P_CPUCL0_CU_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_CU_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_LH_AXI_SI_LP_CPUCL0_HSI1_CD_IPCLKPORT_I_CLKGATE_CLK_CLUSTER0_COMPLEX1CLKCLK_BLK_CPUCL0_UID_LH_AXI_SI_IG_BOOKER_IPCLKPORT_I_CLKCLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_CPU_IPCLKPORT_CLKCLK_BLK_DPUF0_UID_SSMT_D0_DPUF0_IPCLKPORT_ACLKGOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCD_IPCLKPORT_CLKCLK_BLK_DPUF1_UID_RSTNSYNC_SR_CLK_DPUF1_NOCD_IPCLKPORT_CLKCLK_BLK_G3D_UID_LH_ACEL_SI_D1_G3D_IPCLKPORT_I_CLKCLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_G3DCORE_NOCD_IPCLKPORT_CLKGOUT_BLK_GDC_UID_PPMU_D0_GDC1_IPCLKPORT_ACLKGOUT_BLK_GDC_UID_QE_D0_GDC0_IPCLKPORT_PCLKCLK_BLK_GDC_UID_LH_AST_MI_ID_LME_GDC1_IPCLKPORT_I_CLKGOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCP_IPCLKPORT_CLKCLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLKCLK_BLK_GSACORE_UID_PPMU_GSACORE1_IPCLKPORT_ACLKCLK_BLK_GSACORE_UID_RSTNSYNC_SR_CLK_GSACORE_SPI_FPS_IPCLKPORT_CLKGOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TZ_IPCLKPORT_PCLKCLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USB32DRD_U3REWA_ALV_CLKGOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLKGOUT_BLK_HSI2_UID_UASC_PCIE_GEN3A_DBI_1_IPCLKPORT_ACLKGOUT_BLK_HSI2_UID_UASC_PCIE_GEN3B_SLV_1_IPCLKPORT_PCLKCLK_BLK_HSI2_UID_PCIE_GEN3B_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_G3X1_INST_0_I_DRIVER_APB_CLKGOUT_BLK_ISPFE_UID_LH_AXI_SI_D2_ISPFE_IPCLKPORT_I_CLKCLK_BLK_ISPFE_UID_XIU_D1_ISPFE_IPCLKPORT_ACLKCLK_BLK_ISPFE_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS9CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_CLKGOUT_BLK_MISC_UID_LH_AXI_SI_ID_SC_IPCLKPORT_I_CLKGOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_PCLKGOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_PCLKCLK_BLK_NOCL0_UID_LH_AXI_SI_P_CPUCL0_CD_IPCLKPORT_I_CLKGOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_ACLK_P_NOCL1ACLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_PCLKCLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_BW_IPCLKPORT_I_CLKCLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLKGOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLKCLK_BLK_NOCL2AA_UID_SLH_AXI_SI_P_DPUF0_IPCLKPORT_I_CLKCLK_BLK_NOCL2AB_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLKGOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLKGOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLKCLK_BLK_RGBP_UID_PPMU_D0_RGBP_IPCLKPORT_PCLKCLK_BLK_RGBP_UID_QE_D11_MCFP_IPCLKPORT_ACLKCLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLKGOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_ACLKCLK_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_ACLKCLK_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_PCLKCLK_BLK_TNR_UID_XIU_D6_TNR_IPCLKPORT_ACLKCLK_BLK_TNR_UID_BLK_TNR_FRC_OTP_DESERIAL_IPCLKPORT_I_CLKOSCCLK_DPUF0OSCCLK_MIFOSCCLK_RGBPOSCCLK_S2DLH_AXI_SI_LP_AOC_HSI0_CD_QCHAPM_CMU_APM_QCHLH_AXI_SI_LG_SCAN2DRAM_CD_QCHSLH_AXI_MI_P_ALIVE_QCHCLUSTER0_QCH_PPUD_TZPC_CPUCL0_QCHLH_ACEL_SI_D1_CPUCL0_QCHLH_ATB_SI_LT_GSA_CPUCL0_CU_QCHDPUB_QCH_OSC_DSIM1PPMU_D1_DPUF1_QCHSYSMMU_S0_EH_QCHLH_AST_SI_ID_JPEG_G2D1_QCHPPMU_D0_G2D_QCHPPMU_G3D_D2_QCHSLH_AXI_MI_P_G3D_QCHLH_AXI_MI_I_DAP_GSA_QCHLH_AXI_SI_IP_AXI2APB1_GSACORE_QCHLH_AXI_SI_IP_AXI2APB0_GSACTRL_QCHMAILBOX_GSA2AUR_QCHMAILBOX_GSA2NONTZ_QCHMAILBOX_GSA2TPU_QCHUSB32DRD_QCH_EUSBCTLUSI1_HSI0_QCHSYSREG_HSI1_QCHMMC_CARD_QCHUASC_PCIE_GEN3A_DBI_1_QCHQE_D0_ISPFE_QCHSYSMMU_S2_PMMU0_ISPFE_QCH_S0QE_D1_MCSC_QCHSLH_AXI_MI_P_MISC_GIC_QCHSSMT_PDMA0_QCHLH_TAXI_SI_P_NOCL0_NOCL1A_QCHPPC_AUR_D0_EVENT_QCHPPC_NOCL2AB_S0_EVENT_QCHLH_AST_MI_G_NOCL1B_CD_QCHSLH_AXI_SI_P_AOC_QCHLH_AXI_MI_D3_RGBP_QCHLH_AXI_SI_P_HSI2_CD_QCHSLH_AXI_SI_P_DPUB_QCHLH_AXI_MI_D1_GDC_QCHI3C5_QCH_SCLKUSI0_UART_QCHQE_D0_RGBP_QCHLH_AST_SI_L_OTF_TNR_MCSC_QCHPPMU_D8_TNR_QCHLH_ACEL_SI_D1_TPU_QCHPPMU_D1_TPU_QCHVCLK_VDD_CPUCL2VCLK_MUX_CLKCMU_CIS_CLK5VCLK_DIV_CLK_CPUCL0_CMUREFVCLK_DIV_CLK_HSI0_USI4VCLK_BLK_MISCVCLK_BLK_NOCL1AVCLK_IP_LH_AXI_MI_LP_AOC_ALIVE_CDVCLK_IP_APBIF_PMU_ALIVEVCLK_IP_MAILBOX_APM_AOCVCLK_IP_MAILBOX_AP_AURMCUTZVCLK_IP_AURVCLK_IP_D_TZPC_AURVCLK_IP_S2MPU_S0_CPUCL0VCLK_IP_SLH_AXI_MI_LP_ALIVE_CPUCL0VCLK_IP_PPC_INSTRRUN_CLUSTER0_1VCLK_IP_LH_ACEL_SI_D1_CPUCL0VCLK_IP_LH_AXI_MI_LD1_DPUF1_DPUF0VCLK_IP_AD_APB_DPUF1_DMAVCLK_IP_SYSMMU_S0_DPUF1VCLK_IP_BLK_EH_FRC_OTP_DESERIALVCLK_IP_SSMT_D0_G2DVCLK_IP_LH_AXI_MI_P_G3D_CUVCLK_IP_SSMT_G3D3VCLK_IP_XIU_D0_GDCVCLK_IP_SYSREG_GSACOREVCLK_IP_UGMEVCLK_IP_LH_AXI_SI_P_GSA_CUVCLK_IP_LH_AXI_SI_LD_HSI0_AOCVCLK_IP_SYSMMU_S0_HSI0VCLK_IP_PPMU_HSI1VCLK_IP_LH_AXI_SI_LP_AOC_HSI1_CUVCLK_IP_LH_ACEL_SI_D_HSI2VCLK_IP_D_TZPC_ISPFEVCLK_IP_SYSMMU_S0_MCSCVCLK_IP_MCTVCLK_IP_SSMT_PDMA0VCLK_IP_LH_ATB_MI_T_BDU_CDVCLK_IP_PPC_AOC_CYCLEVCLK_IP_LH_TAXI_SI_D0_NOCL2AA_NOCL1AVCLK_IP_LH_AXI_MI_D_YUVPVCLK_IP_SLH_AXI_SI_P_GSEVCLK_IP_SYSMMU_S0_PMMU0_TNRVCLK_IP_SYSREG_TNRVCLK_IP_SYSMMU_S1_PMMU2_TNRVCLK_IP_XIU_D10_TNRVCLK_IP_LH_ATB_MI_LT1_TPU_CPUCL0_CDVCLK_IP_YUVP_CMU_YUVP3 Invalid addr :0x%x vclk_id - %s[%x] is off. - dvfs list pmucal_system_earlywakeup3%s %s: error on PA2VA conversion. seq:status, cluster_id:%d. aborting init... QCH_CON_LH_ATB_SI_LT_G3D_CPUCL0_QCHPLL_CON0_MUX_CLKCMU_DPUB_DSIM_USERDPUF0_CMU_DPUF0_CONTROLLER_OPTIONQCH_CON_LH_AST_SI_ID_JPEG_G2D1_QCHDBG_NFO_QCH_CON_G2D_QCHQCH_CON_LH_AXI_SI_D0_GDC_QCHDBG_NFO_QCH_CON_PPMU_D4_GDC1_QCHDBG_NFO_QCH_CON_QE_D0_GDC0_QCHDBG_NFO_QCH_CON_SYSMMU_S0_PMMU0_GDC_QCH_S0QCH_CON_PPMU_D1_GSE_QCHQCH_CON_SLH_AXI_MI_P_GSE_QCHQCH_CON_SSMT_D2_GSE_QCHDBG_NFO_QCH_CON_LH_AST_MI_L_OTF_YUVP_GSE_QCHQCH_CON_PPMU_D3_MCFP_QCHQCH_CON_QE_D6_MCFP_QCHDBG_NFO_QCH_CON_GPC_RGBP_QCHDBG_NFO_QCH_CON_LH_AST_SI_I_RGBP_MCFP_QCHDBG_NFO_QCH_CON_LH_AST_SI_L_OTF_RGBP_YUVP_QCHDBG_NFO_QCH_CON_PPMU_D1_RGBP_QCHDBG_NFO_QCH_CON_QE_D4_TNR_QCHDBG_NFO_QCH_CON_QE_D7_TNR_QCHDBG_NFO_QCH_CON_YUVP_CMU_YUVP_QCHPLL_CON5_PLL_AURQCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CD_QCHQCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_QCHDBG_NFO_QCH_CON_PPC_EH_CYCLE_QCHDBG_NFO_QCH_CON_QE_D3_ISPFE_QCHPLL_CON7_PLL_TPUCLK_CON_DIV_DIV_CLK_TPU_NOCPQCH_CON_ADD_APBIF_TPU_QCHCLK_CON_MUX_MUX_CLK_NOCL0_NOC_OPTION1QCH_CON_SLH_AXI_SI_P_MISC_GIC_QCHQCH_CON_PPMU_NOCL0_DP_QCHDBG_NFO_DMYQCH_CON_SLC_CH1_QCHDBG_NFO_QCH_CON_LH_ACEL_MI_D0_CPUCL0_QCHDBG_NFO_QCH_CON_LH_AST_SI_G_NOCL1B_CU_QCHDBG_NFO_QCH_CON_SFR_APBIF_CMU_TOPC_QCHDBG_NFO_QCH_CON_PPC_G3D_D2_EVENT_QCHQCH_CON_LH_AXI_MI_D_AOC_QCHQCH_CON_PPC_AOC_CYCLE_QCHQCH_CON_SLH_AXI_SI_P_HSI1_QCHDBG_NFO_QCH_CON_PPMU_NOCL1B_M0_QCHDBG_NFO_QCH_CON_SLH_AXI_SI_P_AOC_QCHDBG_NFO_QCH_CON_SLH_AXI_SI_P_GSA_QCHQCH_CON_LH_AXI_MI_D4_RGBP_QCHQCH_CON_LH_AXI_MI_D6_RGBP_QCHQCH_CON_LH_AXI_MI_P_HSI2_CD_QCHDBG_NFO_QCH_CON_LH_ACEL_MI_D_HSI2_QCHDBG_NFO_QCH_CON_LH_AXI_SI_P_HSI2_CD_QCHQCH_CON_SLH_AXI_SI_P_GSE_QCHCLK_CON_DIV_DIV_CLK_HSI0_NOC_LHCLK_CON_DIV_DIV_CLK_HSI0_USI1PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USERDBG_NFO_QCH_CON_I3C3_HSI0_QCH_PCLKDBG_NFO_QCH_CON_SYSREG_HSI0_QCHPLL_CON0_MUX_CLKCMU_HSI1_PCIE_USERblkpwr_ehCLK_CON_DIV_DIV_CLK_PERIC0_USI0_UARTCLK_CON_DIV_DIV_CLK_PERIC1_USI15_USICLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRCQCH_CON_GPC_APM_CUSTOM_QCHQCH_CON_SYSMMU_S0_PMMU0_ALIVE_QCHDBG_NFO_QCH_CON_APM_USI0_UART_QCHDBG_NFO_QCH_CON_MAILBOX_AP_AURMCUNS3_QCHDBG_NFO_QCH_CON_SLH_AXI_SI_LP_ALIVE_CPUCL0_QCHQCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_QCHQCH_CON_QE_PDMA0_QCHQCH_CON_SYSMMU_S0_MISC_QCHDBG_NFO_DMYQCH_CON_PUF_QCHDBG_NFO_QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_QCHDBG_NFO_QCH_CON_LH_AXI_MI_ID_SC_QCHDBG_NFO_QCH_CON_QE_PDMA1_QCHDBG_NFO_QCH_CON_PCIE_GEN3B_1_QCH_AXIQCH_CON_USI0_UART_QCHAPM_CMU_APM_CONTROLLER_OPTIONPLL_SPARE_D1PLL_MIF_S2DMUX_CLKCMU_PERIC1_NOCMUX_CLKCMU_TOP_CMUREFCLKCMU_DPUB_NOCCLKCMU_HSI0_DPOSCDIV_CLK_CLUSTER0_ACLK_DBGDIV_CLK_CPUCL1_CMUREFDIV_CLK_HSI0_USI4DIV_CLK_SLC2_DCLKCLK_BLK_APM_UID_SLH_AXI_SI_LP_ALIVE_CPUCL0_IPCLKPORT_I_CLKCLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_PCLKGOUT_BLK_BW_UID_RSTNSYNC_CLK_BW_NOCD_IPCLKPORT_CLKGATE_CLKCMU_HSI2_NOCGATE_CLKCMU_HSI1_PCIEGATE_CLKCMU_CPUCL0_CPU_SWITCHCLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_LH_ATB_SI_T_BDU_CU_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_LH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_LH_ACEL_SI_D0_CPUCL0_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_ACLKCLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_OSCCLK_IPCLKPORT_CLKGOUT_BLK_DPUF0_UID_GPC_DPUF0_IPCLKPORT_PCLKCLK_BLK_EH_UID_LH_AXI_MI_IP_EH_IPCLKPORT_I_CLKGOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_ACLKGOUT_BLK_G2D_UID_LH_ACEL_SI_D2_G2D_IPCLKPORT_I_CLKGOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_PCLKGOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_ACLKCLK_BLK_G3D_UID_PPMU_G3D_D0_IPCLKPORT_ACLKCLK_BLK_G3D_UID_SYSMMU_S0_PMMU0_G3D_IPCLKPORT_CLKCLK_BLK_G3D_UID_PPMU_G3D_D2_IPCLKPORT_PCLKGOUT_BLK_GDC_UID_AD_APB_GDC1_IPCLKPORT_PCLKMGOUT_BLK_GDC_UID_GDC1_IPCLKPORT_CLKGOUT_BLK_GDC_UID_GPC_GDC_IPCLKPORT_PCLKCLK_BLK_GDC_UID_LH_AST_SI_ID_GDC0_GDC1_IPCLKPORT_I_CLKCLK_BLK_GDC_UID_SYSMMU_S0_PMMU1_GDC_IPCLKPORT_CLKCLK_BLK_GDC_UID_LH_AXI_SI_D0_GDC_IPCLKPORT_I_CLKCLK_BLK_GDC_UID_LH_AXI_SI_D2_GDC_IPCLKPORT_I_CLKGOUT_BLK_GSACORE_UID_SYSREG_GSACORE_IPCLKPORT_PCLKGOUT_BLK_GSACORE_UID_BAAW_GSACORE_IPCLKPORT_I_PCLKGOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_IPCLKGOUT_BLK_ISPFE_UID_PPMU_D0_ISPFE_IPCLKPORT_PCLKGOUT_BLK_ISPFE_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4GOUT_BLK_ISPFE_UID_SSMT_D1_ISPFE_IPCLKPORT_PCLKGOUT_BLK_ISPFE_UID_LH_AXI_SI_D1_ISPFE_IPCLKPORT_I_CLKCLK_BLK_ISPFE_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS9CLK_BLK_ISPFE_UID_PPMU_D3_ISPFE_IPCLKPORT_PCLKCLK_BLK_ISPFE_UID_XIU_D2_ISPFE_IPCLKPORT_ACLKCLK_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_ACLKCLK_BLK_MFC_UID_XIU_D_MFC_IPCLKPORT_ACLKGOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_ACLKGOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_ACLKGOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_PCLKCLK_BLK_MISC_UID_RSTNSYNC_SR_CLK_MISC_GIC_IPCLKPORT_CLKGOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_PCLKCLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_LH_AXI_MI_P_EH_CD_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_SLC1_ACLK_IPCLKPORT_CLKGOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLKGOUT_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_CD_IPCLKPORT_I_CLKCLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_ACLKCLK_BLK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time out, '%s' %d pmucal_rae_phy2virtPLL_CON6_PLL_G3DCLK_CON_DIV_CLK_G3D_ADD_CH_CLKCLK_CON_DIV_DIV_CLK_G3D_NOCP_LHPLL_CON0_MUX_CLKCMU_G3D_SWITCH_USERDBG_NFO_QCH_CON_LH_ATB_SI_LT_G3D_CPUCL0_QCHQCH_CON_D_TZPC_DPUB_QCHDBG_NFO_QCH_CON_DPUB_QCH_ALV_DSIM1QCH_CON_SYSMMU_S0_PMMU0_DPUF1_QCH_S0QCH_CON_SYSREG_DPUF1_QCHQCH_CON_LH_AST_SI_ID_G2D0_JPEG_QCHQCH_CON_SSMT_D2_G2D_QCHDBG_NFO_QCH_CON_LH_AXI_SI_D1_G2D_QCHQCH_CON_PPMU_D_LME_QCHQCH_CON_QE_D2_GDC1_QCHDBG_NFO_QCH_CON_SSMT_D0_GSE_QCHQCH_CON_SYSMMU_S0_MFC_QCHDBG_NFO_QCH_CON_GPC_MFC_QCHQCH_CON_LH_AXI_SI_D2_RGBP_QCHDBG_NFO_QCH_CON_LH_AXI_SI_D6_RGBP_QCHTNR_STATUSDBG_NFO_QCH_CON_D_TZPC_TNR_QCHDBG_NFO_QCH_CON_GPC_TNR_QCHAUR_CONFIGURATIONPLL_CON0_PLL_AURQCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CD_QCHDBG_NFO_QCH_CON_LH_AXI_SI_IP_BW_QCHDBG_NFO_QCH_CON_SSMT_BW_QCHDBG_NFO_QCH_CON_SYSMMU_S0_PMMU0_BW_QCHQCH_CON_SYSMMU_S0_PMMU0_EH_QCHQCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5CLK_CON_DIV_DIV_CLK_TPU_TPUCTLQCH_CON_LH_AXI_MI_P_TPU_CU_QCHQCH_CON_PPMU_D0_TPU_QCHQCH_CON_SYSMMU_S0_TPU_QCHDBG_NFO_QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CD_QCHTPU_CMU_TPU_CONTROLLER_OPTIONNOCL0_CONFIGURATIONQCH_CON_LH_AST_SI_G_NOCL2AA_CU_QCHQCH_CON_LH_AXI_MI_P_MIF2_CD_QCHQCH_CON_PPMU_NOCL0_IOC0_QCHQCH_CON_PPMU_NOCL0_S0_QCHDBG_NFO_QCH_CON_LH_ACEL_SI_D0_NOCL0_CPUCL0_QCHDBG_NFO_QCH_CON_LH_AST_MI_G_NOCL2AB_CU_QCHDBG_NFO_DMYQCH_CON_SLC_CH2_QCHDBG_NFO_QCH_CON_LH_AXI_MI_P_MISC_GIC_CD_QCHDBG_NFO_QCH_CON_LH_TAXI_MI_D2_NOCL1A_NOCL0_QCHDBG_NFO_QCH_CON_LH_AXI_SI_P_EH_CD_QCHCLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_LHQCH_CON_LH_ACEL_MI_D0_AUR_QCHQCH_CON_LH_TAXI_SI_D0_NOCL1A_NOCL0_QCHQCH_CON_PPC_NOCL2AA_S0_CYCLE_QCHDBG_NFO_QCH_CON_LH_AXI_MI_D_GSA_QCHQCH_CON_LH_AXI_MI_D1_MFC_QCHQCH_CON_LH_AXI_MI_D5_TNR_QCHDBG_NFO_QCH_CON_LH_AXI_MI_D1_GDC_QCHDBG_NFO_QCH_CON_TREX_P_NOCL2AB_QCHPLL_CON7_PLL_USBCLK_CON_MUX_MUX_CLK_HSI0_I3CDBG_NFO_QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CU_QCHQCH_CON_SYSMMU_S0_PMMU0_HSI1_QCH_S0QCH_CON_PCIE_GEN3_0_QCH_DBIHSI1_CMU_HSI1_CONTROLLER_OPTIONCPUCL0_HCHGEN_CLKMUX_BCICLK_CON_DIV_DIV_CLK_APM_USI0_UARTQCH_CON_MAILBOX_AP_AOCA32_QCHQCH_CON_RSTNSYNC_CLK_APM_GREBE_DBGCORE_QCHDBG_NFO_QCH_CON_MAILBOX_AP_AURCORE0_QCHQCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_QCHQCH_CON_SSMT_PDMA0_QCHDBG_NFO_QCH_CON_QE_PDMA0_QCHQCH_CON_MMC_CARD_QCHDBG_NFO_QCH_CON_LH_ACEL_SI_D_HSI2_QCHDMYQCH_CON_I3C4_QCH_SCLKDBG_NFO_DMYQCH_CON_I3C5_QCH_SCLKQCH_CON_GPIO_PERIC1_QCHQCH_CON_SYSREG_PERIC1_QCHDBG_NFO_QCH_CON_USI0_USI_QCHMUX_CLKCMU_MCSC_NOCMUX_CLKCMU_CIS_CLK1MUX_CLKCMU_BW_NOCMUX_CLKCMU_HSI0_USB32DRD_USERMUX_CLKCMU_TPU_NOC_USERCLKCMU_RGBP_RGBPCLKCMU_HSI2_UFS_EMBDCLKCMU_HSI0_PERIDIV_CLK_GSACTRL_NOCDDIV_CLK_TPU_TPUCTL_DBGDIV_CLK_CPUCL2_CPUDIV_CLK_G3D_L2_GLBGOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_IPCLKPORT_CLKGOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLKCLK_BLK_AUR_UID_D_TZPC_AUR_IPCLKPORT_PCLKCLK_BLK_AUR_UID_LH_ACEL_SI_D0_AUR_IPCLKPORT_I_CLKCLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_PCLKCLK_BLK_AUR_UID_RSTNSYNC_SR_CLK_AUR_NOCP_IPCLKPORT_CLKGATE_CLKCMU_MISC_NOCGATE_CLKCMU_CPUCL0_DBG_NOCGATE_CLKCMU_BW_NOCGATE_CLKCMU_CPUCL1_SWITCHGATE_CLKCMU_G3D_NOCDGATE_CLKCMU_AUR_AURCLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLKGATE_CLK_CLUSTER0_SCLKCLK_BLK_CPUCL0_UID_XIU_P0_CPUCL0_IPCLKPORT_ACLKCLK_BLK_DPUF0_UID_LH_AXI_MI_LD1_DPUF1_DPUF0_IPCLKPORT_I_CLKCLK_BLK_DPUF0_UID_SSMT_D1_DPUF0_IPCLKPORT_ACLKCLK_BLK_DPUF0_UID_SSMT_D1_DPUF0_IPCLKPORT_PCLKGOUT_BLK_G2D_UID_LH_AXI_SI_D1_G2D_IPCLKPORT_I_CLKGOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_DD_IPCLKPORT_CLKCLK_BLK_G3D_UID_LH_ACEL_SI_D0_G3D_IPCLKPORT_I_CLKGOUT_BLK_GDC_UID_PPMU_D_LME_IPCLKPORT_PCLKCLK_BLK_GDC_UID_PPMU_D4_GDC1_IPCLKPORT_ACLKGOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_IPCLKCLK_BLK_GSACORE_UID_UGME_IPCLKPORT_CLKGOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_I_PCLKGOUT_BLK_GSE_UID_RSTNSYNC_CLK_GSE_NOCP_IPCLKPORT_CLKGOUT_BLK_GSE_UID_PPMU_D1_GSE_IPCLKPORT_PCLKGOUT_BLK_GSE_UID_QE_D1_GSE_IPCLKPORT_ACLKGOUT_BLK_HSI1_UID_UASC_PCIE_GEN3A_SLV_0_IPCLKPORT_PCLKGOUT_BLK_HSI2_UID_QE_PCIE_GEN3A_HSI2_IPCLKPORT_PCLKGOUT_BLK_ISPFE_UID_SYSMMU_S0_PMMU0_ISPFE_IPCLKPORT_CLKCLK_BLK_ISPFE_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS10CLK_BLK_ISPFE_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS6CLK_BLK_ISPFE_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS8GOUT_BLK_MCSC_UID_LH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLKGOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_PCLKGOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCP_IPCLKPORT_CLKCLK_BLK_MISC_UID_LH_AXI_SI_P_MISC_CU_IPCLKPORT_I_CLKCLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_ACLKGOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_ACLKCLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MISC_GIC_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_CD_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_PPMU_NOCL0_IOC1_IPCLKPORT_PCLKGOUT_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_SLC_ACLK_IPCLKPORT_ACLKCLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLKCLK_BLK_NOCL1A_UID_LH_ACEL_MI_D0_TPU_IPCLKPORT_I_CLKCLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLKCLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_LH_IPCLKPORT_CLKCLK_BLK_NOCL2AB_UID_D_TZPC_NOCL2AB_IPCLKPORT_PCLKCLK_BLK_NOCL2AB_UID_LH_AXI_MI_D0_G2D_IPCLKPORT_I_CLKCLK_BLK_NOCL2AB_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLKCLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_PCLKCLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_PCLKCLK_BLK_RGBP_UID_PPMU_D4_MCFP_IPCLKPORT_PCLKCLK_BLK_RGBP_UID_RGBP_IPCLKPORT_CLK_VOTF0CLK_BLK_RGBP_UID_LH_AST_MI_I_RGBP_MCFP_IPCLKPORT_I_CLKGOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLKGOUT_BLK_S2D_UID_LH_AXI_MI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLKGOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_PCLKGOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_DBG_IPCLKPORT_CLKGOUT_BLK_YUVP_UID_D_TZPC_YUVP_IPCLKPORT_PCLKCLK_BLK_YUVP_UID_PPMU_D4_YUVP_IPCLKPORT_PCLKPLL_SHARED1_D3LH_AXI_SI_LP_AOC_HSI1_CD_QCHRSTNSYNC_CLK_APM_GREBE_QCHSSMT_BW_QCHLH_ATB_MI_T_BDU_QCHLH_ATB_SI_T_BDU_CU_QCHLH_ATB_SI_T_SLC_CU_QCHDPUB_QCH_OSC_DSIM0DPUB_QCH_ALV_DSIM0GPC_DPUB_QCHGPC_DPUF0_QCHSYSREG_DPUF0_QCHLH_ACEL_SI_D3_G3D_QCHPPCFW_G3D0_QCHPPMU_D0_GDC0_QCHPPMU_D0_GDC1_QCHHSI0_CMU_HSI0_QCHLH_AXI_SI_LG_ETR_HSI0_CU_QCHPCIE_GEN3_0_QCH_PMA_APBPCIE_GEN3_0_QCH_REFGPIO_HSI2_QCHSYSMMU_S0_HSI2_QCHSSMT_D6_MCSC_QCHSYSMMU_S0_PMMU1_MFC_QCHPUF_QCHPPC_NOCL0_IO0_EVENT_QCHPPC_NOCL0_IO1_EVENT_QCHSLC_CH1_QCHLH_ACEL_MI_D3_G3D_QCHSLH_AXI_SI_P_TPU_QCHLH_AXI_SI_P_HSI0_CD_QCHGPC_NOCL2AA_QCHLH_AXI_MI_D1_DPUF0_QCHSLH_AXI_SI_P_MFC_QCHLH_AXI_MI_D2_GDC_QCHLH_AXI_MI_D_YUVP_QCHQE_D5_RGBP_QCHSSMT_D2_MCFP_QCHQE_D8_TNR_QCHSSMT_D0_TNR_QCHSSMT_D10_TNRA_QCHSSMT_D7_TNR_QCHGPC_TPU_QCHSLH_AXI_MI_P_YUVP_QCHCTRL_OPTION_CMU_YUVPVCLK_CLK_AUR_ADD_CH_CLKVCLK_DIV_CLK_GSACORE_SPI_GSCVCLK_IP_AOC_CMU_AOCVCLK_IP_LH_ATB_SI_LT_AOC_CDVCLK_IP_SSMT_D_ALIVEVCLK_IP_MAILBOX_AOC_AURCORE2VCLK_IP_AS_APB_SYSMMU_S0_BW_S2VCLK_IP_LH_AST_MI_L_IRI_GIC_CLUSTER0_CUVCLK_IP_LH_ATB_SI_LT_AUR_CPUCL0_CUVCLK_IP_LH_AXI_SI_LP_CPUCL0_HSI1VCLK_IP_ADD0_APBIF_CPUCL0VCLK_IP_LH_ACEL_MI_LD_EH_CPUCL0VCLK_IP_CPUCL2_CMU_CPUCL2VCLK_IP_XIU_D_EHVCLK_IP_AD_APB_SYSMMU_G3DVCLK_IP_PPMU_D0_GDC0VCLK_IP_QE_D2_GDC1VCLK_IP_LH_AST_SI_ID_GDC0_GDC1VCLK_IP_AD_APB_DMA_GSACORE_NSVCLK_IP_LH_AXI_MI_ID_SC_GSACOREVCLK_IP_LH_AXI_MI_ID_GME_GSAVCLK_IP_XIU_D0_HSI0VCLK_IP_D_TZPC_HSI0VCLK_IP_LH_AXI_MI_P_HSI2_CUVCLK_IP_SYSREG_ISPFEVCLK_IP_QE_D2_ISPFEVCLK_IP_QCH_ADAPTER_SMCVCLK_IP_PDMA0VCLK_IP_PPMU_MISCVCLK_IP_XIU_D1_MISCVCLK_IP_PPC_NOCL1A_M0_EVENTVCLK_IP_PPC_CPUCL0_D2_EVENTVCLK_IP_MPACE_ASB_D2_MIFVCLK_IP_SLH_AXI_SI_P_MIF1VCLK_IP_LH_AXI_MI_P_MIF0_CDVCLK_IP_LH_AXI_MI_P_PERIC1_CDVCLK_IP_LH_TAXI_SI_P_NOCL0_NOCL2AAVCLK_IP_LH_AXI_MI_P_CPUCL0_NOCL0VCLK_IP_SLC_CH2VCLK_IP_LH_AXI_SI_P_AOC_CDVCLK_IP_LH_AXI_MI_D0_DPUF0VCLK_IP_SLH_AXI_SI_P_RGBPVCLK_IP_GPC_NOCL2ABVCLK_IP_XIU_D4_RGBPVCLK_IP_LH_AXI_SI_D3_TNRVCLK_IP_BLK_TPU_FRC_OTP_DESERIALVCLK_IP_SYSREG_YUVPCAM3acpm_dvfs_init fail ret = %d 3failed div_rate %s %u:%u:%u:%u 6%s:failed idx:%x reg:%x [%s] %s is off. nonepmucal_cpu_disable3%s there is no sequence element for core(%d) status. PLL_CON7_PLL_G3D_L2CLK_CON_MUX_MUX_CLK_G3D_L2_GLBDBG_NFO_QCH_CON_LH_AXI_MI_P_G3D_CU_QCHDBG_NFO_QCH_CON_SYSMMU_S0_G3D_QCH_S0DBG_NFO_QCH_CON_SYSREG_G3D_QCHQCH_CON_DPUB_CMU_DPUB_QCHDBG_NFO_QCH_CON_DPUB_CMU_DPUB_QCHDBG_NFO_QCH_CON_SSMT_D1_G2D_QCHQCH_CON_GDC0_QCH_C2CLKQCH_CON_SYSMMU_S0_PMMU0_GDC_QCH_S0DBG_NFO_QCH_CON_SSMT_D2_GDC1_QCHGSE_CONFIGURATIONQCH_CON_SSMT_D0_GSE_QCHQCH_CON_SYSMMU_S0_PMMU0_GSE_QCH_S0DBG_NFO_QCH_CON_GSE_QCH_GSE_VOTFDBG_NFO_QCH_CON_QE_D0_GSE_QCHDBG_NFO_QCH_CON_GPC_MCSC_QCHDBG_NFO_QCH_CON_SYSMMU_S0_PMMU1_MCSC_QCH_S0DBG_NFO_QCH_CON_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_QCHQCH_CON_LH_AST_SI_I_RGBP_MCFP_QCHQCH_CON_PPMU_D10_TNRA_QCH_S0QCH_CON_PPMU_D9_TNR_QCHQCH_CON_SSMT_D8_TNR_QCHDBG_NFO_QCH_CON_SYSMMU_S0_PMMU1_TNR_QCH_S0YUVP_CONFIGURATIONQCH_CON_LH_AXI_SI_P_AUR_CU_QCHQCH_CON_PPMU_D0_AUR_QCHDBG_NFO_DMYQCH_CON_AUR_QCHDBG_NFO_QCH_CON_PPMU_BW_QCHEH_CMU_EH_CONTROLLER_OPTIONQCH_CON_SYSREG_ISPFE_QCHPLL_CON0_MUX_CLKCMU_TPU_TPU_USERCLK_CON_DIV_DIV_CLK_SLC3_DCLKQCH_CON_LH_AXI_MI_P_ALIVE_CD_QCHQCH_CON_SLH_AXI_SI_P_PERIC1_QCHDBG_NFO_QCH_CON_PPC_CPUCL0_D3_EVENT_QCHDBG_NFO_QCH_CON_PPC_NOCL1B_M0_CYCLE_QCHNOCL0_SHORTSTOPQCH_CON_PPMU_NOCL1A_M0_QCHQCH_CON_TREX_D_NOCL1A_QCHDBG_NFO_QCH_CON_GPC_NOCL1A_QCHDBG_NFO_QCH_CON_LH_ACEL_MI_D3_G3D_QCHDBG_NFO_QCH_CON_PPC_NOCL2AA_S0_CYCLE_QCHDBG_NFO_QCH_CON_PPC_NOCL2AA_S0_EVENT_QCHDBG_NFO_QCH_CON_PPC_TPU_D1_EVENT_QCHCLK_CON_DIV_DIV_CLK_NOCL1B_NOCD_LHQCH_CON_SLH_AXI_SI_P_HSI0_QCHDBG_NFO_DMYQCH_CON_CMU_NOCL1B_CMUREF_QCHDBG_NFO_QCH_CON_LH_AXI_MI_P_HSI0_CD_QCHDBG_NFO_QCH_CON_SLH_AXI_SI_P_HSI2_QCHDBG_NFO_QCH_CON_SLH_AXI_SI_P_MFC_QCHQCH_CON_LH_AXI_MI_D1_TNR_QCHQCH_CON_LH_AXI_MI_D_YUVP_QCHQCH_CON_SLH_AXI_SI_P_MCSC_QCHDBG_NFO_QCH_CON_LH_AXI_MI_D4_TNR_QCHCLK_CON_DIV_DIV_CLK_HSI0_EUSBCLK_CON_MUX_MUX_CLK_HSI0_USI1QCH_CON_SLH_AXI_MI_LG_ETR_HSI0_QCHDBG_NFO_QCH_CON_UASC_HSI0_LINK_QCHQCH_CON_LH_AXI_MI_P_HSI1_CU_QCHblkpwr_aocblkpwr_nocl0GRP2_INTR_BID_ENABLEQCH_CON_LH_AXI_SI_LP_AOC_ALIVE_CU_QCHQCH_CON_MAILBOX_AP_AURMCUNS0_QCHQCH_CON_SLH_AXI_SI_LG_SCAN2DRAM_QCHDBG_NFO_QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCHDMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2QCH_CON_QE_PCIE_GEN3B_HSI2_QCHQCH_CON_UASC_PCIE_GEN3A_DBI_1_QCHDBG_NFO_QCH_CON_LH_AXI_SI_LP_CPUCL0_HSI2_CU_QCHDBG_NFO_QCH_CON_SLH_AXI_MI_P_PERIC0_QCHDBG_NFO_QCH_CON_USI4_USI_QCHDBG_NFO_QCH_CON_PWM_QCHCPUCL2_CMU_CPUCL2_CONTROLLER_OPTIONMIF_CMU_MIF_CONTROLLER_OPTIONMUX_CLKCMU_MIF_SWITCHMUX_CLKCMU_CIS_CLK3MUX_CLK_HSI0_USI1MUX_CLKCMU_CPUCL0_CPU_SWITCH_USERMUX_CLKCMU_CPUCL0_BCI_SWITCH_USERMUX_CLKCMU_G3D_NOCD_USERMUX_CLKCMU_NOCL0_NOC_USERMUX_CLKCMU_PERIC1_USI10_USI_USERMUX_CLKCMU_PERIC1_USI13_USI_USERMUX_CLKCMU_YUVP_NOC_USERCLKCMU_HSI1_PCIECLKCMU_G3D_NOCDDIV_CLK_CPUCL0_PCLK_LHDIV_CLK_GSACORE_SPI_GSCDIV_CLK_GSACORE_SCDIV_CLK_HSI1_NOC_LHDIV_CLK_MISC_NOCPDIV_CLK_SLC1_DCLKDIV_CLK_PERIC1_USI10_USIDIV_CLK_S2D_CORE_LHGOUT_BLK_AOC_UID_BAAW_AOC_IPCLKPORT_I_PCLKGOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_ACLKCLK_BLK_AOC_UID_SLH_AXI_MI_LG_ALIVE_AOC_IPCLKPORT_I_CLKCLK_BLK_AOC_UID_LH_AXI_SI_LP_AOC_HSI1_CD_IPCLKPORT_I_CLKGOUT_BLK_APM_UID_RSTNSYNC_SR_CLK_APM_USI0_USI_IPCLKPORT_CLKCLK_BLK_APM_UID_RSTNSYNC_SR_CLK_APM_NOC_IPCLKPORT_CLKCLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_CORE_CLKGOUT_BLK_BW_UID_SSMT_BW_IPCLKPORT_ACLKCLK_BLK_BW_UID_BW_IPCLKPORT_ACLKGATE_CLKCMU_CPUCL0_DSU_SWITCHGATE_CLKCMU_NOCL2AA_NOCCLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLKCLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_CPU_IPCLKPORT_CLKCLK_BLK_EH_UID_QE_EH_IPCLKPORT_ACLKCLK_BLK_EH_UID_RSTNSYNC_SR_CLK_EH_OSCCLK_IPCLKPORT_CLKCLK_BLK_G2D_UID_LH_AST_MI_ID_G2D0_JPEG_IPCLKPORT_I_CLKCLK_BLK_G2D_UID_LH_AST_SI_ID_G2D1_JPEG_IPCLKPORT_I_CLKCLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKSCLK_BLK_GDC_UID_XIU_D2_GDC_IPCLKPORT_ACLKCLK_BLK_GDC_UID_RSTNSYNC_CLK_GDC_LME_IPCLKPORT_CLKCLK_BLK_GSACORE_UID_RSTNSYNC_SR_CLK_GSACORE_UART_IPCLKPORT_CLKCLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLKGATE_CLK_HSI0_USI3CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_OSC_CLKGOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLKGOUT_BLK_HSI1_UID_PCIE_GEN3_0_IPCLKPORT_PCIE_SUB_CTRL_A_G3X2_PHY_REFCLK_INGOUT_BLK_HSI2_UID_LH_ACEL_SI_D_HSI2_IPCLKPORT_I_CLKGOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLKCLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCP_LH_IPCLKPORT_CLKGOUT_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLKGOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_PCLKCLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_LH_AXI_MI_P_MISC_CD_IPCLKPORT_I_CLKCLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLKCLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_TPU_IPCLKPORT_I_CLKCLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_LH_IPCLKPORT_CLKCLK_BLK_NOCL1A_UID_SLH_AXI_MI_D_G3DMMU_IPCLKPORT_I_CLKCLK_BLK_NOCL1A_UID_LH_TAXI_SI_D3_NOCL1A_NOCL0_IPCLKPORT_I_CLKCLK_BLK_NOCL1A_UID_PPMU_NOCL1A_M0_IPCLKPORT_ACLKGOUT_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLKCLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLKGOUT_BLK_NOCL2AA_UID_LH_ACEL_MI_D_HSI2_IPCLKPORT_I_CLKGOUT_BLK_NOCL2AA_UID_LH_AXI_MI_D6_RGBP_IPCLKPORT_I_CLKCLK_BLK_NOCL2AB_UID_PPMU_NOCL2AB_M1_IPCLKPORT_ACLKGOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLKCLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_PCLKCLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_SCLKGOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLKCLK_BLK_PERIC1_UID_LH_AXI_SI_P_PERIC1_CU_IPCLKPORT_I_CLKGOUT_BLK_RGBP_UID_SYSREG_RGBP_IPCLKPORT_PCLKCLK_BLK_RGBP_UID_QE_D2_RGBP_IPCLKPORT_PCLKGOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLKGOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLKGOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_PCLKCLK_BLK_TNR_UID_XIU_D3_TNR_IPCLKPORT_ACLKCLK_BLK_TNR_UID_QE_D3_TNR_IPCLKPORT_PCLKGOUT_BLK_TPU_UID_SSMT_D0_TPU_IPCLKPORT_ACLKCLK_BLK_TPU_UID_PPMU_D1_TPU_IPCLKPORT_PCLKCLK_BLK_YUVP_UID_XIU_D0_YUVP_IPCLKPORT_ACLKOSCCLK_CPUCL1OSCCLK_MISCPLL_SHARED1_D4PPMU_PCIE_QCHD_TZPC_APM_CUSTOM_QCHMAILBOX_APM_GSA_QCHADD_AUR_QCHLH_ACEL_SI_D1_AUR_QCHTREX_D_BW_QCHDFTMUX_CMU_QCH_CIS_CLK3LH_AXI_MI_ID_PPU_QCHLH_AXI_MI_IG_CSSYS_QCHLH_AXI_SI_LP_CPUCL0_HSI2_CD_QCHRSTNSYNC_CLK_CLUSTER0_ICN_NSRESET_QCHLH_AXI_MI_IP_CPUCL2_QCHSSMT_D1_DPUF1_QCHSSMT_D1_G2D_QCHLH_AST_SI_ID_GDC1_GDC0_QCHLH_AST_MI_I_CA32_GIC_QCHLH_AXI_MI_IP_AXI2APB1_GSACORE_QCHLH_AXI_SI_ID_GME_GSA_QCHWDT_GSACORE_QCHLH_AXI_MI_ID_GME_GSA_QCHLH_AXI_SI_P_GSA_CU_QCHPPMU_HSI0_QCHSYSREG_HSI0_QCHUSI3_HSI0_QCHQE_MMC_CARD_HSI2_QCHLH_AXI_SI_D1_MCSC_QCHQE_D3_MCSC_QCHMIF_CMU_MIF_QCHQCH_ADAPTER_SMC_QCHDIT_QCHD_TZPC_MISC_QCHMCT_V41_QCHQE_DIT_QCHRTIC_QCHLH_TAXI_MI_D3_NOCL1A_NOCL0_QCHSLC_CH2_QCHCMU_NOCL1A_CMUREF_QCHLH_AXI_SI_P_TPU_CD_QCHLH_AXI_MI_D_ALIVE_QCHLH_AXI_SI_G_CSSYS_CU_QCHLH_AXI_MI_D0_DPUF0_QCHSLH_AXI_SI_P_RGBP_QCHLH_TAXI_SI_D1_NOCL2AB_NOCL1A_QCHQE_D6_MCFP_QCHSYSMMU_S1_PMMU2_TNR_QCH_S0LH_AXI_MI_P_TPU_CU_QCHCTRL_OPTION_CMU_G3DVCLK_IP_UASC_P1_AURVCLK_IP_LH_AXI_SI_P_CPUCL0_NOCL0VCLK_IP_D_TZPC_DPUF1VCLK_IP_SYSREG_G2DVCLK_IP_ADD_G3DVCLK_IP_PPMU_D_LMEVCLK_IP_UART_GSACOREVCLK_IP_XIU_D0_GSEVCLK_IP_USI4_HSI0VCLK_IP_XIU_D0_HSI2VCLK_IP_PCIE_IA_GEN3B_1VCLK_IP_SLH_AXI_MI_P_HSI2VCLK_IP_SYSMMU_S2_ISPFEVCLK_IP_BAAW_ISPFEVCLK_IP_QE_SPDMA1VCLK_IP_PDMA1VCLK_IP_SLH_AXI_MI_P_MISC_GICVCLK_IP_LH_AXI_SI_P_MIF0_CDVCLK_IP_LH_ACEL_MI_D3_CPUCL0VCLK_IP_PPMU_NOCL0_S0VCLK_IP_LH_AST_MI_G_NOCL2ABVCLK_IP_PPC_TPU_D0_EVENTVCLK_IP_LH_AST_SI_G_NOCL2ABVCLK_IP_SLH_AXI_SI_P_YUVPVCLK_IP_USI9_USIVCLK_IP_USI12_USIVCLK_IP_SSMT_D4_MCFPVCLK_IP_QE_D11_MCFPVCLK_IP_PPMU_D2_TNRVCLK_IP_TNR_CMU_TNRVCLK_IP_PPMU_D11_TNRAVCLK_IP_SYSMMU_S0_PMMU1_TPUmargin_tpu_write_fileOSC#echo "clk_name" > clk_info - [%x] BLK info hwacgPMUCAL: 3%s %s: error on PA2VA conversion. seq:enter, mode_id:%d. aborting init... 3%s %s: PA absent in seq element (idx:%d) QCH_CON_GPU_QCHBUS_COMPONENT_DRCG_ENDPUB_CONFIGURATIONQCH_CON_DPUF0_QCH_SRAMCQCH_CON_PPMU_D1_DPUF1_QCHDBG_NFO_QCH_CON_LH_AST_MI_ID_JPEG_G2D1_QCHDBG_NFO_QCH_CON_SSMT_D0_G2D_QCHCLK_CON_DIV_DIV_CLK_GSE_NOCPQCH_CON_LH_AST_MI_L_OTF_TNR_GSE_QCHDBG_NFO_QCH_CON_PPMU_D0_GSE_QCHDBG_NFO_QCH_CON_SYSMMU_S0_GSE_QCH_S0DBG_NFO_QCH_CON_MCSC_CMU_MCSC_QCHDBG_NFO_QCH_CON_MCSC_QCHDBG_NFO_QCH_CON_PPMU_D4_MCSC_QCHDBG_NFO_QCH_CON_PPMU_D5_MCSC_QCHDBG_NFO_QCH_CON_SYSMMU_S0_PMMU0_MCSC_QCH_S0QCH_CON_SSMT_D4_MCFP_QCHDBG_NFO_QCH_CON_PPMU_D4_MCFP_QCHDBG_NFO_QCH_CON_RGBP_CMU_RGBP_QCHDBG_NFO_QCH_CON_SYSMMU_S1_PMMU2_RGBP_QCH_S0QCH_CON_SSMT_D7_TNR_QCHDBG_NFO_QCH_CON_QE_D3_TNR_QCHDBG_NFO_QCH_CON_SSMT_D5_TNR_QCHQCH_CON_GPC_YUVP_QCHQCH_CON_SLH_AXI_MI_P_YUVP_QCHQCH_CON_YUVP_QCHDBG_NFO_QCH_CON_PPMU_D4_YUVP_QCHDBG_NFO_QCH_CON_QE_D0_YUVP_QCHDBG_NFO_QCH_CON_SYSMMU_S0_YUVP_QCH_S0QCH_CON_UASC_P0_AUR_QCHQCH_CON_UASC_BW_QCHDBG_NFO_QCH_CON_TREX_D_BW_QCHCLK_CON_DIV_DIV_CLK_EH_NOCPQCH_CON_LH_AXI_SI_IP_ISPFE_QCHQCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3QCH_CON_PPMU_D0_ISPFE_QCHQCH_CON_PPMU_D1_ISPFE_QCHQCH_CON_SYSMMU_S0_PMMU0_ISPFE_QCH_S0QCH_CON_SYSMMU_S2_ISPFE_QCH_S0DBG_NFO_QCH_CON_ISPFE_CMU_ISPFE_QCHPLL_CON8_PLL_TPUCLK_CON_DIV_DIV_CLK_TPU_NOCP_LHCLK_CON_DIV_DIV_CLK_SLC2_DCLKQCH_CON_LH_ATB_SI_T_BDU_QCHQCH_CON_TREX_D_NOCL0_QCHDBG_NFO_QCH_CON_SLH_AXI_SI_P_MIF0_QCHDBG_NFO_QCH_CON_SYSREG_NOCL0_QCHDBG_NFO_QCH_CON_LH_AXI_SI_P_TPU_CD_QCHDBG_NFO_QCH_CON_LH_TAXI_MI_D0_NOCL2AB_NOCL1A_QCHDBG_NFO_QCH_CON_LH_TAXI_MI_D1_NOCL2AA_NOCL1A_QCHDBG_NFO_QCH_CON_PPMU_NOCL1A_M0_QCHQCH_CON_LH_AXI_MI_G_CSSYS_CU_QCHQCH_CON_LH_AST_SI_G_NOCL2AA_QCHQCH_CON_SLH_AXI_SI_P_DPUB_QCHQCH_CON_SLH_AXI_SI_P_DPUF1_QCHDBG_NFO_QCH_CON_LH_AXI_MI_D5_RGBP_QCHDBG_NFO_QCH_CON_LH_AXI_MI_D6_RGBP_QCHDBG_NFO_QCH_CON_TREX_D_NOCL2AA_QCHQCH_CON_SLH_AXI_SI_P_TNR_QCHDBG_NFO_QCH_CON_SLH_AXI_SI_P_G2D_QCHCLK_CON_DIV_DIV_CLK_HSI0_USI0CLK_CON_DIV_DIV_CLK_HSI0_USI3PLL_CON0_MUX_CLKCMU_HSI0_NOC_USERQCH_CON_D_TZPC_HSI0_QCHQCH_CON_LH_ACEL_SI_D_HSI0_QCHQCH_CON_LH_AXI_SI_LP_AOC_HSI0_CU_QCHDBG_NFO_QCH_CON_USB32DRD_QCH_EUSBPHYDBG_NFO_QCH_CON_USI2_HSI0_QCHQCH_CON_LH_ACEL_SI_D_HSI1_QCHQCH_CON_SSMT_HSI1_QCHCPUCL1_CLKDIVSTEP_VDROOP_FLTCLK_CON_DIV_DIV_CLK_PERIC0_USI14_USIPLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USERQCH_CON_APM_I3C_PMIC_QCH_PQCH_CON_APM_USI1_UART_INT_QCHQCH_CON_GREBEINTEGRATION_QCH_GREBEQCH_CON_SLH_AXI_MI_P_ALIVE_QCHDBG_NFO_QCH_CON_MAILBOX_APM_SWD_QCHDBG_NFO_QCH_CON_MAILBOX_AP_AURCORE2_QCHQCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_QCHQCH_CON_LH_AXI_SI_ID_SC_QCHQCH_CON_MISC_CMU_MISC_QCHDBG_NFO_QCH_CON_GPC_MISC_QCHDBG_NFO_QCH_CON_SPDMA0_QCHDMYQCH_CON_PCIE_GEN3B_1_QCH_REFQCH_CON_PCIE_GEN3B_1_QCH_PMA_APBDBG_NFO_QCH_CON_QE_MMC_CARD_HSI2_QCHDBG_NFO_QCH_CON_SLH_AXI_MI_P_HSI2_QCHDBG_NFO_QCH_CON_PCIE_GEN3B_1_QCH_UDBGDMYQCH_CON_I3C2_QCH_SCLKQCH_CON_USI2_USI_QCHMUX_CLKCMU_HSI0_USB32DRDMUX_CLKCMU_MIF_NOCPMUX_CLKCMU_GDC_LMEMUX_CPUCL2_CMUREFMUX_CLKCMU_HSI0_DPOSC_USERMUX_CLKCMU_MCSC_NOC_USERCLKCMU_MIF_NOCPCLKCMU_GDC_GDC0DIV_CLK_CLUSTER0_ACLK_MAINGOUT_BLK_AOC_UID_XIU_P_AOC_IPCLKPORT_ACLKGOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_IPCLKPORT_CLKGOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLKCLK_CMU_BOOST_OPTION1GOUT_BLK_APM_UID_APM_USI1_UART_INT_IPCLKPORT_PCLKCLK_BLK_APM_UID_MAILBOX_AP_AOCP6_IPCLKPORT_PCLKCLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLKCLK_BLK_AUR_UID_AUR_CMU_AUR_IPCLKPORT_PCLKCLK_BLK_AUR_UID_SYSMMU_S0_PMMU1_AUR_IPCLKPORT_CLKCLK_BLK_AUR_UID_LH_AXI_MI_P_AUR_CU_IPCLKPORT_I_CLKCLK_BLK_AUR_UID_RSTNSYNC_SR_CLK_AUR_AURCTL_IPCLKPORT_CLKCLK_BLK_BW_UID_TREX_D_BW_IPCLKPORT_PCLKGATE_CLKCMU_PERIC1_IPGATE_CLKCMU_CIS_CLK4GATE_CLKCMU_NOCL1B_NOCCLKCMU_MIF_BOOSTGATE_CLKCMU_TPU_TPUCLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_GCLK0CLK_BLK_CPUCL0_UID_ADD0_APBIF_CPUCL0_IPCLKPORT_PCLKCLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_G3D_CPUCL0_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_LH_AXI_SI_LP_CPUCL0_HSI2_CD_IPCLKPORT_I_CLKGATE_CLK_CLUSTER0_ATCLKCLK_BLK_DPUB_UID_SLH_AXI_MI_P_DPUB_IPCLKPORT_I_CLKCLK_BLK_DPUF0_UID_LH_AXI_MI_LD0_DPUF1_DPUF0_IPCLKPORT_I_CLKGOUT_BLK_DPUF1_UID_LH_AXI_SI_LD1_DPUF1_DPUF0_IPCLKPORT_I_CLKCLK_BLK_DPUF1_UID_SSMT_D0_DPUF1_IPCLKPORT_PCLKGOUT_BLK_EH_UID_EH_IPCLKPORT_AXI_ACLKCLK_BLK_G2D_UID_RSTNSYNC_SR_CLK_G2D_NOCD_G2D_IPCLKPORT_CLKCLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_NOCP_IPCLKPORT_CLKCLK_BLK_G3D_UID_DAPAHBAP_GPU_IPCLKPORT_DAPCLKGOUT_BLK_GDC_UID_PPMU_D0_GDC0_IPCLKPORT_PCLKGOUT_BLK_GDC_UID_SSMT_D0_GDC0_IPCLKPORT_ACLKCLK_BLK_GDC_UID_GDC0_IPCLKPORT_C2CLK_MCLK_BLK_GDC_UID_LH_AXI_MI_LD_RGBP_GDC_IPCLKPORT_I_CLKCLK_BLK_GDC_UID_GDC1_IPCLKPORT_C2CLK_MGOUT_BLK_GSACORE_UID_GPIO_GSACORE0_IPCLKPORT_PCLKGOUT_BLK_GSACORE_UID_LH_AXI_MI_I_DAP_GSA_IPCLKPORT_I_CLKGOUT_BLK_GSACTRL_UID_GPC_GSACTRL_IPCLKPORT_PCLKGOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_IPCLKPORT_CLKCLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_USI1_IPCLKPORT_CLKCLK_BLK_HSI0_UID_USI4_HSI0_IPCLKPORT_PCLKCLK_BLK_HSI0_UID_I3C3_HSI0_IPCLKPORT_I_PCLKGOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLKGOUT_BLK_HSI2_UID_UASC_PCIE_GEN3A_SLV_1_IPCLKPORT_ACLKCLK_BLK_HSI2_UID_PCIE_GEN3B_1_IPCLKPORT_PCIE_PHY_TOP_X1_INST_0_SF_PCIEPHY_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:<- %s - CMU_TOP PLL info %s pd index(%d) is out of supported range (0~%d).PLL_CON0_PLL_G3D_L2QCH_CON_D_TZPC_G3D_QCHQCH_CON_LH_ACEL_SI_D0_G3D_QCHQCH_CON_LH_ACEL_SI_D1_G3D_QCHQCH_CON_SYSMMU_S0_PMMU0_G3D_QCH_S0DBG_NFO_QCH_CON_LH_AXI_SI_IP_G3D_QCHQCH_CON_PPMU_D1_DPUF0_QCHDBG_NFO_QCH_CON_SYSMMU_S0_PMMU1_DPUF0_QCH_S0QCH_CON_PPMU_D1_G2D_QCHQCH_CON_LH_AXI_SI_D1_GDC_QCHQCH_CON_QE_D4_GDC0_QCHQCH_CON_SLH_AXI_MI_P_GDC_QCHQCH_CON_SSMT_D_LME_QCHDBG_NFO_QCH_CON_GDC_CMU_GDC_QCHDBG_NFO_QCH_CON_SYSMMU_S0_PMMU2_GDC_QCH_S0QCH_CON_PPMU_D2_GSE_QCHDBG_NFO_QCH_CON_GSE_QCH_GSEQCH_CON_LH_AST_MI_L_OTF_YUVP_MCSC_QCHQCH_CON_SSMT_D1_MCSC_QCHQCH_CON_SYSMMU_S0_PMMU0_MCSC_QCH_S0DBG_NFO_QCH_CON_LH_AXI_SI_D0_MCSC_QCHDBG_NFO_QCH_CON_SSMT_D0_MFC_QCHQCH_CON_PPMU_D0_MCFP_QCHQCH_CON_QE_D7_MCFP_QCHQCH_CON_SSMT_D2_MCFP_QCHQCH_CON_SSMT_D2_RGBP_QCHDBG_NFO_QCH_CON_D_TZPC_RGBP_QCHRGBP_CMU_RGBP_CONTROLLER_OPTIONQCH_CON_GTNR_ALIGN_QCH_MSAQCH_CON_SYSMMU_S1_PMMU2_TNR_QCH_S0DBG_NFO_QCH_CON_PPMU_D8_TNR_QCHDBG_NFO_QCH_CON_SYSMMU_S0_TNR_QCH_S0DBG_NFO_QCH_CON_SSMT_D4_YUVP_QCHPLL_CON0_MUX_CLKCMU_AUR_NOC_USERQCH_CON_LH_ACEL_SI_D0_AUR_QCHDBG_NFO_QCH_CON_LH_AXI_MI_P_AUR_CU_QCHQCH_CON_LH_AXI_SI_D_BW_QCHEH_STATUSDBG_NFO_QCH_CON_QE_D0_ISPFE_QCHDBG_NFO_QCH_CON_SLH_AXI_MI_P_ISPFE_QCHDBG_NFO_QCH_CON_SYSMMU_S2_ISPFE_QCH_S0CLK_CON_MUX_MUX_CLK_TPU_TPU_LPMDBG_NFO_QCH_CON_SYSMMU_S0_PMMU0_TPU_QCHQCH_CON_LH_ACEL_MI_D1_CPUCL0_QCHQCH_CON_PPC_NOCL1A_M0_CYCLE_QCHQCH_CON_PPMU_NOCL0_S1_QCHQCH_CON_PPMU_NOCL0_S3_QCHDBG_NFO_QCH_CON_LH_AST_MI_G_NOCL1B_CU_QCHDBG_NFO_QCH_CON_LH_AXI_SI_P_MISC_GIC_CD_QCHDBG_NFO_QCH_CON_LH_TAXI_SI_P_NOCL0_NOCL2AB_QCHDBG_NFO_QCH_CON_PPC_CPUCL0_D0_EVENT_QCHNOCL0_EMBEDDED_CMU_NOCL03_CONTROLLER_OPTIONQCH_CON_LH_ACEL_MI_D3_G3D_QCHQCH_CON_PPC_G3D_D3_EVENT_QCHDBG_NFO_QCH_CON_LH_ACEL_MI_D0_G3D_QCHDBG_NFO_QCH_CON_LH_ACEL_MI_D1_AUR_QCHDBG_NFO_QCH_CON_LH_TAXI_MI_D1_NOCL2AB_NOCL1A_QCHDBG_NFO_QCH_CON_PPMU_NOCL1A_M1_QCHDBG_NFO_QCH_CON_SLH_AXI_SI_P_BW_QCHNOCL1A_HCHGEN_CLKMUX_CMUREFQCH_CON_LH_ACEL_MI_D_HSI0_QCHQCH_CON_LH_AXI_MI_D_GSA_QCHQCH_CON_LH_AXI_MI_P_AOC_CD_QCHQCH_CON_LH_AXI_MI_P_HSI1_CD_QCHDBG_NFO_QCH_CON_PPC_AOC_CYCLE_QCHPLL_CON0_MUX_CLKCMU_NOCL2AA_NOC_USERDBG_NFO_QCH_CON_SLH_AXI_SI_P_DPUB_QCHDBG_NFO_QCH_CON_LH_AXI_MI_D0_GDC_QCHQCH_CON_GPC_HSI0_QCHQCH_CON_LH_AXI_MI_P_HSI0_CU_QCHDBG_NFO_QCH_CON_USB32DRD_QCH_USBDPPHY_TCAQCH_CON_LH_AXI_SI_P_HSI1_CU_QCHQCH_CON_LH_AXI_MI_LP_CPUCL0_HSI1_QCHDBG_NFO_QCH_CON_PCIE_GEN3_0_QCH_PMA_APBblkpwr_dpuf1CLK_CON_DIV_DIV_CLK_PERIC0_I3CQCH_CON_APBIF_GPIO_FAR_ALIVE_QCHQCH_CON_APM_CMU_APM_QCHQCH_CON_D_TZPC_APM_CUSTOM_QCHQCH_CON_MAILBOX_APM_AOC_QCHDBG_NFO_QCH_CON_MAILBOX_APM_GSA_QCHDBG_NFO_QCH_CON_MAILBOX_AP_DBGCORE_QCHDBG_NFO_QCH_CON_SS_DBGCORE_QCH_DBGQCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_QCHDBG_NFO_QCH_CON_TMU_SUB_QCHDBG_NFO_QCH_CON_WDT_CLUSTER0_QCHQCH_CON_LH_ACEL_SI_D_HSI2_QCHQCH_CON_PCIE_GEN3B_1_QCH_AXIDBG_NFO_DMYQCH_CON_PCIE_GEN3B_1_QCH_REFDBG_NFO_QCH_CON_LH_AXI_SI_P_HSI2_CU_QCHDBG_NFO_QCH_CON_UFS_EMBD_QCHDBG_NFO_QCH_CON_PCIE_GEN3B_1_QCH_PMA_APBQCH_CON_I3C5_QCH_PCLKDBG_NFO_QCH_CON_I3C4_QCH_PCLKQCH_CON_LH_AXI_MI_P_PERIC1_CU_QCHPLL_G3D_L2PLL_NOCL0MUX_CLKCMU_RGBP_RGBPMUX_CLKCMU_GSE_NOCMUX_CLKCMU_CIS_CLK7MUX_CLKCMU_AUR_AURMUX_CLKCMU_DPUB_DSIMMUX_CLKCMU_G3D_TRACEMUX_CLK_G3DCORE_TRACE_USERMUX_CLKCMU_MISC_SC_USERCLKCMU_CPUCL0_DBGDIV_CLK_G2D_NOCPDIV_CLK_GDC_NOCPDIV_CLK_NOCL2AA_NOCP_LHDIV_CLK_PERIC0_USI0_UARTDIV_CLK_G3D_STACKSGOUT_BLK_APM_UID_SSMT_D_ALIVE_IPCLKPORT_ACLKGOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLKCLK_NOCL1B_BOOST_OPTION1CLK_NOCL0_BOOST_OPTION1CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_I3C_PMIC_IPCLKPORT_CLKCLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_ACLKCLK_BLK_AUR_UID_SYSMMU_S0_PMMU0_AUR_IPCLKPORT_CLKCLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_IPCLKPORT_CLKGOUT_BLK_BW_UID_LH_AXI_SI_D_BW_IPCLKPORT_I_CLKGOUT_BLK_BW_UID_D_TZPC_BW_IPCLKPORT_PCLKGATE_CLKCMU_HSI0_USB32DRDGATE_CLKCMU_TOP_CMUREFCLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLKCLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CLUSTER0_BCI_IPCLKPORT_CLKCLK_BLK_CPUCL0_UID_ADD0_CPUCL0_IPCLKPORT_CH_CLKGATE_CLK_CLUSTER1_CORE7CLKCLK_BLK_CPUCL2_UID_LH_AXI_MI_IP_CPUCL2_IPCLKPORT_I_CLKCLK_BLK_EH_UID_RSTNSYNC_SR_CLK_EH_NOCP_LH_IPCLKPORT_CLKCLK_BLK_EH_UID_XIU_D_EH_IPCLKPORT_ACLKGOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_G2D_IPCLKPORT_CLKGOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_ACLKGOUT_BLK_GDC_UID_LH_AXI_SI_D1_GDC_IPCLKPORT_I_CLKCLK_BLK_GDC_UID_QE_D2_GDC1_IPCLKPORT_ACLKGOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_IPCLKCLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLKCLK_BLK_GSACORE_UID_RSTNSYNC_SR_CLK_GSACORE_CPU_IPCLKPORT_CLKGOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TPU_IPCLKPORT_PCLKGOUT_BLK_GSACTRL_UID_SECJTAG_GSACTRL_IPCLKPORT_I_CLKCLK_BLK_GSACTRL_UID_RSTNSYNC_SR_CLK_GSACTRL_NOCP_LH_IPCLKPORT_CLKGOUT_BLK_GSE_UID_SYSREG_GSE_IPCLKPORT_PCLKGOUT_BLK_GSE_UID_LH_AXI_SI_D_GSE_IPCLKPORT_I_CLKGOUT_BLK_GSE_UID_SSMT_D0_GSE_IPCLKPORT_PCLKGOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLKGOUT_BLK_HSI0_UID_PPMU_HSI0_IPCLKPORT_ACLKCLK_BLK_HSI0_UID_SYSMMU_S0_PMMU0_HSI0_IPCLKPORT_CLKGOUT_BLK_HSI2_UID_PCIE_IA_GEN3A_1_IPCLKPORT_I_CLKGOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLKGOUT_BLK_HSI2_UID_QE_PCIE_GEN3A_HSI2_IPCLKPORT_ACLKGOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLKGOUT_BLK_ISPFE_UID_SYSREG_ISPFE_IPCLKPORT_PCLKGOUT_BLK_ISPFE_UID_AD_APB_SYSMMU_S0_ISPFE_S1_NS_IPCLKPORT_PCLKMCLK_BLK_ISPFE_UID_ISPFE_IPCLKPORT_CLK_REFGOUT_BLK_MCSC_UID_SSMT_D2_MCSC_IPCLKPORT_PCLKCLK_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_PCLKCLK_BLK_MCSC_UID_SSMT_D5_MCSC_IPCLKPORT_ACLKCLK_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLKCLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLKGOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_PCLKCLK_BLK_MIF_UID_QCH_ADAPTER_DDRPHY_IPCLKPORT_PCLKGOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLKGOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCD_IPCLKPORT_CLKGOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLKGOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLKGOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_PCLKGOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_PCLKGOUT_BLK_NOCL0_UID_SLH_AXI_MI_G_NOCL0_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_LH_AXI_MI_P_CPUCL0_CD_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2AA_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLKCLK_BLK_NOCL0_UID_LH_TAXI_SI_P_NOCL0_NOCL2AB_IPCLKPORT_I_CLKGOUT_BLK_NOCL1A_UID_PPC_NOCL2AB_S0_EVENT_IPCLKPORT_ACLKCLK_BLK_NOCL1A_UID_PPMU_NOCL1A_M1_IPCLKPORT_ACLKCLK_BLK_NOCL1A_UID_PPMU_NOCL1A_M1_IPCLKPORT_PCLKCLK_BLK_NOCL1B_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLKCLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD_IPCLKPORT_CLKGOUT_BLK_NOCL2AA_UID_GPC_NOCL2AA_IPCLKPORT_PCLKCLK_BLK_NOCL2AA_UID_PPMU_NOCL2AA_M1_IPCLKPORT_PCLKCLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_IPCLKCLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_PCLKCLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_IPCLKGOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLKCLK_BLK_RGBP_UID_PPMU_D1_RGBP_IPCLKPORT_PCLKCLK_BLK_RGBP_UID_PPMU_D2_MCFP_IPCLKPORT_ACLKCLK_BLK_RGBP_UID_SYSMMU_S1_PMMU4_RGBP_IPCLKPORT_CLKCLK_BLK_RGBP_UID_SSMT_D2_RGBP_IPCLKPORT_PCLKCLK_BLK_RGBP_UID_QE_D5_MCFP_IPCLKPORT_ACLKCLK_BLK_RGBP_UID_XIU_D1_RGBP_IPCLKPORT_ACLKGOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_PCLKCLK_BLK_TNR_UID_PPMU_D11_TNRA_IPCLKPORT_PCLKCLK_BLK_TNR_UID_SSMT_D10_TNRA_IPCLKPORT_ACLKCLK_BLK_TNR_UID_SYSMMU_S2_PMMU0_TNR_IPCLKPORT_CLKCLK_BLK_TPU_UID_SSMT_D1_TPU_IPCLKPORT_PCLKCLK_BLK_YUVP_UID_BLK_YUVP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLKI_CLK_AOC_TRACELH_ATB_SI_LT_AOC_QCHAPM_USI0_USI_QCHAPM_USI1_UART_INT_QCHCSSYS_QCHLH_ACEL_SI_D0_CPUCL0_QCHLH_ACEL_SI_D2_CPUCL0_QCHLH_AXI_SI_ID_PPU_QCHLH_AXI_SI_IP_BOOKER_QCHDPUF0_CMU_DPUF0_QCHPPC_EH_CYCLE_QCHADD_APBIF_G3D_QCHLH_AST_SI_ID_GDC0_GDC1_QCHLH_AST_SI_ID_LME_GDC1_QCHSYSMMU_S0_PMMU2_GDC_QCH_S0LH_AXI_MI_IP_GSA_QCHMAILBOX_GSA2AOC_QCHSECJTAG_GSACTRL_QCHSYSMMU_S0_PMMU0_GSA_ZM_QCHPPMU_D2_GSE_QCHSLH_AXI_MI_P_GSE_QCHDP_LINK_QCH_OSC_CLKLH_AXI_MI_P_HSI2_CU_QCHPCIE_GEN3B_1_QCH_APBLH_AXI_SI_IP_ISPFE_QCHMCSC_QCHQE_D2_MCSC_QCHSLH_AXI_MI_P_MFC_QCHLH_AXI_MI_P_MISC_CU_QCHTMU_TOP_QCHLH_ATB_SI_T_BDU_CD_QCHSLH_AXI_MI_G_NOCL0_QCHLH_ACEL_MI_D1_G3D_QCHLH_AXI_SI_P_AOC_CD_QCHLH_AXI_MI_D0_GDC_QCHLH_AXI_MI_D5_TNR_QCHI3C3_QCH_PCLKUSI11_USI_QCHPPMU_D0_RGBP_QCHQE_D1_RGBP_QCHGTNR_MERGE_QCH_01QE_D1_TNR_QCHLH_AXI_SI_P_TPU_CU_QCHSSMT_D0_YUVP_QCHYUVP_QCH_VOTF0CTRL_OPTION_CMU_DPUF0CTRL_OPTION_EMBEDDED_CMU_NOCL02VCLK_IP_SLH_AXI_MI_P_AOCVCLK_IP_SYSREG_APMVCLK_IP_MAILBOX_AP_AOCA32VCLK_IP_MAILBOX_AP_AURCORE1VCLK_IP_APBIF_INTCOMB_VGPIO2APMVCLK_IP_SLH_AXI_MI_LP_AOC_ALIVEVCLK_IP_SLH_AXI_MI_P_BWVCLK_IP_LH_AXI_MI_IP_BOOKERVCLK_IP_LH_AXI_MI_LP_ALIVE_CPUCL0_CUVCLK_IP_PPC_INSTRRET_CLUSTER0_0VCLK_IP_CPUCL0_QOSVCLK_IP_ADM_DAP_G_GPUVCLK_IP_QE_D0_GDC1VCLK_IP_WDT_GSACOREVCLK_IP_LH_AST_MI_I_GIC_CA32VCLK_IP_LH_AST_SI_I_GIC_CA32VCLK_IP_PPMU_D1_GSEVCLK_IP_SSMT_D2_GSEVCLK_IP_HSI1_CMU_HSI1VCLK_IP_UASC_PCIE_GEN3A_SLV_0VCLK_IP_LH_AXI_SI_LP_CPUCL0_HSI1_CUVCLK_IP_SYSMMU_S0_PMMU0_HSI1VCLK_IP_SSMT_PCIE_IA_GEN3B_1VCLK_IP_LH_AXI_SI_P_HSI2_CUVCLK_IP_LH_AXI_MI_LP_CPUCL0_HSI2VCLK_IP_LH_AXI_SI_LP_CPUCL0_HSI2_CUVCLK_IP_PPMU_D2_ISPFEVCLK_IP_SSMT_D0_MFCVCLK_IP_PPC_NOCL1A_M0_CYCLEVCLK_IP_SLH_AXI_SI_P_PERIC0VCLK_IP_PPC_NOCL2AA_S0_EVENTVCLK_IP_PPC_AUR_D0_EVENTVCLK_IP_LH_TAXI_SI_D3_NOCL1A_NOCL0VCLK_IP_LH_TAXI_MI_P_NOCL0_NOCL2AAVCLK_IP_SLH_AXI_SI_P_MCSCVCLK_IP_GPC_PERIC0VCLK_IP_GPC_PERIC1VCLK_IP_PPMU_D0_MCFPVCLK_IP_QE_D4_MCFPVCLK_IP_XIU_D5_RGBPVCLK_IP_LH_AST_MI_L_OTF_YUVP_TNRVCLK_IP_SSMT_D5_TNRVCLK_IP_SSMT_D8_TNRVCLK_IP_SYSMMU_S1_TNRVCLK_IP_PPMU_D1_TPUVCLK_IP_GPC_YUVPVCLK_IP_LH_AST_MI_L_OTF_RGBP_YUVPcmu_top_base is NULL 3%s %s: there is no pd list. aborting init... PLL_CON5_PLL_G3DQCH_CON_SLH_AXI_SI_D_G3DMMU_QCHG3D_CLKDIVSTEP_SMPL_FLTEMBEDDED_G3D_STATUSQCH_CON_SLH_AXI_MI_P_DPUF0_QCHQCH_CON_LH_AXI_SI_LD0_DPUF1_DPUF0_QCHQCH_CON_SYSMMU_S0_DPUF1_QCH_S0DBG_NFO_QCH_CON_DPUF1_QCH_SRAMCDBG_NFO_QCH_CON_LH_AXI_SI_LD1_DPUF1_DPUF0_QCHDBG_NFO_QCH_CON_PPMU_D0_DPUF1_QCHDBG_NFO_QCH_CON_LH_AST_SI_ID_G2D0_JPEG_QCHDBG_NFO_QCH_CON_SYSREG_G2D_QCHDBG_NFO_QCH_CON_GDC1_QCH_C2CLKDBG_NFO_QCH_CON_SLH_AXI_MI_P_GDC_QCHDBG_NFO_QCH_CON_SSMT_D0_GDC1_QCHQCH_CON_PPMU_D0_MCSC_QCHQCH_CON_QE_D0_MCSC_QCHQCH_CON_SLH_AXI_MI_P_MCSC_QCHDBG_NFO_QCH_CON_QE_D3_MCSC_QCHQCH_CON_SSMT_D1_RGBP_QCHQCH_CON_SSMT_D5_MCFP_QCHDBG_NFO_QCH_CON_QE_D1_RGBP_QCHPLL_CON0_MUX_CLKCMU_TNR_ALIGN_USERQCH_CON_LH_AXI_SI_D5_TNR_QCHQCH_CON_QE_D7_TNR_QCHDBG_NFO_QCH_CON_PPMU_D4_TNR_QCHYUVP_STATUSQCH_CON_LH_AST_SI_L_OTF_YUVP_TNR_QCHDBG_NFO_QCH_CON_D_TZPC_AUR_QCHDBG_NFO_QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CD_QCHQCH_CON_SYSMMU_S0_BW_QCHQCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS10QCH_CON_SSMT_D2_ISPFE_QCHDBG_NFO_QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS9DBG_NFO_QCH_CON_SYSMMU_S0_ISPFE_QCH_S0QCH_CON_TPU_CMU_TPU_QCHDBG_NFO_QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CD_QCHTPU_CLKDIVSTEP_SMPL_FLTDMYQCH_CON_PPC_DBG_CC_QCHQCH_CON_LH_AST_MI_G_NOCL1B_QCHQCH_CON_LH_AXI_MI_P_CPUCL0_NOCL0_QCHQCH_CON_LH_TAXI_MI_D0_NOCL1A_NOCL0_QCHQCH_CON_PPC_CPUCL0_D2_EVENT_QCHQCH_CON_SLH_AXI_SI_P_MIF1_QCHDBG_NFO_DMYQCH_CON_CMU_NOCL0_CMUREF_QCHDBG_NFO_QCH_CON_LH_AST_MI_G_NOCL2AB_QCHDBG_NFO_QCH_CON_SLH_AXI_SI_P_CPUCL0_QCHDBG_NFO_QCH_CON_SLH_AXI_SI_P_MIF1_QCHNOCL0_EMBEDDED_CMU_NOCL01_CONTROLLER_OPTIONQCH_CON_PPC_NOCL2AA_S0_EVENT_QCHDBG_NFO_QCH_CON_PPC_G3D_D1_EVENT_QCHDBG_NFO_QCH_CON_PPC_NOCL2AA_S1_EVENT_QCHDBG_NFO_QCH_CON_LH_AXI_SI_G_CSSYS_CU_QCHQCH_CON_GPC_NOCL2AA_QCHQCH_CON_LH_AXI_MI_D1_DPUF0_QCHQCH_CON_PPMU_NOCL2AA_M0_QCHDBG_NFO_QCH_CON_GPC_NOCL2AA_QCHCLK_CON_DIV_DIV_CLK_NOCL2AB_NOCP_LHPLL_CON5_PLL_USBDMYQCH_CON_USB32DRD_QCH_REFQCH_CON_ETR_MIU_QCH_PCLKQCH_CON_USI0_HSI0_QCHQCH_CON_USI2_HSI0_QCHDBG_NFO_QCH_CON_PPMU_HSI0_QCHDBG_NFO_QCH_CON_USB32DRD_QCH_SUBCTLHSI1_STATUSQCH_CON_PCIE_IA_GEN3A_0_QCHDBG_NFO_QCH_CON_LH_AXI_SI_LD_HSI1_AOC_QCHblkpwr_ispfeCLUSTER0_CPU0_INT_ENPLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USERPLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USERQCH_CON_LH_AXI_SI_D_ALIVE_QCHQCH_CON_QE_SC_QCHDBG_NFO_QCH_CON_D_TZPC_MISC_QCHDBG_NFO_QCH_CON_LH_AXI_SI_P_MISC_CU_QCHDBG_NFO_QCH_CON_MCT_V41_QCHDBG_NFO_QCH_CON_QE_SPDMA1_QCHQCH_CON_PCIE_GEN3B_1_QCH_DBGQCH_CON_PCIE_IA_GEN3A_1_QCHDBG_NFO_QCH_CON_GPIO_HSI2_QCHDBG_NFO_QCH_CON_LH_AXI_MI_LP_CPUCL0_HSI2_QCHQCH_CON_USI11_USI_QCHDBG_NFO_QCH_CON_USI9_USI_QCHCLKOUT_CON_BLK_HSI2_CMU_HSI2_CLKOUT0PLL_MIF_SUBMUX_CMU_CMUREFMUX_CLKCMU_PERIC0_IPMUX_CLKCMU_HSI1_PCIEMUX_CLKCMU_CPUCL0_CPU_SWITCHMUX_CLK_GSACORE_CPU_HCHMUX_CLKCMU_AUR_NOC_USERMUX_CLKCMU_BW_NOC_USERMUX_CLKCMU_DPUB_NOC_USERMUX_CLKCMU_TNR_ALIGN_USERCLKCMU_MCSC_NOCCLKCMU_YUVP_NOCCLKCMU_MISC_SCCLKCMU_CPUCL0_BCI_SWITCHDIV_CLK_HSI2_NOCPDIV_CLK_MFC_NOCPDIV_CLK_NOCL1B_NOCP_LHDIV_CLK_NOCL2AB_NOCP_LHDIV_CLK_PERIC0_USI2_USIDIV_CLK_PERIC1_NOCP_LHDIV_CLK_YUVP_NOCPCLK_BLK_APM_UID_MAILBOX_AP_AURCORE2_IPCLKPORT_PCLKCLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_ACLKGATE_CLKCMU_MCSC_NOCGATE_CLKCMU_HSI2_MMCCARDGOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLKCLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_LH_AXI_MI_LP_CPUCL0_HSI1_CD_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLKGATE_CLK_CLUSTER0_COMPLEX0CLKCLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_NRESET_IPCLKPORT_CLKCLK_BLK_CPUCL2_UID_ADD2_APBIF_CPUCL2_IPCLKPORT_PCLKCLK_BLK_DPUF0_UID_RSTNSYNC_SR_CLK_DPUF0_NOCD_IPCLKPORT_CLKGOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_PCLKCLK_BLK_EH_UID_QE_EH_IPCLKPORT_PCLKGOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_ACLKCLK_BLK_G3D_UID_PPCFW_G3D0_IPCLKPORT_ACLKGOUT_BLK_GDC_UID_LH_AST_MI_ID_GDC1_GDC0_IPCLKPORT_I_CLKGOUT_BLK_GDC_UID_LH_AST_MI_ID_GDC1_LME_IPCLKPORT_I_CLKGOUT_BLK_GDC_UID_QE_D2_GDC0_IPCLKPORT_PCLKCLK_BLK_GDC_UID_SSMT_D2_GDC1_IPCLKPORT_PCLKCLK_BLK_GDC_UID_AD_APB_LME_IPCLKPORT_PCLKMCLK_BLK_GDC_UID_SSMT_D4_GDC1_IPCLKPORT_ACLKGOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_PCLKGOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_PCLKGOUT_BLK_GSACORE_UID_PUF_GSACORE_IPCLKPORT_I_CLKGOUT_BLK_GSACORE_UID_XIU_DP0_GSA_ZM_IPCLKPORT_ACLKCLK_BLK_GSACORE_UID_GIC_GSACORE_IPCLKPORT_GICCLKCLK_BLK_GSACORE_UID_PPMU_GSACORE1_IPCLKPORT_PCLKGOUT_BLK_GSACTRL_UID_TIMER_GSACTRL_IPCLKPORT_PCLKCLK_BLK_GSACTRL_UID_LH_AXI_SI_P_GSA_CU_IPCLKPORT_I_CLKGOUT_BLK_GSE_UID_PPMU_D2_GSE_IPCLKPORT_ACLKGOUT_BLK_HSI0_UID_PPMU_HSI0_IPCLKPORT_PCLKGOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLKGOUT_BLK_HSI0_UID_SSMT_HSI0_IPCLKPORT_PCLKGOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLKCLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_NOC_IPCLKPORT_CLKCLK_BLK_HSI0_UID_I3C2_HSI0_IPCLKPORT_I_PCLKGOUT_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLKGOUT_BLK_HSI1_UID_PCIE_GEN3_0_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UGGOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_PCLKGOUT_BLK_HSI2_UID_PCIE_GEN3A_1_IPCLKPORT_PCIE_QUADRA_G3X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UGGOUT_BLK_ISPFE_UID_GPC_ISPFE_IPCLKPORT_PCLKGOUT_BLK_ISPFE_UID_PPMU_D1_ISPFE_IPCLKPORT_PCLKCLK_BLK_ISPFE_UID_RSTNSYNC_CLK_ISPFE_OSCCLK_IPCLKPORT_CLKCLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_ACLKGOUT_BLK_MFC_UID_LH_AXI_SI_D0_MFC_IPCLKPORT_I_CLKGOUT_BLK_MFC_UID_SYSMMU_S0_PMMU0_MFC_IPCLKPORT_CLKGOUT_BLK_MIF_UID_AXI2APB_P_MIF_IPCLKPORT_ACLKCLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLKCLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLKCLK_BLK_MISC_UID_LH_AXI_SI_P_MISC_GIC_CU_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_SLH_AXI_SI_P_ALIVE_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MISC_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_DCLKCLK_BLK_NOCL0_UID_LD_SLC2_FRC_OTP_DESERIAL_IPCLKPORT_I_CLKGOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLKGOUT_BLK_NOCL1A_UID_PPC_TPU_D0_CYCLE_IPCLKPORT_ACLKCLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_LH_IPCLKPORT_CLKCLK_BLK_NOCL1A_UID_PPC_NOCL2AB_S0_CYCLE_IPCLKPORT_ACLKCLK_BLK_NOCL1A_UID_PPC_BW_D_EVENT_IPCLKPORT_PCLKCLK_BLK_NOCL1B_UID_BLK_NOCL1B_FRC_OTP_DESERIAL_IPCLKPORT_I_CLKCLK_BLK_NOCL2AA_UID_RSTNSYNC_SR_CLK_NOCL2AA_NOCP_IPCLKPORT_CLKCLK_BLK_NOCL2AB_UID_LH_AST_SI_G_NOCL2AB_CD_IPCLKPORT_I_CLKCLK_BLK_NOCL2AB_UID_LH_AXI_MI_D5_TNR_IPCLKPORT_I_CLKCLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_IPCLKCLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_SCLKCLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_PCLKCLK_BLK_RGBP_UID_PPMU_D3_MCFP_IPCLKPORT_PCLKCLK_BLK_RGBP_UID_SYSMMU_S0_PMMU0_RGBP_IPCLKPORT_CLKCLK_BLK_RGBP_UID_LH_AXI_SI_D3_RGBP_IPCLKPORT_I_CLKCLK_BLK_RGBP_UID_QE_D1_RGBP_IPCLKPORT_PCLKCLK_BLK_RGBP_UID_QE_D7_MCFP_IPCLKPORT_ACLKCLK_BLK_RGBP_UID_QE_D9_MCFP_IPCLKPORT_PCLKGOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_PCLKGOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_ACLKCLK_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_ACLKCLK_BLK_TNR_UID_QE_D4_TNR_IPCLKPORT_PCLKGOUT_BLK_TPU_UID_SYSMMU_S0_PMMU0_TPU_IPCLKPORT_CLKI_CLK_HSI1_ALTOSCCLK_FRC_NOCL1BLH_ATB_MI_LT_AOC_CD_QCHSSMT_AOC_QCHAPBIF_INTCOMB_VGPIO2AP_QCHLH_AXI_MI_LP_AOC_ALIVE_CU_QCHMAILBOX_APM_AUR_QCHMAILBOX_AP_AURMCUNS3_QCHSYSREG_APM_CUSTOM_QCHBW_QCHLH_AXI_SI_D_BW_QCHLH_ATB_MI_LT_GSA_CPUCL0_CU_QCHLH_AXI_SI_LP_CPUCL0_HSI1_CD_QCHCMU_CPUCL1_SHORTSTOP_QCHLH_AXI_SI_LD0_DPUF1_DPUF0_QCHLH_AST_MI_ID_JPEG_G2D1_QCHLH_AST_SI_ID_G2D0_JPEG_QCHLH_AXI_SI_D0_G2D_QCHDAP_GSACTRL_QCHGPC_HSI0_QCHPCIE_GEN3_0_QCH_DBISSMT_PCIE_IA_GEN3A_1_QCHSLH_AXI_MI_P_ISPFE_QCHSSMT_D1_ISPFE_QCHSMC_QCHSYSMMU_S0_PMMU0_MISC_QCHLH_ACEL_SI_D1_NOCL0_CPUCL0_QCHLH_TAXI_MI_D2_NOCL1A_NOCL0_QCHLH_TAXI_MI_P_NOCL0_NOCL1A_QCHLH_TAXI_SI_D1_NOCL1A_NOCL0_QCHPPC_NOCL2AA_S0_EVENT_QCHPPC_TPU_D1_EVENT_QCHLH_AXI_MI_D_GSA_QCHSLH_AXI_MI_G_CSSYS_QCHSLH_AXI_SI_P_TNR_QCHI3C4_QCH_SCLKUSI6_USI_QCHUSI0_USI_QCHQE_D4_MCFP_QCHQE_D7_MCFP_QCHQE_D8_MCFP_QCHSSMT_D0_MCFP_QCHQE_D4_TNR_QCHSYSMMU_S1_PMMU0_TNR_QCH_S0TNR_CMU_TNR_QCHLH_AST_SI_L_OTF_YUVP_MCSC_QCHCTRL_OPTION_EMBEDDED_CMU_G3DCTRL_OPTION_CMU_MISCCTRL_OPTION_EMBEDDED_CMU_NOCL03VCLK_MUX_CPUCL2_CMUREFVCLK_BLK_GSACTRLVCLK_BLK_HSI0VCLK_IP_LH_AXI_SI_D_ALIVEVCLK_IP_MAILBOX_AP_AURMCUNS2VCLK_IP_LH_ACEL_SI_D1_AURVCLK_IP_SYSMMU_S0_BWVCLK_IP_LH_ATB_MI_T_BDU_CUVCLK_IP_LH_ATB_SI_T_SLC_CUVCLK_IP_LH_AXI_SI_IP_BOOKERVCLK_IP_SLH_AXI_MI_P_DPUBVCLK_IP_D_TZPC_EHVCLK_IP_LH_AXI_SI_P_EH_CUVCLK_IP_LH_AXI_SI_IP_EHVCLK_IP_GRAY2BIN_G3DVCLK_IP_LH_ATB_SI_LT_G3D_CPUCL0VCLK_IP_QE_D4_GDC1VCLK_IP_SPI_GSC_GSACOREVCLK_IP_MAILBOX_GSA2AOCVCLK_IP_PMU_GSAVCLK_IP_AD_APB_GSEVCLK_IP_LH_AXI_SI_D_GSEVCLK_IP_LH_AXI_SI_P_HSI0_CUVCLK_IP_AD_APB_EUSBPHY_HSI0VCLK_IP_UASC_PCIE_GEN3A_DBI_0VCLK_IP_LH_AXI_MI_LP_CPUCL0_HSI1_CUVCLK_IP_UASC_PCIE_GEN3A_SLV_1VCLK_IP_GPIO_HSI2UFSVCLK_IP_D_TZPC_MCSCVCLK_IP_PPMU_D1_MCSCVCLK_IP_AXI2APB_P_MIFVCLK_IP_QE_SCVCLK_IP_SSMT_SPDMA0VCLK_IP_BLK_MISC_FRC_OTP_DESERIALVCLK_IP_LH_AXI_SI_P_MIF1_CDVCLK_IP_PPC_AUR_D0_CYCLEVCLK_IP_LH_AXI_MI_P_G3D_CDVCLK_IP_PPMU_NOCL1A_M0VCLK_IP_PPMU_NOCL2AA_M1VCLK_IP_LH_ACEL_MI_D_MISCVCLK_IP_LH_AXI_MI_D2_GDCVCLK_IP_I3C2VCLK_IP_D_TZPC_PERIC1VCLK_IP_SYSMMU_S0_PMMU1_RGBPVCLK_IP_LH_AXI_SI_LG_SCAN2DRAM_CUVCLK_IP_LH_ACEL_SI_D0_TPUG3DL2exynos_acpm_set_volt_marginGATE3%s:[%x]type : %x 3recalc_rate overflow id:%x %s %s: there is no sequence element for entering mode(%d).3%s %s: error on PA2VA conversion. seq:off, pd_id:%d. aborting init... 3%s there is no sequence element for core(%d) power-on. CLK_CON_MUX_MUX_CLK_G3D_TOPPLL_CON0_MUX_CLKCMU_G3D_GLB_USERQCH_CON_LH_AXI_MI_P_G3D_CU_QCHDPUF1_STATUSQCH_CON_PPMU_D0_DPUF1_QCHQCH_CON_SYSMMU_S0_PMMU1_G2D_QCHDBG_NFO_QCH_CON_JPEG_QCHDBG_NFO_QCH_CON_LH_AXI_SI_D2_GDC_QCHGSE_STATUSDBG_NFO_QCH_CON_SYSMMU_S0_PMMU0_GSE_QCH_S0DBG_NFO_QCH_CON_SLH_AXI_MI_P_MCSC_QCHDBG_NFO_QCH_CON_SSMT_D2_MCSC_QCHDBG_NFO_QCH_CON_SYSREG_MCSC_QCHPLL_CON0_MUX_CLKCMU_RGBP_RGBP_USERDBG_NFO_QCH_CON_LH_AXI_SI_LD_RGBP_GDC_QCHPLL_CON0_MUX_CLKCMU_TNR_MERGE_USERQCH_CON_PPMU_D3_TNR_QCHDBG_NFO_QCH_CON_PPMU_D7_TNR_QCHDBG_NFO_QCH_CON_YUVP_QCHDBG_NFO_QCH_CON_LH_AXI_SI_P_AUR_CU_QCHDBG_NFO_QCH_CON_UASC_P0_AUR_QCHQCH_CON_PPC_EH_EVENT_QCHDBG_NFO_QCH_CON_LH_ACEL_SI_LD_EH_CPUCL0_QCHQCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4QCH_CON_QE_D3_ISPFE_QCHDBG_NFO_QCH_CON_ISPFE_QCH_ISPFEDBG_NFO_QCH_CON_SYSMMU_S0_PMMU1_ISPFE_QCH_S0DBG_NFO_QCH_CON_SYSMMU_S2_PMMU0_ISPFE_QCH_S0QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CD_QCHDBG_NFO_QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CD_QCHCLK_CON_DIV_DIV_CLK_NOCL0_NOCD_LHQCH_CON_LH_ACEL_MI_D0_CPUCL0_QCHQCH_CON_PPC_NOCL1A_M2_EVENT_QCHQCH_CON_SLH_AXI_SI_P_ALIVE_QCHDBG_NFO_QCH_CON_LH_AST_SI_G_NOCL2AB_CU_QCHDBG_NFO_QCH_CON_LH_AXI_MI_P_MIF0_CD_QCHDBG_NFO_QCH_CON_LH_TAXI_MI_D0_NOCL1A_NOCL0_QCHDMYQCH_CON_CMU_NOCL1A_CMUREF_QCHQCH_CON_LH_ACEL_MI_D0_G3D_QCHQCH_CON_SLH_AXI_SI_P_BW_QCHNOCL1B_STATUSQCH_CON_SYSREG_NOCL1B_QCHDBG_NFO_QCH_CON_NOCL1B_CMU_NOCL1B_QCHCLK_CON_DIV_DIV_CLK_NOCL2AA_NOCP_LHDMYQCH_CON_CMU_NOCL2AA_CMUREF_QCHQCH_CON_LH_AXI_MI_D0_MFC_QCHQCH_CON_SLH_AXI_SI_P_ISPFE_QCHDBG_NFO_QCH_CON_NOCL2AA_CMU_NOCL2AA_QCHQCH_CON_LH_AST_MI_G_NOCL2AB_CD_QCHCLK_CON_MUX_MUX_CLK_HSI0_USI3QCH_CON_USB32DRD_QCH_USBDPPHY_CTRLQCH_CON_GPIO_HSI1_QCHQCH_CON_LH_AXI_SI_LD_HSI1_AOC_QCHDBG_NFO_DMYQCH_CON_PCIE_GEN3_0_QCH_REFblkpwr_embedded_g3dblkpwr_dpuf0CPUCL0_CLKDIVSTEP_CONSYSTEM_CTRLCLK_CON_DIV_DIV_CLK_APM_USI1_UARTCLK_CON_DIV_DIV_CLK_PERIC1_USI10_USIPLL_CON0_MUX_CLKCMU_HSI2_NOC_USERDBG_NFO_QCH_CON_GPC_APM_CUSTOM_QCHDBG_NFO_QCH_CON_LH_AXI_SI_P_ALIVE_CU_QCHDBG_NFO_QCH_CON_RSTNSYNC_CLK_APM_GREBE_DBGCORE_QCHDBG_NFO_QCH_CON_PPMU_MISC_QCHDBG_NFO_QCH_CON_SYSREG_MISC_QCHQCH_CON_PCIE_GEN3B_1_QCH_APBQCH_CON_SSMT_HSI2_QCHQCH_CON_I3C4_QCH_PCLKQCH_CON_LH_AXI_MI_P_PERIC0_CU_QCHQCH_CON_I3C0_QCH_PCLKDBG_NFO_QCH_CON_GPIO_PERIC1_QCHDBG_NFO_QCH_CON_USI11_USI_QCHHSI2_CMU_HSI2_CONTROLLER_OPTIONCPUCL0_HCHGEN_CLKMUX_CPU_SWMUX_CLKCMU_TPU_NOCMUX_CLK_HSI0_I3CMUX_CLKCMU_ISPFE_NOC_USERMUX_CLKCMU_PERIC0_USI6_USI_USERMUX_CLKCMU_PERIC0_I3C_USERMUX_CLK_TPU_NOC_LPMCLKCMU_BW_NOCCLKCMU_TPU_NOCCLKCMU_CPUCL2_SWITCHDIV_CLK_CPUCL0_PCLKDIV_CLK_DPUF0_NOCPDIV_CLK_EH_NOCP_LHDIV_CLK_MISC_GICDIV_CLK_NOCL2AA_NOCD_LHDIV_CLK_NOCL2AB_NOCPCLK_BLK_AOC_UID_LH_AXI_MI_LP_AOC_HSI0_CD_IPCLKPORT_I_CLKCLK_BLK_AOC_UID_SLH_AXI_SI_LP_AOC_ALIVE_IPCLKPORT_I_CLKGOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLKCLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLKCLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_OSCCLK_IPCLKPORT_CLKCLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_IPCLKPORT_I_CLKCLK_BLK_AUR_UID_RSTNSYNC_SR_CLK_AUR_NOCP_LH_IPCLKPORT_CLKCLK_BLK_AUR_UID_SSMT_P_AUR_IPCLKPORT_PCLKGOUT_BLK_BW_UID_AS_APB_SYSMMU_S0_BW_S2_IPCLKPORT_PCLKMGATE_CLKCMU_HSI2_PCIEGATE_CLKCMU_CIS_CLK1GATE_CLKCMU_NOCL1A_NOCGATE_CLKCMU_TPU_TPUCTLGATE_CLKCMU_HSI0_PERICLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLKCLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_LH_AXI_MI_LP_ALIVE_CPUCL0_CU_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CLUSTER0_ACLK_DBG_IPCLKPORT_CLKGOUT_BLK_DPUF0_UID_SYSREG_DPUF0_IPCLKPORT_PCLKGOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_ACLKGOUT_BLK_G2D_UID_SYSMMU_S0_PMMU2_G2D_IPCLKPORT_CLKCLK_BLK_G2D_UID_BLK_G2D_FRC_OTP_DESERIAL_IPCLKPORT_I_CLKCLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_TRACECLK_BLK_G3D_UID_SSMT_G3D2_IPCLKPORT_ACLKCLK_BLK_G3D_UID_PPMU_G3D_D3_IPCLKPORT_PCLKGOUT_BLK_GDC_UID_SSMT_D0_GDC0_IPCLKPORT_PCLKGOUT_BLK_GDC_UID_SYSREG_GDC_IPCLKPORT_PCLKCLK_BLK_GDC_UID_SSMT_D4_GDC0_IPCLKPORT_ACLKGOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_PCLKGOUT_BLK_GSACTRL_UID_TZPC_GSACTRL_IPCLKPORT_PCLKCLK_BLK_GSE_UID_GSE_CMU_GSE_IPCLKPORT_PCLKGOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLKGATE_CLK_HSI0_I3CCLK_BLK_HSI1_UID_SLH_AXI_MI_LP_AOC_HSI1_IPCLKPORT_I_CLKGOUT_BLK_HSI2_UID_PCIE_GEN3A_1_IPCLKPORT_PCIE_QUADRA_G3X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UGGOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOCP_IPCLKPORT_CLKGOUT_BLK_ISPFE_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1GOUT_BLK_ISPFE_UID_PPMU_D0_ISPFE_IPCLKPORT_ACLKCLK_BLK_ISPFE_UID_UASC_ISPFE_IPCLKPORT_ACLKCLK_BLK_ISPFE_UID_BAAW_ISPFE_IPCLKPORT_I_PCLKCLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLKGOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLKGOUT_BLK_NOCL0_UID_SLC_CB_TOP_IPCLKPORT_I_ACLKGOUT_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLKGOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_CLKCLK_BLK_NOCL0_UID_LH_AXI_MI_P_ALIVE_CD_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2AB_IPCLKPORT_I_CLKGOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLKGOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLKGOUT_BLK_NOCL1A_UID_PPC_NOCL2AA_S0_EVENT_IPCLKPORT_PCLKGOUT_BLK_NOCL1A_UID_PPC_NOCL2AB_S1_EVENT_IPCLKPORT_ACLKCLK_BLK_NOCL1A_UID_LH_AXI_MI_P_G3D_CD_IPCLKPORT_I_CLKGOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLKCLK_BLK_NOCL1B_UID_PPMU_NOCL1B_M0_IPCLKPORT_ACLKGOUT_BLK_NOCL2AA_UID_LH_AXI_MI_D0_MFC_IPCLKPORT_I_CLKGOUT_BLK_NOCL2AA_UID_LH_AXI_MI_D3_ISPFE_IPCLKPORT_I_CLKGOUT_BLK_NOCL2AA_UID_LH_AXI_MI_D0_RGBP_IPCLKPORT_I_CLKGOUT_BLK_NOCL2AA_UID_LH_AXI_MI_D2_ISPFE_IPCLKPORT_I_CLKGOUT_BLK_NOCL2AA_UID_TREX_P_NOCL2AA_IPCLKPORT_ACLK_P_NOCL2AACLK_BLK_NOCL2AB_UID_TREX_D_NOCL2AB_IPCLKPORT_ACLKCLK_BLK_NOCL2AB_UID_LH_AXI_MI_D_YUVP_IPCLKPORT_I_CLKGOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLKCLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_PCLKCLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLKCLK_BLK_RGBP_UID_RSTNSYNC_SR_CLK_RGBP_MCFP_IPCLKPORT_CLKGOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_ACLKCLK_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_ACLKCLK_BLK_TNR_UID_SSMT_D9_TNR_IPCLKPORT_ACLKCLK_BLK_TNR_UID_AD_APB_GTNR_ALIGN_IPCLKPORT_PCLKMGOUT_BLK_TPU_UID_PPMU_D0_TPU_IPCLKPORT_ACLKCLK_BLK_TPU_UID_RSTNSYNC_SR_CLK_TPU_TPUCTL_IPCLKPORT_CLKPLL_ALV_DIV16_APMPAD_CLK_GSAPLL_ALV_DIV16GREBEINTEGRATION_QCH_GREBEGREBEINTEGRATION_QCH_DBGLH_AXI_MI_IG_SWD_QCHMAILBOX_TPU_AURMCU_QCHSLH_AXI_SI_LG_SCAN2DRAM_QCHSSMT_LP_ALIVE_CPUCL0_QCHCLUSTER0_QCH_PCLKLH_ACEL_MI_D1_NOCL0_CPUCL0_QCHLH_AST_SI_L_ICC_CLUSTER0_GIC_CD_QCHLH_AXI_MI_LD0_DPUF1_DPUF0_QCHDPUF1_QCH_SRAMCSSMT_EH_QCHG2D_QCHGPU_QCHPPMU_D_LME_QCHDMA_GSACORE_QCHGPIO_GSACORE3_QCHSPI_GSC_GSACORE_QCHUSB32DRD_QCH_SUBCTLUSB32DRD_QCH_REFUSI0_HSI0_QCHPPMU_HSI2_QCHUASC_ISPFE_QCHPPMU_D3_MCSC_QCHQCH_ADAPTER_DDRPHY_QCHLH_AXI_SI_ID_SC_QCHCMU_NOCL0_CMUREF_QCHLH_AXI_MI_P_CPUCL0_NOCL0_QCHLH_AXI_SI_P_ALIVE_CD_QCHPPC_NOCL1A_M2_EVENT_QCHSLH_AXI_SI_P_MISC_QCHLH_TAXI_SI_D0_NOCL2AA_NOCL1A_QCHSLH_AXI_SI_P_DPUF0_QCHLH_AXI_MI_D1_G2D_QCHI3C1_QCH_SCLKUSI12_USI_QCHLH_AXI_SI_D2_RGBP_QCHSSMT_D9_TNR_QCHLH_AST_MI_L_OTF_RGBP_YUVP_QCHVCLK_VDD_CAMVCLK_MUX_NOCL1B_CMUREFVCLK_CLKCMU_HSI0_DPGTCVCLK_MUX_CLKCMU_CIS_CLK3VCLK_IP_ROM_CRC32_HOSTVCLK_IP_ADD_AURVCLK_IP_SSMT_CPUCL0VCLK_IP_LH_AXI_MI_LP_CPUCL0_HSI1_CDVCLK_IP_LH_AXI_SI_LP_CPUCL0_HSI1_CDVCLK_IP_LH_AXI_SI_IG_BOOKERVCLK_IP_LH_AXI_MI_IG_BOOKERVCLK_IP_PPMU_D1_DPUF0VCLK_IP_PPC_EH_EVENTVCLK_IP_PPMU_G3D_D2VCLK_IP_PPMU_D0_GDC1VCLK_IP_LMEVCLK_IP_PPMU_GSACORE1VCLK_IP_MAILBOX_GSA2TPUVCLK_IP_SYSREG_GSACTRLEXTVCLK_IP_SLH_AXI_MI_P_GSAVCLK_IP_LH_ACEL_SI_D_HSI0VCLK_IP_QE_MMC_CARD_HSI2VCLK_IP_LH_AXI_SI_D1_ISPFEVCLK_IP_XIU_D2_ISPFEVCLK_IP_SSMT_D2_MCSCVCLK_IP_AS_APB_MFCVCLK_IP_WDT_CLUSTER0VCLK_IP_RTICVCLK_IP_XIU_D0_MISCVCLK_IP_LH_AST_MI_L_ICC_CLUSTER0_GICVCLK_IP_PPC_CPUCL0_D3_EVENTVCLK_IP_PPMU_NOCL0_IOC0VCLK_IP_LH_AXI_MI_P_EH_CDVCLK_IP_LH_ACEL_MI_D0_CPUCL0VCLK_IP_SYSREG_NOCL1AVCLK_IP_PPC_AOC_EVENTVCLK_IP_LH_ACEL_MI_D_HSI2VCLK_IP_SLH_AXI_SI_P_DPUF1VCLK_IP_PERIC0_CMU_PERIC0VCLK_IP_SYSREG_PERIC1VCLK_IP_PPMU_D2_MCFPVCLK_IP_QE_D10_MCFPVCLK_IP_PPMU_D1_TNRVCLK_IP_SSMT_D1_TNRVCLK_IP_SSMT_D2_TNRVCLK_IP_PPMU_D4_TNRVCLK_IP_LH_AXI_SI_D5_TNRVCLK_IP_TPUVCLK_IP_SYSMMU_S0_TPUVCLK_IP_SSMT_D1_YUVPmargin_g3d_write_fileexynos-cal-ifMUXra_set_qch3%s:[%x]type : %x, params : %x 3%s %s: error on PA2VA conversion. seq:exit, mode_id:%d. aborting init... 3%s %s: error on handling enable sequence. (cluster : %d) PLL_CON8_PLL_G3DDBG_NFO_QCH_CON_LH_ACEL_SI_D1_G3D_QCHQCH_CON_LH_AXI_SI_D0_DPUF0_QCHQCH_CON_DPUF1_QCH_SRAMCQCH_CON_GPC_DPUF1_QCHDBG_NFO_QCH_CON_SLH_AXI_MI_P_DPUF1_QCHDBG_NFO_QCH_CON_SSMT_D2_GDC0_QCHDBG_NFO_QCH_CON_SSMT_D4_GDC0_QCHQCH_CON_GSE_CMU_GSE_QCHQCH_CON_D_TZPC_MCSC_QCHQCH_CON_MCSC_QCH_C2RQCH_CON_QE_D6_MCSC_QCHQCH_CON_SSMT_D2_MCSC_QCHDBG_NFO_QCH_CON_QE_D2_MCSC_QCHDBG_NFO_QCH_CON_QE_D4_MCSC_QCHQCH_CON_LH_AXI_SI_D6_RGBP_QCHDBG_NFO_QCH_CON_SYSMMU_S0_PMMU0_RGBP_QCH_S0DBG_NFO_QCH_CON_SYSMMU_S1_PMMU1_RGBP_QCH_S0QCH_CON_QE_D0_TNR_QCHQCH_CON_SSMT_D1_TNR_QCHCLK_CON_DIV_DIV_CLK_YUVP_NOCPDBG_NFO_QCH_CON_GPC_BW_QCHDBG_NFO_QCH_CON_LH_AXI_SI_D_BW_QCHCLK_CON_DIV_DIV_CLK_EH_NOCP_LHQCH_CON_LH_AXI_MI_P_EH_CU_QCHQCH_CON_SLH_AXI_MI_P_ISPFE_QCHQCH_CON_SYSMMU_S0_PMMU1_ISPFE_QCH_S0DBG_NFO_QCH_CON_LH_AXI_SI_D0_ISPFE_QCHDBG_NFO_QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4DBG_NFO_QCH_CON_SSMT_D0_ISPFE_QCHDBG_NFO_QCH_CON_SSMT_D0_TPU_QCHPLL_LOCKTIME_PLL_NOCL0QCH_CON_LH_AST_MI_G_NOCL2AA_QCHQCH_CON_LH_AXI_MI_P_MIF3_CD_QCHQCH_CON_LH_AXI_SI_P_PERIC1_CD_QCHDBG_NFO_QCH_CON_PPMU_NOCL0_S3_QCHNOCL0_HCHGEN_CLKMUX_CMUREFQCH_CON_PPC_NOCL2AA_S1_EVENT_QCHDBG_NFO_QCH_CON_LH_TAXI_SI_D1_NOCL1A_NOCL0_QCHNOCL1B_CONFIGURATIONDBG_NFO_QCH_CON_LH_AXI_SI_P_HSI0_CD_QCHQCH_CON_LH_ACEL_MI_D_HSI2_QCHQCH_CON_LH_TAXI_SI_D1_NOCL2AB_NOCL1A_QCHDBG_NFO_QCH_CON_LH_AXI_MI_D1_G2D_QCHDBG_NFO_QCH_CON_LH_AXI_MI_D3_TNR_QCHDBG_NFO_QCH_CON_LH_TAXI_SI_D1_NOCL2AB_NOCL1A_QCHCLK_CON_MUX_MUX_CLK_HSI0_USB20_REFCLK_CON_MUX_MUX_CLK_HSI0_USI2PLL_CON0_MUX_CLKCMU_HSI0_ALT_USERPLL_CON0_PLL_USBDBG_NFO_QCH_CON_LH_AXI_MI_LP_AOC_HSI0_CU_QCHDBG_NFO_QCH_CON_HSI1_CMU_HSI1_QCHDBG_NFO_QCH_CON_PPMU_HSI1_QCHCPUCL1_CLKDIVSTEPEARLY_WAKEUP_DPU_CTRLPLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USERQCH_CON_GPC_APM_QCHQCH_CON_RTC_QCHDBG_NFO_QCH_CON_APBIF_PMU_ALIVE_QCHDBG_NFO_QCH_CON_LH_AXI_MI_LP_AOC_ALIVE_CU_QCHQCH_CON_PDMA0_QCHQCH_CON_SSMT_RTIC_QCHDBG_NFO_QCH_CON_MCT_SUB_QCHDBG_NFO_QCH_CON_QE_RTIC_QCHDBG_NFO_QCH_CON_SLH_AXI_MI_P_MISC_GIC_QCHDBG_NFO_QCH_CON_TMU_TOP_QCHQCH_CON_PCIE_GEN3A_1_QCH_AXIQCH_CON_PCIE_IA_GEN3B_1_QCHQCH_CON_SSMT_PCIE_IA_GEN3B_1_QCHQCH_CON_UFS_EMBD_QCH_FMPDBG_NFO_QCH_CON_QE_UFS_EMBD_HSI2_QCHDBG_NFO_QCH_CON_I3C1_QCH_PCLKDBG_NFO_QCH_CON_USI5_USI_QCHDBG_NFO_QCH_CON_USI6_USI_QCHPLL_LF_MIFMUX_CLKCMU_CPUCL0_DSU_SWITCHMUX_CLKCMU_CIS_CLK5MUX_CLKCMU_CPUCL2_SWITCHMUX_CPUCL1_CMUREFMUX_CLKCMU_G2D_G2D_USERMUX_CLK_G3DCORE_TOP_USERMUX_CLKCMU_HSI1_NOC_USERMUX_CLKCMU_HSI2_UFS_EMBD_USERMUX_CLKCMU_TNR_MERGE_USERCLKCMU_MFC_MFCCLKCMU_PERIC1_NOCCLKCMU_CIS_CLK0CLKCMU_GSE_NOCDIV_CLK_HSI0_USB32DRDDIV_CLK_PERIC0_USI5_USIDIV_CLK_PERIC0_USI1_USIDIV_CLK_PERIC1_USI9_USICLK_BLK_AOC_UID_LH_ATB_MI_LT_AOC_CD_IPCLKPORT_I_CLKCLK_BLK_APM_UID_SLH_AXI_MI_LP_AOC_ALIVE_IPCLKPORT_I_CLKCLK_BLK_AUR_UID_UASC_P1_AUR_IPCLKPORT_ACLKCLK_BLK_BW_UID_RSTNSYNC_SR_CLK_BW_NOCD_IPCLKPORT_CLKGATE_CLKCMU_NOCL0_NOCGATE_CLKCMU_CIS_CLK2GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_PCLKGOUT_BLK_CPUCL0_UID_S2MPU_S0_CPUCL0_IPCLKPORT_CLKCLK_BLK_CPUCL0_UID_LH_AXI_SI_LP_CPUCL0_HSI1_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_LH_AXI_SI_LP_CPUCL0_HSI2_IPCLKPORT_I_CLKCLK_BLK_CPUCL1_UID_LH_AXI_MI_IP_CPUCL1_IPCLKPORT_I_CLKCLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_PCLK_IPCLKPORT_CLKCLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM1GOUT_BLK_DPUF0_UID_SLH_AXI_MI_P_DPUF0_IPCLKPORT_I_CLKGOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_NOCD_IPCLKPORT_CLKCLK_BLK_DPUF1_UID_SSMT_D1_DPUF1_IPCLKPORT_ACLKCLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLKCLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_LH_IPCLKPORT_CLKCLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_NOCP_LH_IPCLKPORT_CLKCLK_BLK_G3D_UID_SYSMMU_S0_PMMU1_G3D_IPCLKPORT_CLKCLK_BLK_GDC_UID_PPMU_D2_GDC0_IPCLKPORT_ACLKCLK_BLK_GDC_UID_PPMU_D_LME_IPCLKPORT_ACLKCLK_BLK_GDC_UID_LME_IPCLKPORT_CLKGOUT_BLK_GSACORE_UID_CA32_GSACORE_IPCLKPORT_CLKINGOUT_BLK_GSACORE_UID_OTP_CON_GSACORE_IPCLKPORT_PCLKGOUT_BLK_GSACTRL_UID_LH_AXI_MI_P_GSA_CU_IPCLKPORT_I_CLKCLK_BLK_GSACTRL_UID_LH_AXI_SI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLKCLK_BLK_GSACTRL_UID_XIU_D1_GSA_ZM_IPCLKPORT_ACLKCLK_BLK_GSACTRL_UID_SYSMMU_S0_GSA_ZM_IPCLKPORT_CLKGATE_CLK_GSACTRL2CORE_PERIGOUT_BLK_GSE_UID_D_TZPC_GSE_IPCLKPORT_PCLKGOUT_BLK_GSE_UID_XIU_D0_GSE_IPCLKPORT_ACLKGOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLKGATE_CLK_HSI0_USI1CLK_BLK_HSI0_UID_BLK_HSI0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLKGOUT_BLK_HSI1_UID_PCIE_GEN3_0_IPCLKPORT_PCIE_PHY_TOP_INST_0_SF_PCIEPHY_X2_QCH_TM_WRAPPER_INST_0_I_APB_PCLKGOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLKCLK_BLK_HSI2_UID_PCIE_GEN3B_1_IPCLKPORT_PCIE_QUADRA_G3X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UGCLK_BLK_ISPFE_UID_PPMU_D3_ISPFE_IPCLKPORT_ACLKCLK_BLK_ISPFE_UID_LH_AXI_SI_IP_ISPFE_IPCLKPORT_I_CLKCLK_BLK_ISPFE_UID_AD_APB_MIPI_PHY_IPCLKPORT_PCLKMCLK_BLK_MCSC_UID_SYSMMU_S0_PMMU0_MCSC_IPCLKPORT_CLKCLK_BLK_MCSC_UID_XIU_D0_MCSC_IPCLKPORT_ACLKGOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_IPCLKPORT_CLKGOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_ACLKGOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_ACLKGOUT_BLK_NOCL0_UID_PPC_CPUCL0_D3_EVENT_IPCLKPORT_ACLKCLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF0_CD_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF1_CD_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_LH_ACEL_MI_D2_CPUCL0_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_PPMU_NOCL0_S0_IPCLKPORT_PCLKGOUT_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLKCLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_AUR_IPCLKPORT_I_CLKCLK_BLK_NOCL1A_UID_LH_AXI_SI_P_TPU_CD_IPCLKPORT_I_CLKCLK_BLK_NOCL1A_UID_PPC_TPU_D1_EVENT_IPCLKPORT_PCLKGOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_PCLKCLK_BLK_NOCL1B_UID_LH_AXI_MI_P_AOC_CD_IPCLKPORT_I_CLKGOUT_BLK_NOCL2AA_UID_RSTNSYNC_CLK_NOCL2AA_NOCD_IPCLKPORT_CLKGOUT_BLK_NOCL2AA_UID_LH_AXI_MI_D5_RGBP_IPCLKPORT_I_CLKGOUT_BLK_NOCL2AA_UID_LH_AXI_MI_D1_RGBP_IPCLKPORT_I_CLKCLK_BLK_NOCL2AB_UID_GPC_NOCL2AB_IPCLKPORT_PCLKCLK_BLK_NOCL2AB_UID_BLK_NOCL2AB_FRC_OTP_DESERIAL_IPCLKPORT_I_CLKCLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLKGOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLKGOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLKCLK_BLK_RGBP_UID_PPMU_D5_MCFP_IPCLKPORT_ACLKCLK_BLK_RGBP_UID_LH_AXI_SI_D4_RGBP_IPCLKPORT_I_CLKCLK_BLK_RGBP_UID_QE_D8_MCFP_IPCLKPORT_PCLKCLK_BLK_RGBP_UID_RSTNSYNC_SR_CLK_RGBP_RGBP_IPCLKPORT_CLKGOUT_BLK_TNR_UID_SYSMMU_S0_PMMU0_TNR_IPCLKPORT_CLKGOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_ACLKCLK_BLK_TNR_UID_RSTNSYNC_SR_CLK_TNR_NOCP_IPCLKPORT_CLKCLK_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_ACLKCLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLKCLK_BLK_TNR_UID_QE_D11_TNRA_IPCLKPORT_ACLKCLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF0OSCCLK_APMOSCCLK_CMUOSCCLK_MFCSYSMMU_S0_AOC_QCH_S0APBIF_PMU_ALIVE_QCHADD_APBIF_AUR_QCHD_TZPC_BW_QCHLH_ACEL_MI_LD_EH_CPUCL0_QCHLH_AST_MI_L_ICC_CLUSTER0_GIC_CD_QCHSYSMMU_S0_PMMU2_G2D_QCHLH_AST_MI_ID_GDC0_GDC1_QCHSSMT_D4_GDC1_QCHOTP_CON_GSACORE_QCHSPI_FPS_GSACORE_QCHGSACTRL_CMU_GSACTRL_QCHINTMEM_GSACTRL_QCHPPMU_D0_GSE_QCHDP_LINK_QCH_PCLKLH_AXI_SI_LP_CPUCL0_HSI1_CU_QCHPPMU_HSI1_QCHQE_PCIE_GEN3B_HSI2_QCHISPFE_CMU_ISPFE_QCHMIPI_PHY_LINK_WRAP_QCH_CSIS10LH_ACEL_SI_D_MISC_QCHLH_AST_SI_L_IRI_GIC_CLUSTER0_CD_QCHOTP_CON_BISR_QCHLH_AST_MI_G_NOCL1B_CU_QCHLH_AST_MI_G_NOCL2AB_QCHLH_AXI_MI_P_MISC_CD_QCHLH_TAXI_MI_D0_NOCL1A_NOCL0_QCHPPC_NOCL1A_M1_EVENT_QCHSLH_AXI_SI_P_PERIC1_QCHSYSREG_NOCL0_QCHLH_TAXI_MI_D1_NOCL2AA_NOCL1A_QCHSLH_AXI_MI_D_G3DMMU_QCHSLH_AXI_SI_P_AUR_QCHSYSREG_NOCL1A_QCHLH_AXI_MI_G_CSSYS_CU_QCHPPMU_NOCL2AA_M0_QCHLH_TAXI_MI_P_NOCL0_NOCL2AB_QCHSYSREG_NOCL2AB_QCHPERIC0_CMU_PERIC0_QCHD_TZPC_PERIC1_QCHQE_D4_RGBP_QCHSSMT_D2_RGBP_QCHSSMT_D3_MCFP_QCHD_TZPC_TNR_QCHSYSREG_YUVP_QCHCTRL_OPTION_CMU_CPUCL1CTRL_OPTION_CMU_GSACTRLVCLK_DIV_CLK_CPUCL1_CMUREFVCLK_CLK_G3D_ADD_CH_CLKVCLK_DIV_CLK_PERIC1_USI10_USIVCLK_IP_SYSMMU_S0_PMMU_AOCVCLK_IP_SLH_AXI_MI_LG_ALIVE_AOCVCLK_IP_LH_AXI_SI_LP_AOC_HSI1_CDVCLK_IP_INTMEMVCLK_IP_XIU_D_ALIVEVCLK_IP_SYSMMU_S0_AURVCLK_IP_LH_AST_SI_L_IRI_GIC_CLUSTER0_CUVCLK_IP_D_TZPC_DPUBVCLK_IP_SYSMMU_S0_PMMU1_DPUF0VCLK_IP_LH_AST_MI_ID_G2D1_JPEGVCLK_IP_LH_ACEL_SI_D0_G3DVCLK_IP_LH_ACEL_SI_D3_G3DVCLK_IP_SSMT_G3D2VCLK_IP_GPC_GDCVCLK_IP_LH_AST_MI_ID_GDC0_GDC1VCLK_IP_LH_AST_MI_ID_GDC1_LMEVCLK_IP_KDN_GSACOREVCLK_IP_QE_DMA_GSACOREVCLK_IP_LH_ATB_SI_LT_GSA_CPUCL0_CDVCLK_IP_APBIF_GPIO_GSACTRLVCLK_IP_AXI_US_128TO256_QE_D2_GSEVCLK_IP_PCIE_IA_GEN3A_0VCLK_IP_GPC_HSI2VCLK_IP_PPMU_D1_ISPFEVCLK_IP_XIU_D1_ISPFEVCLK_IP_SSMT_D3_MCSCVCLK_IP_PPMU_D0_MFCVCLK_IP_MIF_CMU_MIFVCLK_IP_QCH_ADAPTER_DDRPHYVCLK_IP_SSMT_PDMA1VCLK_IP_SYSMMU_S0_MISCVCLK_IP_MCT_SUBVCLK_IP_D_TZPC_NOCL0VCLK_IP_SFR_APBIF_CMU_TOPCVCLK_IP_SLH_AXI_MI_G_NOCL0VCLK_IP_SLH_AXI_SI_P_ALIVEVCLK_IP_LH_TAXI_MI_D0_NOCL1A_NOCL0VCLK_IP_LH_TAXI_SI_P_NOCL0_NOCL1AVCLK_IP_PPC_NOCL0_IO1_EVENTVCLK_IP_LH_ACEL_MI_D0_G3DVCLK_IP_PPC_G3D_D2_EVENTVCLK_IP_NOCL2AA_CMU_NOCL2AAVCLK_IP_SYSREG_NOCL2AAVCLK_IP_LH_AXI_MI_D1_MFCVCLK_IP_LH_AXI_MI_D0_RGBPVCLK_IP_LH_AXI_MI_P_PERIC0_CUVCLK_IP_USI1_USIVCLK_IP_USI14_USIVCLK_IP_LH_AXI_SI_D1_RGBPVCLK_IP_PPMU_D1_RGBPVCLK_IP_PPMU_D3_MCFPVCLK_IP_SSMT_D0_MCFPVCLK_IP_SSMT_D3_MCFPVCLK_IP_QE_D1_RGBPVCLK_IP_D_TZPC_YUVPVCLK_IP_LH_AST_SI_L_OTF_YUVP_GSEVCLK_IP_QE_D4_YUVPBWdvfs id : %d %d Khz : %d uv 3%s:cannot find qch [%x] 3time out, '%s' [%p]=%x [%p]=%x set_margin DMYQCH_CON_ADM_DAP_G_GPU_QCHQCH_CON_G3D_CMU_G3D_QCHDBG_NFO_QCH_CON_SLH_AXI_SI_D_G3DMMU_QCHQCH_CON_DPUF0_QCH_DPUFPLL_CON0_MUX_CLKCMU_DPUF1_NOC_USERQCH_CON_LH_AST_MI_ID_G2D0_JPEG_QCHQCH_CON_LH_AST_MI_ID_G2D1_JPEG_QCHQCH_CON_PPMU_D0_GDC0_QCHQCH_CON_PPMU_D4_GDC1_QCHQCH_CON_SYSMMU_S0_PMMU2_GDC_QCH_S0DBG_NFO_QCH_CON_LH_AST_SI_ID_GDC1_LME_QCHDBG_NFO_QCH_CON_PPMU_D1_GSE_QCHDBG_NFO_QCH_CON_QE_D1_GSE_QCHGSE_CMU_GSE_CONTROLLER_OPTIONQCH_CON_LH_AXI_SI_D1_MCSC_QCHQCH_CON_SSMT_D3_MCSC_QCHDBG_NFO_QCH_CON_D_TZPC_MCSC_QCHDBG_NFO_QCH_CON_PPMU_D3_MCSC_QCHQCH_CON_LH_AXI_SI_D1_MFC_QCHDBG_NFO_QCH_CON_SYSMMU_S0_MFC_QCHQCH_CON_QE_D10_MCFP_QCHQCH_CON_SYSMMU_S1_PMMU1_RGBP_QCH_S0DBG_NFO_QCH_CON_QE_D0_RGBP_QCHQCH_CON_D_TZPC_TNR_QCHQCH_CON_SSMT_D10_TNRA_QCHQCH_CON_SSMT_D4_TNR_QCHDBG_NFO_QCH_CON_PPMU_D6_TNR_QCHDBG_NFO_QCH_CON_QE_D0_TNR_QCHDBG_NFO_QCH_CON_SYSMMU_S1_PMMU0_TNR_QCH_S0QCH_CON_D_TZPC_AUR_QCHQCH_CON_SSMT_P_AUR_QCHDBG_NFO_QCH_CON_SSMT_P_AUR_QCHDBG_NFO_QCH_CON_LH_AXI_MI_IP_EH_QCHDBG_NFO_QCH_CON_PPMU_EH_QCHDBG_NFO_QCH_CON_SYSREG_EH_QCHPLL_CON6_PLL_TPUPLL_CON0_PLL_TPUPLL_CON1_PLL_TPUPLL_CON2_PLL_NOCL0QCH_CON_LH_AXI_MI_P_PERIC1_CD_QCHQCH_CON_LH_TAXI_SI_P_NOCL0_NOCL2AB_QCHQCH_CON_SLH_AXI_SI_P_EH_QCHQCH_CON_SLH_AXI_SI_P_MIF0_QCHQCH_CON_SLH_AXI_SI_P_MIF2_QCHDBG_NFO_QCH_CON_LH_ACEL_MI_D1_CPUCL0_QCHDBG_NFO_QCH_CON_LH_AST_MI_G_NOCL1A_QCHDBG_NFO_QCH_CON_TREX_P_NOCL0_QCHQCH_CON_LH_ACEL_MI_D1_TPU_QCHQCH_CON_LH_AXI_MI_P_G3D_CD_QCHQCH_CON_PPC_TPU_D0_EVENT_QCHQCH_CON_TREX_P_NOCL1A_QCHDBG_NFO_QCH_CON_LH_AST_MI_G_NOCL1A_CD_QCHDBG_NFO_QCH_CON_LH_AXI_SI_P_GSA_CD_QCHQCH_CON_LH_AXI_MI_D_GSE_QCHDBG_NFO_QCH_CON_SLH_AXI_SI_P_YUVP_QCHCPUCL2_CLKDIVSTEP_VDROOP_FLTGRP4_INTR_BID_CLEARCLK_CON_DIV_DIV_CLK_PERIC0_USI4_USIDMYQCH_CON_APM_I3C_PMIC_QCH_SQCH_CON_D_TZPC_APM_QCHQCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CD_QCHQCH_CON_MAILBOX_AP_AURMCUNS4_QCHDBG_NFO_QCH_CON_INTMEM_QCHDBG_NFO_QCH_CON_MAILBOX_AOC_AURCORE0_QCHDBG_NFO_QCH_CON_MAILBOX_AOC_AURCORE1_QCHDBG_NFO_QCH_CON_SLH_AXI_MI_P_ALIVE_QCHDBG_NFO_QCH_CON_SYSMMU_S0_ALIVE_QCHQCH_CON_DIT_QCHQCH_CON_LH_AXI_SI_P_MISC_CU_QCHQCH_CON_GPIO_HSI2UFS_QCHDBG_NFO_QCH_CON_PCIE_IA_GEN3A_1_QCHQCH_CON_SYSREG_PERIC0_QCHDBG_NFO_QCH_CON_SYSREG_PERIC0_QCHQCH_CON_D_TZPC_PERIC1_QCHPERIC1_CMU_PERIC1_CONTROLLER_OPTIONMUX_CLKCMU_TNR_MERGEMUX_CLK_G3D_TOPMUX_CLKCMU_GSA_FUNCMUX_CLK_GSACTRL_NOCMUX_CLKCMU_DPUB_DSIM_USERMUX_CLKCMU_HSI1_PCIE_USERMUX_CLKCMU_MIF_NOCP_USERMUX_CLKCMU_PERIC1_USI9_USI_USERDIV_CLK_CMU_CMUREFDIV_CLK_NOCL0_NOCPDIV_CLK_PERIC1_USI11_USIGOUT_BLK_AOC_UID_LH_AXI_SI_D_AOC_IPCLKPORT_I_CLKCLK_BLK_AOC_UID_RSTNSYNC_SR_CLK_AOC_TRACE_IPCLKPORT_CLKCLK_BLK_APM_UID_MAILBOX_AP_AURCORE0_IPCLKPORT_PCLKCLK_BLK_APM_UID_MAILBOX_AOC_AURCORE1_IPCLKPORT_PCLKGOUT_BLK_BW_UID_SYSMMU_S0_PMMU0_BW_IPCLKPORT_CLKGOUT_BLK_BW_UID_RSTNSYNC_CLK_BW_NOCP_IPCLKPORT_CLKGATE_CLKCMU_HSI0_USBDPDBGGATE_CLKCMU_GDC_GDC1GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CLUSTER0_GICCLK_LH_IPCLKPORT_CLKCLK_BLK_CPUCL0_UID_LH_AXI_SI_P_CPUCL0_NOCL0_IPCLKPORT_I_CLKGATE_CLK_CLUSTER0_PERIPHCLKCLK_BLK_CPUCL0_UID_LH_ATB_SI_IT1_BOOKER_IPCLKPORT_I_CLKGOUT_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKMCLK_BLK_DPUF1_UID_SYSMMU_S0_DPUF1_IPCLKPORT_CLKCLK_BLK_G3D_UID_PPMU_G3D_D3_IPCLKPORT_ACLKGOUT_BLK_GDC_UID_SYSMMU_S0_PMMU2_GDC_IPCLKPORT_CLKGOUT_BLK_GSACORE_UID_DMA_GSACORE_IPCLKPORT_ACLKGOUT_BLK_GSACORE_UID_PPMU_GSACORE0_IPCLKPORT_ACLKCLK_BLK_GSACORE_UID_RSTNSYNC_CLK_CA32_CPUPORESET_IPCLKPORT_CLKCLK_BLK_GSACORE_UID_XIU_D0_GSA_ZM_IPCLKPORT_ACLKCLK_BLK_GSACORE_UID_RSTNSYNC_CLK_UGME_FULL_RESET_IPCLKPORT_CLKGOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AOC_IPCLKPORT_PCLKGOUT_BLK_GSE_UID_QE_D2_GSE_IPCLKPORT_ACLKGOUT_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_CTRL_PCLKGATE_CLK_HSI0_USI0GOUT_BLK_HSI1_UID_PCIE_GEN3_0_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UGGOUT_BLK_HSI2_UID_UASC_PCIE_GEN3A_SLV_1_IPCLKPORT_PCLKGOUT_BLK_ISPFE_UID_PPMU_D1_ISPFE_IPCLKPORT_ACLKCLK_BLK_ISPFE_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS8GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLKCLK_BLK_MCSC_UID_PPMU_D5_MCSC_IPCLKPORT_PCLKCLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC0_CD_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_LH_TAXI_SI_P_NOCL0_NOCL1B_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_ACLKCLK_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_ACLKCLK_BLK_NOCL1A_UID_LH_ACEL_MI_D1_TPU_IPCLKPORT_I_CLKCLK_BLK_NOCL1A_UID_PPMU_NOCL1A_M3_IPCLKPORT_PCLKGOUT_BLK_NOCL2AA_UID_D_TZPC_NOCL2AA_IPCLKPORT_PCLKCLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_NOCP_LH_IPCLKPORT_CLKCLK_BLK_RGBP_UID_LH_AXI_SI_LD_RGBP_GDC_IPCLKPORT_I_CLKCLK_BLK_RGBP_UID_SSMT_D1_RGBP_IPCLKPORT_PCLKCLK_BLK_RGBP_UID_RSTNSYNC_CLK_RGBP_RGBP_IPCLKPORT_CLKCLK_BLK_S2D_UID_LH_AXI_SI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLKGOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLKCLK_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_PCLKCLK_BLK_TPU_UID_SYSMMU_S0_PMMU1_TPU_IPCLKPORT_CLKOSCCLK_FRC_NOCL0D_TZPC_AOC_QCHLH_AXI_MI_LP_AOC_ALIVE_CD_QCHSLH_AXI_MI_LG_ALIVE_AOC_QCHMAILBOX_AP_AOCP6_QCHLH_AXI_SI_P_AUR_CU_QCHPPMU_D0_AUR_QCHSYSREG_AUR_QCHUASC_P1_AUR_QCHADD0_CPUCL0_QCH_CHCLUSTER0_QCH_ATCLKCLUSTER0_QCH_CORE1LH_AXI_SI_G_CSSYS_CD_QCHLH_AXI_SI_LP_CPUCL0_HSI1_QCHPPC_INSTRRUN_CLUSTER0_1_QCHDPUF0_QCH_DPUFLH_AXI_SI_LD1_DPUF1_DPUF0_QCHPPMU_D0_DPUF1_QCHUASC_EH_QCHSYSMMU_S0_PMMU1_G2D_QCHLH_ATB_SI_LT_G3D_CPUCL0_QCHLH_AXI_MI_P_G3D_CU_QCHLH_AXI_SI_IP_G3D_QCHLH_AST_MI_ID_GDC1_LME_QCHQE_D2_GDC0_QCHGPIO_GSACORE2_QCHRESETMON_GSACORE_QCHSYSMMU_S0_GSA_ZM_QCHPPMU_D1_GSE_QCHSYSMMU_S0_PMMU0_GSE_QCH_S0I3C2_HSI0_QCH_PCLKGPIO_HSI1_QCHPCIE_GEN3B_1_QCH_REFQE_D6_MCSC_QCHSYSREG_MCSC_QCHD_TZPC_MIF_QCHLH_ACEL_MI_D0_CPUCL0_QCHLH_AST_MI_G_NOCL1A_CU_QCHLH_AST_SI_G_NOCL2AA_CU_QCHPPMU_NOCL0_ALIVE_P_QCHPPMU_NOCL0_CPUCL0_P_QCHSLH_AXI_SI_P_PERIC0_QCHGPC_NOCL1A_QCHLH_ACEL_MI_D0_AUR_QCHLH_AXI_MI_D0_RGBP_QCHLH_AXI_SI_P_PERIC1_CU_QCHLH_AXI_SI_D3_RGBP_QCHPPMU_D0_MCFP_QCHPPMU_D2_RGBP_QCHRGBP_CMU_RGBP_QCHLH_AXI_SI_D3_TNR_QCHSYSMMU_S2_TNR_QCH_S0ADD_TPU_QCHGPC_YUVP_QCHCTRL_OPTION_CMU_TOPVCLK_DIV_CLK_PERIC1_USI13_USIVCLK_CLK_TPU_ADD_CH_CLKVCLK_IP_SYSMMU_S0_ALIVEVCLK_IP_LH_ATB_MI_LT_AUR_CPUCL0_CDVCLK_IP_LH_AXI_MI_IG_STMVCLK_IP_SLH_AXI_MI_P_CPUCL0VCLK_IP_LH_ATB_MI_LT1_TPU_CPUCL0VCLK_IP_APB_ASYNC_P_CSSYS_1VCLK_IP_LH_AXI_MI_LP_CPUCL0_HSI2_CDVCLK_IP_BPS_CPUCL0VCLK_IP_ADD1_APBIF_CPUCL1VCLK_IP_EH_CMU_EHVCLK_IP_EHVCLK_IP_D_TZPC_G3DVCLK_IP_LH_AXI_SI_P_G3D_CUVCLK_IP_TIMER_GSACTRLVCLK_IP_QE_D0_GSEVCLK_IP_QE_D2_GSEVCLK_IP_SYSMMU_S0_HSI1VCLK_IP_GPIO_HSI2VCLK_IP_XIU_D2_MCSCVCLK_IP_SSMT_D1_MFCVCLK_IP_SYSMMU_S0_MFCVCLK_IP_SLH_AXI_SI_P_EHVCLK_IP_LH_AXI_SI_P_PERIC0_CDVCLK_IP_PPC_NOCL2AA_S0_CYCLEVCLK_IP_LH_AXI_MI_P_TPU_CDVCLK_IP_LH_ACEL_MI_D1_TPUVCLK_IP_SLH_AXI_SI_P_HSI0VCLK_IP_USI0_UARTVCLK_IP_LH_AXI_MI_P_PERIC1_CUVCLK_IP_D_TZPC_RGBPVCLK_IP_PPMU_D5_MCFPVCLK_IP_SSMT_D1_RGBPVCLK_IP_SLH_AXI_MI_LG_SCAN2DRAMVCLK_IP_AD_APB_GTNR_MERGEVCLK_IP_LH_AXI_SI_D1_TNRVCLK_IP_LH_AXI_SI_D4_TNRVCLK_IP_D_TZPC_TPUVCLK_IP_SYSMMU_S0_PMMU0_YUVPexynos_acpm_set_init_freqPLLra_compare_clk_list6%s:failed idx:%x sfr:%x 3ECT DVFS [%s] not found %d MINMAX_%s%s <%x> [%s] value : %lu rate : %u clk name : %s id : 0x%x rate : %u value : %lu path : %s %s: there is no sequence element for exiting mode(%d).3%s %s: error on PA2VA conversion. seq:status, pd_id:%d. aborting init... PLL_LOCKTIME_PLL_G3DCLK_CON_MUX_MUX_CLK_G3D_STACKSQCH_CON_SYSMMU_S0_PMMU3_G3D_QCH_S0DBG_NFO_QCH_CON_LH_ACEL_SI_D2_G3D_QCHDBG_NFO_QCH_CON_UASC_G3D_QCHG3D_CMU_G3D_CONTROLLER_OPTIONDBG_NFO_QCH_CON_D_TZPC_DPUF0_QCHDBG_NFO_QCH_CON_SSMT_D1_DPUF0_QCHDBG_NFO_QCH_CON_LH_AST_MI_ID_JPEG_G2D0_QCHQCH_CON_SSMT_D0_GDC0_QCHQCH_CON_GPC_GSE_QCHDBG_NFO_QCH_CON_SYSREG_GSE_QCHQCH_CON_SSMT_D0_MCSC_QCHQCH_CON_SSMT_D4_MCSC_QCHDBG_NFO_QCH_CON_SSMT_D0_MCSC_QCHQCH_CON_SLH_AXI_MI_P_MFC_QCHDBG_NFO_QCH_CON_SSMT_D1_MFC_QCHQCH_CON_LH_AST_SI_L_OTF_RGBP_YUVP_QCHDBG_NFO_QCH_CON_PPMU_D2_MCFP_QCHQCH_CON_QE_D3_TNR_QCHQCH_CON_SSMT_D3_TNR_QCHDBG_NFO_QCH_CON_PPMU_D3_TNR_QCHDBG_NFO_QCH_CON_SSMT_D10_TNRA_QCHDBG_NFO_QCH_CON_SSMT_D11_TNRA_QCHDBG_NFO_QCH_CON_SYSREG_TNR_QCHDBG_NFO_QCH_CON_LH_AXI_SI_D_YUVP_QCHAOC_STATUSAUR_SHORTSTOPDBG_NFO_QCH_CON_UASC_BW_QCHQCH_CON_SYSREG_EH_QCHCLK_CON_DIV_DIV_CLK_ISPFE_DCPHYQCH_CON_ISPFE_QCH_ISPFEQCH_CON_UASC_ISPFE_QCHDBG_NFO_QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS7DBG_NFO_QCH_CON_D_TZPC_TPU_QCHQCH_CON_LH_AST_MI_G_NOCL2AA_CU_QCHQCH_CON_LH_AXI_SI_P_CPUCL0_CD_QCHQCH_CON_LH_TAXI_MI_D1_NOCL1A_NOCL0_QCHQCH_CON_PPC_CPUCL0_D0_CYCLE_QCHQCH_CON_SLH_AXI_SI_P_MIF3_QCHQCH_CON_TREX_P_NOCL0_QCHQCH_CON_PPC_NOCL0_IO1_EVENT_QCHDBG_NFO_QCH_CON_GPC_NOCL0_QCHDBG_NFO_QCH_CON_LH_AST_SI_G_NOCL1A_CU_QCHDBG_NFO_QCH_CON_LH_AXI_MI_P_CPUCL0_NOCL0_QCHDBG_NFO_QCH_CON_LH_AXI_SI_P_ALIVE_CD_QCHDBG_NFO_QCH_CON_LH_TAXI_SI_P_NOCL0_NOCL2AA_QCHDBG_NFO_QCH_CON_PPMU_NOCL0_CPUCL0_P_QCHDBG_NFO_QCH_CON_SLH_AXI_SI_P_MIF3_QCHNOCL1A_STATUSQCH_CON_LH_AXI_MI_D_BW_QCHQCH_CON_PPC_G3D_D0_CYCLE_QCHQCH_CON_PPC_NOCL2AB_S1_EVENT_QCHQCH_CON_SLH_AXI_MI_D_G3DMMU_QCHDBG_NFO_QCH_CON_LH_AST_SI_G_NOCL1A_QCHDBG_NFO_QCH_CON_TREX_D_NOCL1A_QCHDBG_NFO_QCH_CON_TREX_P_NOCL1A_QCHDBG_NFO_QCH_CON_SLH_AXI_SI_P_RGBP_QCHQCH_CON_GPC_NOCL2AB_QCHQCH_CON_LH_AXI_MI_D4_TNR_QCHQCH_CON_SLH_AXI_SI_P_GDC_QCHQCH_CON_ETR_MIU_QCH_ACLKQCH_CON_SYSMMU_S0_HSI0_QCH_S0QCH_CON_USB32DRD_QCH_USBDPPHY_TCAQCH_CON_D_TZPC_HSI1_QCHblkpwr_tpuEARLY_WAKEUP_ISPFE_DESTPLL_CON0_MUX_CLKCMU_PERIC1_USI15_USI_USERQCH_CON_INTMEM_QCHQCH_CON_MAILBOX_AP_AOCF1_QCHDBG_NFO_QCH_CON_D_TZPC_APM_CUSTOM_QCHDBG_NFO_QCH_CON_MAILBOX_TPU_AURMCU_QCHDBG_NFO_QCH_CON_RTC_QCHQCH_CON_LH_AXI_SI_P_MISC_GIC_CU_QCHQCH_CON_SPDMA1_QCHDBG_NFO_QCH_CON_OTP_CON_BISR_QCHDBG_NFO_QCH_CON_SSMT_SPDMA1_QCHDBG_NFO_QCH_CON_SYSMMU_S0_MISC_QCHQCH_CON_GPC_HSI2_QCHQCH_CON_LH_AXI_SI_P_HSI2_CU_QCHQCH_CON_UASC_PCIE_GEN3A_SLV_1_QCHDBG_NFO_QCH_CON_GPC_HSI2_QCHDBG_NFO_QCH_CON_USI2_USI_QCHDBG_NFO_QCH_CON_D_TZPC_PERIC1_QCHDBG_NFO_QCH_CON_I3C0_QCH_PCLKDBG_NFO_QCH_CON_USI10_USI_QCHDBG_NFO_QCH_CON_USI15_USI_QCHPLL_DSUMUX_CLKCMU_HSI0_USBDPDBGMUX_CLKCMU_CPUCL0_BCI_SWITCHMUX_CLK_CPUCL0_CPUMUX_CLK_HSI0_USB32DRDMUX_CLKCMU_HSI0_ALT_USERMUX_CLKCMU_MISC_NOC_USERDIV_CLK_APM_BOOSTCLKCMU_G3D_SWITCHCLKCMU_TNR_MERGECLKCMU_TPU_TPUCLKCMU_NOCL2AB_NOCDIV_CLK_CLUSTER0_PCLKDBGDIV_CLK_MCSC_NOCPDIV_CLK_MISC_GIC_LHDIV_CLK_PERIC0_USI4_USICLK_BLK_AOC_UID_RSTNSYNC_SR_CLK_AOC_TRACE_LH_IPCLKPORT_CLKGOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLKGOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLKGOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLKCLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_PCLKCLK_BLK_APM_UID_LH_AXI_SI_LP_ALIVE_CPUCL0_CD_IPCLKPORT_I_CLKCLK_BLK_APM_UID_MAILBOX_AP_AURMCUNS3_IPCLKPORT_PCLKCLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_PERI_CLKCLK_BLK_AUR_UID_SYSMMU_S0_AUR_IPCLKPORT_CLKGOUT_BLK_BW_UID_PPMU_BW_IPCLKPORT_PCLKGATE_CLKCMU_CIS_CLK3GATE_CLKCMU_TNR_MERGECLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CLUSTER0_PERIPHCLK_IPCLKPORT_CLKCLK_BLK_CPUCL0_UID_LH_AXI_SI_IP_BOOKER_IPCLKPORT_I_CLKGOUT_BLK_DPUF0_UID_PPMU_D1_DPUF0_IPCLKPORT_ACLKGOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_PCLKCLK_BLK_G2D_UID_LH_AST_MI_ID_JPEG_G2D0_IPCLKPORT_I_CLKCLK_BLK_G2D_UID_LH_AST_MI_ID_JPEG_G2D1_IPCLKPORT_I_CLKGOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLKGOUT_BLK_GDC_UID_LH_AST_MI_ID_GDC0_GDC1_IPCLKPORT_I_CLKGOUT_BLK_GSACORE_UID_PPMU_GSACORE0_IPCLKPORT_PCLKGOUT_BLK_GSACORE_UID_RESETMON_GSACORE_IPCLKPORT_PCLKCLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLKCLK_BLK_GSACORE_UID_LH_AXI_SI_ID_GME_GSA_IPCLKPORT_I_CLKCLK_BLK_GSACORE_UID_SC_GSACORE_IPCLKPORT_I_ACLKGOUT_BLK_GSE_UID_LH_AST_MI_L_OTF_YUVP_GSE_IPCLKPORT_I_CLKCLK_BLK_GSE_UID_RSTNSYNC_SR_CLK_GSE_NOCP_IPCLKPORT_CLKCLK_BLK_HSI0_UID_SLH_AXI_MI_LP_AOC_HSI0_IPCLKPORT_I_CLKCLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_USI4_IPCLKPORT_CLKCLK_BLK_HSI1_UID_LH_AXI_SI_LP_AOC_HSI1_CU_IPCLKPORT_I_CLKCLK_BLK_HSI1_UID_BLK_HSI1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLKGOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLKGOUT_BLK_HSI2_UID_QE_PCIE_GEN3B_HSI2_IPCLKPORT_ACLKGOUT_BLK_HSI2_UID_UASC_PCIE_GEN3B_DBI_1_IPCLKPORT_PCLKCLK_BLK_HSI2_UID_SYSMMU_S0_HSI2_IPCLKPORT_CLKGOUT_BLK_ISPFE_UID_LH_AXI_SI_D0_ISPFE_IPCLKPORT_I_CLKGOUT_BLK_ISPFE_UID_D_TZPC_ISPFE_IPCLKPORT_PCLKGOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLKGOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_PCLKCLK_BLK_MCSC_UID_SSMT_D5_MCSC_IPCLKPORT_PCLKCLK_BLK_MCSC_UID_SYSMMU_S0_PMMU1_MCSC_IPCLKPORT_CLKCLK_BLK_MFC_UID_SYSMMU_S0_MFC_IPCLKPORT_CLKCLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLKGOUT_BLK_NOCL0_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLKCLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF2_CD_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_PPMU_NOCL0_S3_IPCLKPORT_PCLKCLK_BLK_NOCL0_UID_PPMU_NOCL0_S0_IPCLKPORT_ACLKGOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_PCLKCLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_ACLKCLK_BLK_NOCL1A_UID_PPMU_NOCL1A_M2_IPCLKPORT_PCLKGOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLKCLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI0_CD_IPCLKPORT_I_CLKCLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLKCLK_BLK_NOCL2AA_UID_PPMU_NOCL2AA_M0_IPCLKPORT_ACLKCLK_BLK_NOCL2AB_UID_NOCL2AB_CMU_NOCL2AB_IPCLKPORT_PCLKCLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_PCLKCLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLKCLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLKCLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_PCLKGOUT_BLK_RGBP_UID_GPC_RGBP_IPCLKPORT_PCLKGOUT_BLK_RGBP_UID_SLH_AXI_MI_P_RGBP_IPCLKPORT_I_CLKCLK_BLK_RGBP_UID_QE_D3_RGBP_IPCLKPORT_PCLKCLK_BLK_S2D_UID_RSTNSYNC_SR_CLK_S2D_SCLK_IPCLKPORT_CLKGOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_ACLKCLK_BLK_TNR_UID_SYSMMU_S0_TNR_IPCLKPORT_CLKCLK_BLK_TNR_UID_RSTNSYNC_SR_CLK_TNR_ALIGN_IPCLKPORT_CLKGOUT_BLK_TPU_UID_LH_ACEL_SI_D0_TPU_IPCLKPORT_I_CLKGOUT_BLK_TPU_UID_SSMT_D0_TPU_IPCLKPORT_PCLKGOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLKGOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLKGOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLKCLK_BLK_TPU_UID_SLH_AXI_MI_P_TPU_IPCLKPORT_I_CLKCLK_BLK_TPU_UID_RSTNSYNC_SR_CLK_TPU_NOCD_IPCLKPORT_CLKCLK_BLK_TPU_UID_RSTNSYNC_SR_CLK_TPU_NOCP_IPCLKPORT_CLKCLK_BLK_TPU_UID_TPU_IPCLKPORT_DBG_UART_SCLKGOUT_BLK_YUVP_UID_AD_APB_YUVP_IPCLKPORT_PCLKMOSCCLK_G2DPLL_ALV_DIV2USB20PHY_PHY_CLOCKOSCCLK_PERIC1PPMU_USB_QCHLH_AXI_SI_D_ALIVE_QCHD_TZPC_AUR_QCHSLH_AXI_MI_P_AUR_QCHSSMT_D0_AUR_QCHLH_AXI_MI_IP_CPUCL1_QCHDPUF1_CMU_DPUF1_QCHLH_AST_SI_I_CA32_GIC_QCHUART_GSACORE_QCHLH_AXI_SI_I_DAP_GSA_QCHTIMER_GSACTRL_QCHSSMT_D1_GSE_QCHHSI1_CMU_HSI1_QCHLH_AXI_MI_LP_CPUCL0_HSI2_CU_QCHQE_D1_ISPFE_QCHSSMT_D3_ISPFE_QCHSYSREG_ISPFE_QCHQE_D4_MCSC_QCHSSMT_D3_MCSC_QCHGPC_MFC_QCHLH_AXI_SI_D0_MFC_QCHSSMT_D1_MFC_QCHLH_AST_SI_L_ICC_CLUSTER0_GIC_CU_QCHWDT_CLUSTER0_QCHPPC_CPUCL0_D1_EVENT_QCHSLH_AXI_SI_P_MIF1_QCHSLH_AXI_SI_P_MISC_GIC_QCHPPC_G3D_D0_EVENT_QCHNOCL1B_CMU_NOCL1B_QCHLH_AST_SI_G_NOCL2AA_CD_QCHLH_AXI_MI_D1_ISPFE_QCHSYSREG_NOCL2AA_QCHGPC_PERIC0_QCHI3C2_QCH_SCLKPWM_QCHSYSMMU_S0_PMMU1_RGBP_QCH_S0PPMU_D6_TNR_QCHSSMT_D6_TNR_QCHLH_ATB_MI_LT1_TPU_CPUCL0_CD_QCHSYSMMU_S0_TPU_QCHVCLK_MUX_NOCL0_CMUREFVCLK_MUX_CLKCMU_CIS_CLK2VCLK_DIV_CLK_SLC1_DCLKVCLK_DIV_CLK_PERIC1_USI15_USIVCLK_BLK_AOCVCLK_BLK_EHVCLK_BLK_ISPFEVCLK_BLK_RGBPVCLK_IP_MAILBOX_AP_DBGCOREVCLK_IP_LH_AXI_MI_IG_SWDVCLK_IP_LH_AST_SI_L_ICC_CLUSTER0_GICVCLK_IP_LH_AXI_SI_LG_ETR_HSI0_CDVCLK_IP_LH_AXI_SI_LP_CPUCL0_HSI2VCLK_IP_LH_ACEL_SI_D0_CPUCL0VCLK_IP_APB_ASYNC_P_BOOKER_0VCLK_IP_D_TZPC_DPUF0VCLK_IP_AD_APB_LMEVCLK_IP_LH_AST_SI_I_CA32_GICVCLK_IP_TZPC_GSACTRLVCLK_IP_LH_AST_MI_L_OTF_YUVP_GSEVCLK_IP_PCIE_GEN3_0VCLK_IP_PPMU_HSI2VCLK_IP_PCIE_GEN3A_1VCLK_IP_QE_PCIE_GEN3B_HSI2VCLK_IP_XIU_D1_HSI2VCLK_IP_PCIE_GEN3B_1VCLK_IP_MIPI_PHY_LINK_WRAPVCLK_IP_LH_AXI_SI_D3_ISPFEVCLK_IP_GPC_ISPFEVCLK_IP_AD_APB_MCSCVCLK_IP_LH_AXI_SI_D1_MCSCVCLK_IP_GPC_MIFVCLK_IP_LH_AXI_SI_P_MIF_CUVCLK_IP_QE_PDMA0VCLK_IP_AD_APB_DITVCLK_IP_LH_AST_SI_L_ICC_CLUSTER0_GIC_CUVCLK_IP_PPC_DBG_CCVCLK_IP_LH_AXI_SI_P_CPUCL0_CDVCLK_IP_PPMU_NOCL0_S1VCLK_IP_LH_AXI_SI_P_EH_CDVCLK_IP_PPC_NOCL2AB_S1_EVENTVCLK_IP_PPMU_NOCL1A_M2VCLK_IP_PPC_BW_D_CYCLEVCLK_IP_LH_TAXI_MI_P_NOCL0_NOCL1AVCLK_IP_GPC_NOCL1BVCLK_IP_SLH_AXI_SI_P_HSI1VCLK_IP_LH_AXI_SI_G_CSSYS_CUVCLK_IP_D_TZPC_NOCL2AAVCLK_IP_LH_AXI_MI_D4_RGBPVCLK_IP_SYSREG_NOCL2ABVCLK_IP_LH_AXI_MI_D1_G2DVCLK_IP_LH_AXI_SI_D6_RGBPVCLK_IP_SSMT_D3_TNRVCLK_IP_GTNR_ALIGNVCLK_IP_QE_D4_TNRVCLK_IP_XIU_D7_TNRVCLK_IP_AS_APB_SYSMMU_S1_NS_TPUVCLK_IP_LH_ATB_SI_LT0_TPU_CPUCL0VCLK_IP_DAPAPBAP_TPUVCLK_IP_SYSMMU_S0_YUVP3%s: sscanf failed (%d) vclk_tablepmucal_system_exit3%s %s: error on handling disable sequence. (cluster : %d) 3%s %s:invalid PMUCAL access type PLL_CON2_PLL_G3D_L2PLL_CON0_MUX_CLK_G3DCORE_COREGROUP_USERPLL_CON0_MUX_CLK_G3DCORE_STACKS_USERDBG_NFO_QCH_CON_D_TZPC_G3D_QCHDBG_NFO_QCH_CON_PPMU_G3D_D3_QCHDBG_NFO_QCH_CON_LH_AXI_MI_LD0_DPUF1_DPUF0_QCHDBG_NFO_QCH_CON_SSMT_D0_DPUF0_QCHQCH_CON_SSMT_D0_DPUF1_QCHDBG_NFO_QCH_CON_LH_AST_MI_ID_G2D1_JPEG_QCHPLL_CON0_MUX_CLKCMU_GSE_NOC_USERQCH_CON_LH_AXI_SI_D_GSE_QCHPLL_CON0_MUX_CLKCMU_MCSC_NOC_USERDBG_NFO_QCH_CON_QE_D5_MCSC_QCHQCH_CON_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_QCHDBG_NFO_QCH_CON_SYSMMU_S0_PMMU0_MFC_QCHQCH_CON_LH_AST_MI_I_RGBP_MCFP_QCHQCH_CON_LH_AXI_SI_D0_RGBP_QCHQCH_CON_LH_AXI_SI_D3_RGBP_QCHQCH_CON_QE_D8_MCFP_QCHQCH_CON_SYSMMU_S0_RGBP_QCH_S0QCH_CON_LH_AXI_SI_D2_TNR_QCHQCH_CON_SYSMMU_S2_TNR_QCH_S0DBG_NFO_QCH_CON_PPMU_D1_TNR_QCHDBG_NFO_QCH_CON_SYSMMU_S2_TNR_QCH_S0QCH_CON_SYSMMU_S0_AUR_QCH_S0BW_CONFIGURATIONQCH_CON_EH_QCHQCH_CON_BAAW_ISPFE_QCHDBG_NFO_QCH_CON_BAAW_ISPFE_QCHDBG_NFO_QCH_CON_LH_AXI_SI_D1_ISPFE_QCHDBG_NFO_QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1ISPFE_CMU_ISPFE_CONTROLLER_OPTIONDBG_NFO_QCH_CON_LH_ATB_SI_T_BDU_CD_QCHDBG_NFO_QCH_CON_LH_AXI_MI_P_MIF2_CD_QCHDBG_NFO_QCH_CON_LH_AXI_MI_P_MISC_CD_QCHDBG_NFO_QCH_CON_LH_AXI_SI_P_PERIC0_CD_QCHDBG_NFO_QCH_CON_LH_TAXI_MI_D1_NOCL1A_NOCL0_QCHDBG_NFO_QCH_CON_PPC_NOCL1A_M2_EVENT_QCHQCH_CON_LH_TAXI_MI_D1_NOCL2AA_NOCL1A_QCHQCH_CON_LH_TAXI_MI_P_NOCL0_NOCL1A_QCHDBG_NFO_QCH_CON_NOCL1A_CMU_NOCL1A_QCHQCH_CON_LH_AST_SI_G_NOCL1B_QCHDBG_NFO_QCH_CON_TREX_D_NOCL1B_QCHQCH_CON_LH_AXI_MI_D2_ISPFE_QCHDBG_NFO_QCH_CON_LH_AXI_MI_D0_RGBP_QCHDBG_NFO_QCH_CON_LH_AXI_MI_D1_RGBP_QCHDBG_NFO_QCH_CON_LH_TAXI_SI_D1_NOCL2AA_NOCL1A_QCHCLK_CON_DIV_DIV_CLK_HSI0_USI4CLK_CON_MUX_MUX_CLK_HSI0_USI4DBG_NFO_QCH_CON_DP_LINK_QCH_GTC_CLKDBG_NFO_QCH_CON_ETR_MIU_QCH_ACLKDBG_NFO_QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CU_QCHDBG_NFO_QCH_CON_DP_LINK_QCH_OSC_CLKDBG_NFO_QCH_CON_USI1_HSI0_QCHCLK_CON_DIV_CLK_HSI1_ALTDBG_NFO_QCH_CON_SLH_AXI_MI_LP_AOC_HSI1_QCHTCXO_DURATIONCLK_CON_DIV_DIV_CLK_PERIC1_USI9_USIQCH_CON_APM_USI0_USI_QCHQCH_CON_MAILBOX_APM_GSA_QCHQCH_CON_SLH_AXI_MI_LP_AOC_ALIVE_QCHQCH_CON_SS_DBGCORE_QCH_DBGQCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_QCHDBG_NFO_QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_QCHDBG_NFO_QCH_CON_LH_AXI_MI_LP_CPUCL0_HSI2_CU_QCHDBG_NFO_QCH_CON_I3C3_QCH_PCLKDBG_NFO_QCH_CON_SLH_AXI_MI_P_PERIC1_QCHCLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0CMU_CMU_TOP_CONTROLLER_OPTIONPLL_CPUCL2MUX_CLKCMU_NOCL0_NOCMUX_CLK_NOCL0_NOCMUX_CLK_TPU_TPUCTLMUX_CLKCMU_G3D_GLB_USERMUX_CLKCMU_GDC_GDC0_USERCLKCMU_HSI0_USB32DRDCLKCMU_GDC_GDC1DIV_CLK_CPUCL0_ADD_CH_CLKDIV_CLK_DPUB_NOCPDIV_CLK_EH_NOCPDIV_CLK_HSI0_USI0DIV_CLK_PERIC0_USI3_USICLK_BLK_APM_UID_RSTNSYNC_SR_CLK_APM_NOC_LH_IPCLKPORT_CLKCLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_PCLKCLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_FABRIC_CLKGATE_CLKCMU_ISPFE_NOCGATE_CLKCMU_DPUB_DSIMGOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_ACLKCLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CLUSTER0_ACLK_NON_MAIN_LH_IPCLKPORT_CLKGATE_CLK_CLUSTER1_CORE5CLKGOUT_BLK_DPUF0_UID_PPMU_D1_DPUF0_IPCLKPORT_PCLKCLK_BLK_DPUF0_UID_SYSMMU_S0_PMMU1_DPUF0_IPCLKPORT_CLKGOUT_BLK_DPUF1_UID_LH_AXI_SI_LD0_DPUF1_DPUF0_IPCLKPORT_I_CLKCLK_BLK_DPUF1_UID_PPMU_D1_DPUF1_IPCLKPORT_ACLKCLK_BLK_EH_UID_EH_CMU_EH_IPCLKPORT_PCLKGOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCP_IPCLKPORT_CLKGOUT_BLK_G2D_UID_SYSMMU_S0_PMMU1_G2D_IPCLKPORT_CLKCLK_BLK_G2D_UID_SYSMMU_S0_G2D_IPCLKPORT_CLKGOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLKCLK_BLK_G3D_UID_LH_AXI_SI_P_G3D_CU_IPCLKPORT_I_CLKGOUT_BLK_GDC_UID_PPMU_D0_GDC1_IPCLKPORT_PCLKCLK_BLK_GDC_UID_SSMT_D4_GDC0_IPCLKPORT_PCLKCLK_BLK_GDC_UID_QE_D4_GDC0_IPCLKPORT_ACLKCLK_BLK_GDC_UID_RSTNSYNC_SR_CLK_GDC_GDC1_IPCLKPORT_CLKGOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_ACLKCLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_IPCLKPORT_I_CLKGOUT_BLK_GSACTRL_UID_LH_AXI_SI_I_DAP_GSA_IPCLKPORT_I_CLKGOUT_BLK_GSE_UID_SLH_AXI_MI_P_GSE_IPCLKPORT_I_CLKGOUT_BLK_GSE_UID_SSMT_D1_GSE_IPCLKPORT_ACLKCLK_BLK_GSE_UID_RSTNSYNC_SR_CLK_GSE_NOCD_IPCLKPORT_CLKCLK_BLK_HSI0_UID_USI3_HSI0_IPCLKPORT_PCLKGOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLKGOUT_BLK_HSI1_UID_PCIE_GEN3_0_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UGCLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_OSCCLK_IPCLKPORT_CLKCLK_BLK_HSI2_UID_RSTNSYNC_SR_CLK_HSI2_NOC_IPCLKPORT_CLKCLK_BLK_HSI2_UID_AS_APB_PCIEPHY_0_HSI2_IPCLKPORT_PCLKMGOUT_BLK_ISPFE_UID_LH_AXI_SI_D3_ISPFE_IPCLKPORT_I_CLKGOUT_BLK_ISPFE_UID_SYSMMU_S2_PMMU0_ISPFE_IPCLKPORT_CLKGOUT_BLK_ISPFE_UID_QE_D3_ISPFE_IPCLKPORT_PCLKCLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLKGOUT_BLK_MCSC_UID_SSMT_D2_MCSC_IPCLKPORT_ACLKGOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLKGOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_PCLKCLK_BLK_MCSC_UID_SSMT_D4_MCSC_IPCLKPORT_ACLKGOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_PCLKGOUT_BLK_MFC_UID_GPC_MFC_IPCLKPORT_PCLKCLK_BLK_MFC_UID_BLK_MFC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLKCLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLKCLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCP_IPCLKPORT_CLKGOUT_BLK_MISC_UID_LH_ACEL_SI_D_MISC_IPCLKPORT_I_CLKGOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_PCLKGOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKMGOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_PCLKGOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLKCLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_PCLKCLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_PCLKCLK_BLK_MISC_UID_MCT_V41_IPCLKPORT_I_PCLKCLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_OSCCLK_IPCLKPORT_CLKGOUT_BLK_NOCL0_UID_PPMU_NOCL0_CPUCL0_P_IPCLKPORT_ACLKCLK_BLK_NOCL0_UID_LH_TAXI_SI_P_NOCL0_NOCL2AA_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_SLC1_DCLK_IPCLKPORT_CLKGOUT_BLK_NOCL1A_UID_PPC_NOCL2AA_S0_EVENT_IPCLKPORT_ACLKCLK_BLK_NOCL1A_UID_LH_TAXI_MI_D0_NOCL2AA_NOCL1A_IPCLKPORT_I_CLKCLK_BLK_NOCL1A_UID_LH_TAXI_SI_D2_NOCL1A_NOCL0_IPCLKPORT_I_CLKGOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_ALIVE_IPCLKPORT_I_CLKGOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_GSA_CD_IPCLKPORT_I_CLKCLK_BLK_NOCL2AA_UID_LH_TAXI_SI_D1_NOCL2AA_NOCL1A_IPCLKPORT_I_CLKCLK_BLK_NOCL2AB_UID_SYSREG_NOCL2AB_IPCLKPORT_PCLKCLK_BLK_NOCL2AB_UID_LH_AXI_MI_D2_TNR_IPCLKPORT_I_CLKGOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLKCLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_PCLKCLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_NOCP_IPCLKPORT_CLKGOUT_BLK_RGBP_UID_LH_AXI_SI_D0_RGBP_IPCLKPORT_I_CLKCLK_BLK_RGBP_UID_QE_D0_RGBP_IPCLKPORT_ACLKCLK_BLK_RGBP_UID_SSMT_D5_MCFP_IPCLKPORT_ACLKCLK_BLK_RGBP_UID_QE_D4_RGBP_IPCLKPORT_ACLKCLK_BLK_RGBP_UID_QE_D6_RGBP_IPCLKPORT_PCLKCLK_BLK_RGBP_UID_QE_D5_MCFP_IPCLKPORT_PCLKCLK_BLK_RGBP_UID_QE_D11_MCFP_IPCLKPORT_PCLKGOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLKGOUT_BLK_TNR_UID_LH_AST_MI_L_OTF_YUVP_TNR_IPCLKPORT_I_CLKCLK_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_ACLKCLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_PCLKCLK_BLK_TNR_UID_XIU_D7_TNR_IPCLKPORT_ACLKGOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCD_IPCLKPORT_CLKGOUT_BLK_TPU_UID_AS_APB_SYSMMU_S1_NS_TPU_IPCLKPORT_PCLKMGOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_DD_IPCLKPORT_CLKPLL_ALV_DIV4OSCCLK_NOCL2ABPLL_SHARED2_D2LH_AXI_MI_P_AOC_CU_QCHMAILBOX_APM_AOC_QCHLH_ACEL_SI_D0_AUR_QCHLH_ATB_MI_LT_G3D_CPUCL0_QCHCPUCL1_CMU_CPUCL1_QCHLH_AXI_SI_D1_DPUF0_QCHSLH_AXI_MI_P_DPUF0_QCHSSMT_D0_DPUF0_QCHPPC_EH_EVENT_QCHSYSREG_G2D_QCHLH_ACEL_SI_D0_G3D_QCHRSTNSYNC_CLK_G3D_DD_QCHPPMU_D4_GDC0_QCHSSMT_D2_GDC0_QCHSYSREG_GDC_QCHGPIO_GSACORE1_QCHLH_AXI_MI_ID_SC_GSACORE_QCHTZPC_GSACTRL_QCHD_TZPC_GSE_QCHQE_D2_GSE_QCHLH_AXI_MI_LP_CPUCL0_HSI1_CU_QCHLH_AXI_MI_P_HSI1_CU_QCHLH_AXI_SI_P_HSI1_CU_QCHSLH_AXI_MI_LP_AOC_HSI1_QCHUASC_PCIE_GEN3B_DBI_1_QCHISPFE_QCH_ISPFEMIPI_PHY_LINK_WRAP_QCH_CSIS2MIPI_PHY_LINK_WRAP_QCH_CSIS7PPMU_D1_ISPFE_QCHQE_PDMA1_QCHLH_TAXI_SI_P_NOCL0_NOCL1B_QCHLH_AST_SI_G_NOCL1A_QCHLH_AXI_SI_P_AUR_CD_QCHSLH_AXI_SI_P_BW_QCHLH_AXI_SI_P_GSA_CD_QCHLH_AXI_MI_D0_ISPFE_QCHSLH_AXI_SI_P_GDC_QCHI3C6_QCH_SCLKUSI5_USI_QCHPPMU_D2_MCFP_QCHSSMT_D4_MCFP_QCHLH_AXI_MI_LG_SCAN2DRAM_CU_QCHLH_AXI_SI_D0_TNR_QCHPPMU_D3_TNR_QCHSYSMMU_S1_PMMU1_TNR_QCH_S0QE_D1_YUVP_QCHSYSMMU_S0_YUVP_QCH_S0CTRL_OPTION_CMU_NOCL1BCTRL_OPTION_CMU_PERIC0VCLK_BLK_TNRVCLK_IP_SLH_AXI_SI_LP_AOC_ALIVEVCLK_IP_LH_AXI_SI_P_AUR_CUVCLK_IP_PPMU_BWVCLK_IP_LH_ATB_SI_LT_AOC_CUVCLK_IP_LH_AXI_SI_P_CPUCL0_CUVCLK_IP_AD_APB_DPUF0_DMAVCLK_IP_LH_AXI_SI_D0_G2DVCLK_IP_SSMT_D1_G2DVCLK_IP_GDC_CMU_GDCVCLK_IP_SSMT_D2_GDC0VCLK_IP_LH_AXI_SI_D0_GDCVCLK_IP_BLK_GDC_FRC_OTP_DESERIALVCLK_IP_GIC_GSACOREVCLK_IP_XIU_DP1_GSA_ZMVCLK_IP_SSMT_D1_GSEVCLK_IP_BLK_GSE_FRC_OTP_DESERIALVCLK_IP_SLH_AXI_MI_P_HSI1VCLK_IP_BLK_ISPFE_FRC_OTP_DESERIALVCLK_IP_QE_D1_MCSCVCLK_IP_WDT_CLUSTER1VCLK_IP_LH_AXI_MI_ID_SCVCLK_IP_LH_AXI_SI_P_MISC_CUVCLK_IP_BDUVCLK_IP_SLC_CB_TOPVCLK_IP_LH_ACEL_SI_D0_NOCL0_CPUCL0VCLK_IP_LH_AST_SI_G_NOCL1A_CDVCLK_IP_LH_AXI_SI_P_AUR_CDVCLK_IP_LH_TAXI_SI_D1_NOCL1A_NOCL0VCLK_IP_LH_AXI_MI_D0_MFCVCLK_IP_LH_TAXI_SI_D0_NOCL2AB_NOCL1AVCLK_IP_LH_AXI_MI_D5_TNRVCLK_IP_MCFPVCLK_IP_BLK_TNR_FRC_OTP_DESERIALVCLK_IP_SLH_AXI_MI_P_TPUVCLK_IP_XIU_D_TPUVCLK_IP_LH_ACEL_SI_D1_TPUVCLK_IP_AD_APB_YUVPVCLK_CLKOUT1CPUCL1exynos_acpm_get_ratemargin_bci_write_fileGOUTCLK_BLKVCLK3%s:[%x] 3%s %s: error on handling lpm_init sequence. DPUF0_CONFIGURATIONDBG_NFO_QCH_CON_SLH_AXI_MI_P_DPUF0_QCHDBG_NFO_QCH_CON_SYSMMU_S0_DPUF0_QCH_S0DPUF1_CMU_DPUF1_CONTROLLER_OPTIONDBG_NFO_QCH_CON_GPC_G2D_QCHPLL_CON0_MUX_CLKCMU_GDC_GDC0_USERQCH_CON_GDC0_QCH_CLKQCH_CON_QE_D0_GDC1_QCHDBG_NFO_QCH_CON_GSE_CMU_GSE_QCHDBG_NFO_QCH_CON_QE_D2_GSE_QCHDBG_NFO_QCH_CON_SYSMMU_S0_MCSC_QCH_S0DBG_NFO_QCH_CON_MFC_CMU_MFC_QCHQCH_CON_PPMU_D0_RGBP_QCHQCH_CON_QE_D1_RGBP_QCHDBG_NFO_QCH_CON_LH_AXI_SI_D0_RGBP_QCHDBG_NFO_QCH_CON_PPMU_D0_RGBP_QCHDBG_NFO_QCH_CON_SSMT_D0_RGBP_QCHDBG_NFO_QCH_CON_SSMT_D4_MCFP_QCHTNR_CONFIGURATIONQCH_CON_QE_D4_TNR_QCHQCH_CON_SLH_AXI_MI_P_TNR_QCHQCH_CON_SYSMMU_S2_PMMU0_TNR_QCH_S0DBG_NFO_QCH_CON_PPMU_D11_TNRA_QCH_S0DBG_NFO_QCH_CON_SYSREG_YUVP_QCHDBG_NFO_QCH_CON_ADD_APBIF_AUR_QCHQCH_CON_LH_AXI_SI_IP_BW_QCHQCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2QCH_CON_PPMU_D3_ISPFE_QCHQCH_CON_SSMT_D3_ISPFE_QCHDBG_NFO_QCH_CON_LH_AXI_SI_D2_ISPFE_QCHDBG_NFO_QCH_CON_QE_D1_ISPFE_QCHPLL_LOCKTIME_PLL_TPUPLL_CON3_PLL_TPUQCH_CON_PPMU_D1_TPU_QCHDBG_NFO_QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CD_QCHDBG_NFO_QCH_CON_SYSREG_TPU_QCHPLL_LOCKTIME_REG_PLL_NOCL0QCH_CON_LH_AXI_MI_P_CPUCL0_CD_QCHQCH_CON_PPC_NOCL1A_M0_EVENT_QCHQCH_CON_SLH_AXI_SI_P_MISC_QCHQCH_CON_SLH_AXI_SI_P_PERIC0_QCHDBG_NFO_QCH_CON_SLH_AXI_SI_P_ALIVE_QCHDBG_NFO_QCH_CON_PPC_NOCL0_IO0_CYCLE_QCHDBG_NFO_QCH_CON_PPC_NOCL0_IO0_EVENT_QCHNOCL0_EMBEDDED_CMU_NOCL0_CONTROLLER_OPTIONQCH_CON_SYSREG_NOCL1A_QCHDBG_NFO_QCH_CON_SLH_AXI_SI_P_G3D_QCHQCH_CON_LH_AXI_SI_P_AOC_CD_QCHQCH_CON_PPMU_NOCL1B_M0_QCHQCH_CON_LH_AST_MI_G_NOCL2AA_CD_QCHQCH_CON_LH_AXI_MI_D1_RGBP_QCHDBG_NFO_QCH_CON_LH_AST_SI_G_NOCL2AA_QCHDBG_NFO_QCH_CON_LH_AXI_MI_D1_ISPFE_QCHDBG_NFO_QCH_CON_LH_AXI_MI_D3_RGBP_QCHCLK_CON_DIV_DIV_CLK_NOCL2AB_NOCPDBG_NFO_QCH_CON_LH_AXI_MI_D2_GDC_QCHPLL_CON0_MUX_CLKCMU_HSI0_DPOSC_USERPLL_CON0_MUX_CLKCMU_HSI0_PERI_USERQCH_CON_SLH_AXI_MI_P_HSI0_QCHDBG_NFO_DMYQCH_CON_USB32DRD_QCH_REFCPUCL0_SHORTSTOPEXT_REGULATOR_TOP_DURATIONPLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USERPLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USERQCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCHQCH_CON_SSMT_D_ALIVE_QCHDBG_NFO_QCH_CON_PMU_INTR_GEN_QCHDMYQCH_CON_PUF_QCHQCH_CON_PDMA1_QCHQCH_CON_TMU_TOP_QCHDBG_NFO_QCH_CON_QE_SC_QCHDBG_NFO_DMYQCH_CON_PCIE_GEN3A_1_QCH_REFDBG_NFO_QCH_CON_QE_PCIE_GEN3A_HSI2_QCHQCH_CON_LH_AXI_SI_P_PERIC0_CU_QCHDBG_NFO_QCH_CON_LH_AXI_SI_P_PERIC0_CU_QCHDBG_NFO_QCH_CON_LH_AXI_MI_P_PERIC1_CU_QCHCLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0PLL_SHARED1_D1PLL_CPUCL1MUX_CLKCMU_CIS_CLK2MUX_CLKCMU_G3D_SWITCHMUX_CLKCMU_DPUF1_NOCMUX_MIF_CMUREFMUX_NOCL1A_CMUREFMUX_CLKCMU_NOCL2AA_NOC_USERMUX_CLKCMU_PERIC0_USI3_USI_USERMUX_CLKCMU_PERIC0_USI0_UART_USERDIV_CLK_APM_USI0_USICLKCMU_CIS_CLK4DIV_CLKCMU_CMU_BOOSTCLKCMU_NOCL2AA_NOCCLKCMU_CIS_CLK7DIV_CLK_GSACORE_CPU_LHDIV_CLK_NOCL1A_NOCD_LHGOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_PCLKGOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_ACLKGOUT_BLK_AOC_UID_SYSMMU_S0_PMMU_AOC_IPCLKPORT_CLKGOUT_BLK_APM_UID_LH_AXI_SI_D_ALIVE_IPCLKPORT_I_CLKGOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLKCLK_BLK_APM_UID_LH_AXI_SI_LP_AOC_ALIVE_CU_IPCLKPORT_I_CLKCLK_BLK_APM_UID_MAILBOX_AP_AURMCUNS2_IPCLKPORT_PCLKCLK_BLK_AUR_UID_AS_APB_SYSMMU_S1_NS_AUR_IPCLKPORT_PCLKMCLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_IPCLKPORT_CLKCLK_BLK_CPUCL0_UID_LH_AXI_MI_IP_BOOKER_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_LH_AXI_SI_LP_ALIVE_CPUCL0_CU_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_LH_AXI_MI_IG_HSI0_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CLUSTER0_ACLK_MAIN_IPCLKPORT_CLKCLK_BLK_CPUCL0_UID_APB_ASYNC_P_SYSMMU_IPCLKPORT_PCLKMCLK_BLK_CPUCL0_UID_PPMU_CPUCL0_D2_IPCLKPORT_ACLKCLK_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_OSCCLK_IPCLKPORT_CLKGOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCP_IPCLKPORT_CLKCLK_BLK_EH_UID_LH_AXI_SI_IP_EH_IPCLKPORT_I_CLKCLK_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_JPEG_IPCLKPORT_CLKGOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLKCLK_BLK_G3D_UID_ADM_DAP_G_GPU_IPCLKPORT_DAPCLKMGOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_NOCP_IPCLKPORT_CLKCLK_BLK_GDC_UID_AD_APB_GDC0_IPCLKPORT_PCLKMGOUT_BLK_GSACTRL_UID_LH_AXI_MI_IP_GSA_IPCLKPORT_I_CLKGOUT_BLK_GSACTRL_UID_SYSREG_GSACTRLEXT_IPCLKPORT_PCLKCLK_BLK_HSI0_UID_LH_AXI_MI_P_HSI0_CU_IPCLKPORT_I_CLKCLK_BLK_HSI0_UID_USI1_HSI0_IPCLKPORT_IPCLKGOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLKGOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLKCLK_BLK_HSI1_UID_LH_AXI_MI_LP_CPUCL0_HSI1_CU_IPCLKPORT_I_CLKGOUT_BLK_ISPFE_UID_RSTNSYNC_CLK_ISPFE_NOCP_IPCLKPORT_CLKGOUT_BLK_ISPFE_UID_ISPFE_IPCLKPORT_CLK_ISPFECLK_BLK_ISPFE_UID_SSMT_D2_ISPFE_IPCLKPORT_ACLKCLK_BLK_ISPFE_UID_PPMU_D2_ISPFE_IPCLKPORT_ACLKCLK_BLK_ISPFE_UID_PPMU_D2_ISPFE_IPCLKPORT_PCLKCLK_BLK_ISPFE_UID_SYSMMU_S1_ISPFE_IPCLKPORT_CLKCLK_BLK_ISPFE_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS5CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLKGOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLKGOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLKGOUT_BLK_MISC_UID_PDMA0_IPCLKPORT_ACLKCLK_BLK_MISC_UID_SLH_AXI_MI_P_MISC_IPCLKPORT_I_CLKCLK_BLK_MISC_UID_SYSMMU_S0_MISC_IPCLKPORT_CLKCLK_BLK_NOCL0_UID_LH_TAXI_MI_D2_NOCL1A_NOCL0_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_ACLKGOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_ACLKGOUT_BLK_NOCL2AA_UID_LH_AXI_MI_D1_DPUF0_IPCLKPORT_I_CLKCLK_BLK_NOCL2AA_UID_LH_TAXI_MI_P_NOCL0_NOCL2AA_IPCLKPORT_I_CLKCLK_BLK_NOCL2AB_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLKCLK_BLK_NOCL2AB_UID_LH_ACEL_MI_D_MISC_IPCLKPORT_I_CLKGOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLKGOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLKGOUT_BLK_RGBP_UID_D_TZPC_RGBP_IPCLKPORT_PCLKCLK_BLK_RGBP_UID_MCFP_IPCLKPORT_CLKCLK_BLK_RGBP_UID_SSMT_D4_MCFP_IPCLKPORT_PCLKCLK_BLK_RGBP_UID_QE_D5_RGBP_IPCLKPORT_ACLKGOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_GSE_IPCLKPORT_I_CLKCLK_BLK_TNR_UID_XIU_D4_TNR_IPCLKPORT_ACLKCLK_BLK_TNR_UID_SSMT_D11_TNRA_IPCLKPORT_ACLKGOUT_BLK_TPU_UID_GPC_TPU_IPCLKPORT_PCLKGOUT_BLK_YUVP_UID_LH_AXI_SI_D_YUVP_IPCLKPORT_I_CLKGOUT_BLK_YUVP_UID_LH_AST_MI_L_OTF_RGBP_YUVP_IPCLKPORT_I_CLKOSCCLK_GSACTRLOSCCLK_HSI0CLKCMU_HSI0_USBDPDBGMAILBOX_AP_AURMCUNS4_QCHSLH_AXI_MI_LP_AOC_ALIVE_QCHADD0_APBIF_CPUCL0_QCHLH_ATB_MI_LT0_TPU_CPUCL0_CU_QCHLH_ATB_MI_LT_AOC_QCHPPMU_CPUCL0_D0_QCHPPMU_CPUCL0_D2_QCHD_TZPC_DPUB_QCHSYSMMU_S0_G2D_QCHSYSREG_GSACTRLEXT_QCHQE_D0_GSE_QCHLH_AXI_MI_LG_ETR_HSI0_CU_QCHUSB32DRD_QCH_USBDPPHY_TCAGPC_HSI1_QCHPCIE_GEN3A_1_QCH_PCS_APBPCIE_GEN3B_1_QCH_PCS_APBUASC_PCIE_GEN3A_SLV_1_QCHGPC_ISPFE_QCHLH_AXI_SI_D2_ISPFE_QCHMIPI_PHY_LINK_WRAP_QCH_CSIS0MCSC_CMU_MCSC_QCHPPMU_D6_MCSC_QCHQE_SC_QCHLH_AST_MI_G_NOCL2AA_CU_QCHLH_AXI_MI_P_ALIVE_CD_QCHPPC_DBG_CC_QCHSLH_AXI_SI_P_EH_QCHTREX_D_NOCL0_QCHPPMU_NOCL1A_M0_QCHLH_AXI_MI_D1_RGBP_QCHSYSREG_PERIC1_QCHD_TZPC_RGBP_QCHLH_AXI_SI_D0_RGBP_QCHSYSMMU_S1_PMMU3_RGBP_QCH_S0PPMU_D10_TNRA_QCH_S0QE_D11_TNRA_QCHPPMU_D4_YUVP_QCHCTRL_OPTION_CMU_EHCTRL_OPTION_CMU_NOCL2ABVCLK_MUX_CMU_CMUREFVCLK_BLK_YUVPVCLK_IP_LH_AXI_SI_LP_AOC_HSI0_CDVCLK_IP_SYSMMU_S0_PMMU0_ALIVEVCLK_IP_GPC_APM_CUSTOMVCLK_IP_UASC_P0_AURVCLK_IP_BAAW_AURVCLK_IP_SYSREG_BWVCLK_IP_LH_AXI_MI_P_EH_CUVCLK_IP_SLH_AXI_MI_P_EHVCLK_IP_PPC_EH_CYCLEVCLK_IP_PPMU_D2_G2DVCLK_IP_SYSMMU_S0_PMMU1_G2DVCLK_IP_LH_AXI_SI_IP_G3DVCLK_IP_PPMU_G3D_D3VCLK_IP_SYSMMU_S0_PMMU1_G3DVCLK_IP_AD_APB_GDC1VCLK_IP_XIU_D1_GDCVCLK_IP_SSMT_D4_GDC0VCLK_IP_XIU_DP0_GSA_ZMVCLK_IP_LH_AXI_MI_IP_AXI2APB1_GSACOREVCLK_IP_XIU_D0_GSA_ZMVCLK_IP_LH_AXI_MI_P_GSA_CUVCLK_IP_LH_AXI_SI_I_DAP_GSAVCLK_IP_GPC_HSI0VCLK_IP_XIU_P_HSI0VCLK_IP_LH_AXI_MI_LP_AOC_HSI1_CUVCLK_IP_HSI2_CMU_HSI2VCLK_IP_SYSMMU_S2_PMMU0_ISPFEVCLK_IP_XIU_D0_ISPFEVCLK_IP_BLK_MCSC_FRC_OTP_DESERIALVCLK_IP_AD_APB_PUFVCLK_IP_SLH_AXI_SI_P_CPUCL0VCLK_IP_LH_AXI_MI_P_MIF2_CDVCLK_IP_LH_ACEL_MI_D2_CPUCL0VCLK_IP_PPC_G3DMMU_D_EVENTVCLK_IP_LH_AXI_SI_P_HSI0_CDVCLK_IP_SLH_AXI_SI_P_AOCVCLK_IP_LH_AXI_MI_D1_ISPFEVCLK_IP_LH_AXI_MI_D1_RGBPVCLK_IP_LH_AXI_MI_D2_ISPFEVCLK_IP_TREX_P_NOCL2ABVCLK_IP_SLH_AXI_SI_P_TNRVCLK_IP_GPIO_PERIC0VCLK_IP_PPMU_D4_MCFPVCLK_IP_SYSMMU_S1_PMMU2_RGBPVCLK_IP_SYSREG_TPUVCLK_IP_ADD_APBIF_TPUVCLK_IP_XIU_D0_YUVPMFCacpm_noti_mif_callbackmargin_mid_write_filemargin_tnr_write_file6%x, id = %x %s : 0x%x 3%s %s: error on PA2VA conversion for lpm_init seq. aborting init... QCH_CON_GPC_G3D_QCHDBG_NFO_QCH_CON_DPUB_QCH_ALV_DSIM0PLL_CON0_MUX_CLKCMU_DPUF0_NOC_USERQCH_CON_LH_AXI_MI_LD1_DPUF1_DPUF0_QCHQCH_CON_SSMT_D1_DPUF0_QCHDBG_NFO_QCH_CON_DPUF0_QCH_DPUFDBG_NFO_QCH_CON_SSMT_D1_DPUF1_QCHDBG_NFO_QCH_CON_G2D_CMU_G2D_QCHDBG_NFO_QCH_CON_LH_AST_SI_ID_JPEG_G2D0_QCHQCH_CON_LH_AST_MI_ID_GDC0_GDC1_QCHQCH_CON_LH_AST_MI_ID_GDC1_GDC0_QCHDBG_NFO_QCH_CON_PPMU_D0_GDC0_QCHDBG_NFO_QCH_CON_SSMT_D4_GDC1_QCHQCH_CON_QE_D2_GSE_QCHDBG_NFO_QCH_CON_LH_AXI_SI_D_GSE_QCHDBG_NFO_QCH_CON_PPMU_D1_MCSC_QCHQCH_CON_SYSMMU_S0_PMMU1_RGBP_QCH_S0DBG_NFO_QCH_CON_LH_AXI_SI_D2_RGBP_QCHDBG_NFO_QCH_CON_QE_D5_MCFP_QCHQCH_CON_SYSREG_TNR_QCHDBG_NFO_QCH_CON_QE_D11_TNRA_QCHQCH_CON_PPMU_D0_YUVP_QCHYUVP_CMU_YUVP_CONTROLLER_OPTIONQCH_CON_ADD_APBIF_AUR_QCHQCH_CON_QE_EH_QCHDBG_NFO_QCH_CON_UASC_EH_QCHQCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS8DBG_NFO_QCH_CON_SYSMMU_S1_PMMU0_ISPFE_QCH_S0PLL_CON2_PLL_TPUPLL_CON5_PLL_TPUCLK_CON_DIV_DIV_CLK_TPU_TPUQCH_CON_SYSMMU_S0_PMMU0_TPU_QCHDBG_NFO_QCH_CON_SYSMMU_S0_PMMU1_TPU_QCHPLL_CON7_PLL_NOCL0PLL_CON0_PLL_NOCL0QCH_CON_LH_AST_MI_G_NOCL1B_CU_QCHQCH_CON_LH_AST_MI_G_NOCL2AB_QCHQCH_CON_LH_ATB_SI_T_BDU_CD_QCHQCH_CON_LH_AXI_MI_P_MISC_GIC_CD_QCHQCH_CON_LH_AXI_SI_P_MISC_GIC_CD_QCHQCH_CON_SLH_AXI_MI_G_NOCL0_QCHDBG_NFO_QCH_CON_LH_AXI_SI_P_CPUCL0_CD_QCHDBG_NFO_QCH_CON_PPC_NOCL1A_M1_EVENT_QCHNOCL0_CMU_NOCL0_CONTROLLER_OPTIONQCH_CON_PPC_NOCL2AB_S0_CYCLE_QCHDBG_NFO_QCH_CON_SLH_AXI_SI_P_TPU_QCHCLK_CON_DIV_DIV_CLK_NOCL1B_NOCPNOCL2AA_STATUSQCH_CON_LH_AXI_MI_D0_RGBP_QCHQCH_CON_LH_AXI_MI_D1_ISPFE_QCHQCH_CON_LH_AXI_MI_D3_ISPFE_QCHDBG_NFO_QCH_CON_D_TZPC_NOCL2AA_QCHDBG_NFO_QCH_CON_LH_AXI_MI_D_GSE_QCHDBG_NFO_QCH_CON_PPMU_NOCL2AB_M1_QCHDBG_NFO_QCH_CON_SLH_AXI_MI_P_HSI0_QCHDBG_NFO_QCH_CON_USI0_HSI0_QCHDBG_NFO_QCH_CON_PCIE_IA_GEN3A_0_QCHDBG_NFO_QCH_CON_LH_AXI_MI_LP_CPUCL0_HSI1_QCHCPUCL1_CLKDIVSTEP_CON_HEAVYPLL_CON0_MUX_CLKCMU_HSI2_PCIE_USERPLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USERQCH_CON_LH_AXI_MI_P_MISC_GIC_CU_QCHQCH_CON_QE_SPDMA0_QCHDBG_NFO_QCH_CON_SLH_AXI_MI_P_MISC_QCHQCH_CON_LH_AXI_SI_LP_CPUCL0_HSI2_CU_QCHQCH_CON_SYSMMU_S0_PMMU0_HSI2_QCHQCH_CON_USI13_USI_QCHDBG_NFO_QCH_CON_USI12_USI_QCHPLL_GSAMUX_CLKCMU_APM_FUNCMUX_CLKCMU_DPUF0_NOCMUX_CLK_GSACTRL_SCMUX_CLK_TPU_TPUCTRL_LPMDIV_CLK_GSACTRL_NOCP_LHDIV_CLK_HSI0_USBDIV_CLK_HSI0_I3CDIV_CLK_HSI0_EUSBDIV_CLK_NOCL2AB_NOCD_LHDIV_CLK_PERIC1_I3CCLK_BLK_AOC_UID_LH_AXI_MI_P_AOC_CU_IPCLKPORT_I_CLKGOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLKGOUT_BLK_APM_UID_APM_USI1_UART_INT_IPCLKPORT_IPCLKCLK_BLK_APM_UID_LH_AXI_MI_LP_ALIVE_CPUCL0_CD_IPCLKPORT_I_CLKCLK_BLK_APM_UID_MAILBOX_AOC_AURCORE0_IPCLKPORT_PCLKCLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_TRACE_CLKCLK_BLK_AUR_UID_ADD_AUR_IPCLKPORT_CLKCLK_BLK_BW_UID_BW_CMU_BW_IPCLKPORT_PCLKCLK_BLK_BW_UID_LH_AXI_SI_IP_BW_IPCLKPORT_I_CLKGATE_CLKCMU_G2D_JPEGGATE_CLKCMU_HSI0_DPOSCGOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLKCLK_BLK_CPUCL0_UID_LH_AXI_SI_G_CSSYS_CD_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AOC_CU_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_CU_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_PPMU_CPUCL0_D3_IPCLKPORT_ACLKCLK_BLK_CPUCL0_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_ACLKCLK_BLK_CPUCL0_UID_BPS_CPUCL0_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_LH_ACEL_MI_D0_NOCL0_CPUCL0_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_LH_ACEL_MI_LD_EH_CPUCL0_IPCLKPORT_I_CLKCLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLKCLK_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_PCLK_IPCLKPORT_CLKCLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_SRAMCGOUT_BLK_EH_UID_SYSMMU_S0_EH_IPCLKPORT_CLKGOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLKGOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_PCLKGOUT_BLK_G2D_UID_AS_APB_JPEG_IPCLKPORT_PCLKMCLK_BLK_G3D_UID_AD_APB_SYSMMU_G3D_IPCLKPORT_PCLKMCLK_BLK_GDC_UID_PPMU_D4_GDC1_IPCLKPORT_PCLKGOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_PCLKGOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_REFCLK_IPCLKPORT_CLKGOUT_BLK_GSACORE_UID_LH_AST_MI_I_GIC_CA32_IPCLKPORT_I_CLKCLK_BLK_GSACORE_UID_RSTNSYNC_SR_CLK_GSACORE_NOCP_IPCLKPORT_CLKCLK_BLK_GSACTRL_UID_XIU_DP1_GSA_ZM_IPCLKPORT_ACLKGOUT_BLK_GSE_UID_SYSMMU_S0_PMMU0_GSE_IPCLKPORT_CLKGOUT_BLK_GSE_UID_GPC_GSE_IPCLKPORT_PCLKCLK_BLK_HSI0_UID_USI3_HSI0_IPCLKPORT_IPCLKGOUT_BLK_HSI1_UID_LH_AXI_MI_P_HSI1_CU_IPCLKPORT_I_CLKGOUT_BLK_HSI1_UID_PCIE_GEN3_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLKGOUT_BLK_HSI2_UID_PCIE_GEN3A_1_IPCLKPORT_PCIE_PHY_TOP_X1_INST_0_PIPE_PAL_PCIE_X1_INST_0_I_APB_PCLKGOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_IPCLKPORT_CLKCLK_BLK_HSI2_UID_LH_AXI_SI_LP_CPUCL0_HSI2_CU_IPCLKPORT_I_CLKCLK_BLK_ISPFE_UID_RSTNSYNC_CLK_ISPFE_OSCCLK_IPTOP_IPCLKPORT_CLKGOUT_BLK_MCSC_UID_QE_D6_MCSC_IPCLKPORT_ACLKGOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_PCLKGOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKMGOUT_BLK_MFC_UID_SYSMMU_S0_PMMU1_MFC_IPCLKPORT_CLKCLK_BLK_MIF_UID_QCH_ADAPTER_SMC_IPCLKPORT_PCLKGOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLKCLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_ACLKCLK_BLK_MISC_UID_SC_IPCLKPORT_I_ACLKGOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLKGOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_LH_ATB_MI_T_SLC_CD_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_LH_TAXI_MI_D_NOCL1B_NOCL0_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_LH_TAXI_MI_D3_NOCL1A_NOCL0_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_DCLKGOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_IPCLKPORT_CLKGOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_GSA_IPCLKPORT_I_CLKGOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLKGOUT_BLK_NOCL2AA_UID_LH_AST_SI_G_NOCL2AA_CD_IPCLKPORT_I_CLKCLK_BLK_NOCL2AA_UID_RSTNSYNC_SR_CLK_NOCL2AA_NOCD_LH_IPCLKPORT_CLKCLK_BLK_NOCL2AA_UID_LH_AST_MI_G_NOCL2AA_CD_IPCLKPORT_I_CLKCLK_BLK_RGBP_UID_SSMT_D0_RGBP_IPCLKPORT_PCLKCLK_BLK_S2D_UID_SLH_AXI_MI_LG_SCAN2DRAM_IPCLKPORT_I_CLKCLK_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_ACLKCLK_BLK_TNR_UID_SYSMMU_S1_TNR_IPCLKPORT_CLKCLK_BLK_TNR_UID_PPMU_D11_TNRA_IPCLKPORT_ACLKCLK_BLK_TNR_UID_XIU_D10_TNR_IPCLKPORT_ACLKGOUT_BLK_TPU_UID_D_TZPC_TPU_IPCLKPORT_PCLKCLK_BLK_TPU_UID_LH_AXI_SI_P_TPU_CU_IPCLKPORT_I_CLKPAD_CLK_APMBAAW_AOC_QCHCMU_TOP_CMUREF_QCHDFTMUX_CMU_QCH_CIS_CLK5CMU_CPUCL0_SHORTSTOP_QCHLH_ATB_MI_LT_AUR_CPUCL0_CU_QCHPPMU_CPUCL0_D1_QCHDPUF0_QCH_SRAMCG2D_CMU_G2D_QCHJPEG_QCHLH_ACEL_SI_D2_G2D_QCHPPMU_G3D_D1_QCHCA32_GSACORE_QCHUSB32DRD_QCH_EUSBPHYSSMT_HSI1_QCHGPIO_HSI2UFS_QCHLH_AXI_MI_LP_CPUCL0_HSI2_QCHLH_AXI_SI_P_HSI2_CU_QCHSSMT_HSI2_QCHMIPI_PHY_LINK_WRAP_QCH_CSIS5QE_D3_ISPFE_QCHSSMT_D0_MFC_QCHSYSREG_MFC_QCHLH_AST_MI_L_IRI_GIC_CLUSTER0_CD_QCHSSMT_DIT_QCHSLH_AXI_SI_P_ALIVE_QCHLH_ACEL_MI_D0_TPU_QCHLH_AXI_MI_P_G3D_CD_QCHLH_AXI_MI_P_HSI1_CD_QCHLH_TAXI_MI_P_NOCL0_NOCL1B_QCHLH_AXI_MI_D3_TNR_QCHTREX_D_NOCL2AB_QCHPERIC1_CMU_PERIC1_QCHLH_AST_SI_L_OTF_RGBP_YUVP_QCHQE_D2_TNR_QCHQE_D7_TNR_QCHLH_AST_SI_L_OTF_YUVP_TNR_QCHQE_D0_YUVP_QCHVCLK_MUX_CLKCMU_CIS_CLK1VCLK_DIV_CLK_CPUCL2_CMUREFVCLK_BLK_NOCL1BVCLK_BLK_GDCVCLK_BLK_MIFVCLK_IP_PPMU_AOCVCLK_IP_LH_AXI_MI_LP_AOC_HSI1_CDVCLK_IP_APM_CMU_APMVCLK_IP_GPC_APMVCLK_IP_MAILBOX_AP_AURCORE0VCLK_IP_MAILBOX_APM_AURVCLK_IP_LH_AXI_MI_LP_ALIVE_CPUCL0_CDVCLK_IP_ADD_APBIF_AURVCLK_IP_LH_AXI_MI_LG_ETR_HSI0_CDVCLK_IP_LH_ATB_MI_T_SLCVCLK_IP_SYSREG_DPUF0VCLK_IP_DPUF1VCLK_IP_AS_P_SYSMMU_S1_NS_EHVCLK_IP_UASC_EHVCLK_IP_GDC1VCLK_IP_PPMU_D4_GDC1VCLK_IP_XIU_D2_GDCVCLK_IP_PPMU_GSACORE0VCLK_IP_LH_AXI_MI_IP_GSAVCLK_IP_HSI0_CMU_HSI0VCLK_IP_QE_UFS_EMBD_HSI2VCLK_IP_SYSMMU_S0_HSI2VCLK_IP_SSMT_D1_MCSCVCLK_IP_QE_D6_MCSCVCLK_IP_BLK_MFC_FRC_OTP_DESERIALVCLK_IP_GEN_WREN_SECUREVCLK_IP_DITVCLK_IP_QE_SPDMA0VCLK_IP_PPC_NOCL1A_M3_EVENTVCLK_IP_PPC_G3D_D3_EVENTVCLK_IP_LH_AXI_SI_P_HSI2_CDVCLK_IP_LH_AXI_MI_D0_ISPFEVCLK_IP_LH_AST_SI_G_NOCL2AA_CDVCLK_IP_SLH_AXI_SI_P_MFCVCLK_IP_SLH_AXI_SI_P_DPUBVCLK_IP_I3C6VCLK_IP_QE_D6_MCFPVCLK_IP_LH_AST_MI_I_RGBP_MCFPVCLK_IP_D_TZPC_TNRVCLK_IP_PPMU_D0_TNRVCLK_IP_QE_D10_TNRAVCLK_IP_QE_D7_TNRVCLK_IP_SSMT_D6_TNRVCLK_IP_PPMU_D1_YUVPBCI3Un-support clk type %x DVFSmargin : %u pmucal_local_enable%s there is no sequence element for pd(%d) power-off.%s %s: DTZPC save smc error. (pd_id : %d)QCH_CON_PPMU_G3D_D3_QCHQCH_CON_SSMT_G3D1_QCHQCH_CON_SYSREG_G3D_QCHDBG_NFO_DMYQCH_CON_ADD_G3D_QCHDBG_NFO_QCH_CON_ADD_APBIF_G3D_QCHDBG_NFO_QCH_CON_SSMT_G3D1_QCHPLL_CON0_MUX_CLKCMU_DPUB_NOC_USERQCH_CON_DPUF0_CMU_DPUF0_QCHQCH_CON_SYSMMU_S0_PMMU0_DPUF0_QCH_S0QCH_CON_DPUF1_QCH_DPUFDBG_NFO_QCH_CON_LH_ACEL_SI_D2_G2D_QCHQCH_CON_GDC1_QCH_C2CLKQCH_CON_QE_D2_GDC0_QCHDBG_NFO_QCH_CON_D_TZPC_GSE_QCHDBG_NFO_QCH_CON_PPMU_D0_MCFP_QCHDBG_NFO_QCH_CON_PPMU_D3_MCFP_QCHQCH_CON_SSMT_D5_TNR_QCHQCH_CON_SYSMMU_S1_TNR_QCH_S0DBG_NFO_QCH_CON_SSMT_D4_TNR_QCHCLK_CON_DIV_CLK_AUR_ADD_CH_CLKCLK_CON_DIV_DIV_CLK_AUR_AURCLK_CON_DIV_DIV_CLK_AUR_NOCP_LHQCH_CON_GPC_AUR_QCHDBG_NFO_QCH_CON_PPMU_D1_AUR_QCHDBG_NFO_QCH_CON_D_TZPC_BW_QCHBW_CMU_BW_CONTROLLER_OPTIONQCH_CON_SLH_AXI_MI_P_EH_QCHQCH_CON_UASC_EH_QCHDBG_NFO_QCH_CON_EH_QCHQCH_CON_LH_AXI_SI_D0_ISPFE_QCHQCH_CON_SSMT_D1_ISPFE_QCHQCH_CON_SYSMMU_S2_PMMU0_ISPFE_QCH_S0TPU_CONFIGURATIONCLK_CON_DIV_DIV_CLK_NOCL0_NOCPDMYQCH_CON_SLC_CH_TOP_QCHQCH_CON_LH_ATB_SI_T_SLC_QCHDBG_NFO_QCH_CON_PPC_NOCL1A_M3_EVENT_QCHDBG_NFO_QCH_CON_PPMU_NOCL0_S0_QCHNOCL1A_CONFIGURATIONDBG_NFO_DMYQCH_CON_CMU_NOCL1A_CMUREF_QCHDBG_NFO_QCH_CON_LH_AXI_SI_P_AUR_CD_QCHDBG_NFO_QCH_CON_LH_TAXI_SI_D3_NOCL1A_NOCL0_QCHDMYQCH_CON_CMU_NOCL1B_CMUREF_QCHQCH_CON_LH_AXI_MI_P_GSA_CD_QCHQCH_CON_NOCL1B_CMU_NOCL1B_QCHNOCL1B_CMU_NOCL1B_CONTROLLER_OPTIONNOCL1B_HCHGEN_CLKMUX_CMUREFQCH_CON_LH_TAXI_MI_P_NOCL0_NOCL2AA_QCHQCH_CON_TREX_P_NOCL2AA_QCHDBG_NFO_QCH_CON_LH_TAXI_MI_P_NOCL0_NOCL2AA_QCHDBG_NFO_QCH_CON_SLH_AXI_SI_P_DPUF1_QCHCLK_CON_DIV_DIV_CLK_HSI0_USB32DRDCLK_CON_MUX_MUX_CLK_HSI0_NOCCLK_CON_MUX_MUX_CLK_HSI0_USI0QCH_CON_DP_LINK_QCH_OSC_CLKQCH_CON_USI3_HSI0_QCHDBG_NFO_QCH_CON_ETR_MIU_QCH_PCLKDBG_NFO_QCH_CON_USB32DRD_QCH_EUSBCTLDBG_NFO_QCH_CON_USB32DRD_QCH_LINKQCH_CON_PCIE_GEN3_0_QCH_UDBGblkpwr_g2dblkpwr_nocl2abblkpwr_hsi0CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USIPLL_CON0_MUX_CLKCMU_MISC_SC_USERPLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USERQCH_CON_MAILBOX_APM_AP_QCHQCH_CON_SYSREG_APM_QCHDBG_NFO_QCH_CON_D_TZPC_APM_QCHDBG_NFO_QCH_CON_LH_AXI_MI_IG_SWD_QCHDBG_NFO_QCH_CON_MAILBOX_AOC_AURMCU_QCHDBG_NFO_QCH_CON_MAILBOX_AP_AURCORE1_QCHDBG_NFO_QCH_CON_SLH_AXI_MI_LP_AOC_ALIVE_QCHDBG_NFO_QCH_CON_SLH_AXI_SI_LG_SCAN2DRAM_QCHDBG_NFO_QCH_CON_SSMT_D_ALIVE_QCHDBG_NFO_QCH_CON_SSMT_LP_ALIVE_CPUCL0_QCHQCH_CON_D_TZPC_MISC_QCHQCH_CON_GPC_MISC_QCHDBG_NFO_QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_QCHDBG_NFO_QCH_CON_SSMT_SPDMA0_QCHDBG_NFO_QCH_CON_LH_AXI_MI_P_HSI2_CU_QCHDBG_NFO_QCH_CON_PCIE_GEN3A_1_QCH_APBDBG_NFO_QCH_CON_PCIE_GEN3A_1_QCH_PMA_APBQCH_CON_USI1_USI_QCHPERIC0_CMU_PERIC0_CONTROLLER_OPTIONMUX_CLKCMU_NOCL1B_NOCMUX_CLKCMU_AUR_NOCMUX_CLK_HSI0_USI3MUX_NOCL2AA_CMUREFMUX_NOCL2AB_CMUREFDIV_CLK_CPUCL0_CPUCLK_BLK_AOC_UID_LH_AXI_MI_LP_AOC_ALIVE_CD_IPCLKPORT_I_CLKGOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLKGOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLKGOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLKCLK_BLK_APM_UID_MAILBOX_AP_AURCORE1_IPCLKPORT_PCLKCLK_BLK_APM_UID_D_TZPC_APM_CUSTOM_IPCLKPORT_PCLKCLK_BLK_APM_UID_SYSREG_APM_CUSTOM_IPCLKPORT_PCLKCLK_BLK_APM_UID_MAILBOX_AOC_AURMCU_IPCLKPORT_PCLKCLK_BLK_AUR_UID_LH_ACEL_SI_D1_AUR_IPCLKPORT_I_CLKCLK_BLK_AUR_UID_BAAW_AUR_IPCLKPORT_I_PCLKCLK_BLK_AUR_UID_UASC_P1_AUR_IPCLKPORT_PCLKGOUT_BLK_BW_UID_SLH_AXI_MI_P_BW_IPCLKPORT_I_CLKGOUT_BLK_BW_UID_UASC_BW_IPCLKPORT_ACLKGATE_CLKCMU_CIS_CLK0GATE_CLKCMU_HSI0_DPGTCCLKCMU_CPUCL2_BOOSTGATE_CLKCMU_EH_NOCCLKCMU_NOCL2AB_BOOSTGOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLKCLK_BLK_CPUCL0_UID_LH_AXI_SI_ID_PPU_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_DBG_IPCLKPORT_CLKCLK_BLK_CPUCL0_UID_APB_ASYNC_P_BOOKER_0_IPCLKPORT_PCLKMCLK_BLK_CPUCL1_UID_ADD1_APBIF_CPUCL1_IPCLKPORT_PCLKCLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_CPU_IPCLKPORT_CLKGOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCP_IPCLKPORT_CLKGOUT_BLK_DPUF0_UID_LH_AXI_SI_D0_DPUF0_IPCLKPORT_I_CLKCLK_BLK_DPUF0_UID_XIU_D1_DPUF0_IPCLKPORT_ACLKCLK_BLK_DPUF1_UID_SLH_AXI_MI_P_DPUF1_IPCLKPORT_I_CLKCLK_BLK_EH_UID_PPC_EH_EVENT_IPCLKPORT_ACLKGOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_ACLKGOUT_BLK_G2D_UID_D_TZPC_G2D_IPCLKPORT_PCLKGOUT_BLK_GDC_UID_LH_AST_SI_ID_GDC1_LME_IPCLKPORT_I_CLKGOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCD_IPCLKPORT_CLKCLK_BLK_GSACTRL_UID_SLH_AXI_MI_P_GSA_IPCLKPORT_I_CLKGOUT_BLK_GSE_UID_GSE_IPCLKPORT_CLK_GSEGOUT_BLK_HSI0_UID_LH_AXI_SI_LD_HSI0_AOC_IPCLKPORT_I_CLKGOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLKGOUT_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_TCA_APB_CLKCLK_BLK_HSI0_UID_LH_AXI_SI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLKCLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_NOC_LH_IPCLKPORT_CLKCLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_APB_CLKGATE_CLK_HSI0_USI4GOUT_BLK_HSI1_UID_AS_APB_PCIEPHY_HSI1_IPCLKPORT_PCLKMGOUT_BLK_HSI2_UID_UASC_PCIE_GEN3B_SLV_1_IPCLKPORT_ACLKCLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN3A_1_IPCLKPORT_ACLKCLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN3B_1_IPCLKPORT_ACLKGOUT_BLK_ISPFE_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS7CLK_BLK_ISPFE_UID_UASC_ISPFE_IPCLKPORT_PCLKGOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLKCLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLKGOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLKGOUT_BLK_MISC_UID_SC_IPCLKPORT_I_PCLKGOUT_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLKGOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_P_NOCL0CLK_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_ACLKCLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF0_CD_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_LH_ACEL_SI_D0_NOCL0_CPUCL0_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_DCLKCLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_SLC3_ACLK_IPCLKPORT_CLKGOUT_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_SLC_DCLK_IPCLKPORT_ACLKCLK_BLK_NOCL0_UID_LH_ACEL_MI_D0_CPUCL0_IPCLKPORT_I_CLKGOUT_BLK_NOCL1A_UID_LH_AXI_SI_P_G3D_CD_IPCLKPORT_I_CLKGOUT_BLK_NOCL1A_UID_PPC_NOCL2AB_S1_EVENT_IPCLKPORT_PCLKCLK_BLK_NOCL1A_UID_PPC_G3DMMU_D_EVENT_IPCLKPORT_ACLKGOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_AOC_CD_IPCLKPORT_I_CLKCLK_BLK_NOCL1B_UID_LH_AST_MI_G_NOCL1B_CD_IPCLKPORT_I_CLKCLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_AOC_IPCLKPORT_I_CLKCLK_BLK_NOCL1B_UID_LH_TAXI_SI_D_NOCL1B_NOCL0_IPCLKPORT_I_CLKGOUT_BLK_NOCL2AA_UID_SYSREG_NOCL2AA_IPCLKPORT_PCLKGOUT_BLK_NOCL2AA_UID_TREX_D_NOCL2AA_IPCLKPORT_PCLKCLK_BLK_NOCL2AB_UID_LH_AXI_MI_D1_G2D_IPCLKPORT_I_CLKCLK_BLK_NOCL2AB_UID_LH_AXI_MI_D2_GDC_IPCLKPORT_I_CLKCLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_IPCLKCLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_PCLKCLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI15_USI_IPCLKPORT_CLKCLK_BLK_RGBP_UID_PPMU_D0_MCFP_IPCLKPORT_PCLKCLK_BLK_RGBP_UID_SYSMMU_S0_PMMU1_RGBP_IPCLKPORT_CLKCLK_BLK_RGBP_UID_SYSMMU_S1_PMMU0_RGBP_IPCLKPORT_CLKCLK_BLK_RGBP_UID_LH_AXI_SI_D5_RGBP_IPCLKPORT_I_CLKGOUT_BLK_TPU_UID_ADM_DAP_G_TPU_IPCLKPORT_DAPCLKMCLK_BLK_TPU_UID_ADD_APBIF_TPU_IPCLKPORT_PCLKGOUT_BLK_YUVP_UID_SYSREG_YUVP_IPCLKPORT_PCLKCLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_ACLKCLK_BLK_YUVP_UID_SSMT_D4_YUVP_IPCLKPORT_PCLKOSCCLK_G3DRTCCLK_HSI0OSCCLK_NOCL0OSCCLK_TNRROM_CRC32_HOST_QCHGPC_AUR_QCHUASC_P0_AUR_QCHBPS_CPUCL0_QCHCLUSTER0_QCH_PERIPHLH_AST_SI_L_IRI_GIC_CLUSTER0_CU_QCHLH_AXI_SI_IG_CSSYS_QCHCPUCL1_QCH_CORE4CLKSYSMMU_S0_PMMU0_DPUF0_QCH_S0SSMT_D0_G2D_QCHLH_ACEL_SI_D2_G3D_QCHPPMU_D2_GDC1_QCHSSMT_D0_GDC0_QCHBAAW_GSACORE_QCHPPMU_GSACORE1_QCHSYSREG_GSACORE_QCHAPBIF_GPIO_GSACTRL_QCHD_TZPC_HSI0_QCHPCIE_GEN3B_1_QCH_AXIUFS_EMBD_QCH_FMPLH_AXI_SI_D1_ISPFE_QCHMIPI_PHY_LINK_WRAP_QCH_CSIS4SYSMMU_S0_PMMU0_ISPFE_QCH_S0SSMT_D1_MCSC_QCHGPC_MIF_QCHLH_AXI_MI_ID_SC_QCHSPDMA1_QCHSSMT_RTIC_QCHLH_ATB_SI_T_SLC_CD_QCHLH_AXI_MI_P_MIF2_CD_QCHSLH_AXI_SI_P_MIF2_QCHTREX_P_NOCL0_QCHLH_AXI_MI_P_AUR_CD_QCHLH_TAXI_SI_D0_NOCL1A_NOCL0_QCHPPC_AUR_D1_EVENT_QCHPPC_NOCL2AB_S0_CYCLE_QCHPPC_NOCL2AB_S1_EVENT_QCHPPC_AOC_EVENT_QCHPPMU_NOCL2AA_M1_QCHSLH_AXI_SI_P_ISPFE_QCHSLH_AXI_SI_P_G2D_QCHPPMU_D3_MCFP_QCHLH_ATB_SI_LT1_TPU_CPUCL0_QCHYUVP_CMU_YUVP_QCHCTRL_OPTION_CMU_DPUBVCLK_MUX_CPUCL0_CMUREFVCLK_MUX_CLKCMU_CIS_CLK4VCLK_CLKCMU_HSI0_PERIVCLK_DIV_CLK_SLC_DCLKVCLK_IP_LH_ACEL_SI_D0_AURVCLK_IP_PPMU_D1_AURVCLK_IP_LH_AXI_SI_IP_BWVCLK_IP_LH_ATB_SI_T_BDU_CUVCLK_IP_CPUCL0_CONVCLK_IP_LH_AXI_MI_ID_PPUVCLK_IP_GPC_DPUF1VCLK_IP_LH_AXI_SI_LD0_DPUF1_DPUF0VCLK_IP_SYSMMU_S0_PMMU2_G2DVCLK_IP_GPUVCLK_IP_BLK_G3D_FRC_OTP_DESERIALVCLK_IP_LH_AXI_MI_LD_RGBP_GDCVCLK_IP_SPI_FPS_GSACOREVCLK_IP_PUF_GSACOREVCLK_IP_LH_AXI_SI_ID_SC_GSACOREVCLK_IP_SSMT_GSACTRLVCLK_IP_SYSMMU_S0_PMMU0_GSEVCLK_IP_SSMT_HSI0VCLK_IP_LH_AXI_MI_P_HSI0_CUVCLK_IP_LH_AXI_MI_P_HSI1_CUVCLK_IP_UASC_PCIE_GEN3B_SLV_1VCLK_IP_AD_APB_SYSMMU_S0_ISPFE_S1_NSVCLK_IP_SYSMMU_S1_PMMU0_ISPFEVCLK_IP_SYSREG_MCSCVCLK_IP_MCSC_CMU_MCSCVCLK_IP_SYSMMU_S0_PMMU0_MCSCVCLK_IP_OTP_CON_TOPVCLK_IP_SSMT_SCVCLK_IP_PUFVCLK_IP_SPDMA1VCLK_IP_LH_ATB_SI_T_SLCVCLK_IP_LH_AXI_SI_P_ALIVE_CDVCLK_IP_LH_AST_MI_G_NOCL2AB_CUVCLK_IP_LH_AXI_MI_D_BWVCLK_IP_LH_AXI_MI_D3_ISPFEVCLK_IP_LH_AXI_MI_D3_RGBPVCLK_IP_SLH_AXI_SI_P_GDCVCLK_IP_PERIC1_CMU_PERIC1VCLK_IP_RGBPVCLK_IP_LH_AXI_SI_D0_RGBPVCLK_IP_BLK_RGBP_FRC_OTP_DESERIALVCLK_IP_SSMT_D0_TNRVCLK_IP_XIU_D4_TNRVCLK_IP_PPMU_D9_TNRVCLK_IP_QE_D1_YUVP6unsupport cmucal sfr node %x 3fixed pll mux change time out, '%s' %s : 0x%x pmucal_tcxo_demand%s %s: mode index(%d) is out of supported range (0~%d).%s %s: there is no sequence element for early_wkup mode(%d).%s %s: DTZPC restore smc error. (pd_id : %d)pmucal_local_init3%s there is no sequence element for cluster(%d) status. 3%s %s: there is no p2vmap. aborting init... pmucal_cpuinform_initPLL_CON4_PLL_G3D_L2PLL_CON8_PLL_G3D_L2QCH_CON_SYSMMU_S0_G3D_QCH_S0DBG_NFO_QCH_CON_LH_ACEL_SI_D3_G3D_QCHG3D_EMBEDDED_CMU_G3D_CONTROLLER_OPTIONDBG_NFO_QCH_CON_GPC_DPUF1_QCHDBG_NFO_QCH_CON_SYSREG_DPUF1_QCHDBG_NFO_QCH_CON_SYSMMU_S0_PMMU2_G2D_QCHQCH_CON_LH_AST_SI_ID_GDC1_LME_QCHDBG_NFO_QCH_CON_LH_AST_MI_ID_GDC1_GDC0_QCHDBG_NFO_QCH_CON_SSMT_D1_GSE_QCHDBG_NFO_QCH_CON_SSMT_D6_MCSC_QCHQCH_CON_PPMU_D4_MCFP_QCHDBG_NFO_QCH_CON_LH_AXI_SI_D4_RGBP_QCHDBG_NFO_QCH_CON_QE_D11_MCFP_QCHDBG_NFO_QCH_CON_QE_D3_RGBP_QCHQCH_CON_TNR_CMU_TNR_QCHTNR_CMU_TNR_CONTROLLER_OPTIONQCH_CON_SLH_AXI_MI_P_AUR_QCHAUR_CLKDIVSTEP_CONQCH_CON_GPC_EH_QCHDBG_NFO_QCH_CON_PPMU_D3_ISPFE_QCHQCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_QCHTPU_CLKDIVSTEP_CON_LIGHTTPU_CLKDIVSTEPQCH_CON_LH_TAXI_MI_D_NOCL1B_NOCL0_QCHDBG_NFO_QCH_CON_LH_ACEL_MI_D2_CPUCL0_QCHDBG_NFO_QCH_CON_PPC_NOCL1A_M0_CYCLE_QCHDBG_NFO_QCH_CON_SLH_AXI_MI_G_NOCL0_QCHQCH_CON_D_TZPC_NOCL1A_QCHQCH_CON_PPC_G3D_D1_EVENT_QCHDBG_NFO_QCH_CON_LH_AXI_SI_P_G3D_CD_QCHDBG_NFO_QCH_CON_PPC_AUR_D0_EVENT_QCHDBG_NFO_QCH_CON_PPC_G3DMMU_D_EVENT_QCHQCH_CON_LH_AXI_SI_P_HSI0_CD_QCHDBG_NFO_QCH_CON_LH_AXI_MI_P_HSI1_CD_QCHDBG_NFO_QCH_CON_LH_AXI_SI_P_HSI1_CD_QCHQCH_CON_LH_ACEL_MI_D2_G2D_QCHQCH_CON_LH_AXI_MI_D0_GDC_QCHQCH_CON_LH_TAXI_MI_P_NOCL0_NOCL2AB_QCHDBG_NFO_DMYQCH_CON_CMU_NOCL2AB_CMUREF_QCHDBG_NFO_QCH_CON_LH_AST_SI_G_NOCL2AB_CD_QCHDBG_NFO_QCH_CON_LH_TAXI_MI_P_NOCL0_NOCL2AB_QCHNOCL2AB_CMU_NOCL2AB_CONTROLLER_OPTIONQCH_CON_USB32DRD_QCH_EUSBPHYHSI1_CONFIGURATIONCLK_CON_DIV_DIV_CLK_HSI1_NOCPDBG_NFO_QCH_CON_LH_AXI_SI_P_HSI1_CU_QCHblkpwr_gseEARLY_WAKEUP_GSE_CTRLGRP27_INTR_BID_CLEARCLK_CON_DIV_DIV_CLK_PERIC0_USI5_USIQCH_CON_SSMT_LP_ALIVE_CPUCL0_QCHDBG_NFO_QCH_CON_APM_USI1_UART_INT_QCHDBG_NFO_QCH_CON_LH_AXI_MI_LP_ALIVE_CPUCL0_CD_QCHDBG_NFO_QCH_CON_MAILBOX_AP_AURMCUNS1_QCHDBG_NFO_QCH_CON_SYSREG_APM_CUSTOM_QCHDMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7QCH_CON_LH_AXI_MI_ID_SC_QCHQCH_CON_QE_SPDMA1_QCHQCH_CON_SLH_AXI_MI_P_MISC_GIC_QCHQCH_CON_SYSREG_MISC_QCHDBG_NFO_QCH_CON_QE_SPDMA0_QCHDBG_NFO_QCH_CON_SSMT_PDMA0_QCHQCH_CON_PCIE_GEN3A_1_QCH_PCS_APBDBG_NFO_QCH_CON_PPMU_HSI2_QCHDBG_NFO_QCH_CON_QE_PCIE_GEN3B_HSI2_QCHDBG_NFO_QCH_CON_SSMT_PCIE_IA_GEN3B_1_QCHDBG_NFO_QCH_CON_SYSMMU_S0_HSI2_QCHQCH_CON_GPIO_PERIC0_QCHDBG_NFO_QCH_CON_PERIC0_CMU_PERIC0_QCHDBG_NFO_QCH_CON_USI3_USI_QCHQCH_CON_PERIC1_CMU_PERIC1_QCHQCH_CON_USI15_USI_QCHPLL_SHARED2_D1MUX_CLKCMU_G2D_JPEGMUX_CLKCMU_HSI0_NOCMUX_CLK_CPUCL0_DSUMUX_CLK_HSI1_NOCMUX_CLKCMU_PERIC1_USI12_USI_USERMUX_CLKCMU_TPU_TPUCTL_USERCLKCMU_CIS_CLK6DIV_CLK_CPUCL0_DBG_PCLKDBGDIV_CLK_CPUCL0_DBG_ATCLK_LHDIV_CLK_GSACORE_UARTDIV_CLK_MISC_NOCP_LHDIV_CLK_NOCL2AA_NOCPDIV_CLK_AUR_AURGOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_ACLKCLK_BLK_AOC_UID_RSTNSYNC_SR_CLK_AOC_NOC_LH_IPCLKPORT_CLKCLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLKCLK_BLK_APM_UID_MAILBOX_AP_AOCA32_IPCLKPORT_PCLKCLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCD_IPCLKPORT_CLKGATE_CLKCMU_MIF_NOCPGATE_CLKCMU_CMU_BOOSTGOUT_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CLUSTER0_GICCLK_IPCLKPORT_CLKCLK_BLK_CPUCL0_UID_LH_AXI_MI_LP_CPUCL0_HSI2_CD_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_LH_AXI_SI_IP_CPUCL2_IPCLKPORT_I_CLKCLK_BLK_DPUF0_UID_XIU_D0_DPUF0_IPCLKPORT_ACLKGOUT_BLK_DPUF1_UID_GPC_DPUF1_IPCLKPORT_PCLKCLK_BLK_DPUF1_UID_SSMT_D1_DPUF1_IPCLKPORT_PCLKGOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_PCLKCLK_BLK_G3D_UID_LH_ACEL_SI_D3_G3D_IPCLKPORT_I_CLKCLK_BLK_G3D_UID_PPCFW_G3D1_IPCLKPORT_PCLKGOUT_BLK_GSACORE_UID_QE_SC_GSACORE_IPCLKPORT_PCLKGOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_I_ACLKGOUT_BLK_GSE_UID_SSMT_D1_GSE_IPCLKPORT_PCLKGOUT_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBSUBCTL_APB_PCLKCLK_BLK_HSI0_UID_LH_AXI_MI_LP_AOC_HSI0_CU_IPCLKPORT_I_CLKCLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_USI0_IPCLKPORT_CLKGOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOCP_IPCLKPORT_CLKCLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLKGOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLKCLK_BLK_HSI2_UID_XIU_D1_HSI2_IPCLKPORT_ACLKCLK_BLK_HSI2_UID_PCIE_GEN3B_1_IPCLKPORT_PCIE_PHY_TOP_X1_INST_0_PHY_UDBG_I_APB_PCLKGOUT_BLK_ISPFE_UID_QE_D0_ISPFE_IPCLKPORT_ACLKGOUT_BLK_ISPFE_UID_QE_D1_ISPFE_IPCLKPORT_ACLKCLK_BLK_ISPFE_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_PHY_S_PCLKGOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_PCLKCLK_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_ACLKGOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_IPCLKPORT_CLKGOUT_BLK_MISC_UID_LH_AXI_MI_ID_SC_IPCLKPORT_I_CLKCLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_ACLKGOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLKGOUT_BLK_NOCL0_UID_PPMU_NOCL0_ALIVE_P_IPCLKPORT_ACLKGOUT_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLKGOUT_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_ACLKGOUT_BLK_NOCL0_UID_GRAY2BIN_ATB_TSVALUE_IPCLKPORT_CLKCLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF1_CD_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL2AA_CU_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL2AB_CU_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_PPMU_NOCL0_DP_IPCLKPORT_PCLKGOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_PCLKCLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD_LH_IPCLKPORT_CLKCLK_BLK_NOCL2AA_UID_SLH_AXI_SI_P_HSI2_IPCLKPORT_I_CLKCLK_BLK_NOCL2AB_UID_LH_AXI_MI_D0_GDC_IPCLKPORT_I_CLKCLK_BLK_NOCL2AB_UID_LH_AST_SI_G_NOCL2AB_IPCLKPORT_I_CLKCLK_BLK_NOCL2AB_UID_RSTNSYNC_CLK_NOCL2AB_NOCP_IPCLKPORT_CLKCLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_IPCLKCLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_PCLKCLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_PCLKCLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_PCLKCLK_BLK_RGBP_UID_RGBP_CMU_RGBP_IPCLKPORT_PCLKCLK_BLK_RGBP_UID_PPMU_D3_MCFP_IPCLKPORT_ACLKCLK_BLK_RGBP_UID_SSMT_D0_MCFP_IPCLKPORT_PCLKCLK_BLK_RGBP_UID_SSMT_D3_MCFP_IPCLKPORT_PCLKCLK_BLK_RGBP_UID_SSMT_D5_MCFP_IPCLKPORT_PCLKCLK_BLK_RGBP_UID_QE_D1_RGBP_IPCLKPORT_ACLKGOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_IPCLKPORT_CLKCLK_BLK_TPU_UID_LH_ACEL_SI_D1_TPU_IPCLKPORT_I_CLKCLK_BLK_YUVP_UID_QE_D1_YUVP_IPCLKPORT_PCLKOSCCLK_CPUCL2OSCCLK_GSEOSCCLK_FRC_NOCL2ABAPBIF_INTCOMB_VGPIO2PMU_QCHLH_AXI_MI_LG_SCAN2DRAM_CD_QCHBAAW_AUR_QCHLH_ATB_MI_LT_AUR_CPUCL0_CD_QCHSSMT_P_AUR_QCHBW_CMU_BW_QCHSYSREG_BW_QCHCLUSTER0_QCH_GCLK0LH_ATB_MI_LT0_TPU_CPUCL0_QCHLH_ATB_MI_LT_GSA_CPUCL0_QCHLH_AXI_SI_IG_HSI0_QCHPPMU_CPUCL0_D3_QCHSLH_AXI_MI_P_DPUB_QCHD_TZPC_EH_QCHGPC_G2D_QCHPPMU_D2_GDC0_QCHSSMT_D4_GDC0_QCHGIC_GSACORE_QCHSLH_AXI_MI_P_HSI2_QCHSYSREG_HSI2_QCHSYSREG_MISC_QCHLH_ATB_MI_T_BDU_CD_QCHLH_ACEL_MI_D1_TPU_QCHPPMU_NOCL1A_M2_QCHSLH_AXI_SI_P_G3D_QCHD_TZPC_NOCL2AA_QCHLH_AXI_SI_D5_RGBP_QCHS2D_CMU_S2D_QCHPPMU_D1_TNR_QCHLH_ACEL_SI_D0_TPU_QCHSSMT_D0_TPU_QCHPPMU_D1_YUVP_QCHYUVP_QCHVCLK_VDD_G3DVCLK_DIV_CLK_APM_USI0_UARTVCLK_DIV_CLK_PERIC0_USI3_USIVCLK_BLK_CPUCL1VCLK_BLK_DPUBVCLK_BLK_DPUF0VCLK_IP_LH_ATB_SI_LT_AOCVCLK_IP_CSSYSVCLK_IP_LH_ATB_MI_LT_AUR_CPUCL0_CUVCLK_IP_ADD0_CPUCL0VCLK_IP_LH_AXI_SI_IP_CPUCL1VCLK_IP_LH_ACEL_SI_D3_CPUCL0VCLK_IP_XIU_D1_DPUF0VCLK_IP_PPMU_D0_DPUF1VCLK_IP_SSMT_G3D0VCLK_IP_LH_AXI_MI_I_DAP_GSAVCLK_IP_GSEVCLK_IP_USI1_HSI0VCLK_IP_USI3_HSI0VCLK_IP_SYSMMU_S0_PMMU1_ISPFEVCLK_IP_SYSMMU_S0_PMMU0_ISPFEVCLK_IP_LH_AST_MI_L_OTF_YUVP_MCSCVCLK_IP_PPMU_D2_MCSCVCLK_IP_SYSREG_MIFVCLK_IP_SSMT_DITVCLK_IP_LH_TAXI_MI_D1_NOCL1A_NOCL0VCLK_IP_LD_SLC_FRC_OTP_DESERIALVCLK_IP_PPC_G3D_D0_EVENTVCLK_IP_NOCL2AB_CMU_NOCL2ABVCLK_IP_SLH_AXI_SI_P_G2DVCLK_IP_SSMT_D0_RGBPTPU6unsupport cmucal node %x DIVra_get_valueidle%s %s: error on handling exit sequence. (mode : %d)%s %s: error on handling restore sequence. (mode : %d)pmucal_system_init3%s cluster index(%d) is out of supported range (0~%d). CLK_CON_DIV_DIV_CLK_G3D_STACKSQCH_CON_LH_AXI_MI_IP_G3D_QCHQCH_CON_PPMU_G3D_D0_QCHQCH_CON_SSMT_G3D2_QCHQCH_CON_SSMT_G3D3_QCHDBG_NFO_QCH_CON_DPUF0_CMU_DPUF0_QCHQCH_CON_SYSMMU_S0_PMMU1_DPUF1_QCH_S0QCH_CON_LH_AXI_SI_D0_G2D_QCHQCH_CON_SYSMMU_S0_G2D_QCHDBG_NFO_QCH_CON_SYSMMU_S0_G2D_QCHPLL_CON0_MUX_CLKCMU_GDC_GDC1_USERQCH_CON_PPMU_D0_GDC1_QCHQCH_CON_SSMT_D1_GSE_QCHMCSC_CONFIGURATIONQCH_CON_SLH_AXI_MI_P_RGBP_QCHDBG_NFO_QCH_CON_LH_AXI_SI_D3_RGBP_QCHDBG_NFO_QCH_CON_SLH_AXI_MI_P_RGBP_QCHCLK_CON_DIV_DIV_CLK_TNR_NOCPQCH_CON_LH_AXI_SI_D0_TNR_QCHQCH_CON_PPMU_D7_TNR_QCHQCH_CON_QE_D9_TNR_QCHQCH_CON_SYSMMU_S0_PMMU1_TNR_QCH_S0DBG_NFO_QCH_CON_LH_AXI_SI_D2_TNR_QCHDBG_NFO_QCH_CON_SSMT_D0_TNR_QCHDBG_NFO_QCH_CON_SYSMMU_S1_PMMU1_TNR_QCH_S0QCH_CON_QE_D1_YUVP_QCHDBG_NFO_QCH_CON_LH_AST_SI_L_OTF_YUVP_GSE_QCHDBG_NFO_QCH_CON_SSMT_D1_YUVP_QCHAUR_STATUSCLK_CON_DIV_DIV_CLK_AUR_AURCTL_LHQCH_CON_BAAW_AUR_QCHQCH_CON_GPC_BW_QCHQCH_CON_LH_AXI_SI_P_EH_CU_QCHDBG_NFO_QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS11PLL_LOCKTIME_REG_PLL_TPUQCH_CON_D_TZPC_TPU_QCHDBG_NFO_QCH_CON_LH_ACEL_SI_D1_TPU_QCHNOCL0_STATUSPLL_CON1_PLL_NOCL0QCH_CON_LH_AXI_MI_P_MIF1_CD_QCHQCH_CON_LH_AXI_SI_P_ALIVE_CD_QCHQCH_CON_LH_AXI_SI_P_MIF1_CD_QCHQCH_CON_PPMU_NOCL0_S2_QCHQCH_CON_SLC_CB_TOP_QCHDBG_NFO_QCH_CON_LH_ATB_MI_T_BDU_CD_QCHDBG_NFO_QCH_CON_PPMU_NOCL0_IOC1_QCHDBG_NFO_QCH_CON_SLC_CB_TOP_QCHQCH_CON_LH_AXI_SI_P_G3D_CD_QCHDBG_NFO_QCH_CON_D_TZPC_NOCL1A_QCHDBG_NFO_QCH_CON_PPC_BW_D_EVENT_QCHDBG_NFO_QCH_CON_SLH_AXI_MI_D_G3DMMU_QCHQCH_CON_D_TZPC_NOCL1B_QCHQCH_CON_SLH_AXI_SI_P_GSA_QCHDBG_NFO_QCH_CON_LH_ACEL_MI_D_HSI1_QCHNOCL2AA_HCHGEN_CLKMUX_CMUREFQCH_CON_LH_AXI_MI_D1_GDC_QCHQCH_CON_PPMU_NOCL2AB_M1_QCHDBG_NFO_QCH_CON_LH_AXI_MI_D_YUVP_QCHDBG_NFO_QCH_CON_PPMU_NOCL2AB_M0_QCHCLK_CON_DIV_DIV_CLK_HSI0_USBPLL_CON0_MUX_CLKCMU_HSI0_USB20_USERQCH_CON_LH_AXI_SI_LP_CPUCL0_HSI1_CU_QCHQCH_CON_SSMT_PCIE_IA_GEN3A_0_QCHCLK_CON_DIV_DIV_CLK_APM_USI0_USICLK_CON_DIV_DIV_CLK_PERIC0_NOCP_LHCLK_CON_DIV_DIV_CLK_PERIC1_USI11_USIPLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USERQCH_CON_MAILBOX_AP_AURMCUNS2_QCHDBG_NFO_QCH_CON_APBIF_GPIO_FAR_ALIVE_QCHDBG_NFO_QCH_CON_MAILBOX_APM_AURMCU_QCHDBG_NFO_QCH_CON_ROM_CRC32_HOST_QCHDMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1DBG_NFO_QCH_CON_SYSMMU_S0_PMMU0_MISC_QCHDBG_NFO_QCH_CON_GPIO_HSI2UFS_QCHDBG_NFO_QCH_CON_SYSMMU_S0_PMMU0_HSI2_QCHQCH_CON_I3C2_QCH_PCLKDBG_NFO_QCH_CON_GPIO_PERIC0_QCHDBG_NFO_DMYQCH_CON_I3C0_QCH_SCLKCLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0MUX_CLKCMU_MFC_MFCMUX_CLKCMU_CPUCL0_DBGMUX_CLKCMU_HSI1_NOCMUX_CLKCMU_HSI2_MMC_CARDMUX_NOCL0_CMUREFMUX_NOCL1B_CMUREFMUX_CLK_TPU_TPUMUX_CLKCMU_PERIC0_NOC_USERMUX_CLKCMU_PERIC0_USI4_USI_USERCLK_AUR_ADD_CH_CLKCLKCMU_PERIC0_NOCCLKCMU_DPUF0_NOCCLKCMU_NOCL0_NOCCLKCMU_G2D_JPEGCLKCMU_CIS_CLK2DIV_CLK_CPUCL0_DBG_NOCDIV_CLK_CLUSTER0_GICCLK_LHDIV_CLK_CLUSTER0_ACLK_NON_MAINDIV_CLK_G3D_NOCPDIV_CLK_GSE_NOCPDIV_CLK_NOCL0_NOCD_LHDIV_CLK_NOCL1A_NOCP_LHDIV_CLK_NOCL1B_NOCD_LHGOUT_BLK_AOC_UID_GPC_AOC_IPCLKPORT_PCLKGOUT_BLK_AOC_UID_LH_AXI_MI_LD_HSI0_AOC_IPCLKPORT_I_CLKGOUT_BLK_AOC_UID_AOC_SYSCTRL_APB_IPCLKPORT_PCLKGOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLKCLK_BLK_BW_UID_LH_AXI_MI_IP_BW_IPCLKPORT_I_CLKGATE_CLKCMU_CIS_CLK5GATE_CLKCMU_DPUB_NOCCLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLKGOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_STM_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_ATCLK_LH_IPCLKPORT_CLKCLK_BLK_CPUCL0_UID_SLH_AXI_MI_LP_ALIVE_CPUCL0_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLKCLK_BLK_CPUCL0_UID_LH_ACEL_SI_D1_CPUCL0_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ICN_NSRESET_IPCLKPORT_CLKGOUT_BLK_DPUF0_UID_SYSMMU_S0_DPUF0_IPCLKPORT_CLKGOUT_BLK_DPUF0_UID_D_TZPC_DPUF0_IPCLKPORT_PCLKCLK_BLK_DPUF0_UID_BLK_DPUF0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLKGOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_PCLKGOUT_BLK_G2D_UID_LH_AXI_SI_D0_G2D_IPCLKPORT_I_CLKGOUT_BLK_G3D_UID_LH_AXI_MI_P_G3D_CU_IPCLKPORT_I_CLKCLK_BLK_G3D_UID_SSMT_G3D3_IPCLKPORT_ACLKCLK_BLK_G3D_UID_SSMT_G3D2_IPCLKPORT_PCLKCLK_BLK_GDC_UID_QE_D4_GDC0_IPCLKPORT_PCLKCLK_BLK_GDC_UID_QE_D4_GDC1_IPCLKPORT_ACLKGOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_PCLKGOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_I_ACLKCLK_BLK_GSACORE_UID_RSTNSYNC_SR_CLK_GSACORE_SPI_GSC_IPCLKPORT_CLKGOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLKCLK_BLK_HSI0_UID_LH_AXI_SI_LP_AOC_HSI0_CU_IPCLKPORT_I_CLKCLK_BLK_HSI0_UID_USI0_HSI0_IPCLKPORT_PCLKCLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_PHY_REFCLK_26GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLKGOUT_BLK_HSI2_UID_XIU_D0_HSI2_IPCLKPORT_ACLKCLK_BLK_HSI2_UID_PCIE_GEN3B_1_IPCLKPORT_PCIE_PHY_TOP_X1_INST_0_PIPE_PAL_PCIE_X1_INST_0_I_APB_PCLKGOUT_BLK_ISPFE_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5GOUT_BLK_ISPFE_UID_QE_D2_ISPFE_IPCLKPORT_ACLKCLK_BLK_MCSC_UID_PPMU_D5_MCSC_IPCLKPORT_ACLKCLK_BLK_MCSC_UID_PPMU_D6_MCSC_IPCLKPORT_ACLKCLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLKCLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLKGOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_ACLKCLK_BLK_MISC_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLKCLK_BLK_MISC_UID_BLK_MISC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLKCLK_BLK_MISC_UID_MCT_SUB_IPCLKPORT_PCLKGOUT_BLK_NOCL0_UID_GPC_NOCL0_IPCLKPORT_PCLKGOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_ACLKCLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF2_CD_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_LH_IPCLKPORT_CLKCLK_BLK_NOCL0_UID_LH_TAXI_MI_D1_NOCL1A_NOCL0_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_BLK_NOCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLKGOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_PCLKCLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLKCLK_BLK_NOCL1A_UID_LH_TAXI_SI_D0_NOCL1A_NOCL0_IPCLKPORT_I_CLKCLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_GSA_IPCLKPORT_I_CLKCLK_BLK_NOCL1B_UID_LH_TAXI_MI_P_NOCL0_NOCL1B_IPCLKPORT_I_CLKCLK_BLK_NOCL2AA_UID_PPMU_NOCL2AA_M0_IPCLKPORT_PCLKCLK_BLK_NOCL2AB_UID_PPMU_NOCL2AB_M0_IPCLKPORT_ACLKCLK_BLK_NOCL2AB_UID_SLH_AXI_SI_P_YUVP_IPCLKPORT_I_CLKCLK_BLK_NOCL2AB_UID_RSTNSYNC_SR_CLK_NOCL2AB_NOCD_IPCLKPORT_CLKGOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLKCLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLKCLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_IPCLKCLK_BLK_RGBP_UID_SYSMMU_S1_PMMU3_RGBP_IPCLKPORT_CLKCLK_BLK_RGBP_UID_QE_D9_MCFP_IPCLKPORT_ACLKCLK_BLK_RGBP_UID_LH_AST_SI_I_RGBP_MCFP_IPCLKPORT_I_CLKGOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLKCLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_LH_IPCLKPORT_CLKGOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLKGOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLKCLK_BLK_TNR_UID_GTNR_MERGE_IPCLKPORT_C2CLKCLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_AXI_IPCLKPORT_CLKGOUT_BLK_YUVP_UID_YUVP_IPCLKPORT_CLKGOUT_BLK_YUVP_UID_LH_AST_SI_L_OTF_YUVP_MCSC_IPCLKPORT_I_CLKGOUT_BLK_YUVP_UID_LH_AST_SI_L_OTF_YUVP_GSE_IPCLKPORT_I_CLKCLK_BLK_YUVP_UID_PPMU_D4_YUVP_IPCLKPORT_ACLKAOC_CMU_AOC_QCHAPBIF_INTCOMB_VGPIO2APM_QCHAPM_USI0_UART_QCHMAILBOX_APM_SWD_QCHAUR_CMU_AUR_QCHLH_ATB_SI_LT_AUR_CPUCL0_QCHDFTMUX_CMU_QCH_CIS_CLK0CLUSTER0_QCH_CORE2LH_ATB_MI_IT1_BOOKER_QCHLH_ATB_MI_T_SLC_QCHLH_ATB_SI_LT1_TPU_CPUCL0_CU_QCHSLH_AXI_MI_P_DPUF1_QCHSYSMMU_S0_PMMU1_DPUF1_QCH_S0SSMT_D2_G2D_QCHSC_GSACORE_QCHLH_AST_MI_L_OTF_YUVP_GSE_QCHI3C2_HSI0_QCH_SCLKPCIE_GEN3_0_QCH_UDBGPCIE_GEN3A_1_QCH_DBGMIPI_PHY_LINK_WRAP_QCH_CSIS6PPMU_D0_ISPFE_QCHPPMU_D2_ISPFE_QCHPPMU_D0_MCSC_QCHRSTNSYNC_CLK_MFC_NOCD_SW_RESET_QCHTMU_SUB_QCHBDU_QCHLH_AXI_MI_P_EH_CD_QCHLH_AXI_MI_P_MIF3_CD_QCHLH_AXI_SI_P_MIF2_CD_QCHPPC_CPUCL0_D0_CYCLE_QCHLH_TAXI_SI_D3_NOCL1A_NOCL0_QCHTREX_D_NOCL1A_QCHPPMU_NOCL1B_M0_QCHLH_AXI_MI_D5_RGBP_QCHLH_AST_MI_G_NOCL2AB_CD_QCHI3C1_QCH_PCLKI3C6_QCH_PCLKGPC_RGBP_QCHQE_D6_RGBP_QCHSYSMMU_S1_PMMU4_RGBP_QCH_S0PPMU_D4_TNR_QCHQE_D0_TNR_QCHQE_D3_TNR_QCHSSMT_D5_TNR_QCHCTRL_OPTION_CMU_HSI0CTRL_OPTION_CMU_TNRVCLK_DIV_CLK_PERIC0_USI1_USIVCLK_MUX_CLKCMU_PERIC1_IPVCLK_IP_APM_USI0_USIVCLK_IP_LH_AXI_SI_LP_AOC_ALIVE_CUVCLK_IP_ADM_DAP_G_AURVCLK_IP_LH_AXI_MI_P_AUR_CUVCLK_IP_LH_AXI_MI_IP_BWVCLK_IP_TREX_D_BWVCLK_IP_LH_AXI_SI_IG_STMVCLK_IP_PPMU_CPUCL0_D2VCLK_IP_LH_AXI_SI_IP_CPUCL2VCLK_IP_PPMU_D0_DPUF0VCLK_IP_BLK_DPUF1_FRC_OTP_DESERIALVCLK_IP_LH_ACEL_SI_D2_G2DVCLK_IP_XIU_D_G2DVCLK_IP_SYSREG_GDCVCLK_IP_GDC0VCLK_IP_GPIO_GSACORE0VCLK_IP_INTMEM_GSACOREVCLK_IP_LH_AXI_SI_IP_AXI2APB1_GSACOREVCLK_IP_SECJTAG_GSACTRLVCLK_IP_BLK_HSI0_FRC_OTP_DESERIALVCLK_IP_LH_AXI_MI_LP_CPUCL0_HSI1VCLK_IP_BLK_HSI2_FRC_OTP_DESERIALVCLK_IP_SLH_AXI_MI_P_ISPFEVCLK_IP_LH_AXI_SI_D0_MCSCVCLK_IP_MFC_CMU_MFCVCLK_IP_LH_ACEL_SI_D_MISCVCLK_IP_QE_DITVCLK_IP_LH_AST_SI_G_NOCL1B_CUVCLK_IP_LH_AST_SI_G_NOCL2AA_CUVCLK_IP_LH_AST_SI_G_NOCL2AB_CUVCLK_IP_PPC_AUR_D1_EVENTVCLK_IP_LH_AST_SI_G_NOCL1AVCLK_IP_LH_ACEL_MI_D0_AURVCLK_IP_LH_TAXI_SI_D0_NOCL1A_NOCL0VCLK_IP_SLH_AXI_SI_P_GSAVCLK_IP_LH_AXI_MI_D6_RGBPVCLK_IP_BLK_NOCL2AA_FRC_OTP_DESERIALVCLK_IP_LH_AST_SI_G_NOCL2AB_CDVCLK_IP_USI4_USIVCLK_IP_I3C3VCLK_IP_QE_D5_MCFPVCLK_IP_SSMT_D0_TPUVCLK_IP_ADM_DAP_G_TPUVCLK_IP_YUVPVCLK_IP_LH_AXI_SI_D_YUVPVCLK_IP_SSMT_D4_YUVP3Un-support clk type %x, rate = %u 3failed %s table %u %-64s : [0x%02x] %6s, %12u Hz, <- %s freq : %u pmucal_cpu_init3%s %s:ioremap failed. 3%s %s:timed out during write-retry. (value:0x%x, seq_idx = %d) PLL_LOCKTIME_PLL_G3D_L2PLL_CON6_PLL_G3D_L2QCH_CON_DPUB_QCH_OSC_DSIM0QCH_CON_GPC_DPUB_QCHDBG_NFO_QCH_CON_GPC_DPUB_QCHG2D_CONFIGURATIONCLK_CON_DIV_DIV_CLK_G2D_NOCPQCH_CON_SSMT_D0_G2D_QCHGDC_STATUSPLL_CON0_MUX_CLKCMU_GDC_LME_USERQCH_CON_LH_AST_SI_ID_LME_GDC1_QCHQCH_CON_LME_QCH_CLKQCH_CON_QE_D4_GDC1_QCHQCH_CON_SSMT_D4_GDC1_QCHMCSC_STATUSQCH_CON_PPMU_D2_MCSC_QCHQCH_CON_SYSREG_MCSC_QCHDBG_NFO_QCH_CON_PPMU_D0_MCSC_QCHQCH_CON_PPMU_D1_MFC_QCHQCH_CON_QE_D2_RGBP_QCHQCH_CON_LH_AXI_SI_D4_TNR_QCHDBG_NFO_QCH_CON_LH_AXI_SI_D0_TNR_QCHDBG_NFO_QCH_CON_SSMT_D7_TNR_QCHQCH_CON_SYSREG_YUVP_QCHPLL_LOCKTIME_REG_PLL_AURPLL_CON2_PLL_AURPLL_CON0_MUX_CLKCMU_AUR_SWITCH_USERDBG_NFO_QCH_CON_LH_ACEL_SI_D1_AUR_QCHDBG_NFO_QCH_CON_PPMU_D0_AUR_QCHDBG_NFO_QCH_CON_SSMT_D1_AUR_QCHPLL_CON0_MUX_CLKCMU_EH_NOC_USERQCH_CON_SSMT_EH_QCHQCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS7DBG_NFO_QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0DBG_NFO_QCH_CON_QE_D2_ISPFE_QCHDBG_NFO_QCH_CON_SYSREG_ISPFE_QCHTPU_STATUSCLK_CON_MUX_MUX_CLK_TPU_TPUCTLQCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_QCHQCH_CON_LH_AXI_SI_P_TPU_CU_QCHDBG_NFO_QCH_CON_PPMU_D0_TPU_QCHTPU_SHORTSTOPDBG_NFO_QCH_CON_LH_ACEL_SI_D1_NOCL0_CPUCL0_QCHDBG_NFO_QCH_CON_LH_AXI_SI_P_MIF2_CD_QCHDBG_NFO_QCH_CON_SLH_AXI_SI_P_EH_QCHNOCL0_EMBEDDED_CMU_NOCL02_CONTROLLER_OPTIONQCH_CON_LH_AXI_MI_P_TPU_CD_QCHQCH_CON_PPC_AUR_D1_EVENT_QCHQCH_CON_PPC_TPU_D1_EVENT_QCHQCH_CON_SLH_AXI_SI_P_AOC_QCHDBG_NFO_QCH_CON_LH_AXI_MI_P_AOC_CD_QCHQCH_CON_NOCL2AA_CMU_NOCL2AA_QCHDBG_NFO_DMYQCH_CON_CMU_NOCL2AA_CMUREF_QCHDBG_NFO_QCH_CON_LH_AXI_MI_D1_MFC_QCHDBG_NFO_QCH_CON_LH_ACEL_MI_D_MISC_QCHDBG_NFO_QCH_CON_SLH_AXI_SI_P_MCSC_QCHPLL_CON2_PLL_USBQCH_CON_HSI0_CMU_HSI0_QCHQCH_CON_USB32DRD_QCH_LINKDBG_NFO_QCH_CON_D_TZPC_HSI0_QCHQCH_CON_PCIE_GEN3_0_QCH_PCS_APBblkpwr_aurblkpwr_bwCPUCL2_CLKDIVSTEP_SMPL_FLTCLK_CON_DIV_DIV_CLK_PERIC0_USI3_USIPLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USERQCH_CON_APBIF_GPIO_ALIVE_QCHQCH_CON_LH_AXI_SI_P_ALIVE_CU_QCHQCH_CON_MAILBOX_AOC_AURCORE1_QCHQCH_CON_SYSMMU_S0_ALIVE_QCHQCH_CON_SYSREG_APM_CUSTOM_QCHDBG_NFO_QCH_CON_GPC_APM_QCHDBG_NFO_QCH_CON_LH_AXI_SI_D_ALIVE_QCHQCH_CON_SSMT_SPDMA0_QCHDBG_NFO_QCH_CON_PDMA1_QCHDBG_NFO_QCH_CON_SSMT_PDMA1_QCHQCH_CON_GPIO_HSI2_QCHQCH_CON_PCIE_GEN3A_1_QCH_UDBGQCH_CON_UASC_PCIE_GEN3B_SLV_1_QCHDBG_NFO_QCH_CON_UASC_PCIE_GEN3A_SLV_1_QCHDBG_NFO_DMYQCH_CON_I3C3_QCH_SCLKDBG_NFO_QCH_CON_PERIC1_CMU_PERIC1_QCHCPUCL0_EMBEDDED_CMU_CPUCL0_CONTROLLER_OPTIONTOP_OUTPLL_MIF_MAINMUX_CLKCMU_GDC_GDC1MUX_CLKCMU_MISC_SCMUX_CLKCMU_CPUCL1_SWITCH_USERMUX_CLKCMU_PERIC1_USI0_USI_USERCLKCMU_HSI1_NOCCLKCMU_HSI2_PCIECLKCMU_CIS_CLK3CLKCMU_HSI2_NOCCLKCMU_DPUF1_NOCCLK_G3D_ADD_CH_CLKDIV_CLK_G3D_NOCP_LHDIV_CLK_HSI0_USI2DIV_CLK_MIF_NOCP_LHDIV_CLK_SLC3_DCLKDIV_CLK_TPU_NOCP_LHDIV_CLK_CPUCL0_BCIGOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLKCLK_BLK_APM_UID_MAILBOX_AP_AURMCUNS0_IPCLKPORT_PCLKCLK_BLK_APM_UID_XIU_D_ALIVE_IPCLKPORT_ACLKCLK_BLK_APM_UID_PMU_IPCLKPORT_ACLKCLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_PCLKCLK_BLK_AUR_UID_SYSREG_AUR_IPCLKPORT_PCLKCLK_BLK_AUR_UID_ADM_DAP_G_AUR_IPCLKPORT_DAPCLKMGOUT_BLK_BW_UID_SSMT_BW_IPCLKPORT_PCLKCLK_BLK_BW_UID_XIU_D_BW_IPCLKPORT_ACLKGATE_CLKCMU_CIS_CLK6GATE_CLKCMU_DNS_NOCGATE_CLKCMU_DPUF1_NOCGOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT1_BOOKER_IPCLKPORT_I_CLKGOUT_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CLUSTER0_SCLK_IPCLKPORT_CLKCLK_BLK_CPUCL0_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_APB_ASYNC_P_PCSM_IPCLKPORT_PCLKMCLK_BLK_CPUCL0_UID_PPMU_CPUCL0_D1_IPCLKPORT_ACLKCLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCP_IPCLKPORT_CLKCLK_BLK_DPUF0_UID_RSTNSYNC_SR_CLK_DPUF0_NOCP_IPCLKPORT_CLKCLK_BLK_DPUF1_UID_RSTNSYNC_SR_CLK_DPUF1_NOCP_IPCLKPORT_CLKGOUT_BLK_EH_UID_AS_P_SYSMMU_S1_NS_EH_IPCLKPORT_PCLKMCLK_BLK_EH_UID_SYSMMU_S0_PMMU0_EH_IPCLKPORT_CLKGOUT_BLK_G2D_UID_AS_APB_G2D_IPCLKPORT_PCLKMGOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLKCLK_BLK_G3D_UID_GPU_IPCLKPORT_CLKCLK_BLK_G3D_UID_SYSMMU_S0_G3D_IPCLKPORT_CLKGOUT_BLK_GDC_UID_SYSMMU_S0_PMMU0_GDC_IPCLKPORT_CLKCLK_BLK_GSACORE_UID_LH_AXI_MI_ID_SC_GSACORE_IPCLKPORT_I_CLKCLK_BLK_GSACTRL_UID_LH_AXI_MI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLKCLK_BLK_GSACTRL_UID_AD_APB_SYSMMU_GSA_S1_NS_IPCLKPORT_PCLKMCLK_BLK_GSACTRL_UID_SSMT_GSACTRL_IPCLKPORT_ACLKGOUT_BLK_GSE_UID_SSMT_D2_GSE_IPCLKPORT_ACLKCLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLKGOUT_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USB32DRD_REF_CLK_40CLK_HSI0_ALTCLK_BLK_HSI0_UID_LH_AXI_MI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLKCLK_BLK_HSI1_UID_LH_AXI_MI_LP_AOC_HSI1_CU_IPCLKPORT_I_CLKGOUT_BLK_ISPFE_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0GOUT_BLK_ISPFE_UID_QE_D0_ISPFE_IPCLKPORT_PCLKCLK_BLK_ISPFE_UID_RSTNSYNC_SR_CLK_ISPFE_NOCP_IPCLKPORT_CLKGOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLKCLK_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_ACLKGOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_ACLKGOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLKGOUT_BLK_MISC_UID_QE_SC_IPCLKPORT_ACLKCLK_BLK_MISC_UID_RSTNSYNC_SR_CLK_MISC_GIC_LH_IPCLKPORT_CLKCLK_BLK_MISC_UID_RSTNSYNC_SR_CLK_MISC_NOCP_IPCLKPORT_CLKGOUT_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_LH_TAXI_MI_D0_NOCL1A_NOCL0_IPCLKPORT_I_CLKCLK_BLK_NOCL0_UID_PPMU_NOCL0_IOC0_IPCLKPORT_ACLKCLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLKGOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLKCLK_BLK_NOCL2AB_UID_TREX_P_NOCL2AB_IPCLKPORT_ACLK_P_NOCL2ABGOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLKCLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_NOCP_IPCLKPORT_CLKGOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLKCLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_IPCLKCLK_BLK_RGBP_UID_SSMT_D1_RGBP_IPCLKPORT_ACLKCLK_BLK_RGBP_UID_QE_D7_MCFP_IPCLKPORT_PCLKCLK_BLK_S2D_UID_RSTNSYNC_SR_CLK_S2D_CORE_IPCLKPORT_CLKCLK_BLK_YUVP_UID_QE_D1_YUVP_IPCLKPORT_ACLKCLK_BLK_YUVP_UID_QE_D4_YUVP_IPCLKPORT_PCLKOSCCLK_BWOSCCLK_FRC_MIFSLH_AXI_SI_LP_AOC_ALIVE_QCHMAILBOX_AOC_AURCORE0_QCHPMU_QCHRSTNSYNC_CLK_APM_GREBE_DBGCORE_QCHLH_ATB_MI_LT_AUR_CPUCL0_QCHLH_ATB_MI_T_SLC_CU_QCHLH_ATB_SI_LT_AOC_CU_QCHGPC_EH_QCHSYSMMU_S0_PMMU0_EH_QCHSSMT_G3D2_QCHSYSMMU_S0_G3D_QCH_S0QE_D0_GDC1_QCHQE_D4_GDC0_QCHLH_ATB_MI_LT_GSA_CPUCL0_CD_QCHPPMU_GSACORE0_QCHETR_MIU_QCH_ACLKLH_AXI_SI_LD_HSI0_AOC_QCHLH_AXI_SI_P_HSI0_CU_QCHUSI2_HSI0_QCHPCIE_GEN3_0_QCH_APBPCIE_IA_GEN3A_0_QCHD_TZPC_HSI2_QCHPCIE_GEN3A_1_QCH_REFLH_AXI_SI_D0_ISPFE_QCHLH_AXI_SI_D3_ISPFE_QCHSYSMMU_S0_PMMU1_ISPFE_QCH_S0LH_AXI_SI_D1_MFC_QCHGEN_WREN_SECURE_QCHPPMU_MISC_QCHQE_SPDMA1_QCHGPC_NOCL0_QCHLH_AXI_SI_P_CPUCL0_CD_QCHLH_AXI_SI_P_EH_CD_QCHLH_AXI_SI_P_MIF1_CD_QCHLH_TAXI_SI_P_NOCL0_NOCL2AB_QCHNOCL0_CMU_NOCL0_QCHPPMU_NOCL0_IOC1_QCHSLH_AXI_SI_P_MIF3_QCHLH_ACEL_MI_D_MISC_QCHLH_AXI_MI_D2_TNR_QCHI3C4_QCH_PCLKSYSREG_PERIC0_QCHQE_D11_MCFP_QCHD_TZPC_TPU_QCHCTRL_OPTION_CMU_HSI1CTRL_OPTION_CMU_TPUVCLK_VDD_TPUVCLK_MUX_CLKCMU_CIS_CLK7VCLK_BLK_CMUVCLK_BLK_HSI2VCLK_IP_D_TZPC_AOCVCLK_IP_SSMT_AOCVCLK_IP_LH_AXI_SI_LP_AOC_ALIVE_CDVCLK_IP_SYSMMU_S0_AOCVCLK_IP_SLH_AXI_SI_LP_ALIVE_CPUCL0VCLK_IP_PMUVCLK_IP_SSMT_D1_AURVCLK_IP_LH_ATB_SI_LT_GSA_CPUCL0_CUVCLK_IP_LH_ATB_MI_LT0_TPU_CPUCL0_CUVCLK_IP_LH_ATB_MI_LT1_TPU_CPUCL0_CUVCLK_IP_LH_AXI_MI_IG_CSSYSVCLK_IP_DPUF1_CMU_DPUF1VCLK_IP_SLH_AXI_MI_P_DPUF1VCLK_IP_PPMU_D1_DPUF1VCLK_IP_LH_AST_SI_ID_G2D1_JPEGVCLK_IP_LH_AST_MI_ID_JPEG_G2D0VCLK_IP_LH_AXI_MI_IP_G3DVCLK_IP_D_TZPC_GDCVCLK_IP_SYSMMU_S0_GSEVCLK_IP_SYSMMU_S0_PMMU1_MCSCVCLK_IP_SLH_AXI_MI_P_MFCVCLK_IP_SSMT_SPDMA1VCLK_IP_OTP_CON_BISRVCLK_IP_SYSREG_NOCL0VCLK_IP_PPMU_NOCL0_IOC1VCLK_IP_LH_TAXI_MI_D0_NOCL2AB_NOCL1AVCLK_IP_LH_TAXI_MI_D1_NOCL2AB_NOCL1AVCLK_IP_PPC_NOCL2AB_S0_CYCLEVCLK_IP_NOCL1A_CMU_NOCL1AVCLK_IP_LH_AXI_MI_D_AOCVCLK_IP_LH_AST_SI_G_NOCL1BVCLK_IP_PPMU_NOCL1B_M0VCLK_IP_LH_AST_MI_G_NOCL2AA_CDVCLK_IP_SLH_AXI_SI_P_HSI2VCLK_IP_PPMU_NOCL2AB_M0VCLK_IP_LH_AXI_MI_D_GSEVCLK_IP_LH_AST_SI_I_RGBP_MCFPVCLK_IP_LH_AXI_SI_D2_TNRVCLK_IP_QE_D11_TNRAVCLK_IP_XIU_D2_TNRVCLK_IP_XIU_D6_TNRVCLK_IP_XIU_D11_TNRVCLK_IP_LH_AXI_MI_P_TPU_CUVCLK_IP_LH_ATB_MI_LT0_TPU_CPUCL0_CDVCLK_IP_LH_AST_SI_L_OTF_YUVP_TNR3%s:[%d] latency = %llu ret = %dfvmap_marginmargin_big_write_fileCAL_PM_ENTER_%d3samsung_cal_if_driver probe failed. dvfs6%s:failed idx:%x vclk_num_list - CMU_TOP DIV info %s %s: error on handling elry_wkup sequence. (mode : %d)3%s %s: there is no lpm init seq or lpm list. aborting init... DBG_NFO_QCH_CON_GPU_QCHDBG_NFO_QCH_CON_SYSMMU_S0_PMMU1_G3D_QCH_S0G3D_CLKDIVSTEP_CON_LIGHTDPUB_STATUSDBG_NFO_QCH_CON_D_TZPC_DPUB_QCHQCH_CON_LH_AXI_MI_LD0_DPUF1_DPUF0_QCHQCH_CON_SYSMMU_S0_PMMU1_DPUF0_QCH_S0QCH_CON_LH_AXI_SI_LD1_DPUF1_DPUF0_QCHPLL_CON0_MUX_CLKCMU_G2D_JPEG_USERQCH_CON_PPMU_D0_G2D_QCHQCH_CON_SLH_AXI_MI_P_G2D_QCHQCH_CON_SYSREG_G2D_QCHDBG_NFO_QCH_CON_PPMU_D0_G2D_QCHDBG_NFO_QCH_CON_SSMT_D2_G2D_QCHQCH_CON_LH_AST_SI_ID_GDC1_GDC0_QCHQCH_CON_SSMT_D2_GDC0_QCHQCH_CON_SSMT_D4_GDC0_QCHDBG_NFO_QCH_CON_GDC0_QCH_C2CLKDBG_NFO_QCH_CON_PPMU_D2_GDC1_QCHDBG_NFO_QCH_CON_SSMT_D_LME_QCHDBG_NFO_QCH_CON_SYSMMU_S0_GDC_QCH_S0QCH_CON_D_TZPC_GSE_QCHCLK_CON_DIV_DIV_CLK_MCSC_NOCPQCH_CON_LH_AXI_SI_D0_MCSC_QCHQCH_CON_PPMU_D3_MCSC_QCHQCH_CON_QE_D5_MCSC_QCHMCSC_CMU_MCSC_CONTROLLER_OPTIONQCH_CON_SSMT_D1_MFC_QCHDBG_NFO_QCH_CON_LH_AXI_SI_D1_MFC_QCHQCH_CON_SYSMMU_S1_PMMU4_RGBP_QCH_S0QCH_CON_PPMU_D11_TNRA_QCH_S0DBG_NFO_QCH_CON_PPMU_D10_TNRA_QCH_S0DBG_NFO_QCH_CON_SSMT_D1_TNR_QCHDBG_NFO_QCH_CON_SYSMMU_S1_PMMU2_TNR_QCH_S0AOC_CMU_AOC_CONTROLLER_OPTIONPLL_CON0_MUX_CLKCMU_AUR_AURCTL_USERDBG_NFO_QCH_CON_LH_ACEL_SI_D0_AUR_QCHDBG_NFO_QCH_CON_SYSREG_AUR_QCHDBG_NFO_QCH_CON_GPC_EH_QCHQCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS11QCH_CON_LH_ACEL_SI_D1_TPU_QCHQCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CD_QCHQCH_CON_SSMT_D1_TPU_QCHDBG_NFO_QCH_CON_LH_ACEL_SI_D0_TPU_QCHDMYQCH_CON_CMU_NOCL0_CMUREF_QCHDMYQCH_CON_SLC_CH1_QCHQCH_CON_GPC_NOCL0_QCHQCH_CON_LH_AXI_MI_P_MISC_CD_QCHQCH_CON_SLH_AXI_SI_P_CPUCL0_QCHDBG_NFO_QCH_CON_PPC_NOCL1A_M0_EVENT_QCHDBG_NFO_QCH_CON_SLH_AXI_SI_P_PERIC0_QCHQCH_CON_LH_ACEL_MI_D1_AUR_QCHQCH_CON_PPC_BW_D_EVENT_QCHQCH_CON_D_TZPC_NOCL2AA_QCHQCH_CON_LH_AST_SI_G_NOCL2AA_CD_QCHDBG_NFO_QCH_CON_TREX_P_NOCL2AA_QCHQCH_CON_LH_AST_SI_G_NOCL2AB_QCHQCH_CON_LH_AXI_MI_D1_G2D_QCHQCH_CON_SLH_AXI_SI_P_YUVP_QCHDBG_NFO_QCH_CON_LH_AXI_MI_D0_MCSC_QCHDBG_NFO_QCH_CON_SYSREG_NOCL2AB_QCHHSI0_STATUSPLL_LOCKTIME_REG_PLL_USBQCH_CON_DP_LINK_QCH_PCLKDMYQCH_CON_PCIE_GEN3_0_QCH_REFDBG_NFO_QCH_CON_LH_AXI_MI_LP_AOC_HSI1_CU_QCHGRP31_INTR_BID_CLEARCLK_CON_DIV_DIV_CLK_PERIC1_I3CPLL_CON0_MUX_CLKCMU_PERIC1_I3C_USERQCH_CON_APBIF_INTCOMB_VGPIO2AP_QCHQCH_CON_MAILBOX_AOC_AURMCU_QCHQCH_CON_MAILBOX_AP_AURCORE2_QCHQCH_CON_SS_DBGCORE_QCH_GREBEQCH_CON_TRTC_QCHDBG_NFO_QCH_CON_LH_AXI_MI_P_ALIVE_CU_QCHDBG_NFO_QCH_CON_MAILBOX_AP_AOCP6_QCHQCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_QCHQCH_CON_LH_AXI_MI_P_MISC_CU_QCHQCH_CON_MCT_SUB_QCHDBG_NFO_QCH_CON_MISC_CMU_MISC_QCHDBG_NFO_QCH_CON_OTP_CON_TOP_QCHQCH_CON_D_TZPC_HSI2_QCHDBG_NFO_QCH_CON_HSI2_CMU_HSI2_QCHDBG_NFO_QCH_CON_UASC_PCIE_GEN3A_DBI_1_QCHCLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT0MUX_CLKCMU_G2D_G2DCLK_CPUCL0_BCI_SHORTSTOP_SYNCMUX_CLKCMU_AUR_SWITCH_USERMUX_CLKCMU_CPUCL0_DBG_NOC_USERCLKCMU_HSI0_DPGTCCLKCMU_CPUCL1_SWITCHCLKCMU_HSI0_NOCCLKCMU_AUR_AURDIV_CLK_CPUCL0_CMUREFDIV_CLK_HSI0_NOC_LHGOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_PCLKCLK_BLK_AOC_UID_LH_AXI_SI_LP_AOC_HSI0_CD_IPCLKPORT_I_CLKGOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLKCLK_BLK_APM_UID_SLH_AXI_MI_P_ALIVE_IPCLKPORT_I_CLKCLK_BLK_APM_UID_MAILBOX_TPU_AURMCU_IPCLKPORT_PCLKGATE_CLKCMU_PERIC0_NOCCLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_IPCLKPORT_I_CLKCLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CLUSTER0_PPUCLK_IPCLKPORT_CLKCLK_BLK_CPUCL0_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLKCLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLKGATE_CLK_CLUSTER0_GICCLKCLK_BLK_CPUCL0_UID_GRAY2BIN_TSVALUEB_IPCLKPORT_CLKCLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLKGOUT_BLK_DPUF1_UID_PPMU_D0_DPUF1_IPCLKPORT_ACLKGOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCD_IPCLKPORT_CLKCLK_BLK_EH_UID_BLK_EH_FRC_OTP_DESERIAL_IPCLKPORT_I_CLKGOUT_BLK_G3D_UID_LH_AXI_SI_IP_G3D_IPCLKPORT_I_CLKGOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLKCLK_BLK_GDC_UID_XIU_D0_GDC_IPCLKPORT_ACLKCLK_BLK_GDC_UID_RSTNSYNC_SR_CLK_GDC_NOCP_IPCLKPORT_CLKGOUT_BLK_GSACORE_UID_QE_SC_GSACORE_IPCLKPORT_ACLKCLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLKCLK_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SC_IPCLKPORT_CLKGOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AUR_IPCLKPORT_PCLKGOUT_BLK_GSACTRL_UID_APBIF_GPIO_GSACTRL_IPCLKPORT_PCLKCLK_BLK_GSACTRL_UID_RSTNSYNC_SR_CLK_GSACTRL_NOCD_IPCLKPORT_CLKGOUT_BLK_GSE_UID_SSMT_D2_GSE_IPCLKPORT_PCLKGOUT_BLK_GSE_UID_QE_D2_GSE_IPCLKPORT_PCLKCLK_BLK_HSI0_UID_LH_AXI_SI_P_HSI0_CU_IPCLKPORT_I_CLKGOUT_BLK_HSI1_UID_UASC_PCIE_GEN3A_DBI_0_IPCLKPORT_ACLKCLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_NOC_LH_IPCLKPORT_CLKGOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLKCLK_BLK_ISPFE_UID_SSMT_D2_ISPFE_IPCLKPORT_PCLKGOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLKCLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLKGOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_ACLKGOUT_BLK_MISC_UID_SSMT_SC_IPCLKPORT_PCLKCLK_BLK_MISC_UID_XIU_D1_MISC_IPCLKPORT_ACLKGOUT_BLK_NOCL0_UID_LH_ACEL_MI_D1_CPUCL0_IPCLKPORT_I_CLKGOUT_BLK_NOCL0_UID_PPMU_NOCL0_ALIVE_P_IPCLKPORT_PCLKCLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_OSCCLK_IPCLKPORT_CLKCLK_BLK_NOCL0_UID_PPMU_NOCL0_IOC0_IPCLKPORT_PCLKCLK_BLK_NOCL0_UID_PPMU_NOCL0_S1_IPCLKPORT_PCLKCLK_BLK_NOCL0_UID_PPMU_NOCL0_S2_IPCLKPORT_PCLKCLK_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_PCLKCLK_BLK_NOCL0_UID_PPC_NOCL0_IO0_EVENT_IPCLKPORT_ACLKGOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLKGOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_ACLKGOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_AOC_IPCLKPORT_I_CLKCLK_BLK_NOCL2AB_UID_LH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLKCLK_BLK_RGBP_UID_PPMU_D2_RGBP_IPCLKPORT_PCLKGOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLKGOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_PCLKCLK_BLK_TNR_UID_LH_AXI_SI_D5_TNR_IPCLKPORT_I_CLKGOUT_BLK_TPU_UID_PPMU_D0_TPU_IPCLKPORT_PCLKGOUT_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_ACLKGOUT_BLK_YUVP_UID_SSMT_D0_YUVP_IPCLKPORT_ACLKOSCCLK_GSAPPMU_AOC_QCHSLH_AXI_MI_P_AOC_QCHPPMU_D1_AUR_QCHPPMU_BW_QCHDFTMUX_CMU_QCH_CIS_CLK1OTP_QCHLH_AST_MI_L_IRI_GIC_CLUSTER0_CU_QCHLH_ATB_MI_LT_AOC_CU_QCHLH_AXI_MI_LP_CPUCL0_HSI2_CD_QCHLH_AXI_SI_IG_BOOKER_QCHLH_AXI_SI_P_CPUCL0_CU_QCHSLH_AXI_MI_P_CPUCL0_QCHDPUB_QCH_ALV_DSIM1LH_AST_MI_ID_G2D0_JPEG_QCHLH_AST_MI_ID_G2D1_JPEG_QCHG3D_CMU_G3D_QCHSSMT_G3D3_QCHSYSMMU_S0_PMMU1_G3D_QCH_S0QE_D0_GDC0_QCHSYSMMU_S0_PMMU0_GDC_QCH_S0LH_AXI_MI_IP_AXI2APB2_GSACORE_QCHLH_AXI_SI_IP_AXI2APB2_GSACORE_QCHLH_AXI_SI_D_GSA_QCHLH_AXI_MI_LP_CPUCL0_HSI1_QCHPCIE_GEN3B_1_QCH_DBGMCSC_QCH_C2RMFC_QCHSLH_AXI_MI_P_MIF_QCHSYSREG_MIF_QCHPDMA1_QCHQE_SPDMA0_QCHLH_ACEL_MI_D1_CPUCL0_QCHLH_ATB_MI_T_SLC_CD_QCHLH_AXI_SI_P_PERIC0_CD_QCHSLH_AXI_SI_P_MIF0_QCHLH_AXI_MI_D_BW_QCHLH_AXI_MI_P_TPU_CD_QCHLH_TAXI_MI_D0_NOCL2AB_NOCL1A_QCHD_TZPC_NOCL1B_QCHLH_AST_SI_G_NOCL1B_QCHLH_AXI_SI_LD_RGBP_GDC_QCHPPMU_D4_MCFP_QCHBIS_S2D_QCHPPMU_D5_TNR_QCHQE_D10_TNRA_QCHSLH_AXI_MI_P_TPU_QCHSSMT_D1_YUVP_QCHVCLK_VDD_MIFVCLK_DIV_CLK_HSI0_USI0VCLK_DIV_CLK_PERIC0_USI2_USIVCLK_BLK_HSI1VCLK_IP_TRTCVCLK_IP_APBIF_GPIO_FAR_ALIVEVCLK_IP_MAILBOX_TPU_AURMCUVCLK_IP_GPC_AURVCLK_IP_SLH_AXI_MI_P_AURVCLK_IP_XIU_D_AURVCLK_IP_BLK_AUR_FRC_OTP_DESERIALVCLK_IP_BLK_BW_FRC_OTP_DESERIALVCLK_IP_LH_AXI_SI_IG_CSSYSVCLK_IP_LH_ACEL_MI_D0_NOCL0_CPUCL0VCLK_IP_DPUF0VCLK_IP_PPMU_D0_G2DVCLK_IP_GPC_G2DVCLK_IP_BLK_G2D_FRC_OTP_DESERIALVCLK_IP_UASC_G3DVCLK_IP_LH_ACEL_SI_D2_G3DVCLK_IP_SYSMMU_S0_PMMU3_G3DVCLK_IP_DAP_GSACTRLVCLK_IP_GSE_CMU_GSEVCLK_IP_PPMU_D0_GSEVCLK_IP_UASC_HSI0_LINKVCLK_IP_USI2_HSI0VCLK_IP_PPMU_D0_ISPFEVCLK_IP_TMU_SUBVCLK_IP_TREX_P_NOCL0VCLK_IP_LH_ACEL_MI_D2_G3DVCLK_IP_LH_ACEL_MI_D3_G3DVCLK_IP_LH_ACEL_MI_D0_TPUVCLK_IP_LH_AXI_MI_P_GSA_CDVCLK_IP_LH_AXI_MI_P_HSI1_CDVCLK_IP_D_TZPC_NOCL2ABVCLK_IP_LH_AXI_MI_D1_MCSCVCLK_IP_LH_AXI_MI_D1_TNRVCLK_IP_LH_AXI_MI_D3_TNRVCLK_IP_USI0_USIVCLK_IP_SYSMMU_S0_RGBPVCLK_IP_LH_AXI_MI_LG_SCAN2DRAM_CUVCLK_IP_SSMT_D7_TNRVCLK_IP_PPMU_D4_YUVP6%s: cal data init margin_cam_write_filesamsung,exynos_cal_if &TTT-8?@@@@@@0 ThX08@ (rtvuuuuuuuuuxuuuuuuuuu|uuuuuuuuu8||DL|||||||||||0P @ Dsamsung,exynos-acpm-dvfsmargin_mifmargin_intmargin_litmargin_midmargin_bigmargin_dsumargin_bcimargin_g3dmargin_g3dl2margin_tpumargin_intcammargin_tnrmargin_cammargin_mfcmargin_dispmargin_bwlicense=GPLdescription=Exynos Chip Abstraction Layer Interfacelicense=GPLlicense=GPLlicense=GPLlicense=GPLlicense=GPLlicense=GPLparmtype=margin_mif:intparmtype=margin_int:intparmtype=margin_lit:intparmtype=margin_mid:intparmtype=margin_big:intparmtype=margin_dsu:intparmtype=margin_bci:intparmtype=margin_g3d:intparmtype=margin_g3dl2:intparmtype=margin_tpu:intparmtype=margin_intcam:intparmtype=margin_tnr:intparmtype=margin_cam:intparmtype=margin_mfc:intparmtype=margin_disp:intparmtype=margin_bw:intlicense=GPLvermagic=5.15.148-android14-11-g3f4e1ccba8ea-ab12065098 SMP preempt mod_unload modversions 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