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"type=0x%02x length=%u last=%d delay=%d tx=[%s]", REC->type, __get_dynamic_array_len(tx_buf), REC->last, REC->delay_ms, __print_hex(__get_dynamic_array(tx_buf), __get_dynamic_array_len(tx_buf)) "cmd=0x%02x length=%u rx=[%s]", REC->cmd, __get_dynamic_array_len(rx_buf), __print_hex(__get_dynamic_array(rx_buf), __get_dynamic_array_len(rx_buf)) "header=%d payload=%d", REC->header, REC->payload "delay=%d", REC->delay_ms "%s %s", __get_str(name), REC->begin ? "begin" : "end" "%c|%d|%s|%d", REC->type, REC->pid, __get_str(name), REC->value B $ / $
$ $ $ $ $ $ $ include/linux/dma-mapping.h 3%s(#%d) not able allocate SRAM inst for DECON%u CWB
decon_reg_stop_perframe_dp 3%s(#%d) ECC error, single-bit(detect and correct)
3%s: invalid bit range [%u, %u]
3%s(#%d) can't find proper dphy timing(%u Mhz)
dsim_reg_set_config odma_reg_print_irqs_msg dqe_reg_print_gamma_matrix %s(#%d) init USBDP Combo PHY
%s(#%d) set lane count & map
dp_smc_write histogram_2 partial_region Dolby Vision mmaped the offset %lu of size %lu to %#lx
Linear failed to create debugfs event file
3%s: invalid input param
3failed to create %s matrix directory
coeff_02 underrun count(%u) 4%s: invalid win state %d
3%s: failed to create a histogram event
decon_id=%u, hist_id=%d hist_state=%d, curr_state=%d
%s: enabled(%d) +
requested update region out plane%d/win%d src[%d.%06ux%d.%06u%+d.%06u%+d.%06u] dst[%dx%d%+d%+d]
_decon_mode_update_bts_handover decon_parse_dt 4%s[%u]: WARN: scaler line delay is not defined in DT.
afbc_yuv_util_pct bts_scen_name bts_scen_max_rt 3%s[%u]: failed to find disp_ss node 3Error creating symlink to decon%d: %d
6%s[%u]: %s -
decon_request_te_irq 4%s[%u]: %s: invalid drm connector!
WB 3%s: %s[%d]: failed to get sramc resource
dma_irq_handler dpp[%u] deadlock in decon[%u]
__dpp_disable %s[%d]: disabled
%s: %s[%d]: %s(p:0x%x,m:0x%x,s:0x%x,k:0x%x)
4%s: %s[%d]: cmd_underrun_cnt is not set correctly
4%s: %s[%d]: RX FIFO is not empty: rx_size:%u, rx_len:%lu
4%s: %s[%d]: warning. changed last command. pend pl/pl(%u,%u) new pl(%zu)
4%s: %s[%d]: failed to get TOUT (TE2) gpio
dphy-extra DPU_UNDERRUN 6dst_f_w[%d %d %d] dst_f_h[%d %d %d]
3%s: failed to init writeback connector
4%s: %s: dp_emulation_mode parse error
%s: DP HPD is same state (%x): Skip
failed to allocate dp device.
B 3%s: failed to train DP Link
3%s: reached max swing level
6%s: enable DP training pattern 3
6%s: DP audio path is disabled: dp_audio=N
6%s: DROP: "%s": %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x
dp_crc_values_write 6%s: dp->num_modes = %d
[BTS] %s +
3%s(#%d) failed to instant_stop(DP)
decon_reg_set_mres dsc_reg_set_encoder 3%s(#%d) %u Mhz can't be used as escape clock
3%s(#%d) invalid CSC type
dpp_reg_set_csc_coef 3%s(#%d) IDMA cfg err irq occur(0x%x)
%s(#%d) threshold: %u
%s(#%d) COEFFS:
DISP %s(#%d) [Blue]
%s(#%d) ATC configuration
%s(#%d) YMIX_VF: 0x%x
%s: dp_smc_read_mask failed: %d
dpphy_reg_switch_to_dp error active EXYNOS_CONTEXT_HISTOGRAM_EVENT_CANCEL max_disp_freq 4legacy property(%s): ignored
C8 mapped dma_addr: 0x%llx
3%s: Failed to find DMA-BUF system heap
(off)
video 3%s: invalid histogram channel id(%d)
exynos_degamma_update scale_mode [PARTIAL]: %s: %s[%dx%d%+d%+d]
3[PARTIAL]: %s: cannot support partial update(%dx%d, %dx%d)
[PARTIAL]: %s: rotation is detected. partial->full
6%s[%u]: successfully probed 3%s[%u]: failed to parse max windows count
%s[%u]: line delay comp(%d)
bts_scen_min_panel_height 3%s[%u]: failed to get main resource
%s[%u]: bypass mode: get extra power ref
3%s[%u]: framestart timeout (%dhz), recovering: %d, pending: %d
early_wakeup early_wakeup_store decon_unbind %s[%d]: unable to find vaddr
dpp_need_enable_hdr 6%s: %s[%d]: src_h_rot_max[%d]
3%s: %s[%d]: failed to remap HDR SFR region
3%s: %s[%d]: failed to remap HDR COMM SFR region
dpp_check_size set_resource_protection %s Unsupported connector type
strnlen %s[%d]: no need to wait for payload fifo empty
__dsim_wait_for_ph_fifo_empty %s[%d]: no need to wait for packet header fifo empty
%s[%d]: %s last command
s-range %s[%d]: framedone irq occurs
dsim_dphy channel %s: %s[%d]: state: %d self_refresh: %d->%d
3failed to remap DPP SFR region
wb_check_type exynos_drm_writeback_reset exynos-drmdp 3%s: create wq failed.
3%s: DP Sink: failed to read sink count
6%s: [HPD IRQ] link status = %02x %02x %02x %02x
3%s: [HPD IRQ] invalid sink count, adjusting to 0
3invalid DPU AXI channel number %u
[BTS] COMP: lat_cycle(%u)
../private/google-modules/display/samsung/exynos_drm_decon.c 3%s(#%d) failed to change off status of DECON%d
3%s(#%d) (rx_fifo=0x%x) Check DPHY values about HS clk.
%s(#%d) slice0 w(%d) slice1 w(%d) slice2 w(%d) slice3(%d)
%s(#%d) -[CMD 1 : offset + 0x100]-
dma_reg_get_shd_addr dpp_reg_set_scale_ratio idma_reg_set_block_mode 3%s(#%d) IDMA deadlock irq occur
cgc_reg_print_irqs_msg cal_write_relaxed %s(#%d) OETF VS[%d]: 0x%x
%s(#%d) HDR: gammut %s
%s(#%d) set DP TX lanes.
3%s(#%d) is timeout. Fail to ack DP TX.
dp_reg_wait_sst1_longhop_power_on exynos_atomic_enter_tui char Decon #%u (state:%d)
trig_mode=%s ddi=%d
BT709 histogram_0 exynos_rmem_register modeset exynos_drm_gem_mmap_object Gamma 2.8 dta_en eotf scaler red 3failed to create regamma lut directory
3failed to create gammut directory
DPU POWER:%s DECON STATE:%u CH:%d, WIN:%d, %s%s ../private/google-modules/display/samsung/exynos_drm_dqe.c histogram_event_request_ioctl 3[PARTIAL]: %s: invalid min size(%dx%d) of partial update
afbc_clk_ppc_margin %s[%u]: plane possible_crtcs = 0x%x
%s[%u]: %s -
3%s[%u]: %s: failed to pm_runtime_get_sync
%s: no private mode config
3%s: fail to get dsim, suppose dsim0
3%s[%u]: cannot support %d dsc
decon_runtime_resume 6%s: %s[%d]: dst_w[%d %d %d] dst_h[%d %d %d] dst_x_y_align[%d %d]
6%s: %s[%d]: blk_w[%d %d %d] blk_h[%d %d %d] blk_x_y_align[%d %d]
3%s: %s[%d]: failed to install DPP irq
%s: %s[%d]: found proper pll parameter
&dsim->cmd_lock dsim1 %s[%d]: %s -
dsim_read_data 4%s: %s[%d]: timed out but payload fifo was empty
__dsim_cmd_write_locked %s: %s[%d]: total pending packet header(%u) payload(%u)
bist_mode _dsim_enable unknown dsim state (%d)
exynos_tui_open wb_init_resources 6%s +
6%s: dp_hdcp_update_cp to %d
auto 0 6%s: Link Training CR Phase with Rate(%d) and Lanes(%u)
6%s: EQ Done. Move to Training_Done.
6%s: EDID: block %u length %zu
6%s: [HPD IRQ] link irq vector esi0 = %02x
%s: %s: Got CRCs R:%04X G:%04X B:%04X
3win config is invalid
[BTS] AXI_DPU%d = %u
[BTS] ROT: lat_cycle(%u)
3%s(#%d) failed to get sub resource
3%s(#%d) EoT error!
dsim_dphy_diag_mask_from_range %s(#%d) escape clock is %u MHz
%s(#%d) SEL_VCO = 1
rcd_reg_set_block_mode %s(#%d) EOTF TS[%d]: 0x%x
%s(#%d) link_rate(%d)
dp_reg_wait_phy_pll_lock dp_reg_set_active_symbol 3%s:unable to enter tui without any active crtcs
(null) fence: err=%d
6encoder[%d] type(0x%x) possible_clones(0x%x)
modeset on [ENCODER:%u:%s]
histogram_ histogram_channels ABGR8888 exynos_drm_gem_fd_to_obj range event dta_hi_thres %s[%u]: DECON disabled(%d)
CH:%u WIN:%u OFF 3%s: decon%u: user_handle should not be 0
%s: terminate remained event(0x%pK)
histogram_channel_ioctl_process_arg -
en dither exynos-crtc-0 max_win afbc_rgb_rt_util_pct _decon_wait_for_framedone _decon_handover_check %s[%u]: new win_id=%d zpos=%d mask=0x%x
4%s[%u]: %s +
6%s: %s[%d]: dst_f_w[%d %d %d] dst_f_h[%d %d %d]
3%s: %s[%d]: failed to get protection id(%u)
4%s: %s[%d]: %s: seamless mode switch not supported for %s
%s: %s[%d]: clock mode change not allowed seamlessly
dsim_set_display_mode %s[%d]: clk_param.hs_clk=%u, pll_freq=%u, pending_hs_clk=%u
3%s: %s[%d]: unable to create dsi packet (%d)
%s: %s[%d]: %s last command
dsim_write_payload dsim_write_data_dual dsim_parse_dt 3%s: %s[%d]: could not find child node of dsim-modes 3%s: %s[%d]: %s failed to get m-range
%s[%d]: pll features: input %llu, optimum%llu
dsim_of_get_pll_diags dsim_of_parse_diag 3%s: %s: failed to read reg-offset
&x->wait 6%s: %s[%d]: dsim power is off state(0x%x)
hw_te_off 6max scale up(%dx), down(1/%dx) ratio
exynos_drm_writeback_duplicate_state writeback_disable writeback_unbind 4%s: DP HPD PLUG work was already queued failed to allocate dp stats attributes
&dp->training_lock reverse 6%s: [HPD_UNPLUG done]
4%s: DP Sink: failed to read DSC support registers
6%s: EDID: Sink Serial: %x
4%s: %s: dp_crc_get failed, res=%d
dpu_bts_init %s(#%d) === DECON%d_MAIN SHADOW SFR DUMP ===
3%s(#%d) failed to get wincon resource
3%s(#%d) failed wincon ioremap
decon_reg_log_dsimif %s(#%d) dual slice(%d)
3%s(#%d) Invalid transmission length!
3%s(#%d) %s invalid config (null)
dsim_reg_enable_lane_phy dsim_reg_wait_hs_clk_ready hdr_dump_regs dqe_reg_init dqe_reg_set_cgc_lut hdr_reg_set_eotf_lut %s(#%d) YMIX_SLOPE: 0x%x
hdr_reg_print_oetf_lut %s(#%d) HDR: tone mapping %s
%s(#%d) reset DP Link
%s(#%d) set system clk to OSC: Mux(%u)
3%s(#%d) val(0x%08x) DP_CONFIG12 read:0x%08x
%s(#%d) CR write failed to (0x%04x)
dp_hw_set_data_path 20110530 Display P3 BT2100 PQ Unspecified On IRC On src[%u %u %u %u], dst[%d %d %u %u]
Y010_8P2 %s: obtained fake mmap offset %llu from handle %u
3%s: Failed to lookup gem object from handle %u.
SMPTE 170M gammut_matrix failed to create debugfs reg dump file
crc_cnt offsets %s %s WIN 6%s: histogram: use cached data
%s: histogram: created event(0x%pK) of decon%u, chan %u
3%s: histogram_event_ioctl_process_arg failed, ret(%d)
%s: no event request for handle#%u
create_histogram_event lt_calc_ab_shift gt_lamda_dstep hiber_blk_cnt 6doesn't need to get camera operation register
hibernation_block_sync exynos_partial_initialize exynos_partial_update changed full: requested region is bigger
clipped src[%d.%06ux%d.%06u%+d.%06u%+d.%06u] dst[%dx%d%+d%+d]
6[RECOVERY] %s: starting recovery...
exynos-decon %s[%u]: line delay scaler(%d)
bus_util 6%s[%u]: support `%s` under %ux%ux%u, rt %u-%u, peak %u-%u, no-video:%s
6%s[%u]: not support to set dpu bts scenario under certain condition.
3%s[%u]: failed to install FRAME START irq
aclk 3Invalid dsim id: %d
decon_update_dsi_config dpu_sysmmu_fault_handler scale_down 3%s: %s[%d]: failed to get scl_coef resource
dpp[%u] mst_security: %#x
%s: %s[%d]: op mode change not allowed seamlessly
%s: %s[%d]: %s(hs:%d,esc:%d)
%s[%d]: === DSIM SFR DUMP ===
%s: %s[%d]: no need to wait for payload fifo empty
pll-out-range 3%s: %s[%d]: %s failed to get p-range
dsim_irq_handler 3%s: %s[%d]: Failed to update pll for hsclk %u
3%s: %s: m %u is out of range (%u, %u)
%s[%d]: preferred panel is %.*s
label dsim_suspend _dsim_enter_ulps_locked 6writeback(dpp%d) disabled(%d)
6wb(%d) already enabled(%d)
unknown 6%s: %s: Service IRQ from sink
link_negotiation_failures 4%s: invalid link training AUX read interval value(%u)
6%s: enable DP training pattern 4
dp_disable 3%s: [HPD IRQ] cannot read DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0
dp_crc_enabled_write CRCs are disabled
dp_get_modes dp_detect [BTS] DPP%d bandwidth: avg %u, rt %u, rot %u
../private/google-modules/display/samsung/cal_9865/dp_reg.c %s(#%d) -[PLL : offset + 0x100]-
%s(#%d) === SRAMC%d SHADOW SFR DUMP ===
dqe_reg_print_degamma_lut [%4d]%4x dp_hw_init dp_hw_reinit dp_hw_init_audio %s(#%d) switch from USB to DP.
dp_get_and_inform_lanes %s(#%d) power off all lanes.
dpphytca_reg_wait_mode_change %s(#%d) enable mpllb for %d lanes.
%s: set lhbm histogram config (x=%d, y=%d, w=%d, h=%d)
%s +
color mode rcd_plane_id sync_op_rate dimming_on ARGB16161616 3%s: Failed to mmap imported buffer: %d
luminance: min=%d max=%d
wr_hi_thres fp16_en 3failed to create %s lut directory
CMD_ID: 0x%x DATA[0]: 0x%x len: %d histogram_request_ioctl histogram_chan_set_state exynos_dqe_hibernation_enter 3%s: failed to find crtc object
%u
exynos_hibernation_suspend [PARTIAL]: %s: partial update is initialized: min rect(%dx%d)
%s[%u]: WARN: bus_util_pct is not defined in DT.
%s[%u]: %s: reset=%d
%s[%u]: seamless mode set to %s
cgc-dma,id 3%s: %s[%d]: failed to get dma resource
3%s: %s[%d]: failed to remap SCL COEF SFR region
%s: %s[%d]: +
dsim_dphy_diag_get_reg %s[%d]: %s +
3%s: %s[%d]: read timeout
4%s: %s[%d]: failed on wait for cmd fifo empty (%d)
3%s: %s[%d]: %s failed to get s-range
3%s: %s[%d]: failed to install DSIM irq
4%s: %s[%d]: %s: unable to get pll param
dsim_set_te_pinctrl is_primary_panel 3%s: failed to init dp resources.
6%s: Pre_Emphasis : %02X %02X %02X %02X
6%s: %s: DP State changed to ON
6%s: %s: detected pending HPD UNPLUG
Pixel 4%s: %s: dp_crc_set_enabled(SST1, %d) failed res=%d
dp_crc_values_show DECON%u [BTS] DPP%d : bpp(%u) src w(%u) h(%u) rot(%d) afbc(%d) yuv(%d)
dpu_bts_update_overlap_bw %s(#%d) === DECON_WINCON%d SFR DUMP ===
decon_reg_stop_perframe_dsi 3%s: smc update error %d for %llx
dsim_reg_set_size_of_slice %s(#%d) -[BIAS]-
dpp_reg_deinit Y2R 3%s(#%d) ODMA deadlock error irq occur
%s(#%d) size(%ux%u)
%s(#%d) [%d]: 0x%x
dqe_reg_print_dither %s(#%d) %s: ignored in protected status
dqe_reg_set_histogram_pos_internal %s(#%d) set sst function
%s(#%d) %s: dp_audio is configured for BIST mode
F %s(#%d) CR read failed to (0x%04x)
dpphy_reg_set_mpllb dpphytca_reg_set_tcpc %s(#%d) Wait to change from USB to DP%d
PHY TCA Native brightness_level exynos_drm_fb_dma_addr failed to create colormap gem
rot[%d] afbc[%d] format[%d] ch[%u] zpos[%u] comp_src[%llu] hdr[%d]
%s: mmaped the offset %lu of size %lu to %#lx
hibernation 3failed to create %s dir
verbose_count Event ID CH:%u WIN:%u SRC:%s COUNT:%u SECURE 3%s: failed to remap dqe registers
dqe-cgc enabled(%d) +
he_clip_max_0 [PARTIAL]: %s: reconfigured coordinates:
[PARTIAL]: %s: min size limitation. width[%d] height[%d]
partial command: [%d %d %d %d]
4%s[%u]: failed to parse urgent rd_lo_thres(%d)
%s[%u]: PPC(%u)
delay_scaler %s[%u]: INFO: afbc_yuv_util_pct is not defined in DT.
%s[%u]: INFO: afbc_clk_margin is not defined in DT.
%s[%u]: DPU DFS Level : 6%s[%u]: dimming start irq is not supported
dimming_end %s[%u]: %s: resource conflict
cgc-dma is not supported
dpp,video 3%s: %s[%d]: failed to remap DPU_DMA SFR region
%s DPU protection status changed to %d %s: %s[%d]: short packet was received
dsim_cmd_packetgo_ready_locked %s[%d]: TE from DDI%d
%s: %s[%d]: pll features: output(%llu, %llu)
read_only dsim_phy_power_on dsim_unbind exynos_tui_release 4%s: %s: audio_bit != 16-bit
6%s: audio_infoframe: type and ch_cnt %02x, SF and bit size %02x, ch_allocation %02x
1 3%s: failed to remap USB/DP Combo PHY SFR region
3%s: DP Sink: invalid sink count
3%s: DP Sink: failed to read sink power state
3%s: failed to pack AVI infoframe: %d
dp_work_hpd_irq 3%s: unable to link displayport sysfs (%d)
%s(#%d) === DECON_SUB.DSC%d SHADOW SFR DUMP ===
4%s(#%d) default outif is set(DSI0)
dpu_sysreg_select_dphy_rst_control dpp_regs_desc_init dqe_reg_print_hist_ch dqe_reg_print_atc_he %s(#%d) DQE_ATC_HE_CLIP_MIN[%d]: %x
[%4d]%8x %s(#%d) %s: dp_audio_init_config
3%s(#%d) DP Sink didn't reply in 1.8ms. Retry after 1.4ms.
%s(#%d) reset All DP TX lanes.
%s(#%d) TCA_REG_TCA_TCPC(0x1 == 0x%08x)
type %d
BT601_625 3%s: create properties(%s): ret %d
Right Side Up wait_for_flip_done FILM help lut_write read %d bytes from userspace
Remarks CH:%d WIN:%d SRC:%llu ecc count(%u) 4%s: invalid number: %d
exynos_dqe_register 4%s: try to enable disp_dither while in_bpc == out_bpc, correct it to "disable"
force_update pl_w1 dim_ratio override-hibernation %s: DPU power %s
%s[%dx%d%+d%+d]
is_partial_supported min size limitation. width[%d] height[%d]
%s[%u]: scaler ppc(%d)
afbc_yuv_rt_util_pct bts_scen_min_peak rcd %s[%u]: TE irq number(%d)
DP1 decon_atomic_begin 3%s: invalid input param(s)
3%s: %s[%d]: failed to get dpp resource
3%s: %s[%d]: rot[0x%x] comp_type[%d]
%s[%d]: payload: 0x%x
mode-name %s[%d]: pll features: vco (%llu, %llu)
%s: %s[%d]: framedone irq occurs
3%s: %s[%d]: RX ECC Multibit error was detected!
3%s: %s[%d]: Failed to update underrun
dsim_calc_pmsk %d:%s 3[TUI Driver] failed to exit TUI
4wb(%d) instant off irq occurs
6%s -
4%s: DP Power Status is off
6%s: audio state (%d ==> %d)
link_status 3%s: failed to install DP irq
3%s: Link training failed during CR phase
4%s: dp_wait_state_change: timeout for enable
6%s: [HPD IRQ] DP link is down, re-establish the link
6%s: AutoTest: set %02x %02x %02x %02x
3%s: failed to create connector ret = %d
dpu_bts_update_scenario ../private/google-modules/display/samsung/exynos_drm_drv.c ../private/google-modules/display/samsung/exynos_drm_crtc.c 3%s(#%d) failed to inst_stop(DSI)
ignored dsim%d crc in protected status
3%s(#%d) failed decon sub ioremap
4%s(#%d) clear CWB SARAM instance (0x%llx, 0x%llx)
3%s(#%d) invalid decon
dsim_reg_wait_exit_ulps_state 3%s(#%d) CGC DMA read error irq occur
%s(#%d) VS:
%s(#%d) AUX buffer read count = %d in EDID read
%s(#%d) %s: dp_audio is disabled
dpphy_reg_reset_tx_lanes %s(#%d) Start USB to DP%d
plane: src-pos=%d.%06ux%d.%06u%+d.%06u%+d.%06u
EXYNOS_HISTOGRAM_CHANNEL_REQUEST is_partial brightness_capability operation_rate offsets[%d](%d) size(%zd) obj[%d]->size(%zd)
rot[%d] afbc[%d] format[%u] ch[%u] comp_src[%llu]
XRGB8888 3%s: Failed to map virtual address
failed to create debugfs recovery file
force_enable 3failed to create cgc directory
3failed to create atc directory
ON DST[%d %d %d %d] histogram_flip_done %s: decon%u histogram%u: decon is already idle
3%s: drm_event_reserve_init failed, ret(%d)
he_clip_min_3 he_clip_max_3 %s: block_cnt(%d)
[PARTIAL]: %s: changed full: requested region is bigger
in 4%s[%u]: failed to parse urgent wr_hi_thres(%d)
%s[%u]: can't find rcd node
decon_exit_hibernation decon_set_color_map decon_suspend sramc 3%s: %s[%d]: not support over %dx scale-up
3%s: %s[%d]: TE error: pinctrl not found
6%s: %s[%d]: hs_clk is changed to %u
%s: %s: underrun_param for mode "%s": %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x not specified dsim_host_transfer dsim_of_parse_modes 3%s: %s[%d]: %s failed to get pll-out-range
pll-vco-range 3%s: %s[%d]: failed to enable ext dphy(%d)
6%s: %s[%d]: no dsi_device
%s 4%s: DP HPD IRQ work was already queued 3%s: failed to DP Link Up
6%s: requested same level. Retry...
[BTS] [Run: D%u] resol clock = %u Khz @%u fps
dpu_bts_calc_dpp_bw [BTS] MAX DISP CH FREQ = %u
[BTS] Max Overlap BW = %u, Max AXI_DPU = %u
../private/google-modules/display/samsung/exynos_drm_gem.c __decon_dump decon_reg_alloc_shared_sram_instance 3%s(#%d) decon(%d) is invalid to set dither
dsim_reg_stop 3%s(#%d) Checksum error(long packet only)!
disable dsim_reg_wait_hs_clk_disable odma_reg_wait_sw_reset_status idma_reg_print_irqs_msg 4%s: invalid hist_id(%d)
%s: pos(%d)
%s(#%d) COEFFS[%d]: 0x%x
%s(#%d) power on %d lanes.
u8 type=0x%02x length=%u last=%d delay=%d tx=[%s]
name begin plane: fb allocated by = %s
type=0x%x
Adobe RGB histogram_3 lp_mode local_hbm_mode failed to get reserve memory phandle
width(%d), height(%d), pitches(%d)
exynos_drm_gem_get_vaddr exynos_drm_gem_prime_import_sg_table
decon_id=%d
standard wr_en ../private/google-modules/display/samsung/exynos_drm_debug.c dump degamma Time ROT 3%s: histogram_channel_ioctl_process_arg failed, ret(%d)
terminate remained event(0x%pK)
4%s: decon%u histogram%u: pending framedone during hibernation
3failed to map camera operation register
3[PARTIAL]: %s: failed to initialize partial update
[PARTIAL]: %s: reconfigure(%d)
4%s[%u]: WARN: bus_width is not defined in DT.
%s[%u]: afbc: rgb_util(%u) yuv_util(%u) rgb_rt_util(%u) yuv_rt_util(%u) margin(%u)
3%s[%u]: failed to map sysreg-disp address. Dual DSI decon_disable decon_enable_vblank %s[%u]: no planes, enable color map win_id=%d
4expected present time seems incorrect(now %llu, earliest %llu)
%s: %s[%d]: enabled
%s[%d]: ch:%u, en:%d
4%s: %s[%d]: idle ip index is not provided
%s: %s[%d]: %s -
%s[%d]: EoTp was received
%s[%d]: payload length(%lu)
pmsk %s: %s[%d]: pll features: input %llu, optimum%llu
3%s: %s: invalid reg-base: %s
3%s: %s: failed to read bit-range
wb(%d) framedone irq occurs
6%s: %s: dp_emulation_mode=%d
3%s: DP Branch Device: invalid sink count
6%s: reducing link rate to %d during CR phase
6%s: [HPD IRQ] Automated Test Request
[BTS] decon%u del bts scenario %u dpu_bts_sum_all_decon_bw dpu_bts_find_nearest_high_freq 3%s(#%d) failed to perframe_stop(DP)
3%s(#%d) failed decon win ioremap
decon_reg_wait_run_is_off_timeout 3%s(#%d) False control error!
%s(#%d) %s: dsc configuration is set
enable dsim_reg_wait_idle_status %s(#%d) === DPU_DMA CGC%d SFR DUMP ===
%s(#%d) ---[%s CSC Type: std=%d, rng=%d]---
3%s(#%d) DPP cfg err irq occur(0x%x)
%s(#%d) === HDR%d SHADOW SFR DUMP ===
off %s(#%d) DQE: regamma %s
%s(#%d) %s: dp_audio is started
dp_crc_set_enabled dp_crc_reset 3%s(#%d) is timeout.
fence: %s-%s %llu-%llu status:%s
fence: timestamp:%lld.%09ld
&private->wait max_avg_luminance panel orientation commit_planes [CRTC-%d] old en:%d active:%d change[%d %d %d]
RGBA8888 mapped vaddr: %pK
3%s: failed to get dma buf
3%s: Failed to create a handle of GEM
eotf_lut hibernation_show DISABLED 6display hibernation is supported
%s: skipping due to crtc disabled
%s: aborted due to normal commit pending
This panel doesn't support partial update feature
[PARTIAL]: %s: plane mask[0x%x]
final update region reconfigured coordinates:
decon_enable_tout_irq 4%s[%u]: failed to parse urgent wr_lo_thres(%d)
delay_comp yes %s[%u]: %6d decon%d hw trigger. DP0 [drm] %s: handover memory defined, but cannot find handover dpp
decon_update_plane decon_disable_plane %s[%u]: in/out/force bpc(%d/%d/%d)
4%s[%u]: decon state = %u at resuming
3%s: %s[%d]: failed to install DPU DMA irq
6%s: %s[%d]: recovery start(0x%x) cnt(%d) src(%s)
dpp_check_dst_size 3%s: %s[%d]: not supported destination alignment
%s: %s[%d]: disabled
%s: %s[%d]: underrun_lp_ref 0x%x
3%s: %s[%d]: failed to add sysfs bist_mode entries
3%s: %s[%d]: failed to disable dphy(%d)
%s: %s[%d]: wait for packet header fifo empty
last=%d delay=%d tx= dsim,id te_from %s[%d]: pll features: output(%llu, %llu)
reg 3%s: %s[%d]: failed to create panel bridge
6writeback(dpp%d) already disabled(%d)
3%s: dpcd_write_for_hdcp22 fail(%d): 0x%X
../private/google-modules/display/samsung/exynos_drm_dp.c dp_hotplug_error_code_store usbc_cable_disconnect 3%s: failed to get DP clks
3%s: failed to get irq resource (%d)
3%s: [HPD_PLUG fail] Check CCIC or USB!!
%s: dp_emulation_mode=1, skipped link training
3%s: DP Branch Device: failed to read DP Downstream Port info
3%s: failed to setup AVI infoframe: %d
6%s: %s: DP State is not RUN
3%s: [HPD IRQ] cannot read DP_SINK_COUNT_ESI
6%s: [HPD IRQ] Sink Specific
%s: %s: dp_crc_reset finished successfully
dp_conn_atomic_check ../private/google-modules/display/samsung/exynos_drm_bts.c 6[BTS] decon%u bts feature is enabled
dpu_bts_update_disp [BTS] dst x(%u) right(%u) y(%u) bottom(%u)
reg-names 3%s(#%d) DECON2 is active, not able to use CWB on DECON%u
decon_reg_set_dither_path 4%s(#%d) decon%d RSC_STATUS_2: SEL_WIN = 0x%x
4%s(#%d) decon%d RSC_STATUS_4: SEL_DSC = 0x%x
%s(#%d) Non error reporting format (rx_fifo=0x%x)
3%s(#%d) ECC error, multi-bit(detect, not correct)
6%s(#%d) DPHY PLL is already stable
dma_reg_dump_com_debug_regs __dpp_check 3%s(#%d) [dpp%d] timeout sw-reset
dma_dump_regs %s(#%d) === DPP%d SFR DUMP ===
dpp_dump_regs %s(#%d) === DPP%d SHADOW SFR DUMP ===
dqe_reg_set_degamma_lut dqe_dump %s(#%d) set interrupts
dp_hw_start_audio 6%s: unable to enter TUI, DP is active
delay=%d
end wait_for_fences exynos-drm sync_ghbm failed to lookup gem object
src[%d %d %d %d], dst[%d %d %d %d]
exynos_drm_gem_dumb_create 3%s: Failed to mmap with offset %lu.
exynos_drm_gem_create %s: decon id is not valid(%d)
regamma 3failed to create degamma directory
gammut atc_en dstep hibernation_unblock_enter &hibernation->lock %s[%u]: %s: configure bts for handover
4%s[%u]: failed to request irq for tout (te2)
(&decon->worker)->lock %s[%u]: can't find rcd structure
6%s[%u]: already enabled(%d)
6%s[%u]: %s mode. %s %s output.(%dx%d@%uhz, bts %uhz)
%s[%d]: buffer doesn't have compressed data
6%s: %s[%d]: src_f_w[%d %d %d] src_f_h[%d %d %d]
6%s: %s[%d]: dma irq no = %d
dpp_update mipi_clk dsim_atomic_check_gs 3%s: %s[%d]: failed to probe exynos dsim driver
dsim_host_detach %s: %s[%d]: rx fifo:0x%8x, response:0x%x, rx_len:%lu
esc-clk 4%s: %s[%d]: %s: diag parsing error for item %u
3%s: %s: invalid bit range %d, %d
dsim_get_phys 4%s: %s[%d]: failed to set pending_hs_clk=%u
6dma irq no = %d
writeback_atomic_commit &dp->typec_notification_lock sink_count_invalid_failures 3%s: failed to get DP Link resource
3%s: [HPD IRQ] cannot read DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1
6%s: [HPD_IRQ done]
4%s: %s: dp_crc_reset failed, res=%d
dp_unbind [BTS] %s -
[BTS] DECON%u total bw = %u, read bw = %u, write bw = %u
../private/google-modules/display/samsung/exynos_drm_hibernation.c decon_reg_set_cwb_enable %s(#%d) d_path(0x%02X) 3%s(#%d) failed to reset decon%d
%s(#%d) slice mode change(%d)
3%s(#%d) Escape mode entry command error!
%s(#%d) -[CMD 0 : offset + 0x100]-
%s(#%d) -[CMD 2 : offset + 0x100]-
%s(#%d) unspecified CSC type! -> BT_601
hdr_reg_set_gm 3%s: failed to remap USB/DP Combo PHY TCA SFR region
__data_loc u8[] rx_buf cmd=0x%02x length=%u rx=[%s]
vid 10bpc failed to initialize framebuffer
disabling [ENCODER:%u:%s]
hw restrictions urgent wr_lo_thres [drm] dsim%d mif(%lu) int(%lu) disp(%lu) peak(%u,%u) rt(%u,%u) total(%u,%u) scen(%u) reconfig(%d) %s %s %s
exynos_atc_update 3%s: create_context_histogram_event failed, ret(%ld)
upgrade_on gain_limit gt_he_enable exynos_recovery_handler 3%s[%u]: failed to get sys resource
decon-ss decon_get_main_dsim_id TE DSI1 decon_enter_hibernation [drm] %s: planes updated on commit, skipping handover
cgc-dma exynos_dpp_parse_dt %s[%d]: +
3%s: %s[%d]: not support under 1/%dx scale-down
3%s: %s[%d]: packet format is invalid.
%s: %s[%d]: PH_FIFO_EMPTY irq occurs
6%s: %s[%d]: %s: hs clock %u, apply now: %u
%s[%d]: %s: doing recovery
dsim_resume 3SBWC Block Size(%llu) is not supported
4%s: %s: parse error, buf=%s
dpcd_read_failures 3%s: no device tree information
6%s: DP Branch Device: DFP count = %d, sink count = %d
exynos-drmdp: dp_get_edid_block 6%s: EDID: PCM audio: ch: %u, sample_rates: 0x%02x, bit_rates: 0x%02x
%s: %s: DP is already disabled
dpu_bts_update_bw dpu_bts_get_vblank_time_ns decon_reg_wait_idle_status_timeout 6%s(#%d) op mode[%d] doesn't support multi resol
decon_reg_set_interrupts 3%s(#%d) failed to get win resource
%s(#%d) OUTIF is WB
%s(#%d) escape clock divider is 0x%x
dsim_reg_get_dphy_timing 3%s(#%d) not supported slice mode dsc(%d), slice(%d)
%s(#%d) image size: %u x %u
%s(#%d) %s mode, frame control %s, frame offset: %d
%s(#%d) DQE: degamma POSX
%s(#%d) DQE_ATC_HE_CLIP_MAX[%d]: %x
dpphy_reg_cr_write %s(#%d) TCA_REG_TCA_TCPC(0x%08x)
3%s(#%d) Fail to change mode from USB to DP%d
%s(#%d) FEC_On(int: %d, frac: %d, thr: %d)
header=%d payload=%d
%s: current win_mask=0x%x new=0x%x avail=0x%x
size=%dx%d
Off exynos_user_fb_create exynos_atomic_commit_tail HLG RGB565 NV12 %s: allocated %zu bytes with flags %#x
obtained fake mmap offset %llu from handle %u
3failed to create dqe directory
req[%d %d %d %d] adj[%d %d %d %d] prev[%d %d %d %d] 6%s: histogram: idle, query now
%s: request event(0x%pK)
histogram_chan_set_run_state_locked ambient_light back_light [PARTIAL]: %s: This panel doesn't support partial update feature
partial update is initialized: min rect(%dx%d)
[PARTIAL]: %s: clipped src[%d.%06ux%d.%06u%+d.%06u%+d.%06u] dst[%dx%d%+d%+d]
TE2 update_dsi_config_from_gs_connector 4%s[%u]: seamless not possible for mode %s
%s[%d]: dpp is protected
dma %s[%d]: enabled
_update_config_timing dsim_host_attach %s: %s[%d]: enabling packetgo
%s[%d]: payload: 0x%x i=%d max=%d
%s[%d]: wait for packet header fifo empty
%s[%d]: header(0x%x 0x%x 0x%x) size(%lu) ph fifo(%d)
3%s: mode %s has wrong pmsk elements number %d
dsi 6%s: %s[%d]: 0:Disable 1:ColorBar 2:GRAY Gradient 3:UserDefined
3%s: %s: p %u is out of range (%u, %u)
%s[%d]: disable right after self refresh. state:%d
%s: %s[%d]: %s: doing recovery
6src_h_rot_max[%d]
3failed to remap DPU_DMA SFR region
3failed to install DPU DMA irq
exynos_drm_writeback_destroy_state orientation 6%s: %s: DP is disabled, ignoring DP notifications
3%s: DP Sink: invalid max lane count
4%s: DP Sink: failed to read FEC support register
6%s: reducing lanes number to %u during EQ phase
6%s: DP Link: training failed
3%s: Failed to write DP_MAIN_LINK_CHANNEL_CODING_SET 6 dp_crc_values R:%04X G:%04X B:%04X
[BTS] %s + : DECON%u
[BTS] DISP bus freq(%u), operating freq(%u)
dpu_bts_deinit 6%s(#%d) pll wake-up is not allowed
sub 3%s(#%d) unsupported dsc path
3%s(#%d) SoT sync error!
__dsim_dump 3%s(#%d) AFBC + ARGB2101010, ABGR2101010 is not supported
%s(#%d) base addr 1p(0x%lx) 2p(0x%lx) 3p(0x%lx) 4p(0x%lx)
hdr_comm_dump_regs ../private/google-modules/display/samsung/cal_9865/dqe_reg.c %s(#%d) [Red]
%s(#%d) [Green]
dqe_reg_set_histogram 3dqe(%d): dma_map_single failed
hdr_reg_print_tm %s(#%d) disable mpllb and power off for %d lanes
%s(#%d) enable mpllb and power on for %d lanes
dpphy_reg_wait_config12_tx_ack %s -
payload NA plane: rotation=%x zpos=%x alpha=%x blend_mode=%x
modeset on [CRTC:%u:%s]
BT2100 HLG force_bpc refresh_on_lp sync_lhbm connector_pre_commit disabling [CRTC:%d:%s]
NV21 P010 3%s: Invalid mmap with empty attach!
Extended reg_dump recovery hdr lut_en hibernation_store ts ymix_vf dpu_print_log_atomic AFBC 3%s: failed to get dqe from decon%u
%s: histogram: run_state: %s -> %s
_exynos_hibernation_run Display hibernation handler is called
partial[%dx%d] vporch[%d %d %d] hporch[%d %d %d]
slice[%d] is %s
6[RECOVERY] %s: ESD recovery is supported
4%s[%u]: failed to parse urgent rd_en(%d)
%s[%u]: found dpp%d
frame_start decon_irq_handler aclk-disp 6%s[%u]: drm_conn_state->max_bpc = %u
%s[%u]: switch to mode %s can be seamless
decon_disable_win decon_atomic_flush decon_seamless_mode_set %s[%u]: %s
decon_resume cgc-dma is supported
%s[%d]: -
dpp_convert_plane_state_to_config exynos_tm_update 3%s: %s: invalid reg_base %u
dsim_calc_underrun 3%s: %s[%d]: could not get secondary dsi
4%s: %s[%d]: failed to get TE gpio
3%s: %s[%d]: %pOF: no modes specified
bit-range 3%s: %s[%d]: failed to map sysreg-disp address. hs_clock sec dsim_encoder_disable 3%s: %s[%d]: Unable to attach panel bridge
dsim_runtime_suspend dsim_runtime_resume 6writeback(dpp%d) successfully probe exynos_wb_parse_dt 6attr(0x%lx), port(%d)
dp_make_audio_infoframe_data failed to allocate dp attributes
&dp->audio_lock LINK %s: triggered intr from PCS block
%s: %s: ignored, because of restart_pending 6%s: unable to handle HPD_PLUG, TUI is active
%s: pm_rtm_put_sync usage_cnt(%d)
6%s: enable DP training pattern 1
3%s: EDID: failed to read EDID from sink, using fake EDID
dp_crc_enabled cal_write %s(#%d) %s: 0x%x
dsim_regs_desc_init dsim_reg_wait_phy_ready_dlane %s(#%d)
=== RCD%d SFR DUMP ===
dpp_reg_print_irqs_msg %s(#%d) DQE: degamma %s
%s(#%d) DQE: cgc %s
%s(#%d) YMIX_TF: 0x%x
%s(#%d) AUX buffer read fail in EDID read
3%s(#%d) val(0x%08x) DP PHY tca read [0x%p]:0x%08x
3%s: there is no suspend_state
cmd 4%s: skip frame update at %s
EXYNOS_HISTOGRAM_CANCEL partial region[%d %d %d %d]
histogram_%d exynos_drm_crtc_create_histogram_properties rr_switch_duration failed to allocate exynos connector state
RGBX8888 NV12_AFBC win_id=%d
%s: histogram: terminated histogram event of decon%u, chan %u
request event(0x%pK)
3%s: failed to get dqe cgc resource
3%s: invalid histogram request, data is NULL
ns exynos_hibernation_check ../private/google-modules/display/samsung/exynos_drm_partial.c reconfigure(%d)
exynos_partial_check slice left(%d) right(%d)
6%s[%u]: requested irq for tout (te2)
4%s[%u]: WARN: comp line delay is not defined in DT.
rot_util %s[%u]: WARN: rot_util_pct is not defined in DT.
frame_done _decon_stop_locked SBWC 6%s: %s[%d]: max scale up(%dx), down(1/%dx) ratio
3%s: %s[%d]: failed to remap SRAMC SFR region
get_connector_funcs dsim_atomic_check_exynos 3%s: %s[%d]: invalid TE config for hw trigger mode
6%s: %s[%d]: %s +
6%s: %s[%d]: %s -
pending packets remaining ph(%u) pl(%u)
3%s: %s[%d]: wrong dsim id(%d)
4%s: %s[%d]: %s: diag parsing error with unexpected index %u
reg-base bist_mode_store %s: %s[%d]: set the same hs_clock=%u while idle
dsim_add_mipi_dsi_device %s[%d]: state: %d self_refresh: %d->%d
%s[%d]: current state: %d
3%s: dpcd_read_for_hdcp22 fail(%d): 0x%X
6%s: %s: disp_pin_config = %d
%s: pm_rtm_get_sync usage_cnt(%d)
6%s: DP Sink: DPCD_%X Rate(%d Mbps) Lanes(%u) EF(%d) SSC(%d) FEC(%d) DSC(%d)
3%s: CR failed during EQ phase
6%s: EDID: SAD %d: fmt: 0x%02x, ch: 0x%02x, freq: 0x%02x, byte2: 0x%02x
3%s: [HPD IRQ] cannot read DP_DEVICE_SERVICE_IRQ_VECTOR
6%s: [HPD IRQ] device irq vector esi0 = %02x
6%s: DP Driver has been removed
dpu_vote_rt_bw dpu_bts_calc_rotate_aclk [BTS] Nearest DFS: %u KHz @L%d
decon_regs_desc_init %s(#%d) = DECON_SUB.DSIMIF%d SHADOW SFR DUMP =
__decon_init_resources %s(#%d) clk_trail(%u) hs_prepare(%u) hs_zero(%u)
%s(#%d) shadow addr 1p(0x%x) 2p(0x%x) 3p(0x%x) 4p(0x%x)
dpp_reg_set_csc_params 3%s(#%d) IDMA FBC error irq occur
%s(#%d)
=== DPU_DMA%d SFR DUMP ===
dqe_reg_print_cgc_lut %s(#%d) DQE_ATC_CDF_DIV: %x
hdr_reg_set_hdr dp_hw_read_edid %s(#%d) set common function
exynos_atomic_commit %s %s
exynos_atomic_helper_wait_for_fences none [drm:%s] devm_drm_dev_alloc failed: %li
bpc=%d
BT601_525_UNADJUSTED sRGB Post DQE Left Side Up offset(%d), handle(%d), size(%lu)
Full colormap 3%s: Invalid decon (%d)
underrun_cnt rd_lo_thres %s: DECON%u +
itmon,port hist_id: %d BUFFER %s: -
la_w_on exynos_hibernation_enter decon%u_kthread 4%s[%u]: failed to parse urgent wr_en(%d)
4%s[%u]: WARN: scaler ppc is not defined in DT.
%s[%u]:
6%s[%u]: dimming end irq is not supported
%s[%u]: %s: frame done
3Unable to support DSI along with out_type: 0x%x
decon_set_tout_gpio decon_disable_vblank %s[%u]: reuse existing win_id=%d zpos=%d mask=0x%x
3%s: %s[%d]: failed to remap DPP SFR region
3%s: SBWC Block Size(%llu) is not supported
%s[%d]: in/force bpc(%d/%d)
%s: %s DPU protection status changed to %d invalid dsim_id=%d for logbuffer registry
4%s: %s[%d]: force batching is attempted in video mode
3%s: %s[%d]: %s failed to get pll-optimum
3%s: failed to get dsi resource
3%s: %s[%d]: RX CRC error was detected!
%s[%d]: failed to get pinctrl (%d)
3%s: %s: s %u is out of range (%u, %u)
%s: %s[%d]: preferred panel is %.*s
dual-dsi already in self refresh state. state:%d
%s: %s[%d]: disable right after self refresh. state:%d
%s: %s[%d]: state: %d
3[TUI Driver] failed to enter TUI
aux-orientation 3%s: dp_wait_audio_state_change: timeout for disable
6%s: AutoTest: pre_emphasis[%d] = %x
4decon%u failed to update bw(%d) to bts(%d)
dpu_bts_update_resources ../private/google-modules/display/samsung/exynos_drm_dpp.c decon_reg_set_win_enable %s(#%d) win id = %d
3%s(#%d) timeout of updating decon registers (0x%x)
win dsc_get_partial_update_info decon_reg_read_resource_status 3%s(#%d) HS receive timeout error!
3%s(#%d) DSI VC ID invalid!
%s(#%d) number of DSC slice(%d)
%s(#%d) %s: video mode set
dsim_reg_set_ulps_by_ddi 3%s(#%d) SBWC + RGB format is not supported
dpp_reg_set_bpc %s(#%d) DQE: histogram EN(%u) ROI_ON(%u) LUMA_SEL(%u)
CGC Dither dqe_reg_get_histogram_bins dqe_reg_print_dump hdr_reg_set_oetf_lut %s(#%d) HDR: eotf %s
hdr_reg_print_eotf_lut dp_hw_set_bist_audio_config 3%s(#%d) UNKNOWN DP PIN TYPE
3%s(#%d) is timeout. Fail to request DP TX update.
cgc_lut_fd 3create drm property expected_present_time failed
BT601_625_UNADJUSTED histogram_roi crtc_disable HDR10 3%s: Failed to create mmap fake offset for handle %u
tone_mapping idma_err_cnt [%2d] %4x 4%s: decon%u histogram event (handle#%u) already registered
3%s: failed to get dqe resource
dqe%u create_context_histogram_event 3[RECOVERY] %s: Failed to recover display
4%s[%u]: unexpected tout_ref (%d)
3%s[%u]: can't find dpp%d structure
3%s[%u]: failed decon ioremap
3Unsupported encoder type: %d
vblank %s[%u]: plane idx[%d]: alpha(0x%x) hw alpha(0x%x)
%s[%u]: blend_mode(%d) color(%s:0x%x)
%s[%u]: disabling winid:%d
port 6%s: %s[%d]: attr(0x%lx), port(%d)
%s: %s[%d]: -
mode(%dx%d)
3%s: %s[%d]: not supported destination size range
3%s: %s[%d]: failed to request dsi read command
%s: %s[%d]: TE from DDI%d
3%s: %s[%d]: %s failed to get pll-input
dsim_remap_regs %s: %s[%d]: set the same hs_clock=%u while active
3%s: %s[%d]: failed to get possible crtc, ret = %d
odma_irq_handler writeback_enable 6%s: DP Driver has been probed.
6%s: [HPD_PLUG done]
dp_link_up 3%s: dp_hw_reinit() failed
D0 D3 3%s: failed Link Training EQ phase with Rate(%d) and Lanes(%u)
dp_on_by_hpd_plug 6%s: dp_wait_audio_state_change: time = %d ms, state = %d
6%s: [HPD_IRQ start]
displayport dp_crc_get failed, res=%d
dpu_bts_find_max_disp_freq 3%s(#%d) failed to perframe_stop(DSI)
decon_reg_wait_run_status_timeout 3%s(#%d) %s : DSIM_status is not IDLE!
%s(#%d) === DSIM %d LINK SFR DUMP(applied to hw) ===
%s(#%d) %s: phy_con_sel val=0x%x 3%s(#%d) DSI Master is not HS state.
3%s(#%d) DSI Master is not stop state.
3%s(#%d) [odma%d] timeout sw-reset
3%s(#%d) IDMA read slave error irq occur
%s(#%d) Histogram%u: %s
%s(#%d) DQE: gamma matrix %s
%s(#%d)
=== DQE_%d SFR ===
%s(#%d) %s
%s(#%d) OFFSETS[%d]: 0x%x
%s(#%d) VS[%d]: 0x%x
%s(#%d) EDID address command in EDID read
%s(#%d) set sw function
dp_hw_stop_audio dp_reg_do_aux_transaction E dpphy_reg_reset_mpllb %s(#%d) configure for SSC
header dqe_enabled histogram_threshold panel_idle_support max_luminance ABGR2101010 3%s: Unable to import created DMA-BUF heap buffer
exynos_drm_gem_offset blue command CH%u: 0x%llx, %ux%u, ZPOS%u, %s %d[%c] GPU he_clip_min_0 exynos_hibernation_cancel 6%s[%u]: update decon bts config for mode: %dx%dx%d(%d)
%s[%u]: found rcd: dpp%d
3%s[%u]: failed to install EXTRA irq
decon_fs_irq_handler dpp,id 3%s: %s[%d]: src[%d %d %d %d %d %d] dst[%d %d %d %d %d %d] fmt[%d]
dpp_bind 3%s: %s[%d]: failed to add sysfs hs_clock entries
3%s: %s[%d]: runtime resume failed (%d). unable to transfer cmd
%s: %s[%d]: last(%lld) cur(%lld) diff(%lld) ready allow period(%d)
tout-gpio pll-input pll-optimum %s: %s[%d]: the same hs_clock=%u
exynos-writeback 6%s: %s: USB Type-C is HPD PLUG status
PHY 6%s: HW configured with Rate(%d) and Lanes(%u)
6%s: DP Link: training defer: DP Branch Device, sink count = 0
6%s: DP Link: training done: Rate(%d Mbps) and Lanes(%u)
Google 6%s: %s: Connector Status = %d
[BTS] decon%u add bts scenario %u [BTS] -allow_ns(%u) dpu_ns(%u)
decon_reg_reset %s(#%d) none blending(no plane alpha) mode
3%s(#%d) CLK lane doesn't be switched to LP mode
3%s(#%d) dsim%d function reset timeout
dsim_reg_set_clocks 3%s(#%d) Error to enable PHY lane(err=%d)
3%s(#%d) DSI Master clock isn't disabled.
3%s(#%d) dsim%d wait timeout idle status
%s(#%d) DSI Master is ULPS state.
%s(#%d) block x(%d) y(%d) w(%d) h(%d)
3%s(#%d) ODMA cfg err irq occur(0x%x)
%s(#%d) DQE: %s dither %s
%s(#%d) OETF TS[%d]: 0x%x
%s(#%d) TU_size: %llu
last %s: visible_win_mask(0x%x)
EXYNOS_CONTEXT_HISTOGRAM_EVENT_REQUEST reserved_win_mask=0x%x
8bpc [CRTC-%d] new en:%d active:%d change[%d %d %d]
simplified rot[0x%x]
ARGB8888 BGRA8888 ABGR16161616 system ecc_cnt rd_wait_cycle atc ID:%u mst_security:%#x PID: %d disp(%u) peak(%u) rt(%u) read(%u) write(%u) %uhz (crtc: %uhz, op: %uhz) %s: %s[0x%llx] CH%d SRC[%d %d %d %d] %s%s%s%s 4%s: decon%u histogram%u already registered
ctmode lt_calc_mode he_clip_min_1 checking plane%d ...
[PARTIAL]: %s: partial command: [%d %d %d %d]
%s[%u]: INFO: afbc_yuv_rt_util_pct is not defined in DT.
connector samsung,exynos9-disp_ss 3%s[%u]: %s: timeout irq occurs
decon_update_config 4TE from DDI is not valid (%d)
unbalanced te irq
3%s[%u]: bypass mode only supported in self refresh
4decon%u scheduler late to service fs irq handle (%d fps)
3%s: failed to get cgc dma resource
3%s: failed to remap cgc-dma registers
dpp_probe 3%s: %s[%d]: could not get main dsi
dsim_update_clock_config %s[%d]: rx fifo:0x%8x, response:0x%x, rx_len:%lu
%s: %s[%d]: payload: 0x%x i=%d max=%d
%s[%d]: wait for packet payload fifo empty
3%s: %s[%d]: %pOF: could not find dsim-modes node
dsim_of_get_pll_features %s: %s[%d]: pll features: vco (%llu, %llu)
%s: %s[%d]: pll limits: p(%u, %u), m(%u, %u), s(%u, %u), k(%u)
4%s: %s[%d]: %s: no memory for %u diag items
%s: %s[%d]: failed to get pinctrl (%d)
3%s: %s[%d]: failed to enable dphy(%d)
6%s: %s[%d]: set pending_hs_clk=%u
_dsim_exit_ulps_locked ../private/google-modules/display/samsung/exynos_drm_tui.c 6writeback state is off
3%s: failed to remap DP LINK SFR region
6%s: adjust to max swing level
6%s: Voltage_Swing: %02X %02X %02X %02X
3%s: EDID: drm_connector_update_edid_property() failed
6%s: Mode("%s": %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x) is requested
6%s: call drm_kms_helper_hotplug_event (disconnected)
6%s: [HPD IRQ] DP downstream port status change
3%s: failed to DP Link Up during re-negotiation
6%s: call DP audio notifier (connected)
%s: %s -
%s(#%d) === DECON_WINCON%d SHADOW SFR DUMP ===
3%s(#%d) Low-power transmit sync error!
dsim_reg_print_size_of_slice %s(#%d) === DSIM %d DPHY SFR DUMP ===
%s(#%d) -[MC : offset + 0x100]-
%s(#%d) -[MD 3 : offset + 0x100]-
rcd_dma_dump_regs %s(#%d) [stride] y(0x%x 0x%x) c(0x%x 0x%x)
%s(#%d) DQE: atc %s
dqe_reg_wait_cgc_dma_done_internal 3%s(#%d) dp_reg_dpcd_read_burst fail
3%s(#%d) AUX_CONTROL : 0x%X, AUX_REQUEST_CONTROL : 0x%X, AUX_COMMAND_CONTROL : 0x%X
%s(#%d) enable DP AUX.
%s(#%d) configure for DP Emulation Mode
dp_smc_read %s: exynos_smc_readvalue failed (smc_result=%lu)
__data_loc char[] 4crtc[%s]: skipping duplication of inactive crtc state
BT601_525 panel sync_none %s base(%pa) size(%pa)
wait_for_crtc_flip Limited DPU_EVENT_LOG_CMD tout_en rd_hi_thres oetf force_disabled <%6llu.%06lu> %20s RCD dpu_itmon_check histogram_channel_cancel_ioctl no event request for handle#%u
6%s: display quality enhancer is not supported
dqe-cgc is not supported
pending_framedone lt tdr_min adjusted update region rotation is detected. partial->full
scaling is detected. partial->full
%s[%u]: seamless mode change from %dhz to %dhz
%s[%u]: bus_width(%u) bus_util(%u) rot_util(%u)
decon %s[%u]: failed to get aclk(optional)
%s: unsupported connector type
decon_te_irq_handler scl_coef 3%s: %s[%d]: failed to get hdr resource
dpp_check_scale %s: %s[%d]: in/force bpc(%d/%d)
exynos_gm_update %s[%d]: op mode change not allowed seamlessly
%s: underrun_param for mode "%s": %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x not specified unable to link %s sysfs (%d)
4%s: %s[%d]: timeout: packet header fifo empty
%s[%d]: packet go ready (ph: %d, pl: %d)
4%s: %s[%d]: failed to get TE from DDI
p-range 4%s: %s[%d]: failed to remap io region. it's optional
3%s: %s[%d]: failed to get dsim phy
3%s: %s[%d]: failed to get hw_te_on pin state
dsim_bind dsim_encoder_enable dsim_attach_bridge failed to find panel
%s[%d]: state: %d
3%s: unable to get decon
&dp->cmd_lock drm-displayport usb_typec_dp_notification_locked 3%s: failed to remap DP registers
3%s: failed to get USB/DP Combo PHY resource
%s: Common Intr = 0x%08X
6%s: reducing link rate to %d during EQ phase
3%s: Failed to write DP_DOWNSPREAD_CTRL 6%s: %s: DP State changed to RUN
[BTS] -dpu_cycle(%u) aclk_x_1k_ns(%u) dpu_lat_t_ns(%u)
decon_reg_stop %s(#%d)
=== DECON%d_MAIN SFR DUMP ===
decon_sub decon_reg_set_data_path decon_reg_clear_dsimif decon_reg_set_winmap 3%s(#%d) mode[%d] doesn't support multi resolution
3%s(#%d) BT601 with limited range is set as default
%s(#%d) === HDR%d SFR DUMP ===
3%s(#%d) Failed to pack regamma %d posx element
disabled ../private/google-modules/display/samsung/cal_9865/hdr_reg.c %s(#%d) YMIX_DV: 0x%x
hdr_reg_print_gm 3%s(#%d) dp_reg_dpcd_write_burst fail
%s(#%d) %s: dp_audio is already disabled, AUDIO_EN = 0
%s(#%d) status update for %d lanes.
%s(#%d) enable %d lanes.
4%s: DPOSC clock rate != 40 MHz (%ld)
3%s: timeout of waiting for fence, name:%s idx:%d
Samsung SoC DRM gamma_matrix histogram_weights hbm_mode memory-region exynos_drm_gem_mmap Gamma 2.2 Gamma 2.6 IDMA_ERROR 4unable to add decon_debug sysfs files (%d)
force_te_on dsim_diag_create_debugfs desc counters 3%s: invalid device
dqe 3failed to create cgc lut directory
%s
----------------------------------------------------
histogram_channel_request_ioctl %s: decon_id=%u, hist_id=%d hist_state=%d, curr_state=%d
3%s: failed to create to atc sysfs device
6%s: display quality enhancer is supported(DQE_V%d)
histogram_event_ioctl_process_arg pl_w2 6display hibernation is not supported
exynos_partial_reconfig_coords &decon->framedone_wait 4%s[%u]: failed to parse urgent rd_hi_thres(%d)
%s[%u]: rotator ppc(%d)
no 3%s[%u]: can't find dpp%d node
extra frame_transfer DSI0 %s[%u]: %s: frame done after: ~%dus (%dhz) decon is not ready 3%s: failed to install CGC DMA irq
hdr_comm 3%s: %s[%d]: failed to get hdr comm resource
3%s: %s[%d]: not supported source alignment
set_protection %s: %s[%d]: ch:%u, en:%d
%s[%d]: dsc change not allowed seamlessly
3%s: %s: max frame time %llu < min frame time %llu
%s[%d]: found proper pll parameter
%s: %s[%d]: EoTp was received
4%s: %s[%d]: timeout: packet payload fifo empty
%s: %s[%d]: packet go ready (ph: %d, pl: %d)
dsim_mode hs-clk underrun irq occurs(%u): MIF(%lu, %d), INT(%lu, %d), DISP(%lu, %d)
hw_te_on 3%s: %s[%d]: failed to get hw_te_off pin state
%s[%d]: set the same hs_clock=%u while idle
%s[%d]: set the same hs_clock=%u while active
dsim_set_hs_clock tui-driver 6src_f_w[%d %d %d] src_f_h[%d %d %d]
param_dp_emulation_mode_set dp_hpd_changed edid_invalid_failures 6%s: DP Sink: sink power state set to %s
3%s: failed Link Training CR phase with Rate(%d) and Lanes(%u)
6%s: Link Training EQ Phase with Rate(%d) and Lanes(%u)
6%s: dp_wait_state_change: time = %d ms, state = %d
6%s: [HPD IRQ] Content Protection
6%s: [HPD IRQ] unknown IRQ (0x%X)
3%s: failed to get possible crtc, ret = %d
%s: %s +
6[BTS] IDMA_TYPE(%d) CH(%d) Port(%u)
dpu_vote_peak_bw dpu_vote_avg_bw dpu_bts_calc_bw [BTS] peak = %u, rt = %u, read = %u, write = %u
../private/google-modules/display/samsung/cal_9865/decon_reg.c %s(#%d) regs->ch(%d)
%s(#%d) === DECON_WIN%d SHADOW SFR DUMP ===
%s(#%d)
=== DECON_SUB.DPIF%d SFR DUMP ===
%s(#%d)
= DECON_SUB.DSC%d SFR DUMP =
dsim_reg_function_reset 3%s(#%d) failed to %s ULPS idma_reg_wait_sw_reset_status %s(#%d) === HDRCOMM%d SHADOW SFR DUMP ===
dp_regs_desc_init %s(#%d) DP Link Version = 0x%X
%s(#%d) Success to change mode from USB to DP%d
pid mipi_sync XBGR8888 3%s: Failed to allocate IOVM (%lld)
DPP #%d underrun: %u
crc: %u
ecc: %u
idma_error: %u
state: %s
block_count: %d
val ymix_slope CHs: G2D dstep(%u), actual dstep(%u), vrefresh(%d)
invalid partial update region exynos_plane_print_info 4%s[%u]: WARN: DPU DFS Info is not defined in DT.
%s[%u]: bypass mode: drop extra power ref
%s[%u]: resumed
3%s: failed to get cgc-dma id
dpp_print_restriction 3%s: %s[%d]: support rotation only for YUV420 format
%s: %s[%d]: dsc change not allowed seamlessly
&dsim->state_lock %s: %s[%d]: %s +
3%s: %s[%d]: fifo would be full. ph(%u) pl(%lu) max(%d/%d)
%*phN 3%s: %s: empty diag-name
%s[%d]: PH_FIFO_EMPTY irq occurs
4%s: %s[%d]: failed to get dsim extra phy
6%s: %s[%d]: not in HS state, set pending_hs_clk=%u
unable to create dev link between decon/dsim
3failed to get dpp resource
dp_link 3%s: failed to read DP Sink device capabilities
6%s: enable DP training pattern 2
3%s: EDID: invalid EDID, using fake EDID
6%s: enabled DP as cur_mode = %s@%d
%s: [HPD IRQ] IRQ work skipped as power is off
3%s: failed to DP Link Up during DFP event
6%s: AutoTest: voltage swing[%d] = %x
3%s: unsupported DP Request(0x%X)
3[BTS] decon%u failed to get `%s` bts scenario %s(#%d) name(%s) type(%d) regs(%p)
decon_reg_set_start_crc %s(#%d)
=== DECON_WIN%d SFR DUMP ===
%s(#%d) %s +
%s(#%d) TEN_BPC=%d : A=%02Xh, R=%03Xh, G=%03Xh, B=%03Xh
%s(#%d) SEL_VCO = 0
dsim_reg_enable_pll exit 3%s(#%d) SBWC is not supported
%s(#%d) coef_id : %d h_ratio : %#x, v_ratio : %#x
dqe_reg_print_regamma_lut dqe_reg_set_gamma_matrix dqe_reg_print_hist_lut hdr_reg_set_fp16 %s(#%d) locked PHY PLL
%s(#%d) set system clk to TX: Mux(%u)
%s(#%d) reconfig USBDP Combo PHY
%s: dp_smc_write_mask failed: %d
dpphy_reg_init %s(#%d) FEC_Off(int: %d, frac: %d, thr: %d)
exynos_drm_drv_set_lhbm_hist exynos_atomic_exit_tui exynos_atomic_check_windows exynos cgc_dither cgc_lut %s:%d, dma_addr[%d] = 0x%llx (+0x%x)
4[drm] %p4cc is not proper format for colormap
ARGB2101010 BGRA1010102 block DPU_EVENT_LOG fp16_cvt_en state %s: en(%d) dirty(%d)
exynos_cgc_update exynos_regamma_update pp_en threshold_1 he_clip_max_1 %s: decon state: %d +
restored partial region align limitation. src_x/y[%d/%d] align[%d]
[PARTIAL]: %s: slice left(%d) right(%d)
[PARTIAL]: %s: slice[%d] is %s
decon_tout_irq_handler dpps TE from DDI%d
%s[%d]: === buffer dump[%s:%s]: dpp%d dma addr 0x%pad, vaddr 0x%p ===
exynos-dpp exynos_eotf_update dsim_mode_is_seamless %s[%d]: underrun_lp_ref 0x%x
%s[%d]: enabling packetgo
%s: %s[%d]: payload length(%lu)
diag-name 6%s: %s[%d]: dsim handover. skip_init=%d
6%s: %s: USB Type-C is HPD UNPLUG status, or not in display ALT mode
dp_hotplug_error_code 3%s: failed to get DP interrupts
dp_enable 6%s: DP Driver has been binded
dpu_bts_release_resources [BTS] final: avg %u, rt %u
[BTS] add DECON%d AXI_DPU%d = %u
../private/google-modules/display/samsung/cal_9865/dsim_reg.c ../private/google-modules/display/samsung/exynos_drm_dsim.c 6%s(#%d) pll sleep is not allowed
%s(#%d)
=== DECON_SUB.DSIMIF%d SFR DUMP ===
wincon decon_reg_stop_inst_dp 3%s(#%d) %s is timeout.
%s(#%d) bps(%u) clk_prepare(%u) clk_zero(%u) clk_post(%u)
3%s(#%d) PHY clock lane is not ready[timeout]
__dphy_dump %s(#%d) -< DMA COMMON DEBUG SFR >-
%s(#%d) 0x%4x 0x%4x 0x%4x
3%s(#%d) CGC DMA deadlock irq occur
3%s(#%d) CGC DMA cfg err irq occur
%s(#%d) weight red(%u) green(%u) blue(%u)
%s(#%d) TS[%d]: 0x%x
%s(#%d) 2nd address only request in EDID read
%s(#%d) post-init USBDP Combo PHY
%s(#%d) PIN_TYPE_%s
6tui enabled reject commit(%pK)
u16 %c|%d|%s|%d
Upside Down 3failed to reserve memory lookup
connector_commit P010_AFBC 3%s: Failed to create dumb of %llu bytes (%ux%u/%ubpp)
exynos_plane_atomic_check BT470M itmon,dest ymix_dv histogram: created event(0x%pK) of decon%u, chan %u
histogram_emmit_event_locked exynos_gamma_matrix_update st applied partial region exynos_partial_restore [PARTIAL]: %s: partial[%dx%d] vporch[%d %d %d] hporch[%d %d %d]
ppc_scaler %s[%u]: INFO: afbc_rgb_util_pct is not defined in DT.
dfs_lv 3%s[%u]: failed to install FRAME DONE irq
%s: mode(%dx%d)
3%s: AFBC Block Size(%llu) is not supported
__dpp_enable %s[%d]: clock mode change not allowed seamlessly
dsim_probe 3%s: %s[%d]: unable to register dsi host
dsim0 dsim %s: %s[%d]: payload: 0x%x
need_wait_vblank dsim_of_get_clock_mode dphy_diag dsim_dphy_extra 3%s: %s: hs clock %llu out of range
&dp->hpd_lock 6%s: %s: disp_orientation = %d
irq_hpd edid_read_failures dp_irq_handler 6%s: [HPD_PLUG fail] call drm_kms_helper_hotplug_event(dp_hotplug_error_code=%d)
4%s: %s: invalid value %s
%s: %s: dp_crc_set_enabled(SST1, %d) successfully
3[BTS] [%s] undefined decon id(%u)!
../private/google-modules/display/samsung/cal_9865/dpp_reg.c 6%s(#%d) set cwb for DECON%u (en:%d)
decon_reg_set_window_control 3%s(#%d) wait timeout decon idle status
%s(#%d) sel(0x%X) OFIFO.%u - dsim%u
%s(#%d) word clock is %u MHz
%s(#%d) requested escape clock %u MHz
dsim%u: PLL_EN is not %s
3%s(#%d) PHY %s failed[timeout]
dsim_reg_wait_phy_ready_clane 3%s(#%d) The ddi(%d) doesn't support ULPS
rcd_reg_wait_sw_reset_status enabled %s(#%d) DQE_ATC_GT_CONTROL: %x
%s(#%d)
=== DQE_%d CGC SFR ===
3%s(#%d) timeout of CGC COEF DMA request (0x%x)
dp_hw_write_dpcd_burst D 3%s(#%d) abnormal lanes
phy-tca tui_status 3%s: failed to atomic commit suspend_state(0x%x)
%s: avail_win=0x%x freed_mask=0x%x
exynos-crtc-%u Pre DQE alpha[%d] blend mode[%d]
dpu_find_fmt_info exynos_drm_gem_alloc 6[drm] #%d event log buffers are allocated
rd_en [%08X] 6%s: port: %s, dest: %s
verbose ymix_tf %14s %20s %20s
DPU POWER:%s DSIM STATE:%u DSIM POWER:%s enable(%d) active(%d) sr(%d) [p:%d m:%d a:%d c:%d] [%d %d %d %d] HDR
decon%u histogram%u: handle event(0x%pK), rstate(%s)
threshold_3 gt_lamda [PARTIAL]: %s: checking plane%d ...
[PARTIAL]: %s: plane%d/win%d src[%d.%06ux%d.%06u%+d.%06u%+d.%06u] dst[%dx%d%+d%+d]
exynos_recovery_register 6[RECOVERY] %s: recovery is successfully finished(%d)
%s[%u]: DECON state is not On(%d)
4%s[%u]: win config[%d] set during handover
3%s[%u]: failed to parse dta_lo_thres(%d)
afbc_rgb_util_pct decon_check_modeset exynos_cgc_dma_register exynos-dsim %s: %s[%d]: dsim mode %s dsc is %s [%d %d %d %d]
%s[%d]: %s(p:0x%x,m:0x%x,s:0x%x,k:0x%x)
6%s: %s[%d]: driver has been probed.
__dsim_cmd_packetgo_enable_locked 6%s: %s[%d]: rx fifo:0x%8x, response:0x%x
dsim_wait_for_cmd_fifo_empty %s: %s[%d]: header(0x%x 0x%x 0x%x) size(%lu) ph fifo(%d)
%s[%d]: the same hs_clock=%u
%s: %s[%d]: current state: %d
writeback_bind 6%s: DP HPD changed to %d
drm-displayport-stats link 6%s: %s: DP is already powered off
6%s: DP Link: training start: Rate(%d Mbps) Lanes(%u) EF(%d) SSC(%d) FEC(%d)
6%s: DP Link: detected pending HPD UNPLUG
6%s: CR Done. Move to Training_EQ.
6%s: EDID: Sink Manufacturer: %s
3%s: Not Supported PHY_TEST_PATTERN: %02x
[BTS] WARN: latency calc is abnormal!(-> %u%%)
[BTS] [ROT-] AFTER latency check: %llu KHz
../private/google-modules/display/samsung/exynos_drm_fb.c decon_wincon 6%s(#%d) clearing dsimif%u sel, val: %u
3%s(#%d) failed to change running status of DECON%d
4%s(#%d) undefined blending mode
3%s(#%d) SoT error!
3%s(#%d) not support attribute(0x%lx)
cgc_dma_dump_regs R2Y %s(#%d) === SRAMC%d SFR DUMP ===
%s(#%d) DQE: linear matrix %s
%s(#%d) DQE: degamma POSY
dqe_reg_set_linear_matrix %s(#%d) COEFF02: 0x%x
%s(#%d) TS:
3%s(#%d) SST LongHop Power is not ON
dp_crc_get dp_reg_set_swreset dposc_clk 3%s: failed to get DPOSC clock
histogram_pos Normal BT2020_CONSTANT_LUMINANCE 4%s: failed to create %s
green 3failed to create regamma directory
histogram: terminated histogram event of decon%u, chan %u
he_clip_max_2 exynos_hibernation_handler [PARTIAL]: %s: scaling is detected. partial->full
exynos_partial_send_command exynos_partial_set_size unbalanced te irq (%d)
%s: state(%d)
4%s[%u]: WARN: rotator ppc is not defined in DT.
bts_scen_min_fps bts_scen_max_peak dfs_lv_cnt decon_get_clock decon_bind decon%d: wait for frame done timed out (%dhz) %s[%d]: dpp state is off
%s[%d]: unable to find vaddr for old buffer
%s: cgc-dma is not supported
3%s: %s[%d]: not supported source size range
%s[%d]: short packet was received
%s[%d]: long packet was received
te-gpio 3%s: %s[%d]: could not get dsi modes
cmd_underrun_cnt k-bits 3writeback(dpp%d) probe failed normal A hpd 6%s: [HPD_PLUG start]
6%s: call drm_kms_helper_hotplug_event (connected)
6%s: PICK: "%s": %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x
6%s: display_info->bpc = %u, bpc = %u
3%s(#%d) type(%d): id(%d)
%s(#%d) %d bpc mode is set
%s(#%d) hs_trail(%u) lpx(%u) hs_exit(%u)
%s(#%d) b_dphyctl(%u)
enter sramc_dump_regs dqe_reg_set_regamma_lut dqe_reg_print_linear_matrix hdr_reg_set_tm 3%s(#%d) sending segment failed
%s(#%d) disable all lanes.
3%s: failed to get USB/DP Combo PHY TCA resource
4[drm] %s: No windows available for req win cnt=%d->%d (0x%x)
exynos_drm_bind &private->dp_tui_lock EXYNOS_HISTOGRAM_CHANNEL_CANCEL 3failed to allocate exynos crtc state
dsi_mode=%s (%d)
sw DCI-P3 BT2020 min_luminance On IRC Off sync_refresh_rate allocated %zu bytes with flags %#x
DPU_EVENT_LOG_ATOMIC_COMMIT 4[drm] failed to alloc event log buf[%d]. retry
failed to create debugfs urgent directory
dta_lo_thres dpu_itmon_notifier cgc coeff_01 remained event(0x%pK)
histogram_event_cancel_ioctl %s: dqe-cgc is not supported
3%s: failed to create dqe class
histogram_chan_collect_bins_locked histogram_chan_handle_event_locked __exynos_dqe_update threshold_2 he_clip_min_2 plane mask[0x%x]
6%s[%u]: %s: en %d, ref %d
bus_width %s[%u]: INFO: afbc_rgb_rt_util_pct is not defined in DT.
main dimming_start %s[%u]: %s: frame start
%s[%u]: %s: irq_sts_reg = %x, ext_irq = %x
%s[%u]: failed to get aclk_disp(optional)
decon_enable 4%s[%u]: %s: conn_state is null!
wait for earliest present time DPP%u: when enabling HDR, EOTF_EN need to be set(GM %s TM %s OETF %s)
%s: cgc-dma is supported
AFBC %s: %s[%d]: clk_param.hs_clk=%u, pll_freq=%u, pending_hs_clk=%u
3%s: %s[%d]: unable to add dsim component
logbuffer register failed
%s: %s[%d]: packetgo disabled
3%s: %s[%d]: invalid rx len(%lu) max(%d)
__dsim_wait_for_pl_fifo_empty dsim_write_data_locked dsim_pktgo_wait_vblank %s[%d]: pll limits: p(%u, %u), m(%u, %u), s(%u, %u), k(%u)
hs_clock_store 3%s: %s: no proper s found
%s: Video Intr = 0x%08X
6%s: %s: DP State changed to INIT
6%s: DP Sink: DPCD_%X MAX_LINK_RATE 0x%X, adjust max to HBR3
memcpy 3%s: [HPD IRQ] cannot read link status
3%s: Not Supported AUTOMATED_TEST_REQUEST: %02x
dpu_bts_convert_config_to_info dpu_bts_update_disp_ch_bw [BTS] aclk_base is greater than L0 frequency! decon_win decon_reg_set_bpc 4%s(#%d) decon%d RSC_STATUS_0: SEL_CH = 0x%x
3%s(#%d) DSIM status is not IDLE!
dsim_reg_stop_and_enter_ulps 3%s(#%d) DSI data type not recognized!
dsim_reg_set_mres %s(#%d) %s: command mode set
%s(#%d) %s: checked = %d
%s(#%d) === DPU_DMA CGC%d SHADOW SFR DUMP ===
3%s(#%d) AFBC is not supported
%s(#%d) OFFSETS:
Shift %s(#%d) Table red(%c) green(%c) blue(%c)
hdr_reg_print 3%s(#%d) AUX_MONITOR_1 : 0x%X, AUX_MONITOR_2 : 0x%X
dpphy_reg_set_config12_status_update dpphy_reg_cr_write_mask %s: exynos_smc failed (smc_result=%lu)
3%s: not in tui
delay_ms disp_dither hw 4[drm] %s: plane-less update is detected, mask=0x%08X
BGRX8888 %s: mapped vaddr: %pK
exynos_drm_gem_dumb_map_offset lut 3failed to create histogram directory
te cnt(%u) WINs: 6%s: decon%u: clear all events
histogram: run_state: %s -> %s
en(%d) dirty(%d)
exynos_dither_update 4%s: unable to enter self refresh (%d)
exynos_partial_prepare decon_seamless_mode_bts_update 4%s[%u]: failed to parse urgent rd_wait_cycle(%d)
3%s[%u]: failed to parse dta_hi_thres(%d)
bts_scen_min_panel_width bts_scen_skip_with_video %s[%u]: %s +
sw trigger. couldn't find win id (%d) for zpos=%d plane_mask=0x%x
%s[%u]: suspended
%s[%d]: === old buffer dump[%s:%s]: dma addr 0x%pad, vaddr 0x%p ===
%s[%d]: rcd state is off
6%s: %s[%d]: dpp irq no = %d
3%s: %s[%d]: failed to %s protection(ch:%u, ret:%d)
6%s: %s[%d]: dsim idle_ip_index[%d]
6%s: %s[%d]: already disabled(%d)
dsim_phy_power_off %s[%d]: last(%lld) cur(%lld) diff(%lld) ready allow period(%d)
dsim_get_pinctrl 6src_w[%d %d %d] src_h[%d %d %d] src_x_y_align[%d %d]
6blk_w[%d %d %d] blk_h[%d %d %d] blk_x_y_align[%d %d]
&dp->hpd_state_lock link_unstable_failures 6%s: [HPD_UNPLUG start]
3%s: DP Sink: invalid max link rate
6%s: DP Sink: sink count = %d
6%s: reducing lanes number to %u during CR phase
6%s: [HPD IRQ] device irq vector = %02x
3%s: failed to initialize connector with drm
%s: %s: c->status=%d dp->state=%d c->dpms=%d dp->hdcp_and_audio_enabled=%d
6[BTS] decon%u gets `%s bts scenario idx %u
[BTS] -line_t_ns(%u) v_blank_t_ns(%u)
[BTS] Overlap BW%d = %u
exynos_drm decon_reg_set_pll_sleep decon_reg_wait_update_done_timeout %s(#%d) sel(0x%X) not connect to dsim%u
%s(#%d) %s -
decon_reg_stop_inst_dsi 4%s(#%d) decon%d RSC_STATUS_5: SEL_DSCC = 0x%x
dsim_reg_wait_enter_ulps_state dma_reg_set_base_addr 3%s(#%d) ODMA write slave error irq occur
%s(#%d) === HDRCOMM%d SFR DUMP ===
%s(#%d) ROI position start x,y(%u,%u)
on dqe_reg_print_atc %s(#%d) COEFF00: 0x%x
dp_hw_deinit %s(#%d) set MPLLB as link_bw.
%s(#%d) [CR][%04X][%04X] dpphy_reg_cr_read %s(#%d) bpp:%u, stream_clk: %u MHz, ls_clk: %u MHz, num_lanes: %u
u32 value %s: win cnt changed: %d -> %d
%s: invalid reserved mask (0x%x) for win_cnt (%d->%d) 4%s: error of waiting for dma fence, ret=%d
plane: crtc-pos=%dx%d%+d%+d
3%s: Failed to allocate %#zx bytes from DMA-BUF system heap
failed to initialize plane
alpha: 0x%x
histogram vs coeff_00 minimum rect size[%dx%d] crc count(%u) %s: en(%d) dirty(%d) vrefresh(%d) dstep(%d/%d)
histogram_cancel_ioctl %s: remained event(0x%pK)
idle tdr_max 6display hibernation is overridden
exynos_crtc_self_refresh_update %s: skipping due to (active=%d enable=%d)
exynos_partial_find_included_slice sys 3%s: %s[%d]: probe failed scale_up Not 3%s: %s[%d]: %s failed to get pll-vco-range
3%s: %s[%d]: failed to remap io region
3%s: %s[%d]: failed to get sys resource
%s[%d]: PL_FIFO_EMPTY irq occurs
3%s: %s[%d]: invalid bist mode
3%s: %s[%d]: failed to control decon TE(%d)
6%s: EDID: Sink Product: %x
6%s: EDID: Sink Name: %s
6%s: disabled DP
[BTS] BTS_BW_TYPE(%d)
3invalid RCD AXI channel number %u
[BTS] [ROT+] BEFORE latency check: %u KHz
%s(#%d) interrupt val = %x
%s(#%d) = DECON_SUB.DPIF%d SHADOW SFR DUMP =
decon_reg_set_win_mapcolor 3%s(#%d) Not specified case for Partial Update
dsim_reg_rx_err_handler %s(#%d) === DPU_DMA%d SHADOW SFR DUMP ===
3%s(#%d) [idma] timeout sw-reset
dqe_reg_print_lut %s %s: rejecting DMA map of vmalloc memory
%s(#%d) EOTF VS[%d]: 0x%x
%s(#%d) COEFF01: 0x%x
%s(#%d) HDR: oetf %s
%s(#%d) dpphy_reg_usbdrd_qch_en is skipped.
C bool int EXYNOS_HISTOGRAM_REQUEST ppc expected_present_time exynos_crtc_atomic_check 3create brightness_capability property failed rmem_device_init disabling bridge chain [ENCODER:%u:%s]
6[drm] %s: can't find format(%d) in supported format list
BGR565 %s: mapped dma_addr: 0x%llx
not supported modifier(0x%llx)
ST2084 transfer oetf_lut dphy 3failed to create %s directory
3failed to create gammut matrix directory
%s mode, %s_trigger, out type:0x%x, dsi_mode:%d.(%dx%d@%dhz) COLOR %d en(%d) dirty(%d) vrefresh(%d) dstep(%d/%d)
%s: decon%u histogram%u: handle event(0x%pK), rstate(%s)
exynos_linear_matrix_update camera-operation exynos_hibernation_exit exynos_partial_init exynos_partial_adjust_region 4%s Unsupported connector type
update_dsi_config_from_exynos_connector %s[%u]: %s: win=%d enabled dpp_ch=%d
4%s[%u]: %s: dpp is owned by decon #%d
%s[%u]: %s: final win_mask=0x%lx
4%s[%u]: unable to get free win_id=%d mask=0x%x
decon_runtime_suspend DPP%u: when enabling HDR for FP16, FP16 or CVT need to be set(GM %s TM %s OETF %s)
6%s: %s[%d]: successfully probed 6%s: %s[%d]: src_w[%d %d %d] src_h[%d %d %d] src_x_y_align[%d %d]
dpp_init_resources dpp_check 3%s: %s[%d]: not support AFBC
exynos_oetf_update %s[%d]: %s(hs:%d,esc:%d)
_dsim_disable 3%s: %s[%d]: failed to disable ext dphy(%d)
%s: %s[%d]: wait for packet payload fifo empty
%s: %s[%d]: no need to wait for packet header fifo empty
dsim_cmd_packetgo_queue_locked %s[%d]: total pending packet header(%u) payload(%u)
3%s: %s[%d]: no device tree information
dsim-modes m-range 3%s: %s[%d]: %s failed to get k-bits
3%s: %s: wrong number of reg-offset: %d
3%s: failed to get dphy resource
dsim_register_irq %s: %s[%d]: PL_FIFO_EMPTY irq occurs
6%s: %s[%d]: 4:Prbs7 Random (%d)
../private/google-modules/display/samsung/exynos_drm_writeback.c 6dst_w[%d %d %d] dst_h[%d %d %d] dst_x_y_align[%d %d]
wb_convert_connector_state_to_config 6%s: audio_config: ch(%d), fs(%d), bit(%d), packed(%d), word_len(%d)
4%s: DP HPD UNPLUG work was already queued 4%s: %s: num_audio_ch != 2
4%s: %s: audio_fs != 48 kHz
pin_assignment dp_work_hpd 3%s: DP Sink: failed to write sink power state
3%s: Failed to write DP_LINK_BW_SET 4%s: %s: unknown EDID block %d requested
3%s: dp_wait_audio_state_change: timeout
6%s: [HPD IRQ] device irq vector esi1 = %02x
[BTS] DSC: lat_cycle(%u)
%s(#%d) %s: WINCON%d = 0x%x
decon_reg_set_pll_wakeup decon_reg_set_win_bnd_function %s(#%d) === DSIM %d LINK SFR DUMP ===
dsim_reg_sw_reset dpp_reg_wait_sw_reset_status dp_hw_read_dpcd_burst %s(#%d) set system clk to OSC with %d MHz: Mux(%u)
dp_hw_start dp_reg_check_aux_monitors dpphy_reg_set_lanes tx_buf linear_matrix no partial region request
histogram_1 sync_bl hdr_formats RGBA1010102 3%s: Invalid decon
[%08lX] %s%s
6%s: power %s state
matrix coeffs HDR Unknown ZPOS%d 3%s: %s: ignored
decon%u histogram%u: decon is already idle
la_w %s: %s took %lldus
[PARTIAL]: %s: align limitation. src_x/y[%d/%d] align[%d]
3%s[%u]: failed to run display thread
decon,id ppc_rotator bts_scen_min_rt 4%s[%u]: %s: irq occurs with decon->state=%d
6%s[%u]: %s +
3%s[%u]: unsupported decon output (%d)
[drm] %s: handover memory defined, but no windows attached
4%s[%u]: decon state = %u at suspending
%s[%d]: framebuffer not found
attr dpp %s[%d]: dsim mode %s dsc is %s [%d %d %d %d]
%s[%d]: packetgo disabled
%s: %s[%d]: long packet was received
4%s: %s[%d]: timed out but header fifo was empty
reg-offset dsim_underrun_info 6%s: %s[%d]: already enabled(%d)
[TUI Driver] %s
3failed to get dma resource
3%s: failed to parse dp device tree.
phy 3%s: dp_hw_init() failed
3%s: Link training failed during EQ phase
3%s: Failed to write DP_LANE_COUNT_SET 6%s: call DP audio notifier (disconnected)
3%s: dp_wait_state_change: timeout for disable
6%s: [HPD IRQ] sink count = %u
3%s: [HPD IRQ] cannot read DP_LINK_SERVICE_IRQ_VECTOR_ESI0
4%s: %s: DP is not ON
dpu_vote_clock [BTS] add DECON%d Overlap BW = %u
[BTS] SCALE: lat_cycle(%u)
[BTS] -tx_allow_t_ns(%u) rot_init_bw(%u) rot_need_clk(%llu)
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5 E O Q R # ) dp_dpcd_read_for_hdcp22 __tracepoint_tracing_mark_write dp_ado_notifier_head exynos_drm_mode_te_freq dp_audio_config dp_dpcd_write_for_hdcp22 __traceiter_dsi_label_scope is_exynos_drm_connector __tracepoint_dsi_label_scope exynos_drm_connector_init exynos_atc_update exynos_drm_connector_get_properties __SCK__tp_func_dsi_label_scope exynos_bts_fps_to_drm_mode_clock of_find_dpp_by_node dp_drvdata exynos_drm_connector_get_lhbm_gray_level exynos_drm_mode_bts_fps exynos_drm_drv_set_lhbm_hist __traceiter_tracing_mark_write exynos_drm_drv_get_lhbm_gray_level exynos_recovery_register exynos_drm_connector_set_lhbm_hist dsim_trace_msleep __SCK__tp_func_tracing_mark_write dp_hdcp_update_cp dsi_tx dsi_rx dsi_cmd_fifo_status msleep dsi_label_scope tracing_mark_write author=Inki Dae author=Joonyoung Shim author=Seung-Woo Kim description=Samsung SoC DRM Driver import_ns=DMA_BUF license=GPL parmtype=event_log_max:uint parmtype=event_print_max:uint parmtype=debug_dump_mask:uint parm=event_log_max:entry count of event log buffer array parm=event_print_max:print entry count of event log buffer parm=debug_dump_mask:mask for dump debug event log author=Hyung-jun Kim author=Seong-gyu Park description=Samsung SoC Display and Enhancement Controller license=GPL v2 author=Seong-gyu Park description=Samsung SoC Display Pre Processor license=GPL v2 parmtype=panel_name:string parm=panel_name:preferred panel name parmtype=sec_panel_name:string parm=sec_panel_name:secondary panel name softdep=pre: phy-exynos-mipi author=Donghwa Lee description=Samsung SoC MIPI DSI Master license=GPL v2 description=Samsung SoC TUI Driver license=GPL author=Wonyeong Choi description=Samsung SoC Display WriteBack license=GPL v2 parmtype=dp_rate:ulong parm=dp_rate:use specific DP link rate by setting dp_rate=x parmtype=dp_lanes:ulong parm=dp_lanes:use specific number of DP lanes by setting dp_lanes=x parmtype=dp_bpc:ulong parm=dp_bpc:use specific BPC by setting dp_bpc=x parmtype=dp_fec:bool parm=dp_fec:Enable/disable DP link forward error correction parmtype=dp_ssc:bool parm=dp_ssc:Enable/disable DP link spread spectrum clocking parmtype=dp_phy_boost:bool parm=dp_phy_boost:Enable/disable DP PHY current boost parmtype=dp_bist_mode:ulong parm=dp_bist_mode:use BIST mode by setting dp_bist_mode=x parmtype=dp_edid_hexdump:bool parm=dp_edid_hexdump:Enable/disable DP EDID hexdump parmtype=dp_audio:bool parm=dp_audio:Enable/disable DP audio parmtype=dp_enabled:bool parm=dp_enabled:Enable/disable DP notification processing parm=dp_emulation_mode:Enable DisplayPort emulation mode author=YongWook Shin author=Petri Gynther description=Samsung SoC DisplayPort driver license=GPL vermagic=6.1.75-android14-11-g48b922851ac5-ab12157876 SMP preempt mod_unload modversions aarch64 name=exynos_drm scmversion=g50426e56d1a5 depends=exynos-pd_el3,dwc3-exynos-usb,gs-drm-connector,exynos_devfreq,exynos_tty,itmon,dss,exynos-cpupm,logbuffer,exynos_pm_qos,drm_display_helper,exynos-hdcp2,bts,cmupmucal alias=of:N*T*Csamsung,exynos-decon alias=of:N*T*Csamsung,exynos-deconC* alias=of:N*T*Csamsung,exynos-dsim alias=of:N*T*Csamsung,exynos-dsimC* alias=of:N*T*Csamsung,exynos-dp alias=of:N*T*Csamsung,exynos-dpC* Linux Linux exynos_drm ~ _printk eb, __dynamic_pr_debug wPl set_priv_reg e? ktime_get __const_udelay !rk log_read_mmio ^ log_post_read_mmio ғ __stack_chk_fail Rw( drm_printf k
of_property_match_string t 6 of_address_to_resource
`V arm64_use_ng_mappings ;@ ioremap_prot S9 iounmap +@ log_write_mmio $ drm_atomic_get_connector_state is_gs_drm_connector Vm drm_connector_list_iter_end
drm_atomic_helper_check_modeset QN. drm_atomic_normalize_zpos drm_atomic_helper_check_planes >8 drm_self_refresh_helper_alter_state 6 drm_atomic_get_private_obj_state $- drm_atomic_helper_setup_commit `p drm_atomic_helper_prepare_planes F' drm_atomic_helper_swap_state wGo drm_atomic_helper_cleanup_planes ' system_highpri_wq *s queue_work_on 8 kthread_queue_work Ӭ cpu_number NY __cpu_online_mask MJ preempt_schedule_notrace _i refcount_warn_saturate * __drm_printfn_info # dma_fence_release 9 dma_fence_wait_timeout {' _raw_spin_lock_irq p= dma_fence_signal_locked e ns_to_timespec64 SuK _raw_spin_unlock_irq (k drm_atomic_helper_wait_for_dependencies lQ drm_atomic_helper_commit_tail _~R drm_atomic_helper_commit_cleanup_done ʹ __drm_atomic_state_free ƒ3 mutex_trylock { mutex_lock E drm_modeset_acquire_init Դy drm_modeset_backoff ~5 drm_modeset_lock_all_ctx drm_atomic_helper_duplicate_state \ drm_atomic_state_alloc drm_atomic_get_crtc_state __pm_runtime_resume 0 drm_atomic_add_affected_planes ,8 drm_atomic_add_affected_connectors l[ drm_atomic_set_fb_for_plane gvF drm_atomic_set_crtc_for_plane G drm_atomic_commit "' sysfs_notify U mutex_unlock o%S drm_modeset_drop_locks Ȯ drm_modeset_acquire_fini __pm_runtime_idle [ drm_atomic_helper_commit_duplicated_state platform_device_register_full ~ϝ platform_find_device_by_driver i! put_device platform_device_unregister :CL __platform_driver_register cU platform_driver_unregister G trace_raw_output_prep 6+ trace_print_hex_seq o trace_event_printf (s trace_handle_return : component_match_add_release component_master_add_with_match &y component_master_del ]l drm_atomic_helper_shutdown BA& __devm_drm_dev_alloc T __init_waitqueue_head q __mutex_init O drmm_mode_config_init kmalloc_caches Cu kmalloc_trace W| drm_atomic_private_obj_init 0 component_bind_all lL drm_vblank_init A component_unbind_all > drm_atomic_private_obj_fini ~ _dev_err z drm_mode_config_reset O drm_kms_helper_poll_init ez~ drm_dev_register Y_ device_create_file = drm_kms_helper_poll_fini *g device_remove_file ( drm_dev_unregister bW drm_dev_put z kfree A̴f kmemdup ) __drm_atomic_helper_private_obj_duplicate_state 'W. trace_event_reg DCا trace_event_raw_init Z drm_gem_prime_handle_to_fd <$ drm_gem_prime_fd_to_handle yN drm_read drm_poll [ drm_ioctl $y drm_compat_ioctl drm_open ai drm_release drm_crtc_vblank_get 4 _raw_spin_lock_irqsave 9 drm_crtc_arm_vblank_event p\ _raw_spin_unlock_irqrestore drm_atomic_set_mode_prop_for_crtc 9 drm_atomic_set_crtc_for_connector PRV drm_atomic_state_clear XWx __drmm_crtc_alloc_with_planes _k drm_property_create_enum ֻ1 drm_object_attach_property cn drm_property_create_range Lm drm_crtc_enable_color_mgmt
# drm_property_create drm_property_create_bool , drm_property_create_bitmask nJne snprintf s drm_property_create_signed_range w2~ ___drm_dbg [k drm_bridge_chain_mode_set U< __drm_atomic_helper_crtc_reset W7 drm_property_blob_get Íd __drm_atomic_helper_crtc_duplicate_state ! drm_property_blob_put w drm_gem_object_free u __drm_atomic_helper_crtc_destroy_state Z strncmp `2 drm_property_lookup_blob $ drm_property_replace_blob D"z1 dma_buf_fd f䲟 drm_crtc_vblank_on &m drm_crtc_vblank_off chS drm_crtc_send_vblank_event c.s drm_atomic_helper_set_config drm_atomic_helper_page_flip u drm_connector_init
4 drm_mode_vrefresh +f8 __drm_atomic_helper_connector_destroy_state __drm_err v sysfs_remove_link fA drm_connector_unregister ' drm_connector_cleanup E&T __drm_atomic_helper_connector_duplicate_state Zom drm_helper_probe_single_connector_modes
& __of_parse_phandle_with_args [ of_reserved_mem_lookup V of_reserved_mem_device_init_by_idx qR __free_pages B adjust_managed_page_count drm_get_format_info N drm_gem_object_lookup Skv drm_helper_mode_fill_fb_struct [Ad drm_framebuffer_init 8U drm_format_info =d| drm_atomic_bridge_chain_disable Z __drm_dev_dbg V drm_atomic_bridge_chain_post_disable 2H4 drm_atomic_helper_update_legacy_modeset_state &v drm_atomic_helper_calc_timestamping_constants 2 drm_atomic_helper_commit_modeset_enables ^Q drm_atomic_helper_commit_planes ֓ complete_all i- drm_atomic_helper_fake_vblank \ drm_atomic_helper_wait_for_flip_done ZE of_reserved_mem_device_release = drm_atomic_helper_commit_hw_done if drm_rotation_simplify -w drm_gem_fb_destroy
L- drm_gem_fb_create_handle DZ dma_buf_vunmap 6\ drm_prime_gem_destroy ' drm_gem_object_release [Ԙ dma_buf_vmap S \ drm_gem_private_object_init \ dma_heap_find dma_heap_buffer_alloc G/~ dma_heap_put y % drm_gem_prime_import_dev = drm_gem_handle_create ٟ dma_buf_put dma_buf_get Ni drm_gem_mmap wVR dma_buf_mmap a={ drm_gem_vm_close Ua drm_gem_create_mmap_offset W drm_gem_vm_open << drm_universal_plane_init { drm_plane_create_alpha_property y drm_plane_create_blend_mode_property 7 drm_plane_create_zpos_property -tW drm_plane_create_zpos_immutable_property Q drm_plane_create_rotation_property =g drm_property_create_blob & __drm_atomic_helper_plane_duplicate_state oC drm_mode_object_get J drm_mode_object_put EB __drm_atomic_helper_plane_destroy_state 2 drm_atomic_helper_check_plane_state o drm_atomic_helper_update_plane E drm_atomic_helper_disable_plane Pb drm_plane_cleanup &S sched_clock b exynos_devfreq_get_domain_freq return_address V exynos_uart_console_enabled I@ vzalloc ͭr debugfs_create_file &5 } sysfs_create_files R debugfs_create_u32 Od debugfs_create_dir 9:f debugfs_create_x32 z e debugfs_create_bool H drmm_kmalloc &Yo debugfs_remove vfree p6~ debugfs_create_u16 E:# __kmalloc m hex_dump_to_buffer ӿ[ pm_runtime_get_if_active $ __drm_printfn_debug ?< sprintf qv of_property_read_string_helper QJ single_open S __drm_printfn_seq_file r0Q __drm_puts_seq_file H seq_printf MK kstrtobool _G kstrtobool_from_user memdup_user_nul J kstrtou16 l߅ strsep Al; kstrtouint Z% strcmp `` kstrtouint_from_user W seq_puts h} param_ops_uint seq_lseek c seq_read * seq_release = single_release i <] drm_event_reserve_init h __list_add_valid UrS __list_del_entry_valid drm_event_cancel_free Zr drm_mode_object_find '4 drm_send_event d _raw_spin_lock 4K _raw_spin_unlock n devm_kmalloc of_iomap 7 __class_create K2k device_create dma_set_mask w dma_set_coherent_mask nj kstrtou8 xF kthread_mod_delayed_work M kthread_cancel_delayed_work_sync 4f kthread_flush_worker tR of_find_property 0 of_get_child_by_name ƌ kthread_delayed_work_timer_fn Yy init_timer_key h drm_atomic_nonblocking_commit drm_rect_clip_scaled J drm_atomic_get_plane_state drm_rect_intersect mipi_dsi_dcs_set_column_address 6m mipi_dsi_dcs_set_page_address enable_irq !' disable_irq_nosync o? gpio_to_desc #f gpiod_to_irq "u irq_modify_status p devm_request_threaded_irq tn devm_free_irq I drm_send_event_locked hN drm_crtc_vblank_put r drm_display_mode_to_videomode of_property_read_variable_u32_array i of_property_read_string N of_count_phandle_with_args X of_prop_next_u32 pEn= of_find_compatible_node U of_irq_get_byname o< disable_irq Bo __kthread_init_worker .[ kthread_worker_fn kthread_create_on_node s wake_up_process
sched_setscheduler_nocheck ,j pm_runtime_enable M component_add \O kthread_stop z component_del gpiod_get_raw_value DC __wake_up uH8 drm_crtc_handle_vblank .)V iommu_register_device_fault_handler tx itmon_notifier_chain_register YV sysfs_create_link itmon_notifier_chain_unregister һE iommu_unregister_device_fault_handler R1<& bcmp < _dev_info U _dev_warn __msecs_to_jiffies :J wait_for_completion_timeout uyH init_wait_entry & prepare_to_wait_event ݍ schedule_timeout T finish_wait s$ jiffies_to_usecs >K of_device_get_match_data > platform_bus_type rx bus_find_device P jiffies b dbg_snapshot_emergency_reboot F of_get_next_child J< of_property_count_elems_of_size j
of_property_read_variable_u16_array >VI of_property_read_variable_u8_array g7 of_property_read_u64 3w devm_kfree of_get_named_gpio_flags A` __init_swait_queue_head _2y devm_phy_get jFq exynos_get_idle_ip_index UC͐ exynos_update_ip_idle_status 'UlD __pm_runtime_use_autosuspend یK pm_runtime_set_autosuspend_delay ~ phy_init [= mipi_dsi_host_register wo logbuffer_register z^ of_property_read_variable_u64_array t __pm_runtime_disable g mipi_dsi_host_unregister Y logbuffer_unregister strnlen fortify_panic Bx devm_pinctrl_get |U pinctrl_lookup_state 4 strchr # mipi_dsi_create_packet o6n ktime_get_mono_fast_ns ؑ| __pm_runtime_suspend 뛁 mutex_is_locked ی[ phy_power_off 'C drm_crtc_vblank_count_and_time }! drm_crtc_wait_one_vblank D logbuffer_log /z% complete j7 exynos_pm_qos_request ef phy_power_on uP hex2bin of_graph_is_present u쪴 of_graph_get_remote_node :x gs_connector_set_panel_name ⻚ of_get_next_available_child
U of_get_property H mipi_dsi_device_register_full J drm_encoder_init =] drm_encoder_cleanup # devm_drm_of_get_bridge m
Q of_drm_find_bridge i~ of_drm_find_panel ' devm_drm_panel_bridge_add_typed drm_bridge_attach y drm_atomic_get_old_connector_for_encoder b pinctrl_select_state %& drm_atomic_get_new_connector_for_encoder ~ device_link_del c3 device_link_add j" __pm_runtime_set_status G{w param_ops_string z misc_register +ѩ misc_deregister JkT drm_writeback_signal_completion d>} drm_writeback_connector_init a drm_add_modes_noedid : drm_mode_duplicate drm_mode_probed_add drm_writeback_queue_job H drm_modeset_lock ֕ drm_hdcp_update_content_protection
k drm_modeset_unlock drm_dp_dpcd_read - drm_dp_dpcd_write K= sysfs_create_group C devm_platform_ioremap_resource_byname o3#y platform_get_irq_byname %I alloc_workqueue sysfs_remove_group U0 I device_set_wakeup_capable device_wakeup_enable >85 register_reboot_notifier "b dp_register_func_for_hdcp22 U unregister_reboot_notifier ~ device_wakeup_disable destroy_workqueue a sysfs_emit drm_dp_read_sink_count k drm_dp_dpcd_read_link_status drm_dp_channel_eq_ok l>i hdcp_dplink_handle_irq 8 __sysfs_match_string i kstrtoint cC hdcp_dplink_connect_state pm_stay_awake ؐ pm_relax msleep ϊ@ drm_kms_helper_hotplug_event s drm_dp_bw_code_to_link_rate ]& drm_dp_link_rate_to_bw_code "K drm_do_get_edid xr drm_edid_is_valid B drm_connector_update_edid_property RT| drm_edid_get_monitor_name
ۉ drm_add_edid_modes j drm_edid_to_sad Ay drm_mode_destroy B drm_mode_sort P drm_mode_copy | blocking_notifier_call_chain k} __udelay )p drm_dp_clock_recovery_ok y drm_dp_get_adjust_request_voltage $/X drm_dp_get_adjust_request_pre_emphasis gY| print_hex_dump Mny drm_hdmi_avi_infoframe_from_display_mode hdmi_avi_infoframe_pack d drm_connector_register Vme drm_connector_attach_encoder ? drm_dp_aux_init 0(y drm_atomic_helper_connector_reset Z2 drm_connector_attach_max_bpc_property [ drm_connector_attach_content_protection_property SG
drm_mode_equal $Jp~ kstrtoint_from_user wk param_ops_ulong param_ops_bool XKy drm_atomic_helper_connector_duplicate_state \ drm_atomic_helper_connector_destroy_state A|U bts_get_bwindex ay cal_dfs_get_max_freq DU exynos_pm_qos_add_request_trace < bts_get_scenindex z~g exynos_pm_qos_remove_request R bts_del_scenario 꽷 bts_add_scenario @ bts_update_bw v exynos_pm_qos_update_request u module_layout GNU dEn
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xA G H T $ .note.gnu.property .note.Linux .hyp.text .rela.text .rela___ksymtab_gpl+exynos_drm_drv_set_lhbm_hist .comment .init.plt .rela__tracepoints .rela_ftrace_events .hyp.bss .rela__tracepoints_ptrs .rela.altinstructions __versions __tracepoints_strings __ksymtab_strings .rela__bpf_raw_tp_map .modinfo .rela__param __ksymtab_gpl __kcrctab_gpl .note.GNU-stack .llvm_addrsig .rela__dyndbg .rela___ksymtab+__tracepoint_tracing_mark_write .text.ftrace_trampoline .init.eh_frame .rela.eh_frame .rela.gnu.linkonce.this_module .rela__jump_table .rela__bug_table .note.gnu.build-id .shstrtab .strtab __ksymtab .symtab __kcrctab .hyp.rodata .rela.rodata .rela.exit.data .rela.init.data .hyp.data .rela.ref.data .rela.data exynos_drm_connector_set_property exynos_drm_writeback_set_property exynos_drm_plane_set_property exynos_drm_crtc_set_property exynos_drm_connector_get_property exynos_drm_writeback_get_property of_get_property exynos_drm_plane_get_property exynos_drm_crtc_get_property drm_plane_create_zpos_property drm_connector_attach_content_protection_property drm_plane_create_rotation_property exynos_create_hdr_formats_drm_property exynos_drm_crtc_create_partial_property drm_object_attach_property drm_plane_create_zpos_immutable_property drm_plane_create_blend_mode_property of_find_property drm_connector_update_edid_property exynos_drm_crtc_create_rcd_id_property drm_connector_attach_max_bpc_property drm_plane_create_alpha_property dsim_reg_rx_fifo_is_empty dsim_reg_header_fifo_is_empty dsim_reg_payload_fifo_is_empty dsim_wait_for_cmd_fifo_empty init_wait_entry decon_trigger_recovery drm_mode_copy strcpy memcpy exynos_drm_connector_destroy exynos_hibernation_destroy drm_prime_gem_destroy exynos_drm_writeback_destroy drm_mode_destroy __kcfi_typeid_drm_gem_fb_destroy dsim_reg_set_lanes_dphy sysfs_notify drm_rotation_simplify init_timer_key exynos_hibernation_register.__key exynos_dqe_register.__key init_completion.__key dp_probe.__key decon_probe.__key dsim_probe.__key exynos_drm_bind.__key of_property_read_variable_u8_array of_property_read_variable_u16_array of_property_read_variable_u64_array of_property_read_variable_u32_array __const_udelay __udelay pm_runtime_set_autosuspend_delay drm_modeset_lock_all_ctx trace_raw_output_dsi_tx __tracepoint_dsi_tx trace_event_raw_event_dsi_tx __event_dsi_tx print_fmt_dsi_tx event_class_dsi_tx trace_event_fields_dsi_tx trace_event_type_funcs_dsi_tx __traceiter_dsi_tx __bpf_trace_tp_map_dsi_tx perf_trace_dsi_tx __bpf_trace_dsi_tx __SCK__tp_func_dsi_tx __tpstrtab_dsi_tx trace_raw_output_dsi_rx __tracepoint_dsi_rx trace_event_raw_event_dsi_rx __event_dsi_rx print_fmt_dsi_rx event_class_dsi_rx trace_event_fields_dsi_rx trace_event_type_funcs_dsi_rx __traceiter_dsi_rx __bpf_trace_tp_map_dsi_rx perf_trace_dsi_rx __bpf_trace_dsi_rx __SCK__tp_func_dsi_rx __tpstrtab_dsi_rx dqe_reg_print_linear_matrix dqe_reg_set_linear_matrix exynos_debugfs_add_matrix dqe_reg_print_gamma_matrix dqe_reg_set_gamma_matrix bts_get_bwindex bts_get_scenindex exynos_get_idle_ip_index of_reserved_mem_device_init_by_idx dpu_event_print_max __param_str_event_print_max __param_event_print_max dev_attr_tdr_max dpu_event_log_max __param_str_event_log_max __param_event_log_max pm_relax dpphy_reg_set_cr_clk_low recovery_show tdr_max_show la_w_show dphy_diag_text_show tout_show lut_show st_show dpu_debug_event_show pin_assignment_show lt_show gain_limit_show ambient_light_show back_light_show lt_calc_ab_shift_show link_status_show tui_status_show counters_show ns_show dp_crc_values_show link_negotiation_failures_show link_unstable_failures_show sink_count_invalid_failures_show edid_invalid_failures_show edid_read_failures_show dpcd_read_failures_show dither_show early_wakeup_show dpu_debug_reg_dump_show gt_lamda_dstep_show dim_ratio_show orientation_show hibernation_show la_w_on_show upgrade_on_show tdr_min_show pp_en_show hs_clock_show dphy_diag_reg_show force_te_show gt_he_enable_show ctmode_show bist_mode_show scale_mode_show lt_calc_mode_show dp_hotplug_error_code_show hpd_show dp_crc_enabled_show gt_lamda_show he_clip_max_3_show he_clip_min_3_show threshold_3_show pl_w2_show he_clip_max_2_show he_clip_min_2_show threshold_2_show pl_w1_show he_clip_max_1_show he_clip_min_1_show threshold_1_show he_clip_max_0_show he_clip_min_0_show decon_reg_update_req_window dsim_reg_set_dphy_use_shadow dpu_bts_calc_dpp_bw dpu_bts_update_bw dpu_bts_calc_bw dev_attr_la_w dp_hw_set_hdcp13_bksv dp_hw_get_hdcp13_aksv drm_gem_prime_import_dev compare_dev drm_connector_list_iter_next drm_dev_put drm_gem_object_put drm_mode_object_put dma_heap_put drm_crtc_vblank_put dma_buf_put drm_property_blob_put dma_fence_wait_timeout decon_reg_wait_idle_status_timeout wait_for_completion_timeout decon_reg_wait_run_is_off_timeout decon_reg_wait_update_done_timeout schedule_timeout dqe_reg_print_lut rcd_reg_set_in_qos_lut odma_reg_set_in_qos_lut idma_reg_set_in_qos_lut hdr_reg_print_eotf_lut hdr_reg_set_eotf_lut hdr_reg_print_oetf_lut hdr_reg_set_oetf_lut dqe_reg_print_cgc_lut dqe_reg_set_cgc_lut dqe_reg_print_regamma_lut dqe_reg_set_regamma_lut dqe_reg_print_degamma_lut dqe_reg_set_degamma_lut dp_hw_write_dpcd_burst dp_hw_read_dpcd_burst __param_str_dp_phy_boost __param_dp_phy_boost dpu_formats_list exynos_drm_crtc_histogram_pos_property.histogram_pos_list exynos_drm_plane_create_transfer_property.transfer_list exynos_drm_connector_create_orientation_property.drm_panel_orientation_enum_list exynos_drm_connector_create_brightness_properties.hbm_enum_list exynos_drm_crtc_histogram_channels_property.histogram_list exynos_drm_wb_conn_create_range_property.range_list exynos_drm_plane_create_range_property.range_list exynos_drm_crtc_create_color_mode_property.color_mode_list exynos_drm_wb_conn_create_standard_property.standard_list exynos_drm_plane_create_standard_property.standard_list exynos_drm_crtc_create_force_bpc_property.bpc_list exynos_drm_connector_create_brightness_properties.mipi_sync_list dqe_reg_print_hist __kstrtabns_exynos_drm_drv_set_lhbm_hist __crc_exynos_drm_drv_set_lhbm_hist __kstrtab_exynos_drm_drv_set_lhbm_hist __ksymtab_exynos_drm_drv_set_lhbm_hist __kstrtabns_exynos_drm_connector_set_lhbm_hist __crc_exynos_drm_connector_set_lhbm_hist __kstrtab_exynos_drm_connector_set_lhbm_hist __ksymtab_exynos_drm_connector_set_lhbm_hist dsim_reg_set_bist exynos_pm_qos_request exynos_pm_qos_remove_request exynos_pm_qos_update_request dev_attr_st drm_mode_sort __kcfi_typeid_exynos_drm_gem_prime_import dpphy_reg_clear_cr_port dsim_restart dp_hw_start decon_reg_start dsim_reg_start dsim_reg_exit_ulps_and_start dp_hw_set_video_interrupt ioremap_prot dbg_snapshot_emergency_reboot drm_dp_read_sink_count adjust_managed_page_count kstrtouint param_ops_uint dpu_event_log_print hdr_reg_print kstrtoint dsim_reg_set_int decon_reg_clear_int dsim_reg_clear_int prepare_to_wait_event handle_histogram_event drm_crtc_arm_vblank_event decon_force_vblank_event drm_crtc_send_vblank_event drm_kms_helper_hotplug_event exynos_crtc_handle_event drm_send_event of_graph_is_present dma_coerce_mask_and_coherent dev_attr_pin_assignment dsim_reg_get_ph_cnt drm_crtc_enable_color_mgmt dev_attr_lt exynos_hibernation_exit _hibernation_block_exit exynos_hibernation_async_exit dp_hw_reinit dp_hw_deinit dpu_bts_deinit dpp_reg_deinit rcd_reg_deinit phy_init drm_dp_aux_init __mutex_init dp_hw_init __kcfi_typeid_trace_event_raw_init drm_gem_private_object_init dpu_bts_init __kstrtabns_exynos_drm_connector_init __crc_exynos_drm_connector_init __kstrtab_exynos_drm_connector_init __ksymtab_exynos_drm_connector_init drm_writeback_connector_init drm_framebuffer_init drm_encoder_init drm_kms_helper_poll_init exynos_partial_init drm_vblank_init drm_atomic_private_obj_init exynos_drm_mode_config_init drmm_mode_config_init dpphy_reg_init dpp_reg_init decon_reg_init dsim_reg_init dqe_reg_init rcd_reg_init dsc_reg_init drm_event_reserve_init drm_modeset_acquire_init exynos_plane_init drm_universal_plane_init rmem_device_init hdr_regs_desc_init dpp_regs_desc_init dp_regs_desc_init decon_regs_desc_init dsim_regs_desc_init dqe_regs_desc_init dqe_cgc_regs_desc_init tm_y_axis_2084_1000nit tm_x_axis_2084_1000nit trace_event_buffer_commit drm_atomic_helper_setup_commit drm_atomic_nonblocking_commit __kcfi_typeid_exynos_atomic_commit drm_atomic_commit writeback_atomic_commit ___ratelimit dev_attr_gain_limit sysfs_emit perf_trace_run_bpf_submit finish_wait dev_attr_ambient_light dev_attr_back_light dev_attr_lt_calc_ab_shift tm_y_axis_dft eotf_y_axis_dft tm_x_axis_dft eotf_x_axis_dft memset kimage_voffset drm_gem_create_mmap_offset __kcfi_typeid_exynos_drm_gem_dumb_map_offset regs_dqe_offset dpu_sysreg_dphy_reset dpp_reg_set_sw_reset rcd_reg_set_sw_reset odma_reg_set_sw_reset idma_reg_set_sw_reset dsim_reg_sw_reset drm_atomic_helper_connector_reset dp_connector_reset exynos_drm_connector_reset dsim_reg_function_reset exynos_drm_writeback_reset drm_mode_config_reset exynos_dqe_reset exynos_drm_plane_reset __drm_atomic_helper_crtc_reset exynos_drm_crtc_reset dp_crc_reset drm_atomic_helper_check_modeset decon_seamless_mode_set param_dp_emulation_mode_set drm_bridge_chain_mode_set dp_atomic_mode_set dsim_atomic_mode_set mipi_dsi_create_packet devm_phy_get drm_mode_object_get devm_pinctrl_get drm_crtc_vblank_get devm_clk_get dma_buf_get ktime_get param_dp_emulation_mode_get dp_crc_get drm_property_blob_get drm_helper_mode_fill_fb_struct dp_detect drm_rect_intersect dev_attr_usbc_cable_disconnect exynos_drm_gem_free_object dpp_reg_set_format csc_r2y_3x3_t csc_y2r_3x3_t csc_3x3_t h_coef_8t v_coef_4t exynos_atomic_check_windows irq_modify_status dpp_reg_wait_sw_reset_status rcd_reg_wait_sw_reset_status odma_reg_wait_sw_reset_status idma_reg_wait_sw_reset_status __pm_runtime_set_status trace_raw_output_dsi_cmd_fifo_status __tracepoint_dsi_cmd_fifo_status trace_event_raw_event_dsi_cmd_fifo_status __event_dsi_cmd_fifo_status print_fmt_dsi_cmd_fifo_status event_class_dsi_cmd_fifo_status trace_event_fields_dsi_cmd_fifo_status trace_event_type_funcs_dsi_cmd_fifo_status __traceiter_dsi_cmd_fifo_status __bpf_trace_tp_map_dsi_cmd_fifo_status perf_trace_dsi_cmd_fifo_status __bpf_trace_dsi_cmd_fifo_status __SCK__tp_func_dsi_cmd_fifo_status __tpstrtab_dsi_cmd_fifo_status dev_attr_link_status drm_dp_dpcd_read_link_status dev_attr_tui_status dsim_reg_wait_idle_status exynos_update_ip_idle_status dp_get_training_interval_us seq_puts decon_reg_set_interrupts get_event_name.events pin_assignments drm_atomic_helper_calc_timestamping_constants dqe_reg_set_histogram_weights decon_mode_update_bts writeback_formats dpp_vg_formats dpp_gf_formats rcd_alpha_formats dqe_reg_dimming_in_progress return_address mipi_dsi_dcs_set_column_address mipi_dsi_dcs_set_page_address dsim_mode_is_seamless wake_up_process gm_coef_bypass dp_stats_attrs dp_attrs decon_debug_attrs dma_unmap_page_attrs dma_map_page_attrs atc_attrs drm_atomic_add_affected_connectors exynos_drm_drivers dev_attr_counters exynos_drm_mode_config_helpers dpp_format_modifiers dqe_reg_get_histogram_bins._rs dpp_need_enable_hdr._rs dsim_underrun_info._rs dpu_event_save_freqs atc_groups dsc_reg_set_pps exynos_create_hdr_formats_drm_property.props alt_cb_patch_nops recovery_fops dphy_diag_text_fops tout_fops lut_fops dpu_event_fops dp_crc_values_fops exynos_drm_driver_fops dpu_reg_dump_fops exynos_tui_fops dphy_diag_reg_fops force_te_fops dp_crc_enabled_fops dsim_host_ops exynos_dpp_component_ops dp_component_ops decon_component_ops dsim_component_ops exynos_wb_component_ops exynos_drm_gem_vm_ops exynos_drm_ops decon_pm_ops dsim_pm_ops rmem_ops decon_crtc_ops dsim_reg_exit_ulps dsim_reg_enter_ulps dsim_reg_stop_and_enter_ulps __kstrtabns_exynos_drm_mode_bts_fps __crc_exynos_drm_mode_bts_fps __kstrtab_exynos_drm_mode_bts_fps __ksymtab_exynos_drm_mode_bts_fps drm_atomic_normalize_zpos dsim_atomic_mode_set_exynos update_hs_clk_exynos dsim_atomic_check_exynos set_state_recovering_exynos update_config_for_mode_exynos orientations ____versions dqe_reg_get_histogram_bins ktime_get_mono_fast_ns dev_attr_ns dpp_reg_configure_params rcd_reg_configure_params exynos_ioctls dsim_reg_set_clocks drm_modeset_drop_locks drm_dp_get_adjust_request_pre_emphasis dp_hw_set_voltage_and_pre_emphasis of_count_phandle_with_args __of_parse_phandle_with_args arm64_use_ng_mappings rcd_dma_dump_regs cgc_dma_dump_regs __decon_unmap_regs dma_reg_dump_com_debug_regs of_get_named_gpio_flags dsim_atomic_mode_set_gs update_hs_clk_gs dsim_atomic_check_gs set_state_recovering_gs update_config_for_mode_gs dsim_diag_remove_debugfs dsim_diag_create_debugfs dev_attr_link_negotiation_failures dev_attr_link_unstable_failures dev_attr_sink_count_invalid_failures dev_attr_edid_invalid_failures dev_attr_edid_read_failures dev_attr_dpcd_read_failures decon_reg_set_mres dsim_reg_set_mres drm_atomic_helper_commit_planes drm_atomic_helper_cleanup_planes drm_atomic_helper_check_planes __drmm_crtc_alloc_with_planes drm_atomic_helper_prepare_planes drm_atomic_add_affected_planes __param_str_dp_lanes __param_dp_lanes sysfs_create_files drm_atomic_helper_commit_modeset_enables __kstrtabns_exynos_drm_connector_get_properties __crc_exynos_drm_connector_get_properties __kstrtab_exynos_drm_connector_get_properties __ksymtab_exynos_drm_connector_get_properties exynos_drm_connector_create_brightness_properties exynos_drm_crtc_create_histogram_properties exynos_drm_connector_create_properties __msecs_to_jiffies drm_atomic_helper_wait_for_dependencies kmalloc_caches __free_pages dp_get_modes writeback_get_modes __kcfi_typeid_drm_helper_probe_single_connector_modes exynos_drm_writeback_modes drm_add_edid_modes __decon_init_resources dpu_bts_update_resources dpu_bts_release_resources exynos_partial_reconfig_coords hpds set_protection.protection_ids exynos_drm_get_possible_crtcs exynos_drm_gem_object_funcs get_connector_funcs dp_connector_funcs exynos_drm_connector_funcs exynos_dsim_connector_funcs gs_dsim_connector_funcs wb_connector_funcs dp_connector_helper_funcs wb_connector_helper_funcs dp_encoder_helper_funcs dsim_encoder_helper_funcs wb_encoder_helper_funcs plane_helper_funcs exynos_crtc_helper_funcs dp_encoder_funcs dsim_encoder_funcs hibernation_funcs partial_funcs exynos_drm_mode_config_funcs exynos_priv_state_funcs dqe_funcs exynos_plane_funcs exynos_crtc_funcs exynos_drm_fb_funcs jiffies_to_usecs dp_hw_get_and_clear_video_intr dp_hw_get_and_clear_common_intr _dev_err __drm_err drm_atomic_set_crtc_for_connector __kstrtabns_is_exynos_drm_connector __crc_is_exynos_drm_connector __kstrtab_is_exynos_drm_connector __ksymtab_is_exynos_drm_connector is_gs_drm_connector debugfs_create_dir strchr platform_find_device_by_driver dpp_driver dp_driver decon_driver exynos_drm_platform_driver exynos_drm_driver dsim_driver writeback_driver tui_driver dsim_encoder_early_unregister drm_dp_early_unregister drm_dev_unregister mipi_dsi_host_unregister drm_connector_unregister platform_driver_unregister logbuffer_unregister itmon_notifier_chain_unregister platform_device_unregister misc_deregister __kstrtabns_exynos_recovery_register __crc_exynos_recovery_register __kstrtab_exynos_recovery_register __ksymtab_exynos_recovery_register drm_dev_register mipi_dsi_host_register drm_connector_register __platform_driver_register logbuffer_register exynos_hibernation_register itmon_notifier_chain_register exynos_rmem_register exynos_drm_connector_late_register dsim_encoder_late_register drm_dp_late_register exynos_drm_plane_late_register exynos_drm_crtc_late_register exynos_dqe_register misc_register exynos_cgc_dma_register m_aud_master exynos_drm_crtc_get_vblank_counter exynos_hibernation_enter exynos_dqe_hibernation_enter hibernation_unblock_enter dp_hw_set_hdcp13_repeater kstrtouint_from_user kstrtoint_from_user kstrtobool_from_user of_property_read_string_helper exynos_recovery_handler dp_reboot_handler dp_downstream_port_event_handler dp_link_down_event_handler dpu_sysmmu_fault_handler iommu_unregister_device_fault_handler iommu_register_device_fault_handler dsim_reg_rx_err_handler decon_tout_irq_handler dp_automated_test_irq_handler decon_fs_irq_handler dpp_irq_handler dp_irq_handler decon_irq_handler dsim_irq_handler decon_te_irq_handler cgc_irq_handler odma_irq_handler buf_dump_handler exynos_hibernation_handler exynos_drm_crtc_te_handler dsim_reg_set_esc_clk_prescaler __kthread_init_worker kthread_flush_worker unregister_reboot_notifier __kcfi_typeid_dpu_itmon_notifier dp_remap_regs_other dqe_reg_print_dither dev_attr_dither dqe_reg_set_disp_dither dqe_reg_set_cgc_dither decon_reg_set_trigger dp_aux_transfer dsim_host_transfer dsim_reg_set_num_of_transfer dpp_dump_buffer hex_dump_to_buffer drm_atomic_get_new_connector_for_encoder drm_atomic_get_old_connector_for_encoder drm_connector_attach_encoder dsim_reg_wr_tx_header cpu_number hdr_reg_set_hdr regs_hdr dpp_need_enable_hdr exynos_drm_gem_get_vaddr exynos_drm_fb_to_vaddr memstart_addr dma_reg_get_shd_addr is_vmalloc_addr exynos_drm_fb_dma_addr drm_atomic_state_clear decon_reg_get_interrupt_and_clear decon_reg_get_fs_interrupt_and_clear dsim_reg_get_int_and_clear dpp_reg_get_irq_and_clear odma_reg_get_irq_and_clear idma_reg_get_irq_and_clear system_highpri_wq decon_enable_tout_irq dpp_reg_clear_irq odma_reg_clear_irq idma_reg_clear_irq gpiod_to_irq _raw_spin_unlock_irq _raw_spin_lock_irq decon_request_te_irq decon_enable_te_irq hdcp_dplink_handle_irq disable_irq enable_irq devm_free_irq dp_work_hpd_irq devm_request_threaded_irq trace_print_hex_seq cal_dfs_get_max_freq exynos_devfreq_get_domain_freq __kstrtabns_exynos_drm_mode_te_freq __crc_exynos_drm_mode_te_freq __kstrtab_exynos_drm_mode_te_freq __ksymtab_exynos_drm_mode_te_freq dsim_reg_set_dphy_shadow_update_req decon_reg_all_win_shadow_update_req exynos_crtc_mode_fixup dp_stats_group dp_group sysfs_remove_group sysfs_create_group atc_group __kcfi_typeid_drm_connector_cleanup __kcfi_typeid_drm_encoder_cleanup __kcfi_typeid_drm_plane_cleanup drm_gem_object_lookup of_reserved_mem_lookup dev_attr_early_wakeup decon_reg_set_pll_wakeup kmemdup dp_sink_power_up dp_link_up __wake_up dpu_bts_calc_aclk_disp dpu_bts_update_disp regs_dpp dp_hw_stop decon_reg_stop dsim_reg_stop kthread_stop __param_str_dp_edid_hexdump __param_dp_edid_hexdump dpu_print_hex_dump __dpp_dump __decon_dump __dsim_dump dqe_dump rcd_dump cgc_dump wb_dump strcmp strncmp bcmp __kcfi_typeid_drm_atomic_helper_page_flip dev_attr_dstep dev_attr_gt_lamda_dstep strsep trace_raw_output_prep trace_raw_output_msleep __tracepoint_msleep trace_event_raw_event_msleep __event_msleep print_fmt_msleep event_class_msleep trace_event_fields_msleep trace_event_type_funcs_msleep __traceiter_msleep __bpf_trace_tp_map_msleep __kstrtabns_dsim_trace_msleep __crc_dsim_trace_msleep __kstrtab_dsim_trace_msleep __ksymtab_dsim_trace_msleep perf_trace_msleep __bpf_trace_msleep __SCK__tp_func_msleep __tpstrtab_msleep decon_reg_set_pll_sleep decon_reg_stop_inst_dp regs_dp __kstrtabns_dp_hdcp_update_cp __crc_dp_hdcp_update_cp __kstrtab_dp_hdcp_update_cp __ksymtab_dp_hdcp_update_cp dma_buf_vmap of_iomap dma_buf_vunmap iounmap __kcfi_typeid_exynos_drm_gem_mmap dma_buf_mmap dev_attr_dim_ratio bts_del_scenario dpu_bts_update_scenario bts_add_scenario log_post_write_mmio log_write_mmio log_post_read_mmio log_read_mmio dp_hw_start_audio dp_hw_deinit_audio dp_hw_init_audio dp_hw_stop_audio __param_str_dp_audio __param_dp_audio dsim_reg_ready_packetgo dsim_reg_enable_packetgo _dev_info exynos_plane_print_info dpu_find_fmt_info exynos_get_format_info drm_get_format_info drm_format_info dpu_bts_convert_config_to_info dsim_underrun_info __kcfi_typeid___drm_printfn_info print_drm_plane_state_info dsim_reg_get_rx_fifo drm_atomic_helper_shutdown exynos_drm_platform_shutdown dp_link_down _exynos_hibernation_run trace_handle_return dp_hw_set_quality_pattern dp_hw_set_training_pattern _dev_warn dp_hw_set_hdcp13_encryption dp_hw_set_hdcp22_encryption decon_dump_event_condition drm_writeback_signal_completion dp_hw_set_hdcp13_function dp_hw_set_hdcp22_function drm_hdcp_update_content_protection set_protection set_resource_protection dev_attr_orientation writeback_exit_hibernation dev_attr_hibernation writeback_enter_hibernation exynos_partial_adjust_region regs_decon dev_attr_la_w_on dsim_phy_power_on queue_work_on drm_crtc_vblank_on dev_attr_upgrade_on is_decon_using_win decon_reg_get_rsc_win dev_attr_tdr_min drm_connector_list_iter_begin decon_atomic_begin exynos_crtc_atomic_begin hex2bin blocking_notifier_call_chain __kcfi_typeid_kthread_delayed_work_timer_fn __kcfi_typeid_kthread_worker_fn recovery_open dphy_diag_text_open tout_open lut_open dpu_debug_event_open dp_crc_values_open dpu_debug_reg_dump_open __kcfi_typeid_drm_gem_vm_open exynos_drm_open __kcfi_typeid_drm_open exynos_tui_open dphy_diag_reg_open force_te_open single_open dp_crc_enabled_open strlen strnlen dev_attr_en dsim_reg_set_dphy_dither_en cgc_reg_set_irq_en dev_attr_pp_en dp_hw_get_hdcp13_an audio_async_m_n drm_property_create_enum hdr_reg_print_tm hdr_reg_set_tm hdr_reg_print_gm hdr_reg_set_gm pri_sram shared_sram sec_sram dqe_reg_set_histogram memdup_user_nul b_dphyctl __kcfi_typeid_histogram_event_request_ioctl __kcfi_typeid_histogram_request_ioctl __kcfi_typeid_histogram_channel_request_ioctl __kcfi_typeid_drm_compat_ioctl __kcfi_typeid_drm_ioctl __kcfi_typeid_histogram_event_cancel_ioctl __kcfi_typeid_histogram_cancel_ioctl __kcfi_typeid_histogram_channel_cancel_ioctl exynos_tui_ioctl dsim_get_pinctrl dsim_reg_set_cmd_ctrl dsim_reg_set_vresol dsim_reg_set_hresol decon_reg_set_window_control dpu_bts_control dsc_reg_config_control kstrtobool param_ops_bool drm_property_create_bool debugfs_create_bool exynos_drm_crtc_create_bool exynos_partial_set_full platform_device_register_full mipi_dsi_device_register_full dsim_reg_enable_pll __kcfi_typeid_drm_poll decon_reg_clear_int_all decon_dump_all buf_dump_all dpp_reg_set_irq_mask_all rcd_reg_set_irq_mask_all cgc_reg_set_irq_mask_all odma_reg_set_irq_mask_all idma_reg_set_irq_mask_all complete_all component_unbind_all component_bind_all drm_atomic_helper_commit_tail exynos_atomic_commit_tail __stack_chk_fail __kstrtabns_exynos_drm_drv_get_lhbm_gray_level __crc_exynos_drm_drv_get_lhbm_gray_level __kstrtab_exynos_drm_drv_get_lhbm_gray_level __ksymtab_exynos_drm_drv_get_lhbm_gray_level __kstrtabns_exynos_drm_connector_get_lhbm_gray_level __crc_exynos_drm_connector_get_lhbm_gray_level __kstrtab_exynos_drm_connector_get_lhbm_gray_level __ksymtab_exynos_drm_connector_get_lhbm_gray_level dpphy_reg_set_lane_tx_level writel of_drm_find_panel component_del component_master_del device_link_del exynos_hibernation_cancel readl drm_mode_equal cgc_reg_set_cgc_start_internal dqe_reg_set_histogram_pos_internal cgc_reg_get_irq_and_clear_internal dqe_reg_set_cgc_coef_dma_req_internal dqe_reg_set_rcd_en_internal dqe_reg_set_cgc_en_internal cgc_reg_set_config_internal dqe_reg_wait_cgc_dma_done_internal decon_reg_set_rcd_enable_internal decon_reg_update_req_global __warn_printk drm_property_create_bitmask decon_reg_update_req_and_unmask decon_reg_update_req_window_mask dma_set_coherent_mask dma_set_mask dpu_debug_dump_mask __param_str_debug_dump_mask __param_debug_dump_mask dpphy_reg_cr_write_mask dp_smc_write_mask __cpu_online_mask decon_reg_wait_update_done_and_mask diag_dsim_dphy_reg_read_mask diag_dsim_dphy_extra_reg_read_mask exynos_tui_probe.dma_mask commit_work kthread_queue_work kthread_mod_delayed_work commit_kthread_work drm_dp_clock_recovery_ok drm_dp_channel_eq_ok sysfs_remove_link sysfs_create_link drm_crtc_wait_one_vblank drm_crtc_handle_vblank decon_disable_vblank exynos_drm_crtc_disable_vblank decon_enable_vblank exynos_drm_crtc_enable_vblank drm_atomic_helper_fake_vblank __kcfi_typeid_seq_lseek mutex_trylock mutex_unlock drm_modeset_unlock _raw_spin_unlock dp_get_clock dsim_set_hs_clock dsim_reg_set_hs_clock dev_attr_hs_clock dsim_reg_enable_hs_clock dsim_reg_set_link_clock __kstrtabns_exynos_bts_fps_to_drm_mode_clock __crc_exynos_bts_fps_to_drm_mode_clock __kstrtab_exynos_bts_fps_to_drm_mode_clock __ksymtab_exynos_bts_fps_to_drm_mode_clock sched_clock hibernation_unblock dp_reboot_block hibernation_block dp_get_edid_block mutex_lock drm_modeset_lock _raw_spin_lock g_dsim_lock dp_reg_wait_phy_pll_lock sched_setscheduler_nocheck __dpp_check dpu_itmon_check exynos_hibernation_check exynos_partial_check __kcfi_typeid_exynos_atomic_check dp_atomic_check decon_atomic_check dp_conn_atomic_check dsim_atomic_check writeback_atomic_check exynos_plane_atomic_check exynos_crtc_atomic_check hdmi_avi_infoframe_pack exynos_lhbm_histogram_callback dpphy_reg_wait_config12_tx_ack exynos_drm_gem_fd_to_obj exynos_atomic_exit_tui exynos_atomic_enter_tui dqe_reg_set_histogram_roi dqe_reg_set_histogram_block_roi drm_kms_helper_poll_fini drm_atomic_private_obj_fini drm_modeset_acquire_fini dsim_reg_set_ulps_by_ddi decon_reg_set_dither_path decon_reg_set_bpc_and_dither_path dp_hw_set_data_path decon_atomic_flush exynos_crtc_atomic_flush drm_mode_vrefresh dpphy_reg_set_cr_clk_high decon_driver_dt_match component_master_add_with_match dpp_of_match dp_of_match dsim_of_match wb_of_match of_device_match dsim_reg_set_porch dsim_host_attach drm_bridge_attach dsim_host_detach dqe_reg_print_hist_ch decon_reg_get_win_ch is_decon_using_ch decon_reg_get_rsc_ch dp_work_hpd_unplug dp_on_by_hpd_plug dp_off_by_hpd_plug dp_work_hpd_plug dpu_init_debug __dynamic_pr_debug __kcfi_typeid___drm_printfn_debug histogram_channel_ioctl_process_arg logbuffer_log param_ops_ulong param_ops_string dev_driver_string of_property_match_string __sysfs_match_string of_property_read_string dsim_reg_set_dphy_freq_hopping dp_do_full_link_training dp_validate_link_training dphy_timing _update_config_timing eotf_y_axis_hlg eotf_x_axis_hlg __kcfi_typeid_drm_atomic_helper_set_config dsim_reg_set_rr_config dp_hw_set_lane_map_config dpp_convert_plane_state_to_config dp_hw_set_bist_audio_config dp_hw_set_audio_config __kstrtabns_dp_audio_config __crc_dp_audio_config __kstrtab_dp_audio_config __ksymtab_dp_audio_config dp_hw_set_bist_video_config dp_hw_set_video_config plane_state_to_win_config dpu_print_log_win_config dsim_update_clock_config decon_update_config set_default_atc_config set_priv_reg __kcfi_typeid_trace_event_reg dsim_dphy_diag_set_reg dsim_dphy_diag_get_reg __drm_dev_dbg ___drm_dbg dp_reg_aux_ch_send_buf sprintf snprintf scnprintf trace_event_printf seq_printf drm_printf drm_modeset_backoff dsim_phy_power_off decon_reg_direct_on_off drm_crtc_vblank_off decon_reg_per_frame_off dsim_reg_set_cm_underrun_lp_ref exynos_partial_set_size dqe_reg_set_size decon_reg_config_data_path_size dqe_reg_set_full_img_size decon_reg_set_blender_bg_size of_property_count_elems_of_size decon_reg_config_wb_size exynos_partial_initialize trace_event_buffer_reserve debugfs_remove dpp_remove dp_remove decon_remove exynos_drm_platform_remove dsim_remove writeback_remove exynos_tui_remove pm_runtime_get_if_active _raw_spin_lock_irqsave gpiod_get_raw_value destroy_workqueue alloc_workqueue recovery_write tout_write lut_write dp_crc_values_write dpphy_reg_cr_write trace_raw_output_tracing_mark_write __kstrtabns___tracepoint_tracing_mark_write __crc___tracepoint_tracing_mark_write __kstrtab___tracepoint_tracing_mark_write __ksymtab___tracepoint_tracing_mark_write trace_event_raw_event_tracing_mark_write __event_tracing_mark_write print_fmt_tracing_mark_write event_class_tracing_mark_write trace_event_fields_tracing_mark_write trace_event_type_funcs_tracing_mark_write __kstrtabns___traceiter_tracing_mark_write __crc___traceiter_tracing_mark_write __kstrtab___traceiter_tracing_mark_write __ksymtab___traceiter_tracing_mark_write __bpf_trace_tp_map_tracing_mark_write perf_trace_tracing_mark_write __bpf_trace_tracing_mark_write __kstrtabns___SCK__tp_func_tracing_mark_write __crc___SCK__tp_func_tracing_mark_write __kstrtab___SCK__tp_func_tracing_mark_write __ksymtab___SCK__tp_func_tracing_mark_write __tpstrtab_tracing_mark_write dphy_diag_reg_write decon_reg_dsimif_write force_te_write dp_crc_enabled_write drm_dp_dpcd_write complete __kcfi_typeid_drm_atomic_helper_connector_destroy_state __drm_atomic_helper_connector_destroy_state exynos_drm_connector_destroy_state exynos_drm_writeback_destroy_state __drm_atomic_helper_plane_destroy_state exynos_drm_plane_destroy_state __drm_atomic_helper_crtc_destroy_state exynos_drm_crtc_destroy_state exynos_atomic_destroy_priv_state exynos_atomic_duplicate_priv_state exynos_drm_connector_print_state exynos_drm_plane_print_state exynos_drm_crtc_print_state drm_atomic_helper_update_legacy_modeset_state histogram_chan_set_state hdcp_dplink_connect_state pinctrl_select_state dsim_reg_wait_exit_ulps_state dsim_reg_wait_enter_ulps_state dpu_print_log_win_config.str_state drm_atomic_get_connector_state drm_self_refresh_helper_alter_state pinctrl_lookup_state drm_atomic_helper_swap_state drm_atomic_get_private_obj_state __kcfi_typeid_drm_atomic_helper_connector_duplicate_state __drm_atomic_helper_connector_duplicate_state exynos_drm_connector_duplicate_state drm_atomic_helper_duplicate_state exynos_drm_writeback_duplicate_state __drm_atomic_helper_private_obj_duplicate_state __drm_atomic_helper_plane_duplicate_state exynos_drm_plane_duplicate_state __drm_atomic_helper_crtc_duplicate_state exynos_drm_crtc_duplicate_state drm_atomic_get_plane_state drm_atomic_helper_check_plane_state usleep_range_state dp_set_hpd_state drm_atomic_helper_commit_duplicated_state drm_atomic_get_crtc_state exynos_duplicate_active_crtc_state refcount_warn_saturate clk_get_rate __param_str_dp_rate __param_dp_rate dp_get_max_link_rate drm_dp_bw_code_to_link_rate drm_property_create __class_create drm_gem_handle_create device_create exynos_drm_crtc_create __kcfi_typeid_exynos_drm_gem_dumb_create exynos_user_fb_create dpphy_reg_set_config12_status_update dpp_update decon_reg_set_partial_update dsim_reg_set_partial_update dsc_reg_set_partial_update exynos_partial_update exynos_crtc_self_refresh_update decon_mode_bts_op_rate_update decon_mode_bts_pre_update __exynos_dqe_update dev_attr_force_update decon_reg_win_enable_and_update __kstrtabns_exynos_atc_update __crc_exynos_atc_update __kstrtab_exynos_atc_update __ksymtab_exynos_atc_update exynos_plane_atomic_update drm_mode_duplicate exynos_drm_postclose __kcfi_typeid_drm_gem_vm_close drm_gem_object_release __kcfi_typeid_seq_release __kcfi_typeid_drm_release exynos_tui_release __kcfi_typeid_single_release __kcfi_typeid_dma_fence_release rmem_device_release of_reserved_mem_device_release component_match_add_release histogram_chan_configure _raw_spin_unlock_irqrestore exynos_partial_restore tdr_max_store la_w_store st_store pin_assignment_store lt_store gain_limit_store ambient_light_store back_light_store lt_calc_ab_shift_store usbc_cable_disconnect_store ns_store dither_store early_wakeup_store gt_lamda_dstep_store dim_ratio_store orientation_store hibernation_store la_w_on_store upgrade_on_store tdr_min_store pp_en_store hs_clock_store force_update_store gt_he_enable_store ctmode_store bist_mode_store scale_mode_store lt_calc_mode_store dp_hotplug_error_code_store irq_hpd_store gt_lamda_store he_clip_max_3_store he_clip_min_3_store threshold_3_store pl_w2_store he_clip_max_2_store he_clip_min_2_store threshold_2_store pl_w1_store he_clip_max_1_store he_clip_min_1_store threshold_1_store he_clip_max_0_store he_clip_min_0_store decon_dump_ignore clk_unprepare exynos_partial_prepare clk_prepare regs_dqe decon_reg_update_req_dqe decon_get_crtc_out_type platform_bus_type dpp_reg_set_alpha_type trace_raw_output_dsi_label_scope __kstrtabns___tracepoint_dsi_label_scope __crc___tracepoint_dsi_label_scope __kstrtab___tracepoint_dsi_label_scope __ksymtab___tracepoint_dsi_label_scope trace_event_raw_event_dsi_label_scope __event_dsi_label_scope print_fmt_dsi_label_scope event_class_dsi_label_scope trace_event_fields_dsi_label_scope trace_event_type_funcs_dsi_label_scope __kstrtabns___traceiter_dsi_label_scope __crc___traceiter_dsi_label_scope __kstrtab___traceiter_dsi_label_scope __ksymtab___traceiter_dsi_label_scope __bpf_trace_tp_map_dsi_label_scope perf_trace_dsi_label_scope __bpf_trace_dsi_label_scope __kstrtabns___SCK__tp_func_dsi_label_scope __crc___SCK__tp_func_dsi_label_scope __kstrtab___SCK__tp_func_dsi_label_scope __ksymtab___SCK__tp_func_dsi_label_scope __tpstrtab_dsi_label_scope _decon_wait_for_framedone exynos_drm_crtc_set_property.__already_done dma_map_single_attrs.__already_done drm_atomic_helper_commit_hw_done drm_atomic_helper_commit_cleanup_done drm_atomic_helper_wait_for_flip_done decon_wait_for_flip_done exynos_crtc_wait_for_flip_done histogram_flip_done drm_atomic_set_crtc_for_plane drm_atomic_set_fb_for_plane exynos_drm_plane_format_mod_supported_per_plane __kcfi_typeid_drm_atomic_helper_update_plane decon_update_plane __kcfi_typeid_drm_atomic_helper_disable_plane decon_disable_plane dsim_reg_enable_clocklane dsim_reg_set_esc_clk_on_lane decon_resume dsim_resume decon_runtime_resume __pm_runtime_resume dsim_runtime_resume exynos_crtc_resume dsim_irq_handler.last_dumptime dma_irq_handler.last_dumptime drm_crtc_vblank_count_and_time dp_set_audio_infoframe dp_hw_send_audio_infoframe dp_hw_send_avi_infoframe dp_hw_send_spd_infoframe of_irq_get_byname platform_get_irq_byname devm_platform_ioremap_resource_byname of_get_child_by_name drm_edid_get_monitor_name str__dpu__trace_system_name gs_connector_set_panel_name __param_str_panel_name __param_panel_name __param_string_panel_name dsim_parse_panel_name __param_str_sec_panel_name __param_sec_panel_name __param_string_sec_panel_name init_module __this_module cleanup_module __kcfi_typeid___drm_puts_seq_file __kcfi_typeid___drm_printfn_seq_file device_remove_file debugfs_create_file device_create_file __kcfi_typeid_drm_gem_prime_fd_to_handle __kcfi_typeid_drm_gem_fb_create_handle decon_reg_is_idle __pm_runtime_idle dsim_reg_is_pll_stable __kcfi_typeid_exynos_drm_gem_prime_import_sg_table __mod_of__decon_driver_dt_match_device_table __mod_of__dp_of_match_device_table __mod_of__dsim_of_match_device_table drm_atomic_bridge_chain_post_disable exynos_crtc_needs_disable dsim_encoder_disable device_wakeup_disable dpp_disable dp_disable decon_disable drm_atomic_bridge_chain_disable _dsim_disable clk_disable writeback_disable __pm_runtime_disable exynos_plane_atomic_disable exynos_drm_crtc_atomic_disable device_set_wakeup_capable dwc3_exynos_phy_enable dsim_encoder_enable device_wakeup_enable dp_enable dp_reg_set_aux_ch_operation_enable decon_enable decon_reg_set_win_enable _dsim_enable decon_reg_set_sram_enable clk_enable writeback_enable decon_reg_set_dqe_enable pm_runtime_enable dev_attr_gt_he_enable exynos_drm_crtc_atomic_enable decon_reg_set_cwb_enable pm_stay_awake dqe_reg_print_atc_he dqe_reg_set_atc_he dsim_dphy_diag_mask_from_range drm_property_create_range exynos_drm_crtc_create_range drm_property_create_signed_range exynos_drm_crtc_create_signed_range devm_drm_of_get_bridge dsim_attach_bridge of_drm_find_bridge drm_dp_get_adjust_request_voltage panel_usage vfree devm_kfree __kcfi_typeid_drm_gem_object_free drm_event_cancel_free __kcfi_typeid___drm_atomic_state_free __kstrtabns_of_find_dpp_by_node __crc_of_find_dpp_by_node __kstrtab_of_find_dpp_by_node __ksymtab_of_find_dpp_by_node release_histogram_event_node kthread_create_on_node of_graph_get_remote_node of_find_compatible_node dev_attr_ctmode drm_display_mode_to_videomode dsim_set_display_mode drm_hdmi_avi_infoframe_from_display_mode dev_attr_bist_mode __param_str_dp_bist_mode __param_dp_bist_mode exynos_crtc_set_mode dsim_reg_set_cmd_transfer_mode dsim_reg_set_video_mode param_ops_dp_emulation_mode __param_str_dp_emulation_mode __param_dp_emulation_mode decon_reg_set_qactive_pll_mode dsim_get_clock_mode dev_attr_scale_mode failsafe_mode dev_attr_lt_calc_mode drm_dp_link_rate_to_bw_code dev_attr_dp_hotplug_error_code exynos_debugfs_add_dqe_override of_address_to_resource decon_reg_release_resource dp_hw_get_intr_source put_device dsim_add_mipi_dsi_device bus_find_device dsim_reg_set_size_of_slice preempt_schedule_notrace exynos_pm_qos_add_request_trace kmalloc_trace dpp_probe dp_probe decon_probe exynos_drm_platform_probe dsim_probe writeback_probe exynos_tui_probe dev_attr_hpd dev_attr_irq_hpd dp_work_hpd dsim_reg_set_hperiod drm_mode_object_find dma_heap_find dpp_unbind dp_unbind decon_unbind exynos_drm_unbind dsim_unbind writeback_unbind dpp_bind dp_bind decon_bind exynos_drm_bind dsim_bind writeback_bind __pm_runtime_use_autosuspend exynos_hibernation_suspend decon_suspend dsim_suspend decon_runtime_suspend __pm_runtime_suspend dsim_runtime_suspend exynos_crtc_suspend drm_connector_list_iter_end exynos_partial_send_command dsim_reg_has_pend_cmd dsim_reg_set_threshold dqe_reg_set_histogram_threshold of_get_next_child of_get_next_available_child __list_del_entry_valid dp_hw_get_hdcp13_key_valid drm_edid_is_valid dp_mode_valid dp_conn_mode_valid dsim_mode_valid exynos_crtc_mode_valid __list_add_valid drm_add_modes_noedid drm_do_get_edid dp_fake_edid dp_hw_read_edid exynos_drm_replace_property_blob_from_id dsim_get_panel_id __kcfi_typeid_drm_gem_prime_handle_to_fd dma_buf_fd writel_relaxed decon_reg_set_drm_write_protected dsim_reg_set_drm_write_protected dqe_reg_set_drm_write_protected devm_drm_panel_bridge_add_typed __trace_trigger_soft_disabled dma_reg_is_mst_security_enabled dp_crc_set_enabled __param_str_dp_enabled __param_dp_enabled exynos_uart_console_enabled is_console_enabled drm_rect_clip_scaled histogram_emmit_event_locked decon_send_vblank_event_locked histogram_chan_handle_event_locked drm_send_event_locked _decon_reinit_locked _dsim_exit_ulps_locked _dsim_enter_ulps_locked histogram_chan_collect_bins_locked mutex_is_locked _decon_stop_locked decon_dump_locked usb_typec_dp_notification_locked dma_fence_signal_locked decon_check_fs_pending_locked dsim_cmd_packetgo_queue_locked __dsim_cmd_write_locked _decon_disable_locked __dsim_cmd_packetgo_enable_locked _decon_enable_locked dsim_write_data_locked dma_reg_dump_com_debug_regs.checked dsim_bind.primary_attached dp_hpd_changed component_add device_link_add exynos_drm_debugfs_plane_add drm_mode_probed_add drm_edid_to_sad dsim_reg_wr_tx_payload dsim_reg_enable_shadow_read dpphy_reg_cr_read __kcfi_typeid_seq_read __kcfi_typeid_drm_read drm_dp_dpcd_read __kstrtabns_dp_ado_notifier_head __crc_dp_ado_notifier_head __kstrtab_dp_ado_notifier_head __ksymtab_dp_ado_notifier_head __init_waitqueue_head __init_swait_queue_head drm_atomic_set_mode_prop_for_crtc dqe_reg_print_atc dqe_reg_set_atc dqe_reg_save_lpd_atc dqe_reg_restore_lpd_atc __param_str_dp_ssc __param_dp_ssc dp_disable_dposc dp_enable_dposc regs_desc gpio_to_desc dsim_reg_enable_dsc decon_reg_set_start_crc dpp_reg_set_bpc __param_str_dp_bpc __param_dp_bpc vzalloc devm_kmalloc drmm_kmalloc __kmalloc __devm_drm_dev_alloc dma_heap_buffer_alloc exynos_drm_gem_alloc perf_trace_buf_alloc drm_atomic_state_alloc disable_irq_nosync kthread_cancel_delayed_work_sync __arm_smccc_smc fortify_panic decon_reg_update_req_cgc regs_dqe_cgc dp_hw_set_fec __param_str_dp_fec __param_dp_fec drm_property_lookup_blob drm_property_create_blob exynos_drm_crtc_create_blob drm_property_replace_blob drm_writeback_queue_job dpphy_reg_reset_mpllb tm_y_axis_srgb eotf_y_axis_srgb tm_x_axis_srgb eotf_x_axis_srgb exynos_crtc_mode_set_nofb exynos_plane_cleanup_fb exynos_plane_prepare_fb __kstrtabns_dp_drvdata __crc_dp_drvdata __kstrtab_dp_drvdata __ksymtab_dp_drvdata decon_drvdata dsim_drvdata dpp_drv_data of_device_get_match_data dp_reg_set_infoframe_data exynos_dqe_save_lpd_data exynos_dqe_restore_lpd_data decon_reg_get_crc_data dp_hw_set_audio_dma dev_attr_gt_lamda DPU_EVENT_LOG_ATOMIC_COMMIT DSIM_PHY_PLL_CON_VAL DPU_EVENT_LOG DPU_EVENT_LOG_CMD _note_9 dsim_read_data.__UNIQUE_ID_ddebug599 decon_reg_set_winmap.__UNIQUE_ID_ddebug499 decon_enable.__UNIQUE_ID_ddebug499 __dsim_cmd_packetgo_enable_locked.__UNIQUE_ID_ddebug499 dsim_reg_set_clocks.__UNIQUE_ID_ddebug399 $x.299 $d.299 $x.199 $d.199 $x.99 $d.99 __UNIQUE_ID_author589 __UNIQUE_ID_dp_phy_boost489 decon_seamless_mode_set.__UNIQUE_ID_ddebug489 decon_reg_stop_inst_dsi.__UNIQUE_ID_ddebug489 _dsim_exit_ulps_locked.__UNIQUE_ID_ddebug489 __UNIQUE_ID_license489 dsim_reg_set_config.__UNIQUE_ID_ddebug389 $d.389 $x.289 $d.289 $x.189 $d.189 $x.89 $d.89 decon_get_clock.__UNIQUE_ID_ddebug579 dsim_write_payload.__UNIQUE_ID_ddebug579 dsim_phy_power_on.__UNIQUE_ID_ddebug479 decon_reg_stop_perframe_dsi.__UNIQUE_ID_ddebug479 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