ELFP/@k@8@$# (((($$Ptd00QtdRtd((( GNU7Ծ؝e!SGCC: (Debian 8.3.0-6) 8.3.0, 0 ,!!: ,Q/(;l3V,TVN_tt,tVx,m`,e,0,B ^  , Ѝ !2 @+F 0 N{int'`U{o*z]7M  UL NT RST 0XT YT g& idh T i T lM )n T Rs T v [w T y T Rz T q| T  ) T 6 T  ) T  ) TfO$jdt&q^}M`p/B ] 2|_n IbT ҡdT ?pU ~T JT T T RT QT 5T }T m{n n( T0 pT4 fU8 sbTx |T| |T T in n n ސT %T @!T T PT dT (T r T 2 n n ~n 2Jn -T T ܜT ֜T FT 9gT zvT Tډ T3"T$T)%T `'U6)nP=+nX! -T`{/nhTk  Q%8'F)`T,Kh7J"`/*%'t4 5s@ At &*idLr$F) 8!  `b%h6ewq#  -rDIRN`>B -E . D O  T pad  T c  nv 1q 3MJ 6 Kw 7  8 / 9  : (| ; 0) < 8[ = @Vy @ Hm A P B X! D` Fhc HMp IMt- J xd= MFq N1l O Q 6 Y  [ & \!  ] ^  _ #q `M: b'  OML +SO | & 7 " Md O  O  O  M0 y r  Mr  ?f h! $2 M7 MTu; MQkwTtZF8  M2 Mo Mg M j, M- #? M(0> I O% P busQ  devR  S VT2  j V yW ~X  yY  ~Z  b[ l\ 8 ]t^ bus_ dev` [a  vc d Ze Zf  j: Kk : K  lX  {;n{ o p ^ t Ku : (v  `x y #z  . !pci% !usb K  m !pci !usb "{  N | y} o~ M  M 8  . J m &PI`KM"fbsL yNMO G0QM M0R (TM0U 8#tW % @|cW% DX % H<X% L% Y D[hx{\ % j]  =] ]" 2/]- +]5 )^  \^ xu^" (^- ^5  ` % qb % )c % d$?get1 `jYw`܆9Ke`y_X]u %  %  s %  % |>e % )|% ]EM Eh(M0 8 z@MH P#S % MM0`)` `! #4 $4[u78u%O[>&gbm]u}g'@4^{{(:_Mf^&fd`M)8c*++++%, {+,${- 8T.P -88l.P-\8.P.Q.R7-p8.P.Q.R/8/8-8=.P0.Q.R{-8 .P-8!.P-d9 9.P-x9Q.P/9 -9 v.P09.P-9$ .P0.Q.R@-9.P.Q.R2.S-,91 .P.Q-9> .P-9> &.P-9 >.P-9g.P.Q.R0.S/:K 7  ?1=u5 %@4=9VP%:=CM%)=RM%O=]s&i?M *&devB 1-&fdCMth2`&gbmJu-6> y.P-,6 .P-6T .P06a .P06.Q $\?' M6)%\'5`%t'O*%^($)fX'm* &fd+M  &ret,M } -87.PQ-T7n .P.Q@.R -d7.P-|7=.P.Q.R-7 .P/7 /7K $z M6T%\0` 3fdBMU K %^^) -6".P46=.PP.QQ.RR5 M16dir16retM6fd M6dfdM7m7b77^58~U M01`"9\U,`M C :fdU>M 9^UZ)1 ) ;B)W ;qX <P2=1tE>cgMI C ?1T; Yi -1{ 6.P/ 2 =<4`#O|#>!}>retM -T4 .P}.Q0.R p04 .P.Q5.R|.S =4p\#t|>retM #c % |>d 04 .P.Q'.R|.S@-p1 t.P-1 .P-$2 .P-@2.P 8.Q.R-X2 .P-2.P @.Q.R-2=.P H.Q.R-2h.P P.Q.R-2.P X.Q.R-2.P `.Q.R-3.P h.Q.R-(3.P p.Q.R-@3?.P x.Q.R-X3j.P .Q.R-p3.P .Q.R-3.P .Q.R-3.P .Q.R-3.P .Q.R-3A.P .Q.R-3l.P Ȝ.Q.R-4.P М.Q.R-4.P ؜.Q.R/<5K -`5.P .Q.R0x5.P .Q.R8'`8 M0:fd8M/)# : }#/;};>< 7 {-0n .P.Q@.R  .SP-0 .P.Q.R -0.P/ 1 /01K 8* M 0l9/*%*>num, >l- 7 ^V-40 .P/@0!0t0!.P.Q0.R:@ @2sH@11 A{~{~ t @Y A3 @ Aa @dd % A]] ANN AJ?J?IBAJJ Ann Aww b AqAwxwx  C((AMMuAJ;J;wATTaAAww AXXdA~~(A@zzO#@FF,2 +F:  tW>B-=CCE.=int`nNU{{([)٫+7T,nh7J v1p q3[ J6 = Kw7 = 8 = /9 = : =( |; =0 )< =8 [= =@ Vy@ =H mA =P B =X !D` Fh cH[p I[t -J x d=M~ qN lO Q 6Y [ &\ ] ^ u _ b #q`[ :b ML+ S Cn| | & CnJdp [ r [rf S=h !S $= 2 [ 7 [Tu ; [ ۫  < R T T# E U# V ( vQ  x[  y  z[  |  [ v [  ]0 C  E FZ G Cn/H HXoTtZn*Q =nI []K [_ [[ptr\us32] u32^ s64_ u64`  Pcfdsd Qe  `f  g 0 Jh 8 i < /j @ k D zl H [ n 0nvma8o pu Jq b g r  :s  t  Mu  vu0 yxz y{  J|  }  R  vma    0 =hĽ p J    /    7 b `   ( Q 8  H z P  bX "% ` q& d }' h ( lbo+\drv, -= .x 9/ 0u ?fd@[ A  Bu =C DuH ZEP 'F G 'H\ Cn K L= xM !  ݞN6  O G  nPv >R ( V 0 X 8 Z @ \ H <] P ^ 1 X _K ` ,`k h oak p zb x e ^f Eh  }  !  [6 ' G <  p M [ p  | [ p   [ p  [ p   u1 p    p  7  p e Q    q b  [ p       ʸY" Z c[ W     c  " g n !W ! " C 8Y$ [:  drv$(ret&[+# ' !@ i,"#- hret1[$:b %Q%R&:%P2%Q %R%S3%T! i6" 7 ': %P(;%P)(;&  n*MM *UU,+&K2 q+F(;lHlU{N{ `int'1o*]7*S g Ug padVg]  I g Jg qMg fdPT  } ~g Jg bppg qg g g tg z g g padg 6zF g g(`)1٫+T,h7J۫9TJ`g < R T T# E U#r Vr ( v  x`  y1  z`  |1  ` v `   0 C C E FCZ G S/H H [ptr \s32 ] !u32 ^ 9s64 _ -u64 ` J P c,fds d, Q e < ` f <  g J0 J h 98  i 9< / j 9@  k 9D z l JH`<9Lvma8 o  p J q [ g  r 9 : s 9  t ! M u <  v0  yx z 9y { 9 J | 9  } 9 R (vma (    9L 1 YhĽ>B -E . v 1 q 3` J 6  Kw 7   8  / 9  : ( | ; 0 ) < 8 [ = @ Vy @ H m A P B X ! D`  Fh c H`p I`t - J x d= MM q N8 l O  Q- 6 Y   [8 & \C  ]  ^  _ [ #q `` : bIqML +S q-|3&>Ydeee `mr `rfh!$2 `7 `Tu; `#I `]K `_ ` pI J 9  9 / 9  9 7 [ ` <  <( Q <8  JH z JP  [X "% 9` q& 9d }' !h ( !lbo+ drv, -x . x 9/& 0 ? fd@` A  B =CS DH ZESP 'F G 'H  _6  3k >4 9 5 9 h 6 J ]} 9 /: 9 f;6  z< J K L xM  ݞN  O  nP >RO ( V 0 X 8 Z @ \ H <] P ^ X _ ` ,` h oa p zb A x e ` ^f Eh   }     `      `  999JI  `I  999I 9V! `  999JI 9U `   `      (9 `  ( `    5  9J5 ; 9J [`  9JG `  5 5 ; f 9   L8 7 [ , Z, ,(  # ȟ&# p~ -# 4# 8i;#  B# XI#  > P#  SN| !drvS= >:"/SK9Q#zTJw" T)5 S" U; T$ I M@}#I'I #I69""h IFJR%iK 9rp$_ 6 JMX #6,I "6@9Q"7I R"709S%i9 9%j99$"$U %`L!drv%3 PH&:+\k X&tK&'QX(Kl&-`.:9$` Kp!bo {w!vma.(/(K&$J !bo" !vma2(`X#:@9%ret`*&%i [d`+h0J 11&lJ&I'Rh&J&x'P0'R316$7%0.('S1&K&'P3'Q 'R p'S 'T (Kl&$2`H!bo$ #C /'%ret`)P [+a h&I&o'Q'R&I&'P3'Q 'R p'S 'T &I'P(I&( Jl&$+ `GL!bo# +.p%ret`pj)3 `)P [$%i[rn&`H&'Q'R&H&'P3'Q 'R p'S 'T(H&(Hl&$`F!bo$ %ret`+Op&2F'PP'QQ'RR'SS'TT'U0$n H`D!boH& {#JH39#HC9 y #/HT9$!!#zIJ!!# I#J&""%retK`"")PL [##)BM 9O#;#)M9/$$+( NH3EE >1]$$1P%$1C%%#%16K%I%1*q%o%4E 5jh,E'P'R1'S'T'Uh&hE]#V'P&E&n'RH&DF]#'P(F&&F&'P3'Q 'R p'S 'T  (Fl&$$`hB!bo$/ %%#f$<9 &%#s$M9&&#%9?'7'#/%*9''#&5 ((%p( [x(l()7( [)()6) 9Y)K)6  33#BB+=1D#))4B7P#-*+*,B]#'P0xC0< 1X*P*1**88907++&C&'P 'Q p'R 'S @,\D&'P 'Q p'R 'S @38C8C>1$++)+1P+N+1 u+s+1++,HC"'P'Q'R&8D&'P 'Q p'R ,'S  ,D&'P 'Q p'R 5'S  -8`x:bo# .f09.sA9.9./,9; <  91=/(9=f99=J9=PY[?K 9A2 @/*9++@J;9.,$,@PI[,,AP 2 - -6H A  9G-C-Af 9--&A]#'P,4B&'P 'Q p'R'S  H 8 ? 98AX!@/39--@PB[..AP 2 .|.6#! &LA]# 'PP,A&'P 'Q p'R'S #!!?  9@X!@/89..@PG[..AP 2 ^/Z/6! &@]#!'PP,8A&'P 'Q p'R'S !$!>  9X"=/*9=;9=PJ[BP 2 6H ? [?|3#Cdrv4 //@/B9c0U0@h SJ10A; [11D3#?#1D#2197P#d2`2,@]#'P|Et@'PP'RR> []#=/,9BP 2 F4Y$2 (;#@/Y@922,<&'P3'Q 'R p'S'T XG3#?($1D#337P#B3>3,?]#'PPG"x@h#%1"|3x31 "331,";43478"44H"@@$ %1"441 "441,"#5!54@$I8",@&'P 'Q p'R'S ,@]#'PPG8B,%1J5F51 551551$+6'6,TB"'PP'QR'RSGDLC&1*h6d616661C661P771]\7X75jh&D5&'PP'QQ'RR'SS'TT'Uh(Dl&G(Kl&177JK K  KKL KMM K d=KUU ,Kdd % K##E  2 |+F' 2 V+FN(NU{?Q%1{(xint)?٫+7T,Kh7J`Kj:l۫QYTv1 q3x J6  Kw7  8  /9 : ( |; 0 )< 8 [= @ Vy@ H mA P B X !D` Fh cHxp Ixt -J x d=M8 qNR lO Q 6Y [ &\ ] ^ _ #q`x :b/ ML+ S/  K | &  Kd . . .  x cXr c  xr co]' ? *P c;fds d; Q e K ` f K  g 0 J h 8  i < / j @  k D z l H xK K [ Kvma8 o  p J q  g  r  : s   t  M u K  v0 yx z y {  J |   }  R 7vma 7    [ @ptr A s32 B u32 C s64 D u64 E 5? IU    K2? m B? @D @ooD ]fd ^xJ _  ` f a  / b H g@J h  i / j  k  fds l;Q m; ` n;0h  o @? fZl)drv `(gbmbo  '  u   fbo T !bo)77!x6E898!yB88"JNZ9P9"^99"X:P:"f( ::"7t;f;"PEx<<#h<d<#6<<#: =<$h%pUf &Qh&RU3&S&T%U &Q  $ &'U : xT !bo/p=l="P:==(T&QQ T^ !bo6=="PA'>#>(T&QQ syPT "'y+f>`>)yT Q* PT{+ >>,j -'j2 jaHT( !boa2?>.Z @Tt /boZ1P)Z;Q)[ R U0T !boU<??;?"PUG|?x?(8T&QQ CP(T8 !boP2??"PP=??(0T&QQ >K xT  !boK33@/@"PK;xp@l@($T&Q Q $ & F=S !boFG@@"PFR@@0T&QQ A xSG !boA2'A#A'S  m< xT !bo<)dA`A(T &PP&Q0 7=T !bo7=AA(T &PP&Q0 2S#!bo2<AA -Sh!bo-4BB1S (S!bo(/XBTB'S#(S&Q0 ,#S!bo#2BB N8TJ!bo2BB(@Tt &PP&Q0 S!bo2C C1S/ S!bo1LCHC1S;. `S8!bo)CC"3CC2 3lSGH&QQ0SS&P H&Q (&R &S   K  U !bo(]DYD!x5DD!yADD"JMEE"]QEME"  EE"f ' EE" 6FF0 V&PP&QQ&RR&SS&TT&UU&VV&WW&04xQ5gbm8IFAF6)FFF6R1G'G6GG7boH H89OHGH9&HH9' !II97 rIjI7iII9'J#J2 :>Rp++[_J]J+OJJ;pXQX&P'dQ(tQ&PP4P5gbmGPKHK6JUKK6LL6/$L}L6LL6.SMKM7boMM:>P+[NN+O?N;N;5gbm8NN6JFPODO6VOO6/zPlP6#QQ7boQQ:>P+[ R R+O2R0R;VEM(O&P0=D XO(.5gbmD3V{V'pO(O&PP4J?2OP5fd21xVV7gbm4QWIW% O&P8%0O&P'TO4u, xO5gbm,JWWC/,XQCh -RFN xI@gbm >A/ LA ]Ez" 4N5gbmCWW1N4 xN5gbm1+X'X1NGNT+nXdX+$XX+0PYJYH<INN +0YY+$YY+ZZJN<<QZMZ%Nl&PR0N&QK K LK~~ K"" K   K K K,, K K K K K88 K##E M""K K   K(( M3 K K K'' MKgg KPP K{{ K Kbb 2 +F52 +F>6˅m52 +FVx6>B-=CCE.=intNU{Q%b{([)p٫+7T,wh7J`wj:J = w I [] K [_  [ <R TT# EU#qVq (v x[ yp z[ |p [ v[ ]0C IEFIZG CY w/HHo ۫ Q  T t Zw ( F + ,[ [ v 1 q 3[ J 6 = Kw 7 =  8 = / 9 =  : =( | ; =0 ) < =8 [ = =@ Vy @ =H m A =P B =X ! D`  Fh c H[p I[t - J x d= Mi q N~ l O  Q 6 Y  [ & \  ]  ^  _ #q `[ : bML +S C w|& C w" 4d [ 9.r9 [r9 fo= h!o$=2 [7 [Tu; ['p F8A  [ 2 [ o [ g [ = j, [ -= #? [( =0>M[ptr\s32] lu32^ s64_ xu64`  Pc fdsd  Qe 0 `f 0 g 0 Jh 8 i < /j @ k D zl H [0 w @ wvma8o p Jq  g r  :s  t l Mu 0 v0 yxz y{  J|  }   R !vma!   @ pRhĽ p# J    /    7  ` 0  0( Q 08  H z P  X "% ` q& d }' lh ( llbo+q drv, -R . x 9/ 0 ? fd@[ A  B =CY DH ZEYP 'F G 'H q  S w 3E >4  5  h 6  ]} 9z /:  f;  z<  K L= xM  ݞN  O  nP >R) ( V\ 0 Xq 8 Zq @ \q H <] P ^ X _ ` ,` h oa p zb  x e : ^f^ Eh s z  }     [      [  #  [#  #  [\  # / [q  b [   w   ! [  ! [         :  ! [^     @ s  d z ) O * + , W- .  / '0 1 2 3 4 g5 % w  7 9! xm drv!5 ZZ!m"PP[m\? bo" ZZ#Q/ a[[[#` [[#5 \[$m8&%PW\Q\!lm"PP"SS&Uf0y#('\\#];0]"]# O]]#Y[^^#/^^'(bufy~)T ~*g3"PR*0g3?"P"Q2"R "S}"U}+pg3*g4k"Q"R}+g4 C w10! (ft bo, (_$_% e_a_%P __,p__&e< drv6 /`'`#/D``#zUa`#  maea# + aa- .e"PP"QQ"RR"SS"TT/$f4"P "Q ("R "S  J w   eU#+=b9be bo) zbvb e bo* bb e bo' bb e5 bo' 1c-c em bo0 ncjc  XeD  bo- cc#P8dd- У/e4"P H"Q ("R "S У J w " eD bo+ d{d#P6dd- /Te4"P H"Q ("R "S  J w0 1bo- 2P8- P~[lu bo$ aeOe#P/0f(f,ret[ff(fd [t- *`l'4"S*l'4"R@?$"S+l44+l@4*l?'"P3"Q "R ("S "T *m4g"P H"Q ("R "S +m4 J wuSd  bo4 ff#P?7g3g,{d bo{) sgog0v .1bov' 0q M1boq& 8_[c  bo_& gg#R_: ih3reta[- .d"PP"QQ4dV*,d4#"P "Q ("R c"S *Pd4c"P X"Q ("R g"S *td4"P "Q ("R f"S *d4"P "Q ("R e"S /d4"P "Q ("R d"S P[b boP ZjBj#RP1 tk`k3retR[- .c"PP"QQ*Hc4"P "Q ("R W"S *lc4)"P "Q ("R V"S *c4i"P "Q ("R U"S /c4"P "Q ("R T"S  J w 4 A[X^A boA" ilQl#RA6 mom3retC[-Q h.^D"PP"QQ*^4"P "Q ("R H"S h*^4"P "Q ("R G"S h*_4"P "Q ("R F"S h/4_4"P "Q ("R E"S h JQ wA %[X] bo% jn`n#R%1 nn,drv' fo^o,i( oo,ret)[pp5out<^*]M4"P6]"P+]Z4+]g4*]s4N"Q+^g4*^4s"P*4^4"Q/<^4"P8_! bo pp#9!}qgq#:Hurmr#!rr#P&tvt,drv uu,i uu% !PvDv)RX-! 78a7h(a8%  vv/L`s4"Q8%  w w/`s4"Q9.__G:@3w1w9__{:!XwVw;Xa`  :w{w:ww<`/b2==*,`M4"P+4`g4+`g4+`g4*4a4+ "QX*DaC "P*pa4[ "P*a4x "P1"Q86a "P"R*b4 "P+bZ4* b4 "P*Pb4!"P X"Q ("R "S *xb4O!"P 8"Q ("R "S *b4!"P ؤ"Q ("R "S +b4/b4"P "Q ("R "S   J! w !( 0j$ drv) ww#I xxnx,ret[xx%P -y'y,bo ywy%" TzJz7%!k*\jW,""P"U06tj""P"Q*j*#"P*j4#"Q0"R2*j48#"Q0"R0*k?}#"P3"Q "R ("S "T +k44+k@4*k?#"P3"Q "R ("S "T *k$#"PP+kZ4&g`H' bo zz9*(h(hp%:*Z{T{>(h?*{{@*pA*$?*{{*xh4$"R+h4+i4B*hH.%?*1|-|*h4%"R/h4"P6DhB%"P*PhM4Z%"P/ i4"P9+ i i ':+j|h|> i?+||?+||A,&?,}}A#, &?$,C}=}A0,`&?1,}}6i0&"P+iZ4*i4U&"P/j?"P3"Q "R ("S "T Х*Lis4&"Q/i4"Q+8ig4+pig4*iM4&"P/i4"PC(hZ4&'"PP6j:'"P+0j4q 0\(( drvq8 }}#JqFf~Z~#qV~~#/r#r'# N@#r;,rett[,bou *\W,F("P"Q"R"S"T0"U06\}("P"Q"R"S"T0"U"V6\("P*\*("P+]Z4+(]44DT]"Q"R"S"T"U'M [* drvM) #JM7=1#MGуŃ#/MXeY#zN,retP[,boQ aQ%6R *X[W,)"P"Q"R"S"T"UT $7%6[(*"P"Q"R"S"T"U0"V0*[*@*"P6[T*"P+[44+[Z4D$\"Q"R"S"TE, *1bo,' Fdrv. Fnum/ G*HP5IHPAJ V+ bo' \T,drv 8+%P <(num p*V4+"R+V4+V4*TVM4+"P*V4+"P+V4K  B,Lbo/ Mdrv Midx NR, IOPIOR IFret [ JR, wB,P xZ_-Qdrv& RJ4RD^VR/UʼnRz,$R" Sbo ݊*Z4!-"P1"Q*Z49-"P*[Z4Q-"P+[44Pb.Y.Qdrv8 8,R/FʋRzWF<T.T.Si OA+Yg4+Ys4+Zg4E P{ Y \.Qdrv) P[Y.Qdrv '#Ug(YXG/Qdrv! h`6HY."P+PY4+XY4*`Y4 /"P+hY 5*pY41/"PVYZ4"PPPPj W2Qfdj[͎ǎSdrvl 'Sretm[ŏTt=W4XW8YWXWUXW"XX2WPy0Y%2PWMbN DdW"P\V(63::/ W4"P H"Q ("R "S P\.d_3:@?;\d3:!|x\d$3::'/ e2=P=Q]OO]wwb ]qqF ]ppU ^_##E ]B _dd% ]00]DD ]3 _ _  ]   _  _]""]_ yQ] ]!! ]!! _  _uu] ] _!! ]XXd]TTa]  w]g g  ]gg_XXGR2 ]+Fm`M>B-=CCE.=intNU{{([)p٫+7T,wh7J`wo]۫T' v1 q3[ J6 = Kw7 = 8 = /9 = : =( |; =0 )< =8 [= =@ Vy@ =H mA =P B =X !D` Fh cH[p I[t -J x d=Mi qN~ lO Q 6Y [ &\  ] ^ _ #q`[ :b8 ML+ S8 Cw | & C wJ d 7 7 7  [ &lar l  [r lf =h ! $= 2 [ 7 [Tu ; [ < R  T T#  E U#  V ( v  x[  yp  z[  |p  [ v [  0C EFZG Cw/HH ['p*[]  I4g JqMfdP Dw[ptr\s32] u32^ s64_ u64` ' Pcfdsd Qe ! `f ! g '0 Jh 8 i < /j @ k D zl 'H [!w 1wvma8o p Jq  g r  :s  t  Mu ! v0 yxz y{  J|  }   R vma   1 pChĽ =SwCI []CK [_ [ py J    /    7  ` !  !( Q !8  'H z 'P  X "% ` q& d }' h ( lbo+drv,N - .x 9/T 0y ?N fd@[ A  B =C DH ZEP 'F G 'H Dd w 3 >4  5  h 6 ' K L= xM  ݞN  O  nP >RH ( V{ 0 X 8 Z @ \ H <] P ^ X _ ` ,` h oa p zb : x e Y ^f} Eh   }    [ N   N  [  'y [B  B 3 [{  'B N [   [       [   [    . N '. 4 ' Y N '@ [}  . . 4 _  N  (p"gƅ-ẻ'~"tW TU 5  *l\nf&.&jIac#G0X153,#8^09hk;*@;jA,B"CJBKAlLzMX[ z\]]G!^"p_P`iudM{epIhEiFj1kilW,mNnBropqCrX_sA5t+y0z|H}K.~ZHF&S̍\[CGRC/-lj_"?d!VqTQf/t֎Onΐ:W.[hSjЋ~Er/\Su|+4`Cudah8-3\"w`[^)f's')npr3C#M?Hvx@sBOdq_4}(YTuHX4k%7+8F9{o:o;o<m.=>$C?EW@7 8p 9p :p -i;p {<p f=p >p y?p po@p `Ap X=Bp nCp EDp ~Ep ~.Fp tGp Hp fsIp!uboJp B?Kp Lp Mp ^Np чOp WFPp sQp vrRp QSp FTp Up #?Vp *Wpx@\q] w"R4`R*aub,{c,Dd,he,#j<f%g#zyg#vHh #Qi#)j#k#}l#7m #L\n$#?(o(#Gp,#Uq0"`x~v1y#|z~4#4{~8#G|~<#'}~@#yz~~D#u~H#$~L#~P#R]~T#wX#@\#`#hd#h#,l#p#n*t#xYx#C#|#LQ#1#^*#&#{f#@#L#=###K#?#i}#x:#E#IC#-G#)#V#x #*$#n?(#/),#Y\,0#,p w w w$0%R*&v1&v2#p4#@$D34gRw+7I ^f L3 2 H ^o<ihuWRw4i#+@jvEY` d!?"Q?#+=$Y%g&]'RI(<)E*+n,lZ-.̕/jU0 ?=X 6> g ?pad@ 8` qa /b K=c Jd e f g yh Ai qj$ k( Fl, m0 fn4V) 0 f Q 4 D8y z F{ |' 7 `4 0 Lxyzw hd @,d box  6 f$ g( ., box  6 f$ g( @ g  q $7 | x  pad (0 0 q  F pad cmd "(   '    c hp Dy`FVu݆ex/pFsC 8? "TwD(J&T x "wo(J* (J0  !6)8  9[ :*y;[*[< QS IH; G d; Kw+ 8,[-drv>N .^_ [Pp,/bo_+ 0Q_8. 0``. bZ0`74 ˓1retb[D@2 xc(V@3q$@4Pp5qFX6R7DqF7LqF5tqF6P36Q 6R 6S l6T Ц7|qF8wR t /drvR?N z0/RM0zS'0 S+. XR0 T4 9V tW :  : xr:~ Ηė:q LD:d ;z0 V ?/0<?z0M'? 1. ? 1)4 >PP  -drvBN ?/P?z'? '. ? 4 .o [Hw#/bo& 5-0R: 1ret[1i g_22)2J]~2(!@#ǛśA,# 87wB5hxF!6Q6R7pxF7|xF5xF!6P36Q 6R 6S 6T 5xF"6R~78yB7TyD5py?V"6P6Q6R5yFm"6Q07yF7yF5yF"6P36Q 6R 6S 6T 7zF;(zF6P H6Q 6R 6S 8 J,#w#.,F [(zn&/boF+ 0RF? ]U1retH[Ĝ1iI & 22J+d}2J]K|2(L!}@M#sq@yN 'A~& H9&h|p`M%:&1-BpC&|D&kgD&C&}5|F$6R|5|F$6P6Q 6R 5|F$6P6Q05|G$6P6Q6R7}G5 }G%6P5$}!G>%6P6Q  7}G7 {B5|{Fx%6Q6R7{F7{F5{F%6P37{D5{?%6P6Q6R5$|F%6R|7\}F7h}F5}F$&6Q07}F;~F6P H6Q 6R 6S H J~&wn&,[( &-bo(1 4a *Eret+[Efd+ [Etmp,& C&w.W m(/bo & /vma 60: Dk]9R;P # R(:p; :};c[:d;ȡ¡B D;C;h5 F'6Rh5$.G'6P5D:G'6P06QX6S17tF7|F;F6P36Q 6R 6S 6T 7lFG7F.M- [Hs(/bo( SKF\sRG(6PPG`s^G,9_  [E)-bo 6 ?J C? S?/ ? )B ? 4z  'HEi.  [~tA3/bo' Ţ0J4v0D`N0/U8&0z'9;d~ 2:;ަҦ:;pf:;ߧ:;a[:;BD;D<wuD<C<~C)<9n<~ 1:<٩թBD<I<~~ +:<}{:<:<ͪ˪:<I<~~ \+:<:<DB:<nl:<I<~~ +:<:<:<:<64I<~~ ,:<`^:<:<:<ج֬I< p,:<:<*(:<TR:<zxI<   ,:<:<̭ʭ:<:<I< (-:<HF:<pn:<:<®I<$$ -:<:<:<><:<fdI<44-:<:<:<:< I<<< <.:<53:<][:<:<I<HH .:<ذְ:<:<*(:<QOI<TT .:<{y:<:<ͱ˱:<I<`` P/:<:<GE:<qo:<I<ȀȀ /:<ò:<:<:<=;I<؀؀ 0:<ge:<:<:<߳I<d0:< :<31:<][:<I<0:<:<شִ:<:<*(;(F6P36Q 6R 6S 6T 6UJI<$01DJ<TR5~BN16Q6R5~jGq16P6Q6R05~vG16P6R16S6T7~A5F16R~5\D16Q6R5t@16P6Qq70F78F5`F[26P36Q 6R 6S 6T ب;F6P h6Q 6R 6S `I<D 33:#=|x:=: =:<C=:<;G6P6Q6R6S6T6U17hF,g 3-drv,N ?/:?zK'4#,˘ [4-drv0N -bo@ Eret[4f 4" Ecmd 44*74#4q H4P .4w 8 `s(p4/drv(N 7xsG.4dK [:/drvK&N @M#tl9:0U>6::ַзB0D:%9:< 6::rn::::BD;C;`5Fk56R5ĆF56R7ІF7F5F56P36Q6R6S )6T58F56R7hF;F6P36Q6R6S 26T;XB6R 96P6R~5d=]96P6R~5G|96P6R5G96P5=96P6R}5G96P6R6S `5 G96P6R6S `5<G%:6P6R6S `5XGJ:6P6R@6S 5tGo:6P6RP6S `5G:6P6R`6S `7F>8 :-drv87N 4:#, [;-drv*N ?A;?LEret[4H,E R;-drv AN 4#,0;-bo) -vma9?:GEret[4P=#,s [Y<-bo* ?J7?G?/X?z'Eret[Ei 4f 4A%X4fAi< `H4P Ji<wY<,8<?z3'4K= >L<?S*4 ?9'?K=O. ?E=,`{ [1=-bo{/ ?J{<?{L?/{]?z|'>Yoq =-drvq3N ?iqH=? r?fr6=?zs'Eiu "d 8S}[ W?/drv[2N ս0[@~0f\=aQ0z\2'5ԁB1>6Q6R6PP6QQ6RR5 D~>6Q6R6P26Q 6R 6S g6T 06UQ5PB>6R1B-=CE.=intN{'U{o*]7(V)٫+T,۫T` <RT TT#T EU#T,V, (v xV y zV | V vV Z 0 C   Ef  F Z G C /H H [cptr \s32 ] u32 ^ s64 _ u64 `  P cfds d Q e  ` f   g 0 J h 8  i < / j @  k D z l H V vma8 oo  p J q  g  r  : s   t  M u   v0  yx z y {  J |   } R vma   o   = I V]  K V_   V p  J     /     7   `     ( Q  8   H z  P   X " % ` q & d } ' h  ( lbo +ldrv ,  -M  .x 9 /  0  ?fd @V  AJ  B = C   DH Z E P ' FU  GU ' Hl    3@ > 4  5  h  6   KE L= x M f ݞ N{  O  n P > R(  V"0  X78  Z7@  \7H < ]WP  ^ vX  _` , `h o ap z b x  e ^ f$ E h 9 @E} Pf[V{lVVV"V7(VQQc=v]V|V  V$  9 * O ? O p z j W z z CE XDE O EE (FE WGE  HE `IE JE 0KE gLE 'OE hRE 97 V bo75J7B7R/88(8<i:# V drv#,!@a b "P"Q"R6"S!`a "P"Q"R5"S!m "P"RH!m "P"RX"S `!m "P"Rh"S @!y "P# $ 8a % % nj% % % %!% d^&( ' ( 7 % % % ,(% ie% % ) * + "PP"QQ"RR"SS"T0,W W  ),ii +,U U  --,   +2 l+F wA7`@U{intN{)GT,@h-7J-v1< q3P J6  Kw7  8  /9 : ( |; 0 )< 8 [= @ Vy@ H mA P B X !DU` F[h cHPp IPt -J x d=M^ qNe lOa Qq 6Y [| &\ ][ ^ N _ 4 #q`P :b ML+ SP q @H |w &  @d< P r Pro]sT2G  B? @D @ooD ,  %  z ,aYT 2 +FG~Ѯg 2 +F~ z 2 +FЍ >B-=CCE.=int`nJNU{Q%{'u([)٫+7T,n۫ <R/ TT#/ EU#/V (v x[ y z[ | [ v[ 5] 0C  EA F ZG Cn/HHoQT+  ['  ** Sg  UHpad VH [ptr \s32 ] u32 ^ s64 _ u64 ` + P cXfds dX Q e h ` f h  g +0 J h 8  i < / j @  k D z l +H [hn xnvma8 o  p J q b g  r  : s   t  M u h  v0  yx z y {  J |   }  R Tvma T    x  hĽ =n I []  K [_   [ p  J      /      7  b `  h   h( Q  h8   +H z  +P   bX " % ` q & d } ' h  ( lbo + drv ,  -  .x 9 /  0  ?fd @[  A  B = C  DH Z EP ' F  G ' H  n  3 > 4   5  h  6 +  K L= x M  ݞ N  O ) n PX > R(  V0  X8  Z@  \H < ]P  ^  X  _- ` , `M h o aM p z b ~ x  e ^ f E h } [ )[RR+/[R7^[R+[R[R RT[- RT [G RG 3 r +r x +S b + [ Rr r x    Ԣ2 B)3  4  5  86  'D` cmdE  F  G padH  9K hdrL M  N  hQ hdrR JS  T  U  qV  ?= 6>T g ?Hpad@H (C qDH EH sFT 6GT 2HH  I< JH padKH$ @ g H qH $ |H xH T HpadH (0 0H qH H FH TpadH HcmdT "T(  T cT  HpadH {T   +  | c h p y`FVu݆ex/pFsC 8? & np   & n  W  !! ՟H# $  % & Q'  !bo-R!vma=T":K#ret[$P= %i [&boi.R'Ji;'iK'/i\6.'zj+(retl[ )qm |*n* H+x$y)P,\ܖ w 6-y-m{s. //|/0/ME//($12 /b^30 \- -456Q4456P56P6R6SH6T17)586Q5@6P5 6P8`6P5HN6P5tf6RH4'4$35L@6P36Q 6R P6S 6T 5@ 6P36Q 6R P6S y6T 4L9d k&drvd/)%:6PP7P;e [`?map ~T ݞ" ~* {'Xٞ` ~?! ~@%_A\-B05U6P6Q6R6S54U6P6Q6R:6S5Pa6P6R5hm,6P6R6S @5mQ6P6R6S `5mo6P6R8y6P56P16QH56P6Q056Pp56R54 6R~5d"6R5;6R~5c6P06Q6R36S56P6R~6S@6T07)56P56P74'435(@+6P36Q 6R P6S 26T 48'4@35h@6P36Q 6R P6S 6T `4|'435@6P36Q 6R P6S =6T 4Ĕ'4Д35@H6P36Q 6R P6S G6T 4'4358@6P36Q 6R P6S O6T 4PL nCPVDf=V>6 .@ =ibok5@6R86SE [Fdrv7GfPVHret[IVIIf) I r IP I0JKHiE G(0VGeMVEˠi [Fdrvi3FcmdiBr GiPG@i_Hretk[Il IПm  InL_oE FdrvE-IfGLI* Fdrv*9Hret,[I-I..`MЍPd-5-A-M:6N)N)/Ys0eH0qP/}5@|6RP5h6Q6R4'435܎@6P36Q 6R P6S6T 4'435@V6P36Q 6R P6Sz6T  4 LM6 -HE=-T-a /nvr0{hA6ЏЏ<-H-T-aBЏ<OnO{4ԏ'4܏38@6P36Q 6R P6S 6T 5t6Rh56P56P06QX6S14LMNN//[U0p5TA6Q 4h5pf6PP56Rp5@6P36Q 6R P6S96T 4LQ Q  RDD QR   QMM Qdd% R00QUU ,SQW W )Q  'Qii+QU U -R""Rg g  QXXQ d=R3 QKK Q   Q&QL QuuR % B$ > $ > : ; 9 I I&I I !I/  : ;9  : ;9 I8  : ;9  : ;9 I8  : ;9  : ;9 I I8  : ;9  : ;9 I8> I: ; 9 ((  : ; 9  : ; 9 I8 : ; 9 I<4: ; 9 I?< : ; 9 : ; 9 !4: ;9 I?<: ;9 I !I/! : ;9 I" : ; 9 I8 #4: ; 9 I$.?: ;9 'I@B%: ;9 IB&4: ;9 IB'4: ;9 I(4: ;9 IB)1RB UX YW * U+41B,41-1.B/1011.: ;9 'I@B2 U3: ;9 IB4B15.: ; 9 'I 64: ; 9 I74: ; 9 I8.: ; 9 'I@B9: ; 9 IB:: ; 9 IB;4: ; 9 IB< : ; 9 = >4: ; 9 IB? @.?<n: ; 9 A.?<n: ;9 B.?<nC.?<n: ; % B4: ; 9 I?< I$ > &I$ > : ; 9 I  : ; 9  : ; 9 I8 : ; 9 < I!I/ !4: ;9 I?< : ; 9  : ; 9 I : ; 9  : ; 9 I : ; 9 I8  : ; 9 > I: ; 9 ( 'I'I4: ; 9 I?.: ; 9 'I@B: ; 9 IB4: ; 9 IB 4: ; 9 I! U" U#4: ; 9 I$1%B&1'B(B)1*.?<n: ; 9 +.?<n% B$ > : ; 9 I$ >  I&I  : ;9  : ;9 I8 : ;9 I8  : ; 9  : ; 9 I8  : ; 9  : ; 9 II!I/  : ; 9  : ; 9 I : ; 9 I8  : ; 9 > I: ; 9 ( 4: ; 9 I?<: ; 9 <!4: ;9 I?<'I'I4: ; 9 I .?: ;9 '@B!: ;9 IB": ;9 I#: ;9 IB$.?: ;9 'I@B%4: ;9 IB&1'B(1)4: ;9 IB* +4: ;9 I,1-.?: ;9 'I .: ;9 I/B101RB UX YW 11B2B131RB X YW 4 54164I4741B819 U:: ;9 I;4: ;9 I<.: ; 9 'I =: ; 9 I>.?: ; 9 'I ?.?: ; 9 'I@B@: ; 9 IBA4: ; 9 IBB4: ; 9 IC: ; 9 IBD1RB UX Y W EBF.: ; 9 'I@BG.1@BH1RB X Y W I41J.?<nK.?<n: ; 9 % B% B$ > &I: ; 9 I$ >   I : ; 9  : ; 9 I8 : ; 9 < I !I/ 4: ; 9 I?<! : ; 9 I8  : ; 9  : ; 9  : ; 9 I> I: ; 9 ( (( : ;9  : ;9 I8  : ;9 I8 > I: ;9  : ; 9 <'I .?: ;9 'I@B!: ;9 IB": ;9 IB#4: ;9 IB$4: ;9 I%1&B'1(B1): ;9 I*1RB UX YW +1B,.: ;9 'I -: ;9 I..?: ;9 '@B/: ;9 I011B124I43B14.?: ; 9 'I@B5: ; 9 IB6: ; 9 IB74: ; 9 IB84: ; 9 I94: ; 9 IB:1RB UX Y W ; U<41B=.?: ; 9 '@B>?.: ; 9 'I @: ; 9 IA: ; 9 IB4: ; 9 IC: ; 9 ID: ; 9 IE4: ; 9 IF.?: ; 9 'I G.1@BH41I1RB X Y W J K.?<n: ; 9 L.?<nM.?<n: ;9 % B% B% B4: ; 9 I?< I$ > &I$ > : ; 9 I I !I/ 4: ;9 I?<  : ; 9  : ; 9 I8  : ; 9  : ; 9 I : ;  I8 4: ; 9 <! : ; 9  : ; 9 I : ; 9 I8  : ; 9 > I: ; 9 ( 'I'I4: ; 9 I.?: ;9 'I@B : ;9 IB!B"B#: ;9 IB$ %4: ;9 IB&.?: ;9 '@B'(4: ;9 I)4: ;9 I*1+1,4: ;9 IB-4I4.B/10.?: ;9 'I 1: ;9 I2: ;9 I34: ;9 I 4B15 : ;9 67 : ;9 8 U91RB X YW :1B;1RB UX YW < U=1B> ?41B@41A 1UB 1CB1DE.: ;9 'I F4: ;9 IG H4: ;9 II J.: ;9 '@BK.: ; 9 ' L: ; 9 IM4: ; 9 IN4I4O4: ; 9 IP.?: ; 9 'I@BQ: ; 9 IBR: ; 9 IBS4: ; 9 IBT4: ; 9 IBU.?: ; 9 '@BVB1W : ; 9 X1RB UX Y W Y1Z41[.: ; 9 'I \.1@B].?<n: ;9 ^.?<n_.?<n: ; 9 % B4: ; 9 I?< I$ > &I$ > : ; 9 I  : ; 9  : ; 9 I8 : ; 9 < I!I/ !4: ;9 I?< : ; 9  : ; 9 I : ;9  : ;9 I8  : ;9 I8  : ; 9  : ; 9 I : ; 9 I8  : ; 9 > I: ; 9 ( 'I'I( : ;9 I 8 ! : ;9 I 8 " : ;9 # : ;9 I8$ : ;9 % : ;9 I& : ;9 I' I8 (4: ; 9 I) : ; 9 * : ; 9 I8+4: ;9 I?,.: ;9 'I -: ;9 I..: ;9 'I@B/: ;9 IB0: ;9 IB14: ;9 IB24: ;9 I3 44: ;9 I516B718.: ;9 '@B91RBUX YW :1B;1<1B=1RBUX YW >.: ;9 ' ?: ;9 I@4: ;9 IBA4I4B UC41D41BE4: ;9 IFB1GB1H I1RBX YW J 1K.: ; 9 '@BL: ; 9 IBM: ; 9 IBN4: ; 9 IBO: ; 9 IP4: ; 9 IQ.: ; 9 'I R: ; 9 IS.: ; 9 'I@BT.1@BU1RBX YW V W1X41Y41 Z 1[B1\.?<n: ; 9 ].?<n: ;9 ^.?<n% B$ > $ > : ; 9 I &I : ; 9  : ; 9 I8  I .?: ; 9 '@B : ; 9 IB 4: ; 9 IB 1B1B.?: ; 9 'I@B: ; 9 IB4I41I!I/  U4: ; 9 IB1.?<n: ;9 .?<n: ; 9 .?<n: ; % B% B% B4: ; 9 I?< I$ > $ > : ; 9 I &I  : ; 9  : ; 9 I8  : ; 9  : ; 9 I I!I/  : ; 9  : ; 9 I : ; 9 I8  : ; 9 4: ;9 I?<<'I'I4: ; 9 I4: ; 9 I?.: ; 9 'I : ; 9 I: ; 9 I 4: ; 9 I.: ; 9 'I@B : ; 9 IB!1"B#1$.1@B%1B& '41B(1RB X Y W ) 1*41+B1,.?<n: ; 9 -.?<n% UB$ > : ; 9 I $ >  I&I : ; 9  : ; 9 I8 : ; 9 < I !I/ 4: ; 9 I?<!> I: ; 9 ( ((.?: ; 9 'I@B: ; 9 IB4: ; 9 IB% B% B% B4: ; 9 I?< I$ > &I$ > : ; 9 I  : ; 9  : ; 9 I8  : ; 9  : ; 9 I I!I/  : ;9  : ;9 I8  : ;9 I8  : ; 9  : ; 9 I : ; 9 I8  : ; 9 > I: ; 9 ( 4: ;9 I?<<'I'I4: ; 9 I!4: ;9 I? .: ;9 'I !: ;9 I": ;9 I#4: ;9 I$4: ;9 I%.: ;9 'I@B&: ;9 IB': ;9 IB(4: ;9 IB)4: ;9 IB*4: ;9 I+ ,1RB UX YW -1B. U/41B0411 12 1U31RB UX Y W 41516B71B819.: ;9 '@B:B1;.: ; 9 'I@B<: ; 9 IB=4: ; 9 IB>4: ; 9 IB?4: ; 9 I@ : ;9 A1RB X YW B C.?: ; 9 '@BD: ; 9 IBE.: ; 9 'I F: ; 9 IG: ; 9 IH4: ; 9 II4: ; 9 IJ : ; 9 K L.: ; 9 ' M.1@BN1O41PB1Q.?<n: ; 9 R.?<n: ;9 S.?<n  /source/platform/minigbm/usr/include/asm-generic/working/usr/include/libdrm/usr/include/aarch64-linux-gnu/bits/usr/include/usr/lib/gcc/aarch64-linux-gnu/8/include/usr/include/aarch64-linux-gnu/bits/types/working/usr/include/usr/include/linux/usr/include/aarch64-linux-gnu/asm/usr/include/aarch64-linux-gnu/sys/usr/include/aarch64-linux-gnu/gnuminigbm_helpers.cint-ll64.hamdgpu_drm.htypes.hdirent.hctype.hdirent.hstddef.herrno.hradeon_drm.hstruct_FILE.hFILE.hstdio.hsys_errlist.hunistd.hgetopt_core.hstdint-uintn.hstdint.hxf86drm.hxf86drmMode.hminigbm_helpers.hstring.hfcntl.hstdlib.hgbm.hstdc-predef.hdrm.htypes.h types.h types.hbitsperlong.h bitsperlong.hposix_types.h stddef.h posix_types.h posix_types.hioctl.h ioctl.hdrm_mode.hfeatures.hcdefs.h wordsize.hlong-double.hstubs.h stubs-lp64.h typesizes.hendian.hendian.hbyteswap.huintn-identity.hlocale_t.h__locale_t.hposix1_lim.hlocal_lim.hlimits.h errno.herrno.h errno.h errno.herrno-base.herror_t.hfcntl.hfcntl-linux.hstruct_iovec.hfalloc.h struct_timespec.hstat.hlibc-header-start.hstdarg.h__fpos_t.h__mbstate_t.h__fpos64_t.h__FILE.hcookie_io_functions_t.hstdio_lim.hstdio.hwaitflags.hwaitstatus.hfloatn.hfloatn-common.htypes.h clock_t.hclockid_t.htime_t.htimer_t.hstdint-intn.hselect.h select.hsigset_t.h__sigset_t.hstruct_timeval.hpthreadtypes.hthread-shared-types.hpthreadtypes-arch.halloca.hstdlib-bsearch.hstdlib-float.hstrings.hposix_opt.henvironments.hconfname.hgetopt_posix.hstdint.hwchar.hstdbool.hutil.h  0*<"". < ! >L/ M%)A3)=""K0 ! !  ? t K &" "# /! !/="K K"== 8"98!>= t..1 .J$  ! yJJ^<'!">%! 9J^<'!"> ! 9J Xf'!!> 'y<!  !&!-.<# s.Jf</ !.,<'  % .(_K%2w    $48    R. /A!`x  (! JL L##! z  =< E "$u,2X&L= t c&i< " K "( K$$x (  $ #.! !.!- "!"g%  e!  " '!J 1/t G.I &D.!!!D Z.N%!J.!    <2 . F%).A=!!/&f)!  @1t "#= <% , u    ".t.! ;/ ; 5 ! "K4t. ..y<"  . 31= 2. l  $. 4l  l = ! "" >!(!/  J%  "f.. 1k(!"z 3# x =/% ./ (!-?  u=  u =  u =  u >f w.  61  $=/2<!!-= $!fY.u$$@  Qf ..$ NJ$/!!0 !!/<MJL8 !!!0 & ?%)4A3)A 4% "4 ht.(#K!& X<. 6!&!J.< 2! #%!! !n  .=r = <YS /source/platform/minigbm/usr/includedri.cstdc-predef.h  /source/platform/minigbm/usr/include/aarch64-linux-gnu/bits/usr/lib/gcc/aarch64-linux-gnu/8/include/usr/include/usr/include/aarch64-linux-gnu/bits/types/usr/include/asm-generic/usr/include/aarch64-linux-gnu/sys/usr/include/aarch64-linux-gnu/gnu/usr/include/linux/working/usr/include/working/usr/include/libdrm/usr/include/aarch64-linux-gnu/asmgbm.ctypes.hstddef.hfcntl.hstdint-intn.hstdint-uintn.hstruct_FILE.hFILE.hstdio.hsys_errlist.hint-ll64.hdrv.hgbm.hgbm_priv.hassert.hstdlib.hgbm_helpers.hstdc-predef.hfeatures.hcdefs.hwordsize.hlong-double.hstubs.hstubs-lp64.htypesizes.hfcntl.hfcntl-linux.hstruct_iovec.hfalloc.h struct_timespec.hstat.hendian.hendian.hbyteswap.huintn-identity.hstdint.hstdint.hlibc-header-start.hwchar.hstdarg.h__fpos_t.h__mbstate_t.h__fpos64_t.h__FILE.hcookie_io_functions_t.hstdio_lim.hstdio.hwaitflags.hwaitstatus.hfloatn.hfloatn-common.hlocale_t.h__locale_t.htypes.hclock_t.hclockid_t.htime_t.htimer_t.hselect.hselect.hsigset_t.h__sigset_t.hstruct_timeval.hpthreadtypes.hthread-shared-types.hpthreadtypes-arch.halloca.hstdlib-bsearch.hstdlib-float.hstring.hstrings.hmman.hmman.hmman-linux.hmman-shared.hxf86drm.h drm.h types.h types.h types.hbitsperlong.h bitsperlong.hposix_types.h stddef.h posix_types.h posix_types.hioctl.h ioctl.hdrm_mode.h drm_fourcc.h stdbool.hutil.h N  $  $  +J  " <; .  )%2 #<# 0#   !&.) !! '<! !!   O6  O  1  ! 1 #1 #  O1  #jK# !i " ?  . f"&.  v.Js  . ) !!  XP ,T ,T. !# 0 P ! /Q "*  J"&.  !! 5<! !/!/!   xQ(x Kz^!! X1*!!0" ! 1J//,$-< &!z = -!(J#~K#  ~ !"  ."! !!  ` $ c.,e."z !!$"!(<(X ! !-! ]  $    # / ! @  $   / !1/ !o. . T   (T   0T   8TH . @T<!#  oBJ y !!!!"h Jy !!!!"h Jy !!!!"(   T   T . T lz %/z =2  Y21 .. !1)# ; <" !! !!!  r . ~  =/YS /source/platform/minigbm/usr/includevc4.cstdc-predef.hZT /source/platform/minigbm/usr/includei915.cstdc-predef.hQ /source/platform/minigbm/usr/include/usr/include/aarch64-linux-gnu/bits/usr/lib/gcc/aarch64-linux-gnu/8/include/usr/include/aarch64-linux-gnu/bits/types/usr/include/asm-generic/working/usr/include/usr/include/aarch64-linux-gnu/sys/usr/include/aarch64-linux-gnu/gnu/usr/include/linux/usr/include/aarch64-linux-gnu/asm/working/usr/include/libdrmdrv.cerrno.htypes.hstddef.hfcntl.htime.hthread-shared-types.hpthreadtypes.hstdint-intn.hstdint-uintn.hstdint.hstdarg.hstruct_FILE.hFILE.hstdio.hsys_errlist.hunistd.hgetopt_core.hint-ll64.hxf86drm.hdrv.hdrv_priv.hstring.hassert.hpthread.hstdlib.hdrv_array_helpers.hstdc-predef.hfeatures.hcdefs.hwordsize.hlong-double.hstubs.h stubs-lp64.h errno.herrno.h errno.h errno.herrno-base.herror_t.htypesizes.hfcntl.hfcntl-linux.hstruct_iovec.hfalloc.h struct_timespec.hstat.hendian.hendian.hbyteswap.huintn-identity.hsched.htime_t.hsched.hstruct_sched_param.hcpu-set.htime.htimex.hstruct_timeval.hclock_t.hstruct_tm.hclockid_t.htimer_t.hstruct_itimerspec.hlocale_t.h__locale_t.hpthreadtypes-arch.hsetjmp.hstdint.hlibc-header-start.hwchar.h__fpos_t.h__mbstate_t.h__fpos64_t.h__FILE.hcookie_io_functions_t.hstdio_lim.hstdio.hstrings.hmman.hmman.hmman-linux.hmman-shared.htypes.hselect.hselect.hsigset_t.h__sigset_t.hposix_opt.henvironments.hconfname.hgetopt_posix.hdrm.h types.h types.h types.hbitsperlong.h bitsperlong.hposix_types.h stddef.h posix_types.h posix_types.hioctl.h ioctl.hdrm_mode.h drv_helpers.hstdbool.hdrm_fourcc.h waitflags.hwaitstatus.hfloatn.hfloatn-common.halloca.hstdlib-bsearch.hstdlib-float.hutil.h Vt!==X/ :" #;z &I  .zJ/f.)J%  " ," {X. #!! 3.<$@ 0# =- 1 -< 0 [ c 03.J.<6/( / "J/"J# !#J#.!#.!#.! / . n< !0000 !"!A<!.!"0/0/0!   Y #!? #+1 O <"! ! //0: ! !(. Az.  / 0#< 0   N1 # "# !!!! !"'. z /  / . 4z 4"x 3#x J( "#   ! v 4 & ". r. 3 !  ! !!<  s. ! f   $ % L#   ! v! 4% ". y. !!. .c./ ! /   t f#!.".1y './ Y #/$/<2- /6/. x.=/. ?1!//>  .! " z.< W< W< W< fny *$$y ! ~! ~g00 !? t.<E.#/$y.! "/".=-=  4J@ J<J(KXy2   /.  /" ./-=  4J>2 &= ! <"=  ~  ~ ! !   !! !T = ! <!& ! !!   =5 *"!! * !o. ! !!  & !!/  O        .1!//>  .! " z.< W< W< W<  f1!//=0  .! " w < \< W< W< W< f # # #! .=! < e=! !-! k=! !-! k # # # # &LY 2>! ! J  (f !"#  z 4!!0 0   -/ < 2 4  . 2vK> J m .$ gt x  `} u=%g -  .!.!"=X!J);  .  .;  /; J"/<r>  /X0 ~!= y<'! ./K  =$!  -;  .p< ./ K' vJ !    X1$z&z ^ <"# =% "! ! X !*#!* "4z!)3 !$  8.5#(  4p (  3k  k.  "Xo %  4p (  /t   ! ^  !!#.JfL 01t1&!z  h!  u <f g$ !$  < "  .! # 1.! # 5m /source/platform/minigbm/usr/include/usr/include/aarch64-linux-gnu/bits/usr/lib/gcc/aarch64-linux-gnu/8/include/usr/include/aarch64-linux-gnu/bits/types/usr/include/asm-generic/working/usr/include/libdrm/source/platform/minigbm/external/working/usr/include/usr/include/aarch64-linux-gnu/sys/usr/include/aarch64-linux-gnu/gnu/usr/include/linux/usr/include/aarch64-linux-gnu/asmvirtgpu_virgl.cerrno.htypes.hstddef.hstdint-intn.hstdint-uintn.hstruct_FILE.hFILE.hstdio.hsys_errlist.hunistd.hgetopt_core.hthread-shared-types.hpthreadtypes.hint-ll64.hdrm.hdrv.htime.hdrv_priv.hvirgl_hw.hvirgl_protocol.hvirtgpu_drm.hvirtgpu.hxf86drm.h string.hassert.hfcntl.hdrv_helpers.hmman.h stdlib.hstdc-predef.hfeatures.hcdefs.h wordsize.hlong-double.hstubs.h stubs-lp64.h errno.herrno.h errno.h errno.herrno-base.herror_t.htypesizes.hfcntl.hfcntl-linux.hstruct_iovec.hfalloc.h struct_timespec.hstat.hendian.hendian.hbyteswap.huintn-identity.hstdatomic.hstdint.hstdint.hlibc-header-start.hwchar.hstdarg.h__fpos_t.h__mbstate_t.h__fpos64_t.h__FILE.hcookie_io_functions_t.hstdio_lim.hstdio.hlocale_t.h__locale_t.hstrings.hmman.hmman-linux.hmman-shared.hposix_opt.henvironments.hconfname.hgetopt_posix.htypes.h clock_t.hclockid_t.htime_t.htimer_t.hselect.h select.hsigset_t.h__sigset_t.hstruct_timeval.hpthreadtypes-arch.htypes.h types.h types.hbitsperlong.h bitsperlong.hposix_types.h stddef.h posix_types.h posix_types.hioctl.h ioctl.hdrm_mode.hstdbool.hdrm_fourcc.hwaitflags.hwaitstatus.hfloatn.hfloatn-common.halloca.hstdlib-bsearch.hstdlib-float.hdrv_array_helpers.hpthread.hsched.hsched.hstruct_sched_param.hcpu-set.htime.htimex.hstruct_tm.hstruct_itimerspec.hsetjmp.hutil.h m! "/  "*/%#z &(%u "(*(y /$ !y !!*!I N((u 0z %w  (!(*"*"!  .J%=  . 2NtN0.! !. !2$ !3% #. !2 .!2$ !'%<"$0.! !.$ !2$ !3% #. !2 .!&$<!'%<#. !2C. !&$<!'%<"3C \JL 0$1 "$#5  $$ O (0>=(" j.!!"!g   #! .w . 0 o   w.!  g   X`   Ju %<[  i   <s %<[   e %<[   k  Jc  Jm "<]# ].# ] #g "[.  o %.[  # Qy  ?J %.o.z.<./ "   `s<! ! ! ..,{  #. ! y.1 x|$$#  v.  ~. !#0.+.%  . #  q.  ~ /#0.+.# 4  ~./#0.+.7 0 ..  ! #X< /  . .8 V =0X <[/n XL2 // .  0 / M<N 2 N< )09< W. ./M= zJ#  ,  t J . t.5  5<'.)!!  v. -7  7<).  <(x Rx @)3x =)/#  #<.( 3x. u< % <1<.! !!  J.4  "y.-   / // K!  .<(</  ": "" /  C  f V.0<2w[jJ!!!< 0;..  J3\ ~  Jw  <w @+4w =+/& 3v. $#$2s  '1! <.( #0 %C </ !!  D.:  "y.-   / // K!  / dJw[.!;!!/    .O1 / H$$."!h!!K"f!K$J!//"  :"   !2$./"< O!!!< 0;&@. !.<.`  ~.%%f<%=! }%#%#%/./ KX !!   !r! !   q! !   p! !   o! !   n! !  m! !  l! !  k! !  !h !  'T! !  (S! !  )R! !  +P! !  .#3&w.!#z &#!=+% &!. < |Y  ! ! #  f}vL !$  K/,!!!3J<$`! !  !\ !  c !  $Y! !  /8  } !!</!! &<5K z HI04z &z &z yf $B<8 . #  !#hJ  " c.-4. 4J $4f $~ 0.~J0  ~. !W.6!~.6 ~X6  }  'W.1 1X &1. 1J !1f $/f $.f %. <!f< ["""%1$!K "<n 10!~.0 ~X0  ~  !W.1!~.1 ~X1  ~  'W.0 0f ).5X #5X #1X #0X #3X #;X ./z 'z &y.'/!. !# 9! "!<kt   J.!!==!}<  "!K%  !!  #  }   .  f !<...  s  .@ /source/platform/minigbm/usr/include/aarch64-linux-gnu/bits/usr/include/usr/lib/gcc/aarch64-linux-gnu/8/include/usr/include/aarch64-linux-gnu/sys/usr/include/aarch64-linux-gnu/gnu/usr/include/aarch64-linux-gnu/bits/typesdrv_array_helpers.ctypes.hstdint-uintn.hstdlib.hassert.hstdc-predef.hdrv_array_helpers.hstdint.hstdint.hlibc-header-start.hfeatures.hcdefs.hwordsize.hlong-double.hstubs.hstubs-lp64.htypesizes.hwchar.hstdint-intn.hstddef.hwaitflags.hwaitstatus.hfloatn.hfloatn-common.hlocale_t.h__locale_t.htypes.hclock_t.hclockid_t.htime_t.htimer_t.hendian.hendian.hbyteswap.huintn-identity.hselect.hselect.hsigset_t.h__sigset_t.hstruct_timeval.hstruct_timespec.hpthreadtypes.hthread-shared-types.hpthreadtypes-arch.halloca.hstdlib-bsearch.hstdlib-float.hstring.hstrings.hutil.h  #. # /$ !<!%!.z. !! 6f #  // =!  K=! = .w.< f?/ .0  / "" / %  &  1 /:  : <'z.!/!. +JXs<e< X =!+!-! k #<#  / -!?/!  YS /source/platform/minigbm/usr/includemsm.cstdc-predef.h^X /source/platform/minigbm/usr/includemediatek.cstdc-predef.h /source/platform/minigbm/usr/include/usr/include/asm-generic/usr/include/aarch64-linux-gnu/bits/usr/lib/gcc/aarch64-linux-gnu/8/include/usr/include/aarch64-linux-gnu/sys/usr/include/aarch64-linux-gnu/gnu/usr/include/linux/usr/include/aarch64-linux-gnu/asm/usr/include/aarch64-linux-gnu/bits/types/working/usr/include/libdrmdumb_driver.cerrno.hint-ll64.htypes.hstdint-intn.hstdint-uintn.hstddef.hthread-shared-types.hpthreadtypes.hdrv.htime.hdrv_priv.hdrv_helpers.hstdc-predef.hfeatures.hcdefs.hwordsize.hlong-double.hstubs.hstubs-lp64.herrno.herrno.herrno.h errno.herrno-base.herror_t.h stdbool.hdrm_fourcc.h drm.h types.htypes.h types.hbitsperlong.h bitsperlong.hposix_types.hstddef.hposix_types.h posix_types.hioctl.h ioctl.hdrm_mode.h stdint.hstdint.hlibc-header-start.htypesizes.hwchar.hstdlib.hwaitflags.hwaitstatus.hfloatn.hfloatn-common.hlocale_t.h __locale_t.h types.hclock_t.h clockid_t.h time_t.h timer_t.h endian.hendian.hbyteswap.huintn-identity.hselect.hselect.hsigset_t.h __sigset_t.h struct_timeval.h struct_timespec.h pthreadtypes-arch.halloca.hstdlib-bsearch.hstdlib-float.hdrv_array_helpers.hpthread.hsched.hsched.hstruct_sched_param.h cpu-set.htime.htimex.hstruct_tm.h struct_itimerspec.h setjmp.hutil.h #!-=/= " =# g#.f $0X #0X " /X<2!<...  v  .E /source/platform/minigbm/usr/lib/gcc/aarch64-linux-gnu/8/include/usr/include/aarch64-linux-gnu/bits/usr/include/aarch64-linux-gnu/bits/types/usr/include/usr/include/aarch64-linux-gnu/sys/usr/include/aarch64-linux-gnu/gnu/working/usr/include/libdrm/usr/include/linux/usr/include/aarch64-linux-gnu/asm/usr/include/asm-genericgbm_helpers.cstddef.htypes.hstruct_FILE.hFILE.hstdio.hsys_errlist.hstdint-uintn.hgbm.hstdc-predef.hlibc-header-start.hfeatures.hcdefs.hwordsize.hlong-double.hstubs.hstubs-lp64.hstdarg.htypesizes.h__fpos_t.h__mbstate_t.h__fpos64_t.h__FILE.hcookie_io_functions_t.hstdio_lim.hstdio.hdrv.hdrm_fourcc.hdrm.htypes.h types.h types.h int-ll64.h bitsperlong.h bitsperlong.h posix_types.h stddef.h posix_types.h posix_types.h ioctl.h ioctl.h drm_mode.hstdbool.hstdint.hstdint.hwchar.hstdint-intn.hstdlib.hwaitflags.hwaitstatus.hfloatn.hfloatn-common.hlocale_t.h__locale_t.htypes.hclock_t.hclockid_t.htime_t.htimer_t.hendian.hendian.hbyteswap.huintn-identity.hselect.hselect.hsigset_t.h__sigset_t.hstruct_timeval.hstruct_timespec.hpthreadtypes.hthread-shared-types.hpthreadtypes-arch.halloca.hstdlib-bsearch.hstdlib-float.h    ! = = = = = = = = = = = = = 1^X /source/platform/minigbm/usr/includerockchip.cstdc-predef.h\V /source/platform/minigbm/usr/includeamdgpu.cstdc-predef.h? /source/platform/minigbm/usr/include/usr/lib/gcc/aarch64-linux-gnu/8/include/usr/include/aarch64-linux-gnu/bits/usr/include/asm-generic/working/usr/include/libdrm/source/platform/minigbm/external/working/usr/include/usr/include/aarch64-linux-gnu/sys/usr/include/aarch64-linux-gnu/gnu/usr/include/linux/usr/include/aarch64-linux-gnu/asm/usr/include/aarch64-linux-gnu/bits/typesvirtgpu_cross_domain.cerrno.hstddef.htypes.hstdint-intn.hthread-shared-types.hpthreadtypes.hstdint-uintn.hint-ll64.hdrm.hdrv.htime.hdrv_priv.hvirtgpu_cross_domain_protocol.hvirtgpu_drm.hvirtgpu.hdrv_array_helpers.hpthread.hxf86drm.hstring.hdrv_helpers.hstdlib.hmman.h stdc-predef.hfeatures.hcdefs.h wordsize.hlong-double.hstubs.h stubs-lp64.h errno.herrno.h errno.h errno.herrno-base.herror_t.h libc-header-start.hlocale_t.h __locale_t.h strings.htypesizes.hmman.hmman-linux.hmman-shared.hstdarg.htypes.h clock_t.h clockid_t.h time_t.h timer_t.h endian.hendian.hbyteswap.huintn-identity.hselect.h select.hsigset_t.h __sigset_t.h struct_timeval.h struct_timespec.h pthreadtypes-arch.hstdint.hstdint.hwchar.htypes.h types.h types.hbitsperlong.h bitsperlong.hposix_types.h stddef.h posix_types.h posix_types.hioctl.h ioctl.hdrm_mode.hstdbool.hdrm_fourcc.hwaitflags.hwaitstatus.hfloatn.hfloatn-common.halloca.hstdlib-bsearch.hstdlib-float.hsched.hsched.hstruct_sched_param.h cpu-set.htime.htimex.hstruct_tm.h struct_itimerspec.h setjmp.hutil.h Ѝ '# v tL & /!!#J! (; !;! ,3 %!7 t   !  f2! #$!)=!%  !! f q. 5 | t$ >  /0     !"0g -r  H" !!   . ! <s ! Jv "%'!s =/*y'=4#0 #2(.1 K#./%  !%# !! z&8 "#/( I 6 5%y 'z &!"/&!#.$!/%!$.# !/%f#4"U!!!!$ } "#xvg fyJ !< = Q  p x   !< !   . ! '/   . ~ ![ X 1J!J"! 0 J! <% Bz Pz.=*%*%*)"//./Y+% '!.  . ! .~ .  ~ ! *!/!./'K k..B   . J z.J&/J/ pX!"" 0# !/  w //0/"/ 05 .=!2 2  !5 .5!!1/!!!(x !5!/O~X*KK/.Q .!!!!(x !5 # / <  ~< ! /~ ..AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1PTHREAD_KEYS_MAX 1024GBM_FORMAT_RGB565 __gbm_fourcc_code('R', 'G', '1', '6')__SUSECONDS_T_TYPE __SLONGWORD_TYPEpci_rev_CS_POSIX_V7_LP64_OFF64_LINTFLAGS _CS_POSIX_V7_LP64_OFF64_LINTFLAGS__u64AT_REMOVEDIR 0x200DRM_CAP_CURSOR_WIDTH 0x8_POSIX_V6_LPBIG_OFFBIG -1version_minor_BITS_TYPES___LOCALE_T_H 1INT_FAST8_MIN (-128)AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04AMDGPU_TILING_SET(field,value) (((__u64)(value) & AMDGPU_TILING_ ##field ##_MASK) << AMDGPU_TILING_ ##field ##_SHIFT)_drmPlatformBusInfoDRM_MODE_REFLECT_MASK ( DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y)AMDGPU_CTX_PRIORITY_UNSET -2048__REDIRECT(name,proto,alias) name proto __asm__ (__ASMNAME (#alias))_SC_THREAD_PRIO_PROTECT _SC_THREAD_PRIO_PROTECTDRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob)RADEON_CMD_WAIT 8RADEON_BUFFER_SIZE 65536AMDGPU_FAMILY_SI 110DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw)RADEON_CS_KEEP_TILING_FLAGS 0x01SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP 11DRM_MODE_ENCODER_VIRTUAL 5DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP)DRM_MODE_PAGE_FLIP_ASYNC 0x02ENOTUNIQ 76_CS_POSIX_V7_ILP32_OFFBIG_LIBS _CS_POSIX_V7_ILP32_OFFBIG_LIBSDRM_BUS_PLATFORM 2__FLT_MAX_10_EXP__ 38__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1DRM_CAP_SYNCOBJ 0x13DRM_MODE_FEATURE_KMS 1R200_EMIT_PP_TXCBLEND_3 24__UINT_LEAST16_TYPE__ short unsigned intAMDGPU_INFO_SENSOR_GPU_LOAD 0x4RADEON_CMD_VECLINEAR 9GBM_FORMAT_BGRA1010102 __gbm_fourcc_code('B', 'A', '3', '0')R200_EMIT_PP_TXCBLEND_6 27_CS_POSIX_V7_LPBIG_OFFBIG_LDFLAGS _CS_POSIX_V7_LPBIG_OFFBIG_LDFLAGS__INT32_C(c) c__PTHREAD_SPINS_DATA int __spins_STDLIB_H 1_CTYPE_H 1ELIBBAD 80__pad5__STDC_IEC_559_COMPLEX__ 1AT_NO_AUTOMOUNT 0x800EPERM 1cu_active_numberRADEON_TILING_MICRO 0x2vrefresh__INT_LEAST64_MAX__ 0x7fffffffffffffffL__wchar_t__ AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F__SIZEOF_WCHAR_T__ 4S_IFLNK __S_IFLNK_POSIX_MEMLOCK 200809LDRM_MODE_DITHERING_OFF 0_SC_2_C_DEV _SC_2_C_DEV__FLT32X_MIN__ 2.22507385850720138309023271733240406e-308F32xDRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb)__DEC32_MAX_EXP__ 97DRM_RADEON_CP_STOP 0x02_STDBOOL_H LOCK_EX 2R300_CMD_PACKET3 3SEEK_DATA 3EHOSTUNREACH 113F_SETPIPE_SZ 1031_CS_XBS5_LPBIG_OFFBIG_LDFLAGS _CS_XBS5_LPBIG_OFFBIG_LDFLAGS__need___va_listAMDGPU_CTX_OP_FREE_CTX 2ENOPKG 65_SIZET_ FFSYNC O_FSYNC_POSIX_RTSIG_MAX 8AMDGPU_CTX_PRIORITY_VERY_LOW -1023_POSIX_REGEXP 1__FLT32X_MAX__ 1.79769313486231570814527423731704357e+308F32x__ASM_BITSPERLONG_H R200_EMIT_RB3D_BLENDCOLOR 76__UINT64_C(c) c ## ULRADEON_UPLOAD_CONTEXT 0x00000001_IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)_LFS64_STDIO 1__aarch64__ 1AMDGPU_TILING_BANK_HEIGHT_SHIFT 17DRM_PRIME_CAP_EXPORT 0x2RADEON_EMIT_PP_TEX_SIZE_0 73DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap)__LITTLE_ENDIAN 1234EUSERS 87RADEON_EMIT_PP_TXFILTER_1 14L_XTND SEEK_END_CS_V6_WIDTH_RESTRICTED_ENVS _CS_V6_WIDTH_RESTRICTED_ENVS_BITS_FLOATN_H _SC_SPIN_LOCKS _SC_SPIN_LOCKSGBM_FORMAT_BGRA5551 __gbm_fourcc_code('B', 'A', '1', '5')WIFSTOPPED(status) __WIFSTOPPED (status)__LDBL_DECIMAL_DIG__ 36FALLOC_FL_KEEP_SIZE 0x01DRM_MODE_OBJECT_ENCODER 0xe0e0e0e0AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0DRM_EVENT_CRTC_SEQUENCE 0x03_CS_V6_ENV _CS_V6_ENV__SIZEOF_POINTER__ 8isgraph(c) __isctype((c), _ISgraph)__extern_inline extern __inline __attribute__ ((__gnu_inline__))__USE_XOPEN2K8__WIFSIGNALED(status) (((signed char) (((status) & 0x7f) + 1) >> 1) > 0)RADEON_INFO_NUM_BACKENDS 0x0a__cookie_io_functions_t_defined 1RENAME_EXCHANGE (1 << 1)DRM_CAP_DUMB_PREFERRED_DEPTH 0x3RADEON_UPLOAD_ALL 0x003effff__UINT_FAST8_MAX__ 0xffDRM_MODE_PRESENT_TOP_FIELD (1<<0)__suseconds_t_defined _POSIX_THREAD_PRIO_INHERIT 200809LRADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18_POSIX_READER_WRITER_LOCKS 200809L_ILP32_GCC_WRAP_STDINT_H uintptr_tDRM_RADEON_SURF_FREE 0x1b__DEC32_EPSILON__ 1E-6DFUINT_LEAST32_MAX (4294967295U)DRM_MODE_FLAG_NVSYNC (1<<3)DRM_EVENT_VBLANK 0x01_POSIX_BARRIERS 200809LAMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2drmVersionPtrDRM_MODE_TYPE_BUILTIN (1<<0)S_IWGRP (S_IWUSR >> 3)F_ADD_SEALS 1033PTHREAD_THREADS_MAXRADEON_TILING_SWAP_16BIT 0x4__FLT_EVAL_METHOD__ 0DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)_ISspaceHOST_NAME_MAX 64_LP64 1drmPciBusInfoPtrDRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE (1 << 2)GBM_FORMAT_XBGR16161616F __gbm_fourcc_code('X', 'B', '4', 'H')_SC_SPAWN _SC_SPAWNDRM_RADEON_GEM_PWRITE 0x22__bos0(ptr) __builtin_object_size (ptr, 0)RADEON_PARAM_IRQ_NR 5DRM_MODE_ATOMIC_FLAGS ( DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_PAGE_FLIP_ASYNC | DRM_MODE_ATOMIC_TEST_ONLY | DRM_MODE_ATOMIC_NONBLOCK | DRM_MODE_ATOMIC_ALLOW_MODESET)RADEON_UPLOAD_VIEWPORT 0x00000020_SC_2_VERSION _SC_2_VERSION_SC_2_PBS_MESSAGE _SC_2_PBS_MESSAGE__USE_XOPEN__FLT32X_DENORM_MIN__ 4.94065645841246544176568792868221372e-324F32x_SC_SYSTEM_DATABASE _SC_SYSTEM_DATABASEGBM_FORMAT_XRGB1555 __gbm_fourcc_code('X', 'R', '1', '5')external_rev__CPU_MASK_TYPE __ULONGWORD_TYPEDRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)RADEON_CMD_SCALARS2 7__LDBL_MAX_10_EXP__ 4932__UINT_FAST8_TYPE__ unsigned charF_SET_RW_HINT 1036__INT_LEAST16_TYPE__ short int__PTHREAD_MUTEX_HAVE_PREV 1__S_IFSOCK 0140000EDEADLK 35RADEON_UPLOAD_CLIPRECTS 0x00008000__ARM_FEATURE_CRYPTO__nlink_t_defined __BIG_ENDIAN 4321DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)_POSIX_UIO_MAXIOV 16R300_NEW_WAIT_3D_3D_CLEAN 0x6_POSIX_PRIORITY_SCHEDULING 200809Lhtole64(x) __uint64_identity (x)S_IXGRP (S_IXUSR >> 3)DRM_RADEON_GETPARAM 0x11ENOLINK 67DRM_PLANE_TYPE_CURSOR 2_PC_MAX_INPUT _PC_MAX_INPUT__stub_setlogin DRM_IOCTL_MODE_DESTROYPROPBLOB DRM_IOWR(0xBE, struct drm_mode_destroy_blob)__INT_LEAST64_TYPE__ long int__isalnum_l(c,l) __isctype_l((c), _ISalnum, (l))_CS_POSIX_V6_ILP32_OFF32_CFLAGS _CS_POSIX_V6_ILP32_OFF32_CFLAGSAMDGPU_VM_PAGE_EXECUTABLE (1 << 3)DRM_SYNCOBJ_QUERY_FLAGS_LAST_SUBMITTED (1 << 0)isprint_l(c,l) __isprint_l ((c), (l))F_SETFL 4__glibc_c99_flexarr_available 1S_IROTH (S_IRGRP >> 3)__INT8_C(c) c__toascii_l(c,l) ((l), __toascii (c))GBM_BO_IMPORT_FD_PLANAR 0x5504__FLT64_DECIMAL_DIG__ 17UTIME_NOW ((1l << 30) - 1l)DRM_RADEON_CP_INIT 0x00strncmpDRM_ERR_NO_ACCESS (-1002)DRM_MAX_ORDER 22RADEON_CS_USE_VM 0x02_XOPEN_XCU_VERSION 4__FLT_EVAL_METHOD_C99____S_ISUID 04000AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9_CS_POSIX_V6_LPBIG_OFFBIG_CFLAGS _CS_POSIX_V6_LPBIG_OFFBIG_CFLAGSR300_CMD_R500FP 9DRM_MODE_FLAG_BCAST (1<<10)IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT)_CS_XBS5_LP64_OFF64_LIBS _CS_XBS5_LP64_OFF64_LIBS__FLT32_HAS_QUIET_NAN__ 1INT32_MAX (2147483647)__bitwise __bitwise__SYNC_FILE_RANGE_WRITE 2RADEON_CMD_PACKET3_CLIP 6__SIG_ATOMIC_TYPE__ intAMDGPU_INFO_VIDEO_CAPS 0x21R200_EMIT_PP_CUBIC_FACES_1 63R200_EMIT_PP_TXFILTER_3 39__SIZEOF_FLOAT__ 4F_SHLCK 8le16toh(x) __uint16_identity (x)EUCLEAN 117freeAMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)DRM_RADEON_INIT_HEAP 0x15AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12)_drmUsbDeviceInfo__SSIZE_T_TYPE __SWORD_TYPE_CS_XBS5_LPBIG_OFFBIG_CFLAGS _CS_XBS5_LPBIG_OFFBIG_CFLAGSPUBLIC __attribute__((visibility("default")))DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip)_IO_USER_LOCK 0x8000RADEON_MAX_SURFACES 8__STDC_ISO_10646__ 201706L_XOPEN_XPG4 1SIZE_WIDTH __WORDSIZE_SC_XOPEN_ENH_I18N _SC_XOPEN_ENH_I18NF_GETPIPE_SZ 1032_BSD_SIZE_T_DEFINED_ CLEAR_Y1 1DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8<<14)DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx)RADEON_INFO_ACTIVE_CU_COUNT 0x20DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map)__DEC64_MANT_DIG__ 16connector_type_idAMDGPU_INFO_VIDEO_CAPS_DECODE 0__FLT16_MAX_EXP__ 16GBM_FORMAT_ARGB4444 __gbm_fourcc_code('A', 'R', '1', '2')R200_EMIT_RE_SCISSOR_TL_0 54drmModeConnection__FLT16_HAS_INFINITY__ 1__glibc_likely(cond) __builtin_expect ((cond), 1)FALLOC_FL_UNSHARE_RANGE 0x40_DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)EL2HLT 51_XOPEN_SOURCE 700__S_IEXEC 0100isascii_l(c,l) __isascii_l ((c), (l))_ISpunct_CS_LFS64_LIBS _CS_LFS64_LIBS__TIME_T_TYPE __SLONGWORD_TYPEvirtual_address_offsetDRM_MODE_CURSOR_MOVE 0x02DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)__UINT_FAST64_TYPE__ long unsigned intDRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4ESOCKTNOSUPPORT 94DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0)F_GETFL 3CLEAR_X2 2DRM_MODE_TYPE_PREFERRED (1<<3)__GCC_ATOMIC_LONG_LOCK_FREE 2__BIGGEST_ALIGNMENT__ 16_POSIX_OPEN_MAX 20ispunct(c) __isctype((c), _ISpunct)_GETOPT_CORE_H 1_CS_POSIX_V7_LP64_OFF64_LIBS _CS_POSIX_V7_LP64_OFF64_LIBS__ASM_GENERIC_BITS_PER_LONG DN_ACCESS 0x00000001DRM_MODE_SCALE_ASPECT 3__HAVE_FLOAT32 1drmHost1xDeviceInfoPtr_GCC_PTRDIFF_T S_IRWXG (S_IRWXU >> 3)R200_EMIT_PP_CUBIC_OFFSETS_1 64DT_LNK DT_LNKR300_CMD_END3D 4__f32(x) x ##f32__INT_FAST64_MAX__ 0x7fffffffffffffffLRADEON_USE_COMP_ZBUF 0x20000000DRM_IOCTL_SYNCOBJ_TRANSFER DRM_IOWR(0xCC, struct drm_syncobj_transfer)__LDBL_MIN_EXP__ (-16381)UINT32_WIDTH 32__F_GETOWN 9__DEC128_MAX_EXP__ 6145__BITS_PER_LONG 64ispunct_l(c,l) __ispunct_l ((c), (l))AMDGPU_FAMILY_RV 142DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property)DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0)__stub_sigreturn STDIN_FILENO 0_CS_POSIX_V6_LP64_OFF64_LINTFLAGS _CS_POSIX_V6_LP64_OFF64_LINTFLAGS_SC_V6_ILP32_OFF32 _SC_V6_ILP32_OFF32DRM_MODE_PICTURE_ASPECT_256_135 4__INT_FAST64_WIDTH__ 64_IO_wide_dataNR_OPEN 1024__FD_MASK(d) ((__fd_mask) (1UL << ((d) % __NFDBITS)))ESTALE 116AMDGPU_GEM_USERPTR_READONLY (1 << 0)_POSIX_THREAD_ROBUST_PRIO_PROTECT -1RADEON_BACK 0x2DRM_MODE_SCALE_FULLSCREEN 1AMDGPU_INFO_TIMESTAMP 0x05R200_EMIT_PP_CUBIC_FACES_2 65_ISlower__mode_t_defined DRM_IOCTL_CRTC_QUEUE_SEQUENCE DRM_IOWR(0x3c, struct drm_crtc_queue_sequence)_POSIX_ASYNCHRONOUS_IO 200809LAMDGPU_IB_FLAGS_SECURE (1 << 5)DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique)DRM_RADEON_GEM_CREATE 0x1d__U16_TYPE unsigned short intDRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap)__S_IFDIR 0040000__timeval_defined 1vtotal_POSIX_CHOWN_RESTRICTED 0_SC_IOV_MAX _SC_IOV_MAXAMDGPU_HW_IP_VCN_ENC 7drmHost1xBusInfoPtr_SC_THREAD_CPUTIME _SC_THREAD_CPUTIMEEREMOTE 66__CHAR32_TYPE__ unsigned intGBM_FORMAT_ARGB1555 __gbm_fourcc_code('A', 'R', '1', '5')RADEON_UPLOAD_TCL 0x00000080__DEC128_EPSILON__ 1E-33DL__UINT16_TYPE__ short unsigned intAMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4)__FLT_MIN_EXP__ (-125)__UINT_LEAST64_TYPE__ long unsigned intDRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)AMDGPU_VRAM_TYPE_GDDR4 4R200_EMIT_PP_TXCTLALL_5 93RADEON_GEM_USERPTR_VALIDATE (1 << 2)AT_SYMLINK_FOLLOW 0x400O_APPEND 02000__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1__S_TYPEISSEM(buf) ((buf)->st_mode - (buf)->st_mode)R200_EMIT_RE_POINTSIZE 59__SYSCALL_SLONG_TYPE __SLONGWORD_TYPEEAFNOSUPPORT 97__INT_LEAST8_WIDTH__ 8_POSIX_RE_DUP_MAX 255__USECONDS_T_TYPE __U32_TYPESEEK_CUR 1__USE_XOPEN_EXTENDED 1DRM_CONTROL_MINOR_NAME "controlD"date_lenGBM_FORMAT_XBGR8888 __gbm_fourcc_code('X', 'B', '2', '4')__GNU_LIBRARY__ 6AMDGPU_INFO_FW_SMC 0x0aDRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close)_old_offset__USE_UNIX98__wur EDESTADDRREQ 89__field64__ARM_FEATURE_UNALIGNED 1AMDGPU_TILING_ARRAY_MODE_SHIFT 0EBFONT 59DRM_MODE_CONTENT_PROTECTION_DESIRED 1FOPEN_MAX 16RADEON_SETPARAM_SWITCH_TILING 2_POSIX_MAX_INPUT 255_POSIX_SEM_NSEMS_MAX 256__INO_T_TYPE __ULONGWORD_TYPEDRM_RADEON_INFO 0x27__FLT16_MAX__ 6.55040000000000000000000000000000000e+4F16EXIT_SUCCESS 0_DRM_H_ INT_LEAST8_MIN (-128)AMDGPU_IDS_FLAGS_PREEMPTION 0x2__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____ARM_ALIGN_MAX_STACK_PWR 16RADEON_SETPARAM_PCIGART_LOCATION 3htotal_ISbit(bit) ((bit) < 8 ? ((1 << (bit)) << 8) : ((1 << (bit)) >> 8))EWOULDBLOCK EAGAINF_SETSIG __F_SETSIGDRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding)__FD_SETSIZE 1024_POSIX_NO_TRUNC 1ENAMETOOLONG 36DRM_AMDGPU_GEM_OP 0x10O_RSYNC O_SYNC__GLIBC_INTERNAL_STARTING_HEADER_IMPLEMENTATION DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite)__STDC__ 1_SC_THREAD_KEYS_MAX _SC_THREAD_KEYS_MAX_POSIX_SYNCHRONIZED_IO 200809LEBADF 9__ARM_FEATURE_IDIV 1AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)_ISOC11_SOURCE 1DRM_MODE_FLAG_ALL (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLSCAN | DRM_MODE_FLAG_CSYNC | DRM_MODE_FLAG_PCSYNC | DRM_MODE_FLAG_NCSYNC | DRM_MODE_FLAG_HSKEW | DRM_MODE_FLAG_DBLCLK | DRM_MODE_FLAG_CLKDIV2 | DRM_MODE_FLAG_3D_MASK)_CS_GNU_LIBPTHREAD_VERSION _CS_GNU_LIBPTHREAD_VERSIONprim_buf_gpu_addrGBM_FORMAT_BGR565 __gbm_fourcc_code('B', 'G', '1', '6')DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)gs_prim_buffer_depthR200_EMIT_OUTPUT_VTX_COMP_SEL 49le32toh(x) __uint32_identity (x)ETIMEDOUT 110DRM_MODE_FLAG_3D_FRAME_PACKING (1<<14)devsDRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx)F_SETLK64 6__STRICT_ANSI__ 1DRM_MODE_CONNECTOR_Composite 5MQ_PRIO_MAX 32768_MKNOD_VER_LINUX 0alloca(size) __builtin_alloca (size)DRM_AMDGPU_FENCE_TO_HANDLE 0x14num_shader_arrays_per_engineS_IWOTH (S_IWGRP >> 3)__FLT16_MIN_10_EXP__ (-4)__SLONGWORD_TYPE long int__INO64_T_TYPE __UQUAD_TYPER200_EMIT_PP_CUBIC_OFFSETS_5 72RADEON_CARD_AGP 1_SC_V6_LP64_OFF64 _SC_V6_LP64_OFF64__BLKSIZE_T_TYPE __S32_TYPERADEON_EMIT_RE_LINE_PATTERN 3DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0_ENDIAN_H 1_SC_MB_LEN_MAX _SC_MB_LEN_MAX__isupper_l(c,l) __isctype_l((c), _ISupper, (l))__GNUC_STDC_INLINE__ 1DRM_RADEON_GEM_PREAD 0x21_PC_SYNC_IO _PC_SYNC_IO_POSIX_THREAD_KEYS_MAX 128__ASMNAME(cname) __ASMNAME2 (__USER_LABEL_PREFIX__, cname)__SIZEOF_LONG_LONG__ 8__PTHREAD_MUTEX_LOCK_ELISION 0ESRMNT 69AMDGPU_VM_MTYPE_RW (5 << 5)fwrite_unlocked(ptr,size,n,stream) (__extension__ ((__builtin_constant_p (size) && __builtin_constant_p (n) && (size_t) (size) * (size_t) (n) <= 8 && (size_t) (size) != 0) ? ({ const char *__ptr = (const char *) (ptr); FILE *__stream = (stream); size_t __cnt; for (__cnt = (size_t) (size) * (size_t) (n); __cnt > 0; --__cnt) if (putc_unlocked (*__ptr++, __stream) == EOF) break; ((size_t) (size) * (size_t) (n) - __cnt) / (size_t) (size); }) : (((__builtin_constant_p (size) && (size_t) (size) == 0) || (__builtin_constant_p (n) && (size_t) (n) == 0)) ? ((void) (ptr), (void) (stream), (void) (size), (void) (n), (size_t) 0) : fwrite_unlocked (ptr, size, n, stream))))DRM_RADEON_CP_RESUME 0x18O_NONBLOCK 04000_SC_V7_LP64_OFF64 _SC_V7_LP64_OFF64__USE_ATFILEAMDGPU_CTX_OP_QUERY_STATE2 4_unused2__stub_stty _SC_V7_LPBIG_OFFBIG _SC_V7_LPBIG_OFFBIG_SC_XBS5_ILP32_OFFBIG _SC_XBS5_ILP32_OFFBIG_GETOPT_POSIX_H 1__USE_GNU 1drmCommandWriteRead_XOPEN_SOURCEENOBUFS 105DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy)IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)_POSIX_AIO_LISTIO_MAX 2__WORDSIZE_TIME64_COMPAT32 0_BITS_TYPES_LOCALE_T_H 1AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2)__WCOREFLAG 0x80__FLT64_MIN_EXP__ (-1021)DRM_IOCTL_MODE_CREATE_LEASE DRM_IOWR(0xC6, struct drm_mode_create_lease)__USER_LABEL_PREFIX__ ENODEV 19__GNUC_MINOR__ 3__undef_OPEN_MAXDRM_MODE_PRESENT_BOTTOM_FIELD (1<<1)DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client)__ARM_BIG_ENDIANAMDGPU_TILING_TILE_SPLIT_MASK 0x7__FLT64X_HAS_INFINITY__ 1EMFILE 24R300_WAIT_3D_CLEAN 0x4dri_node_sizeBIG_ENDIAN __BIG_ENDIANCIK_TILE_MODE_DEPTH_STENCIL_1D 5EHOSTDOWN 112DRM_IOC_READWRITE _IOC_READ|_IOC_WRITERADEON_UPLOAD_TEX2 0x00000800DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd)DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version)desc_len__WINT_WIDTH__ 32__need_NULLgbm_create_devicegbm_detect_device_info_pathDRM_AMDGPU_WAIT_FENCES 0x12drm_amdgpu_info_device_POSIX_THREAD_DESTRUCTOR_ITERATIONS 4__linux__ 1_POSIX_SHELL 1__has_include(STR) __has_include__(STR)islower_l(c,l) __islower_l ((c), (l))_IOLBF 1__WCOREDUMP(status) ((status) & __WCOREFLAG)__FLT64X_MAX__ 1.18973149535723176508575932662800702e+4932F64xAMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)AMDGPU_INFO_NUM_EVICTIONS 0x18_POSIX_PATH_MAX 256DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2)RADEON_TILING_EG_TILE_SPLIT_MASK 0xfS_ISGID __S_ISGIDAMDGPU_GEM_DOMAIN_GWS 0x10__GLIBC_USE_LIB_EXT2__S_IFIFO 0010000RADEON_INFO_CRTC_FROM_ID 0x04__FLT_HAS_QUIET_NAN__ 1INT32_MIN (-2147483647-1)AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1Eprogram_invocation_name__HAVE_DISTINCT_FLOAT64X 0RADEON_TRIANGLE_FAN 0x5S_IRWXO (S_IRWXG >> 3)PDP_ENDIAN __PDP_ENDIAN__ENUM_IDTYPE_T 1video_capSSIZE_MAX LONG_MAXRADEON_VM_PAGE_SYSTEM (1 << 3)RADEON_REQUIRE_QUIESCENCE 0x00010000__S_IFLNK 0120000__INT64_C(c) c ## LDRM_IOCTL_BASE 'd'GBM_MAX_PLANES 4SPLICE_F_NONBLOCK 2SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3__FLT64X_MIN__ 3.36210314311209350626267781732175260e-4932F64x_POSIX_TYPED_MEMORY_OBJECTS -1_SC_SHARED_MEMORY_OBJECTS _SC_SHARED_MEMORY_OBJECTS__SIZEOF_PTHREAD_BARRIERATTR_T 8__UINT64_TYPE__ long unsigned intAMDGPU_FAMILY_CI 120ECONNREFUSED 111RADEON_UPLOAD_VERTFMT 0x00000002GBM_FORMAT_ABGR2101010 __gbm_fourcc_code('A', 'B', '3', '0')__DBL_MAX_10_EXP__ 308DRM_BUS_HOST1X 3RADEON_SETPARAM_FB_LOCATION 1__SIZE_MAX__ 0xffffffffffffffffULR200_EMIT_TCL_POINT_SPRITE_CNTL 77R200_EMIT_PP_TXOFFSET_2 44AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f__stub_fattach __S_TYPEISSHM(buf) ((buf)->st_mode - (buf)->st_mode)__ARM_FEATURE_SHA512/workingRADEON_PARAM_GART_BUFFER_OFFSET 1__feof_unlocked_body(_fp) (((_fp)->_flags & _IO_EOF_SEEN) != 0)__CFLOAT32 _Complex _Float32wave_front_sizeDRM_AMDGPU_GEM_USERPTR 0x11GBM_DEV_TYPE_FLAG_3D (1u << 2)DRM_MODE_FEATURE_DIRTYFB 1SEEK_SET 0_SC_PRIORITY_SCHEDULING _SC_PRIORITY_SCHEDULING_SC_AIO_PRIO_DELTA_MAX _SC_AIO_PRIO_DELTA_MAXENETUNREACH 101_CS_V7_ENV _CS_V7_ENV__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1__DEC64_MIN_EXP__ (-382)SEM_VALUE_MAX (2147483647)__O_DIRECTORY 040000AMDGPU_IDS_FLAGS_FUSION 0x1AMDGPU_GEM_METADATA_OP_SET_METADATA 1__FLT128_MAX_10_EXP__ 4932readdir__RLIM_T_TYPE __ULONGWORD_TYPEEFAULT 14__aligned_be64 __be64 __attribute__((aligned(8)))iscntrl_l(c,l) __iscntrl_l ((c), (l))UINT8_WIDTH 8RADEON_VA_MAP 1_DRM_VBLANK_HIGH_CRTC_SHIFT 1__S_IFMT 0170000RADEON_LOCAL_TEX_HEAP 0__GID_T_TYPE __U32_TYPERADEON_TRIANGLE_STRIP 0x6RADEON_GEM_NO_BACKING_STORE (1 << 0)RADEON_CHUNK_ID_CONST_IB 0x04DRM_MODE_FLAG_PIC_AR_64_27 (DRM_MODE_PICTURE_ASPECT_64_27<<19)DRM_MODE_FLAG_PIXMUX (1<<11)param_buf_gpu_addrisalnum(c) __isctype((c), _ISalnum)AMDGPU_INFO_SENSOR_GPU_TEMP 0x3__REDIRECT_NTH_LDBL(name,proto,alias) __REDIRECT_NTH (name, proto, alias)AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)_SC_LEVEL3_CACHE_ASSOC _SC_LEVEL3_CACHE_ASSOC_IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0)EIO 5__FD_SET(d,s) ((void) (__FDS_BITS (s)[__FD_ELT(d)] |= __FD_MASK(d)))RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19RADEON_EMIT_PP_CNTL 1__ino64_tS_IWUSR __S_IWRITEAMDGPU_HW_IP_VCN_JPEG 8EL3RST 47DRM_MODE_CONNECTOR_DSI 16DRM_CONNECTOR_NAME_LEN 32_IO_lock_tDRM_MODE_FLAG_PIC_AR_NONE (DRM_MODE_PICTURE_ASPECT_NONE<<19)EDEADLOCK EDEADLKRADEON_PARAM_DEVICE_ID 16_BITS_UINTN_IDENTITY_H 1W_OK 2LOCK_SH 1__ARM_FP16_FORMAT_IEEE 1DRM_PLANE_TYPE_OVERLAY 0be32toh(x) __bswap_32 (x)RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83_SC_MESSAGE_PASSING _SC_MESSAGE_PASSING__FLT64_HAS_DENORM__ 1AMDGPU_IB_FLAG_CE (1<<0)DRM_MODE_PAGE_FLIP_EVENT 0x01_SC_NL_SETMAX _SC_NL_SETMAX__useconds_t_defined _SC_NETWORKING _SC_NETWORKINGRADEON_UPLOAD_CONTEXT_ALL 0x003e01ffDRM_MODE_DIRTY_OFF 0IS_ALIGNED(A,B) (ALIGN((A), (B)) == (A))UINT_FAST32_MAX (18446744073709551615UL)__FLT64_MIN_10_EXP__ (-307)__W_EXITCODE(ret,sig) ((ret) << 8 | (sig))__OFF64_T_TYPE __SQUAD_TYPEAMDGPU_CTX_OP_GET_STABLE_PSTATE 5__extern_always_inline extern __always_inline __attribute__ ((__gnu_inline__))out_fd_POSIX_FSYNC 200809LRADEON_PARAM_STATUS_HANDLE 8INT_LEAST32_MAX (2147483647)GBM_FORMAT_XRGB2101010 __gbm_fourcc_code('X', 'R', '3', '0')vram_type__S_IFCHR 0020000_POSIX_C_SOURCE_IOC_NRBITS 8UINT32_MAX (4294967295U)DRM_IOCTL_CRTC_GET_SEQUENCE DRM_IOWR(0x3b, struct drm_crtc_get_sequence)__ARM_FEATURE_SHA2__ARM_FEATURE_SHA3__bswap_constant_32(x) ((((x) & 0xff000000u) >> 24) | (((x) & 0x00ff0000u) >> 8) | (((x) & 0x0000ff00u) << 8) | (((x) & 0x000000ffu) << 24))_SC_SYSTEM_DATABASE_R _SC_SYSTEM_DATABASE_RGBM_FORMAT_XBGR2101010 __gbm_fourcc_code('X', 'B', '3', '0')__uint8_t__DBL_MAX__ ((double)1.79769313486231570814527423731704357e+308L)__S_IREAD 0400WCHAR_MIN __WCHAR_MINtoupper(c) __tobody (c, toupper, *__ctype_toupper_loc (), (c))_SC_MEMLOCK _SC_MEMLOCK__POSIX_FADV_NOREUSE 5__GLIBC__ 2_SC_THREAD_ROBUST_PRIO_PROTECT _SC_THREAD_ROBUST_PRIO_PROTECTDRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL (4<<14)RADEON_SETPARAM_VBLANK_CRTC 6DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)_CS_POSIX_V7_LPBIG_OFFBIG_CFLAGS _CS_POSIX_V7_LPBIG_OFFBIG_CFLAGS__UINT8_C(c) c_POSIX2_C_BIND __POSIX2_THIS_VERSIONAMDGPU_TILING_GET(value,field) (((__u64)(value) >> AMDGPU_TILING_ ##field ##_SHIFT) & AMDGPU_TILING_ ##field ##_MASK)EMEDIUMTYPE 124__SIZEOF_PTHREAD_COND_T 48_STATBUF_ST_BLKSIZE drmGetVersion__INTMAX_C(c) c ## LDRM_NODE_NAME_MAX (sizeof(DRM_DIR_NAME) + 1 + MAX3(sizeof(DRM_PRIMARY_MINOR_NAME), sizeof(DRM_CONTROL_MINOR_NAME), sizeof(DRM_RENDER_MINOR_NAME)) + sizeof("144") + 1)AMDGPU_VRAM_TYPE_GDDR6 9__FLT64_MAX__ 1.79769313486231570814527423731704357e+308F64__USE_ISOC11 1__LDBL_DIG__ 33errno (*__errno_location ())AMDGPU_VRAM_TYPE_DDR3 7AMDGPU_INFO_SENSOR_VDDGFX 0x7AMDGPU_CHUNK_ID_DEPENDENCIES 0x03AMDGPU_VA_OP_UNMAP 2htobe16(x) __bswap_16 (x)DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)__blksize_t_defined R200_EMIT_PP_TXFILTER_2 38toascii_l(c,l) __toascii_l ((c), (l))ENOTNAM 118DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)AMDGPU_INFO_VBIOS_SIZE 0x1DRM_MODE_CONNECTOR_eDP 14DRM_SPINUNLOCK(spin,val) do { DRM_CAS_RESULT(__ret); if ((*spin).lock == val) { do { DRM_CAS(spin,val,0,__ret); } while (__ret); } } while(0)_SC_NZERO _SC_NZEROWCONTINUED 8_SC_MONOTONIC_CLOCK _SC_MONOTONIC_CLOCK__FD_CLR(d,s) ((void) (__FDS_BITS (s)[__FD_ELT(d)] &= ~__FD_MASK(d)))__SYSCALL_ULONG_TYPE __ULONGWORD_TYPE__GLIBC_INTERNAL_STARTING_HEADER_IMPLEMENTATION_LFS64_ASYNCHRONOUS_IO 1__SIZEOF_PTHREAD_CONDATTR_T 8__ptr_t void *__BEGIN_DECLS L_SET SEEK_SET__lldiv_t_defined 1O_ASYNC 020000AMDGPU_INFO_FW_UVD 0x2S_IFIFO __S_IFIFO__INT_WIDTH__ 32DRM_CAP_ADDFB2_MODIFIERS 0x10__GLIBC_MINOR__ 28drmUsbDeviceInfoPtrst_mtime st_mtim.tv_secF_GETSIG __F_GETSIGAMDGPU_INFO_MMR_SH_INDEX_MASK 0xff_POSIX_TIMERS 200809LWNOWAIT 0x01000000toascii(c) __toascii (c)RADEON_UPLOAD_LINE 0x00000004_POSIX_MAPPED_FILES 200809L__STDC_VERSION__ 199901L__USE_POSIX2 1__DBL_HAS_INFINITY__ 1__FLT_EVAL_METHOD_TS_18661_3__ 0__DEC64_SUBNORMAL_MIN__ 0.000000000000001E-383DD_CS_XBS5_LP64_OFF64_LINTFLAGS _CS_XBS5_LP64_OFF64_LINTFLAGS_PC_VDISABLE _PC_VDISABLE__ARM_SIZEOF_WCHAR_T 4DRM_MODE_CONNECTOR_DVIA 4DRM_IOCTL_MODE_LIST_LESSEES DRM_IOWR(0xC7, struct drm_mode_list_lessees)_SC_CPUTIME _SC_CPUTIMEAMDGPU_INFO_FW_TOC 0x15_SC_NL_TEXTMAX _SC_NL_TEXTMAX_SC_LEVEL4_CACHE_SIZE _SC_LEVEL4_CACHE_SIZEst_atime st_atim.tv_sec__SIG_ATOMIC_MAX__ 0x7fffffffDRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_PAGE_FLIP_ASYNC | DRM_MODE_PAGE_FLIP_TARGET)DRM_RADEON_RESET 0x05_SC_2_PBS_LOCATE _SC_2_PBS_LOCATE_IOC_NRSHIFT 0DRM_CLIENT_CAP_ASPECT_RATIO 4__stub_fdetach R200_EMIT_PP_TXCTLALL_1 89_SC_PIPE _SC_PIPEXATTR_LIST_MAX 65536AMDGPU_CHUNK_ID_FENCE 0x02SI_TILE_MODE_COLOR_1D 13_SC_THREAD_SPORADIC_SERVER _SC_THREAD_SPORADIC_SERVERAMDGPU_IDS_FLAGS_TMZ 0x4_SC_NL_MSGMAX _SC_NL_MSGMAXst_ctime st_ctim.tv_secle64toh(x) __uint64_identity (x)FALLOC_FL_INSERT_RANGE 0x20_XOPEN_ENH_I18N 1_SC_XOPEN_REALTIME _SC_XOPEN_REALTIMERADEON_TILING_SURFACE 0x10AMDGPU_INFO_FW_VCN 0x0e__WCHAR_MAX__ 0xffffffffUfd_node_num_IOFBF 0RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2INT16_MIN (-32767-1)_POSIX_NAME_MAX 14RADEON_FRONT 0x1drmModeSubPixel__HAVE_FLOAT16 0_drmHost1xDeviceInfoDRM_MODE_PICTURE_ASPECT_16_9 2_SC_XOPEN_LEGACY _SC_XOPEN_LEGACYDRM_RADEON_STIPPLE 0x0C__INT_FAST32_WIDTH__ 64__linux 1_SC_RE_DUP_MAX _SC_RE_DUP_MAXDRM_MODE_FLAG_PCSYNC (1<<7)DRM_ERR_NO_FD (-1005)POSIX_FADV_NOREUSE __POSIX_FADV_NOREUSEDRM_COMMAND_BASE 0x40__FLT32X_MANT_DIG__ 53DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)dir_entSI_TILE_MODE_COLOR_2D_64BPP 17_ATFILE_SOURCE 1__GCC_ATOMIC_SHORT_LOCK_FREE 2_IO_ERR_SEEN 0x0020__NLINK_T_TYPE __U32_TYPEDRM_IOCTL_RADEON_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_USERPTR, struct drm_radeon_gem_userptr)max_widthDRM_CRTC_SEQUENCE_NEXT_ON_MISS 0x00000002_SC_2_LOCALEDEF _SC_2_LOCALEDEFRADEON_EMIT_RB3D_STENCILREFMASK 7DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)__END_DECLS DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)FD_CLR(fd,fdsetp) __FD_CLR (fd, fdsetp)stdin stdinquery_hw_ipd_fileno d_ino__errno_location_GCC_WCHAR_T __SIZEOF_INT128__ 16FALLOC_FL_PUNCH_HOLE 0x02_SC_V6_LPBIG_OFFBIG _SC_V6_LPBIG_OFFBIGAMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf_LINUX_LIMITS_H DT_DIR DT_DIR____FILE_defined 1mmWidthARRAY_SIZE(A) (sizeof(A) / sizeof(*(A)))__RLIM64_T_TYPE __UQUAD_TYPER300_CMD_PACKET3_RAW 1__has_include_next(STR) __has_include_next__(STR)_POSIX_SSIZE_MAX 32767RADEON_EMIT_RE_MISC 11__INTPTR_TYPE__ long intDRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)__INT_LEAST32_WIDTH__ 32_SC_PII_OSI_COTS _SC_PII_OSI_COTSdrmModeModeInfoPtr_CS_XBS5_LP64_OFF64_CFLAGS _CS_XBS5_LP64_OFF64_CFLAGS__USE_XOPEN2KXSI 1F_EXLCK 4__DEC32_MANT_DIG__ 7DRM_MODE_FB_MODIFIERS (1<<1)__u_intN_t(N,MODE) typedef unsigned int u_int ##N ##_t __attribute__ ((__mode__ (MODE)))DRM_ERR_NO_DEVICE (-1001)__bswap_constant_64(x) ((((x) & 0xff00000000000000ull) >> 56) | (((x) & 0x00ff000000000000ull) >> 40) | (((x) & 0x0000ff0000000000ull) >> 24) | (((x) & 0x000000ff00000000ull) >> 8) | (((x) & 0x00000000ff000000ull) << 8) | (((x) & 0x0000000000ff0000ull) << 24) | (((x) & 0x000000000000ff00ull) << 40) | (((x) & 0x00000000000000ffull) << 56))__O_NOATIME 01000000__PDP_ENDIAN 3412ids_flagsRADEON_UPLOAD_MASKS 0x00000010RADEON_VA_RESULT_OK 0__FLT32X_EPSILON__ 2.22044604925031308084726333618164062e-16F32xstrdupa(s) (__extension__ ({ const char *__old = (s); size_t __len = strlen (__old) + 1; char *__new = (char *) __builtin_alloca (__len); (char *) memcpy (__new, __old, __len); }))DRM_MODE_DISCONNECTED___int_ptrdiff_t_h R300_WAIT_3D 0x2__FD_ISSET(d,s) ((__FDS_BITS (s)[__FD_ELT (d)] & __FD_MASK (d)) != 0)UINTPTR_WIDTH __WORDSIZER200_EMIT_PP_CUBIC_OFFSETS_4 70__FLT64_MAX_10_EXP__ 308_T_PTRDIFF_ __INT_WCHAR_T_H _POSIX_CLOCKRES_MIN 20000000DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)EILSEQ 84RADEON_PARAM_LAST_CLEAR 4_SC_LEVEL1_DCACHE_ASSOC _SC_LEVEL1_DCACHE_ASSOC_SYS_CDEFS_H 1_IO_EOF_SEEN 0x0010__SIZEOF_DOUBLE__ 8_CS_XBS5_ILP32_OFFBIG_LIBS _CS_XBS5_ILP32_OFFBIG_LIBSEISDIR 21DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3<<14)GBM_FORMAT_ABGR4444 __gbm_fourcc_code('A', 'B', '1', '2')ENOTSOCK 88_IO_backup_baseDRM_RADEON_ALLOC 0x13R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35_POSIX_TIMEOUTS 200809L__UINT_LEAST8_TYPE__ unsigned char__HAVE_DISTINCT_FLOAT32X 0___int_size_t_h AMDGPU_INFO_SENSOR_GFX_SCLK 0x1ESTRPIPE 86UINT_LEAST16_MAX (65535)__PTHREAD_RWLOCK_ELISION_EXTRA 0_SC_PII_INTERNET_DGRAM _SC_PII_INTERNET_DGRAM__FLT64_EPSILON__ 2.22044604925031308084726333618164062e-16F64_SC_FILE_SYSTEM _SC_FILE_SYSTEMEOPNOTSUPP 95RWF_WRITE_LIFE_NOT_SET 0R200_EMIT_PP_CUBIC_FACES_5 71DRM_NODE_PRIMARY 0__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1EEXIST 17DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode)RADEON_TILING_EG_BANKH_MASK 0xf_CS_POSIX_V6_ILP32_OFF32_LDFLAGS _CS_POSIX_V6_ILP32_OFF32_LDFLAGS_FALLOC_H_ __FLT64X_DENORM_MIN__ 6.47517511943802511092443895822764655e-4966F64x_IOC_NONE 0U_CS_POSIX_V5_WIDTH_RESTRICTED_ENVS _CS_V5_WIDTH_RESTRICTED_ENVS_SC_PII_OSI _SC_PII_OSI_modebe64toh(x) __bswap_64 (x)RADEON_INFO_CURRENT_GPU_TEMP 0x21__FLT_HAS_INFINITY__ 1_DRM_MODE_H RADEON_EMIT_PP_TEX_SIZE_1 74__undef_LINK_MAXEAGAIN 11__INT_FAST16_TYPE__ long int_POSIX_PIPE_BUF 512DT_REG DT_REG_sys_errlistDRM_IOC_WRITE _IOC_WRITEDT_WHT DT_WHTDRM_DEVICE_GET_PCI_REVISION (1 << 0)AMDGPU_INFO_VCE_CLOCK_TABLE 0x1AEADDRINUSE 98RADEON_INFO_FUSION_GART_WORKING 0x0cAMDGPU_TILING_BANK_WIDTH_MASK 0x3_CS_POSIX_V7_LP64_OFF64_CFLAGS _CS_POSIX_V7_LP64_OFF64_CFLAGSconnector_typeDRM_RADEON_INDIRECT 0x0D_ISprint__FLT32_MIN_10_EXP__ (-37)DRM_RADEON_GEM_VA 0x2bDRM_MODE_DPMS_STANDBY 1SIG_ATOMIC_MAX (2147483647)GBM_FORMAT_BGRX1010102 __gbm_fourcc_code('B', 'X', '3', '0')AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11)__FLT64X_MIN_10_EXP__ (-4931)GBM_FORMAT_VYUY __gbm_fourcc_code('V', 'Y', 'U', 'Y')_drmUsbBusInfo__SIZEOF_LONG__ 8AT_STATX_SYNC_TYPE 0x6000RADEON_CLEAR_FASTZ 0x80000000__O_PATH 010000000_CS_XBS5_ILP32_OFFBIG_LDFLAGS _CS_XBS5_ILP32_OFFBIG_LDFLAGS_SC_2_PBS _SC_2_PBSGBM_BO_IMPORT_FD_MODIFIER 0x5505_PC_PATH_MAX _PC_PATH_MAXoptoptDRM_EVENT_FLIP_COMPLETE 0x02vsync_endDRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free)__WCHAR_MAX __WCHAR_MAX____FLT_DIG__ 6RADEON_CMD_SCALARS 2__ferror_unlocked_body(_fp) (((_fp)->_flags & _IO_ERR_SEEN) != 0)__FLT64X_EPSILON__ 1.92592994438723585305597794258492732e-34F64xnum_cu_per_sh__UINT_LEAST32_MAX__ 0xffffffffUAMDGPU_INFO_DEV_INFO 0x16AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0GBM_BO_IMPORT_WL_BUFFER 0x5501GBM_FORMAT_XBGR4444 __gbm_fourcc_code('X', 'B', '1', '2')__ILP32___IO_read_end__ARM_FEATURE_FMA 1S_IFCHR __S_IFCHR_XOPEN_REALTIME_THREADS 1DRM_RADEON_GEM_WAIT_IDLE 0x24AMDGPU_INFO_HW_IP_COUNT 0x03snprintfRADEON_MAX_TEXTURE_UNITS 3__WSTOPSIG(status) __WEXITSTATUS(status)R200_EMIT_VTX_FMT_0 31DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)_SC_V7_ILP32_OFFBIG _SC_V7_ILP32_OFFBIGAMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44__LDBL_MAX_EXP__ 16384_SIZE_T_DEFINED _POSIX_SEM_VALUE_MAX 32767EBADRQC 56ELIBACC 79S_IFREG __S_IFREG_IO_save_baseEMSGSIZE 90__HAVE_FLOAT32X 1RADEON_GEM_GTT_WC (1 << 2)__FLT32X_MAX_EXP__ 1024ENOEXEC 8AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw)__INT16_C(c) c_SC_LEVEL3_CACHE_LINESIZE _SC_LEVEL3_CACHE_LINESIZE__INT_LEAST8_MAX__ 0x7f__bswap_constant_16(x) ((__uint16_t) ((((x) >> 8) & 0xff) | (((x) & 0xff) << 8)))_WCHAR_T_DEFINED __FSWORD_T_TYPE __SWORD_TYPE__stub_gtty RADEON_PARAM_SAREA_HANDLE 9DRM_CLIENT_CAP_UNIVERSAL_PLANES 2__ULONG32_TYPE unsigned int__SWORD_TYPE long int__USE_ISOC11AMDGPU_FAMILY_VGH 144GBM_FORMAT_RGBA4444 __gbm_fourcc_code('R', 'A', '1', '2')tcc_disabled_mask__GNU_LIBRARY__DRM_MODE_FLAG_PVSYNC (1<<2)__TIMER_T_TYPE void *mmHeightreturn_pointerDRM_CLOEXEC O_CLOEXEC_SC_LEVEL4_CACHE_LINESIZE _SC_LEVEL4_CACHE_LINESIZE_IO_write_endnum_rb_pipes_SC_NL_ARGMAX _SC_NL_ARGMAX_POSIX_TIMER_MAX 32DRM_MODE_OBJECT_ANY 0__INT_LEAST8_TYPE__ signed charAMDGPU_VCE_CLOCK_TABLE_ENTRIES 6AT_STATX_DONT_SYNC 0x4000RADEON_INFO_TIMESTAMP 0x11RADEON_INFO_MAX_SCLK 0x1a_SC_2_FORT_DEV _SC_2_FORT_DEV__FP_FAST_FMAF64 1DRM_MODE_ATOMIC_ALLOW_MODESET 0x0400RADEON_NR_SAREA_CLIPRECTS 12DRM_MODE_CONNECTOR_VIRTUAL 15ERESTART 85DRM_MODE_ROTATE_0 (1<<0)__PTRDIFF_T S_IXUSR __S_IEXECAMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3)RADEON_SCRATCH_REG_OFFSET 32__FLT16_MAX_10_EXP__ 4RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK 0xfreadlinkDRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats)GBM_FORMAT_YVU420 __gbm_fourcc_code('Y', 'V', '1', '2')DRM_PRIMARY_MINOR_NAME "card"__FLT64X_MANT_DIG__ 113F_NOTIFY 1026__SIZEOF_PTHREAD_MUTEX_T 48RADEON_EMIT_PP_TXFILTER_0 12__DEC64_MAX_EXP__ 385DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)__ASMNAME2(prefix,cname) __STRING (prefix) cnameAMDGPU_GEM_DOMAIN_OA 0x20__stub_sstk _SC_RTSIG_MAX _SC_RTSIG_MAX__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__bitwise__ __UWORD_TYPE unsigned long int_SC_SIGNALS _SC_SIGNALS__FLT32X_DECIMAL_DIG__ 17__FLT128_DECIMAL_DIG__ 36__ino64_t_defined _IO_buf_baseAMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT)DRM_IOCTL_SET_CLIENT_CAP DRM_IOW( 0x0d, struct drm_set_client_cap)_SC_2_PBS_CHECKPOINT _SC_2_PBS_CHECKPOINTDRM_AMDGPU_GEM_MMAP 0x01__INT_MAX__ 0x7fffffffESHUTDOWN 108WCHAR_MAX __WCHAR_MAX_SC_TRACE _SC_TRACEDRM_ERR_INVALID (-1004)DRM_RADEON_TEXTURE 0x0ERADEON_EMIT_PP_CUBIC_FACES_2 82__uint16_t_SC_TTY_NAME_MAX _SC_TTY_NAME_MAXDRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)__stub___compat_get_kernel_syms R200_EMIT_PP_TXFILTER_0 36__islower_l(c,l) __isctype_l((c), _ISlower, (l))_SC_XOPEN_SHM _SC_XOPEN_SHM_SC_NL_NMAX _SC_NL_NMAXR200_EMIT_VAP_CTL 32F_SEAL_SHRINK 0x0002_SC_XOPEN_XPG2 _SC_XOPEN_XPG2INTPTR_MAX (9223372036854775807L)AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6)_SC_SYNCHRONIZED_IO _SC_SYNCHRONIZED_IO__FLT64_DENORM_MIN__ 4.94065645841246544176568792868221372e-324F64drmModeResPtr__LDBL_HAS_INFINITY__ 1_SC_TRACE_SYS_MAX _SC_TRACE_SYS_MAXdrmModeGetResources__SIZEOF_SHORT__ 2__ssize_t_defined DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb)count_crtcs__NFDBITS (8 * (int) sizeof (__fd_mask))EOWNERDEAD 130__INTMAX_TYPE__ long intINT_LEAST16_MAX (32767)_POSIX_V7_ILP32_OFF32 -1__UINT_FAST32_TYPE__ long unsigned int_LFS64_LARGEFILE 1RADEON_GEM_DOMAIN_CPU 0x1O_NOATIME __O_NOATIMEGBM_FORMAT_GR88 __gbm_fourcc_code('G', 'R', '8', '8')RADEON_LINES 0x2isalpha(c) __isctype((c), _ISalpha)DRM_MODE_SUBPIXEL_HORIZONTAL_RGB_SC_XOPEN_XPG4 _SC_XOPEN_XPG4R200_EMIT_PP_TXCBLEND_5 26_SC_PASS_MAX _SC_PASS_MAXisascii(c) __isascii (c)_PC_REC_MAX_XFER_SIZE _PC_REC_MAX_XFER_SIZE__FLT_MIN_10_EXP__ (-37)DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)DRM_MODE_FLAG_CLKDIV2 (1<<13)AMDGPU_VM_MTYPE_WC (2 << 5)_POSIX_CPUTIME 0F_SETLKW64 7__REDIRECT_LDBL(name,proto,alias) __REDIRECT (name, proto, alias)_POSIX_NGROUPS_MAX 8__attribute_alloc_size__(params) __attribute__ ((__alloc_size__ params))__u_char_defined drmModeConnectorPtr__PTHREAD_COMPAT_PADDING_END __stub_lchmod AMDGPU_INFO_VBIOS_INFO 0x3F_DUPFD 0__glibc_clang_prereq(maj,min) 0__isspace_l(c,l) __isctype_l((c), _ISspace, (l))gs_vgt_table_depthDRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)DN_MODIFY 0x00000002__isctype_l(c,type,locale) ((locale)->__ctype_b[(int) (c)] & (unsigned short int) type)DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle)INT8_MIN (-128)_drmDevice__stub___compat_uselib _SC_FSYNC _SC_FSYNCWNOHANG 1PTRDIFF_MAX (9223372036854775807L)__nonnull(params) __attribute__ ((__nonnull__ params))__error_t_defined 1DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather)AMDGPU_CHUNK_ID_BO_HANDLES 0x06__need_size_t__PTRDIFF_MAX__ 0x7fffffffffffffffL__FLT64_HAS_QUIET_NAN__ 1__USE_ISOC99 1__FLT16_HAS_QUIET_NAN__ 1DRM_MODE_FLAG_HSKEW (1<<9)RADEON_TILING_EG_TILE_SPLIT_SHIFT 24DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc)__ARM_FP_FAST_IO_marker__FLT128_DIG__ 33GBM_FORMAT_YUYV __gbm_fourcc_code('Y', 'U', 'Y', 'V')WIFCONTINUED(status) __WIFCONTINUED (status)WUNTRACED 2__WINT_TYPE__ unsigned intRADEON_UPLOAD_TEX1 0x00000400__FLT32_HAS_DENORM__ 1R500FP_CONSTANT_CLAMP (1 << 2)__UINT32_C(c) c ## U_BITS_STDINT_INTN_H 1DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct drm_mode_create_blob)__ARM_FEATURE_SVE_BITSDRM_RADEON_CMDBUF 0x10GBM_FORMAT_RGBX1010102 __gbm_fourcc_code('R', 'X', '3', '0')__SIZEOF_WINT_T__ 4__USE_XOPEN 1__USE_POSIX2SIZE_MAX (18446744073709551615UL)DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)__UINT_FAST16_TYPE__ long unsigned int_GNU_SOURCE 1GBM_FORMAT_RGB888 __gbm_fourcc_code('R', 'G', '2', '4')fullnameRADEON_PARAM_LAST_DISPATCH 3__FLT32X_HAS_QUIET_NAN__ 1DRM_DEV_NAME "%s/" DRM_PRIMARY_MINOR_NAME "%d"min_heightDRM_AMDGPU_BO_LIST 0x03virtual_address_alignmentDRM_MODE_FLAG_3D_L_DEPTH (5<<14)DRM_RADEON_INDICES 0x0A__SCHAR_MAX__ 0x7f__GCC_ATOMIC_INT_LOCK_FREE 2__LEAF , __leaf____CHAR16_TYPE__ short unsigned intAMDGPU_INFO_FW_VCE 0x1DRM_MODE_ATOMIC_TEST_ONLY 0x0100_SC_MEMORY_PROTECTION _SC_MEMORY_PROTECTION_STRINGS_H 1R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60__UINT16_MAX__ 0xffffGBM_FORMAT_NV12 __gbm_fourcc_code('N', 'V', '1', '2')DRM_MODE_FB_DIRTY_MAX_CLIPS 256_BITS_TYPESIZES_H 1__UINTMAX_MAX__ 0xffffffffffffffffUL__FLT64X_MAX_EXP__ 16384__FLT32X_MIN_EXP__ (-1021)__FLT64X_HAS_DENORM__ 1RWH_WRITE_LIFE_SHORT 2businfoGBM_FORMAT_YVU444 __gbm_fourcc_code('Y', 'V', '2', '4')R200_EMIT_PP_AFS_1 86DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info)DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res)__always_inline_SC_PAGE_SIZE _SC_PAGESIZE_BITS_POSIX_OPT_H 1_IO_read_ptr__USE_ISOC95vram_bit_widthtolower_l(c,locale) __tolower_l ((c), (locale))__USE_ISOC99isupper_l(c,l) __isupper_l ((c), (l))DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut)AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5DRM_MODE_ENCODER_DAC 1RENAME_NOREPLACE (1 << 0)__O_CLOEXEC 02000000__ino_t_defined RADEON_EMIT_PP_BORDER_COLOR_2 17AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9)isdigit_l(c,l) __isdigit_l ((c), (l))__FLT64_HAS_INFINITY__ 1ENODATA 61__FLT_EPSILON__ 1.19209289550781250000000000000000000e-7Fsubpixel__environDRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property)_SC_THREAD_ROBUST_PRIO_INHERIT _SC_THREAD_ROBUST_PRIO_INHERITGBM_FORMAT_XRGB4444 __gbm_fourcc_code('X', 'R', '1', '2')DRM_MODE_CONNECTOR_LVDS 7_IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(size)))_ISupper_flags2RADEON_INFO_GPU_RESET_COUNTER 0x26__HAVE_GENERIC_SELECTION 1_VA_LIST_DEFINED GBM_FORMAT_RGBA8888 __gbm_fourcc_code('R', 'A', '2', '4')GBM_FORMAT_YUV422 __gbm_fourcc_code('Y', 'U', '1', '6')rendernode_nameDRM_IOCTL_SYNCOBJ_FD_TO_HANDLE DRM_IOWR(0xC2, struct drm_syncobj_handle)INT_FAST64_MIN (-__INT64_C(9223372036854775807)-1)__INT8_TYPE__ signed char_SC_2_SW_DEV _SC_2_SW_DEVisgraph_l(c,l) __isgraph_l ((c), (l))_DIRENT_HAVE_D_RECLEN RADEON_INFO_SI_TILE_MODE_ARRAY 0x16DRM_MODE_CONTENT_TYPE_CINEMA 3DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd)RADEON_INFO_VA_START 0x0e__warnattr(msg) __attribute__((__warning__ (msg)))DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather)__ldiv_t_defined 1bustype__SIZE_T__ be16toh(x) __bswap_16 (x)R300_CMD_PACKET0 1RADEON_WAIT_2D 0x1DRM_IOCTL_SYNCOBJ_CREATE DRM_IOWR(0xBF, struct drm_syncobj_create)_ASM_GENERIC_ERRNO_H __SIZE_TYPE__ long unsigned intDRM_RADEON_CP_IDLE 0x04_SC_2_C_VERSION _SC_2_C_VERSION_SC_2_FORT_RUN _SC_2_FORT_RUN_SC_UINT_MAX _SC_UINT_MAXP_ALLR200_EMIT_PP_TRI_PERF_CNTL 84INTMAX_MIN (-__INT64_C(9223372036854775807)-1)_POSIX_SIGQUEUE_MAX 32_POSIX_THREAD_ROBUST_PRIO_INHERIT 200809LWTERMSIG(status) __WTERMSIG (status)GBM_FORMAT_YUV410 __gbm_fourcc_code('Y', 'U', 'V', '9')__INT_LEAST16_MAX__ 0x7fffparam_buf_size__DEC128_MANT_DIG__ 34ENOSTR 60RADEON_PARAM_SCRATCH_OFFSET 11DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0)DELAYTIMER_MAX 2147483647AMDGPU_CHUNK_ID_IB 0x01__always_inline __inline__RADEON_CARD_PCI 0__HAVE_FLOAT64X __HAVE_FLOAT128DRM_RADEON_GEM_GET_TILING 0x29AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3_SC_ADVISORY_INFO _SC_ADVISORY_INFO_CS_POSIX_V6_ILP32_OFFBIG_LIBS _CS_POSIX_V6_ILP32_OFFBIG_LIBSUINTMAX_WIDTH 64__FLT_DENORM_MIN__ 1.40129846432481707092372958328991613e-45FAMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7)__F_SETOWN 8DRM_RENDER_MINOR_NAME "renderD"DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique)drmUsbBusInfoPtr__USE_FILE_OFFSET64 1_SC_SHELL _SC_SHELL__FLT16_DECIMAL_DIG__ 5EALREADY 114DRM_RDWR O_RDWRGBM_BO_IMPORT_EGL_IMAGE 0x5502RADEON_EMIT_PP_CUBIC_FACES_1 80_POSIX_THREADS 200809LRADEON_TRIANGLES 0x4DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)R200_EMIT_VTE_CNTL 48_BSD_WCHAR_T_DRM_RADEON_SWAP 0x07UTIL_H EINTR 4R200_EMIT_PP_TXCTLALL_4 92DRM_RADEON_FLIP 0x12EBADFD 77AMDGPU_GEM_DOMAIN_GDS 0x8__DBL_HAS_QUIET_NAN__ 1AMDGPU_CTX_PRIORITY_NORMAL 0__SHRT_MAX__ 0x7fffRADEON_EMIT_SE_CNTL 9WIFEXITED(status) __WIFEXITED (status)RADEON_INFO_CURRENT_GPU_MCLK 0x23_SC_CHILD_MAX _SC_CHILD_MAXAMDGPU_GEM_METADATA_OP_GET_METADATA 2__GLIBC_USE_IEC_60559_FUNCS_EXTR300_CMD_CP_DELAY 5_IOC(dir,type,nr,size) (((dir) << _IOC_DIRSHIFT) | ((type) << _IOC_TYPESHIFT) | ((nr) << _IOC_NRSHIFT) | ((size) << _IOC_SIZESHIFT))_PC_NO_TRUNC _PC_NO_TRUNC_SC_GETGR_R_SIZE_MAX _SC_GETGR_R_SIZE_MAXDRM_DIR_NAME "/dev/dri"__LONG_LONG_WIDTH__ 64_SC_V6_ILP32_OFFBIG _SC_V6_ILP32_OFFBIG__UINT8_TYPE__ unsigned charAMDGPU_INFO_RAS_ENABLED_HDP (1 << 6)__STDIO_INLINE __extern_inline__HAVE_DISTINCT_FLOAT128X __HAVE_FLOAT128X_XBS5_ILP32_OFFBIG -1isxdigit(c) __isctype((c), _ISxdigit)MAXNAMLEN NAME_MAX__UINTPTR_TYPE__ long unsigned int_SC_LEVEL1_ICACHE_LINESIZE _SC_LEVEL1_ICACHE_LINESIZE__USE_ATFILE 1_POSIX_CHILD_MAX 25__UINT32_MAX__ 0xffffffffU_SC_INT_MIN _SC_INT_MINDRM_MODE_OBJECT_MODE 0xdededede_CS_POSIX_V6_LP64_OFF64_LDFLAGS _CS_POSIX_V6_LP64_OFF64_LDFLAGSFALLOC_FL_COLLAPSE_RANGE 0x08DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)isupper(c) __isctype((c), _ISupper)__FLT128_MAX__ 1.18973149535723176508575932662800702e+4932F128__WINT_MAX__ 0xffffffffU__ARM_FP16_ARGS 1_STATBUF_ST_RDEV R200_EMIT_PP_CUBIC_OFFSETS_0 62RADEON_EMIT_SE_ZBIAS_FACTOR 18AMDGPU_VM_MTYPE_UC (4 << 5)AMDGPU_CTX_GUILTY_RESET 1GBM_DETECT_FLAG_CONNECTED (1u << 0)__WNOTHREAD 0x20000000vscan__attribute_used__ __attribute__ ((__used__))DRM_MODE_CONNECTOR_SPI 19DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx)_BSD_SIZE_T_ ENOANO 55_POSIX_TRACE_INHERIT -1__OFF_T_TYPE __SLONGWORD_TYPE_drmModeModeInfoRADEON_CS_RING_COMPUTE 1__INT16_TYPE__ short intAMDGPU_CTX_UNKNOWN_RESET 3_SC_FIFO _SC_FIFODRM_IOC(dir,group,nr,size) _IOC(dir, group, nr, size)AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1__FD_ZERO(s) do { unsigned int __i; fd_set *__arr = (s); for (__i = 0; __i < sizeof (fd_set) / sizeof (__fd_mask); ++__i) __FDS_BITS (__arr)[__i] = 0; } while (0)AMDGPU_INFO_HW_IP_INFO 0x02GBM_FORMAT_BGR233 __gbm_fourcc_code('B', 'G', 'R', '8')__WINT_MIN__ 0UDRM_MODE_CONNECTEDDRM_MODE_FLAG_NCSYNC (1<<8)false 0_XOPEN_SOURCE_EXTENDED__USE_LARGEFILE__ARM_FP 14_STATBUF_ST_NSEC RADEON_INFO_VA_UNMAP_WORKING 0x25__LDBL_REDIR(name,proto) name proto_SC_BC_STRING_MAX _SC_BC_STRING_MAX__CFLOAT64X _Complex _Float64xR300_CMD_DMA_DISCARD 6AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05AMDGPU_INFO_FW_GFX_CE 0x06DRM_MODE_PROP_TYPE(n) ((n) << 6)_LARGEFILE64_SOURCE__STDIO_INLINESI_TILE_MODE_DEPTH_STENCIL_2D 0__WCLONE 0x80000000__INT32_MAX__ 0x7fffffffDRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP)__HAVE_DISTINCT_FLOAT128 0_IOC_TYPEBITS 8AMDGPU_FAMILY_AI 141DRM_AMDGPU_SCHED 0x15__FLT128_MIN__ 3.36210314311209350626267781732175260e-4932F128__STRING(x) #xR200_EMIT_PP_TXCBLEND_1 22__FLT_MAX__ 3.40282346638528859811704183484516925e+38F__INT_LEAST16_WIDTH__ 16__FLT32_MAX_10_EXP__ 38stderr stderrS_ISVTX __S_ISVTX_ISblankDRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl)drmFreeDevicesGBM_FORMAT_BGRX5551 __gbm_fourcc_code('B', 'X', '1', '5')_PC_LINK_MAX _PC_LINK_MAX__INT_FAST16_WIDTH__ 64RADEON_INFO_ACCEL_WORKING 0x03vendorDRM_MODE_FLAG_NHSYNC (1<<1)_SC_THREADS _SC_THREADSR300_NEW_WAIT_2D_3D 0x3DRM_MODE_OBJECT_BLOB 0xbbbbbbbb__fsblkcnt_t_defined GBM_BO_IMPORT_FD 0x5503_CS_POSIX_V6_LP64_OFF64_CFLAGS _CS_POSIX_V6_LP64_OFF64_CFLAGSoffsetof(TYPE,MEMBER) __builtin_offsetof (TYPE, MEMBER)__stub_chflags _Static_assert(expr,diagnostic) extern int (*__Static_assert_function (void)) [!!sizeof (struct { int __error_if_negative: (expr) ? 2 : -1; })]_PC_REC_INCR_XFER_SIZE _PC_REC_INCR_XFER_SIZE____sigset_t_defined DRM_MODE_CONTENT_PROTECTION_ENABLED 2_POSIX_TRACE -1__uint32_tE2BIG 7_SC_XOPEN_STREAMS _SC_XOPEN_STREAMSSTRINGIZE_NO_EXPANSION(x) #x__LDBL_MAX__ 1.18973149535723176508575932662800702e+4932L_CS_POSIX_V6_ILP32_OFF32_LIBS _CS_POSIX_V6_ILP32_OFF32_LIBSGBM_FORMAT_RGBA1010102 __gbm_fourcc_code('R', 'A', '3', '0')__GNUC_PATCHLEVEL__ 0ESRCH 3F_SETLK F_SETLK64__AARCH64_CMODEL_LARGE___POSIX_THREAD_SPORADIC_SERVER -1__iovec_defined 1_CS_LFS64_LDFLAGS _CS_LFS64_LDFLAGS_THREAD_SHARED_TYPES_H 1RADEON_VM_PAGE_READABLE (1 << 1)DRM_MODE_ENCODER_DPI 8__off64_t_defined __INT8_MAX__ 0x7fAMDGPU_VM_PAGE_PRT (1 << 4)R500FP_CONSTANT_TYPE (1 << 1)ENOMSG 42AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10)DRM_CAP_TIMESTAMP_MONOTONIC 0x6_SC_LEVEL2_CACHE_SIZE _SC_LEVEL2_CACHE_SIZE__off_t_defined __SIG_ATOMIC_WIDTH__ 32__USE_XOPEN2K 1GBM_FORMAT_YUV411 __gbm_fourcc_code('Y', 'U', '1', '1')_SC_LEVEL4_CACHE_ASSOC _SC_LEVEL4_CACHE_ASSOCRWH_WRITE_LIFE_NONE 1_ISalpha_CS_POSIX_V6_LP64_OFF64_LIBS _CS_POSIX_V6_LP64_OFF64_LIBSDRM_NODE_MAX 3_POSIX_MQ_OPEN_MAX 8DRM_COMMAND_END 0xA0__UINT_FAST32_MAX__ 0xffffffffffffffffULstrtolallocaDRM_IOCTL_SET_MASTER DRM_IO(0x1e)RADEON_INDEX_PRIM_OFFSET 20_IOC_READ 2UDRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block)DRM_MODE_ENCODER_DSI 6DRM_MODE_ENCODER_LVDS 3__LDBL_HAS_QUIET_NAN__ 1__UINTMAX_C(c) c ## UL_SC_LEVEL3_CACHE_SIZE _SC_LEVEL3_CACHE_SIZEdword_offsetRADEON_TILING_EG_BANKH_SHIFT 12AMDGPU_TILING_ARRAY_MODE_MASK 0xfDRM_MODE_SUBPIXEL_NONE__stub___compat_bdflush TMP_MAX 238328prop_valuesDRM_LOCK(fd,lock,context,flags) do { if (flags) drmGetLock(fd,context,flags); else DRM_LIGHT_LOCK(fd,lock,context); } while(0)radinfo_POSIX_IPV6 200809LdrmPlatformDeviceInfoPtr_CS_XBS5_ILP32_OFF32_LINTFLAGS _CS_XBS5_ILP32_OFF32_LINTFLAGS__FLT16_DENORM_MIN__ 5.96046447753906250000000000000000000e-8F16__HAVE_FLOAT128 1_PTRDIFF_T_DECLARED DRM_MODE_LINK_STATUS_BAD 1ECONNABORTED 103RADEON_UPLOAD_TEX2IMAGES 0x00004000_STRING_H 1EISNAM 120DRM_MODE_FLAG_CSYNC (1<<6)WCHAR_WIDTH 32_SC_TRACE_EVENT_NAME_MAX _SC_TRACE_EVENT_NAME_MAX__USE_POSIX199506 1_ISalnum_POSIX_ASYNC_IO 1_POSIX_SPORADIC_SERVER -1_IO_buf_end_SC_STREAM_MAX _SC_STREAM_MAXGBM_DEV_TYPE_FLAG_INTERNAL_LCD (1u << 6)R200_EMIT_PP_TXOFFSET_1 43DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)__PTHREAD_MUTEX_NUSERS_AFTER_KIND 0__stub_getmsg detect_flags__putc_unlocked_body(_ch,_fp) (__glibc_unlikely ((_fp)->_IO_write_ptr >= (_fp)->_IO_write_end) ? __overflow (_fp, (unsigned char) (_ch)) : (unsigned char) (*(_fp)->_IO_write_ptr++ = (_ch)))__FLT32_DIG__ 6__FLT32_MIN__ 1.17549435082228750796873653722224568e-38F32RADEON_INFO_WANT_CMASK 0x08AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3isblank_l(c,l) __isblank_l ((c), (l))_POSIX_MONOTONIC_CLOCK 0_CS_XBS5_LP64_OFF64_LDFLAGS _CS_XBS5_LP64_OFF64_LDFLAGSCLEAR_DEPTH 4_SC_DEVICE_SPECIFIC _SC_DEVICE_SPECIFICECHILD 10AMDGPU_INFO_NUM_HANDLES 0x1CL_tmpnam 20closedirLOCK_READ 64__LDBL_MANT_DIG__ 113ENETRESET 102DRM_PROP_NAME_LEN 32PIPE_BUF 4096num_tcc_blocks_BITS_WCHAR_H 1DRM_MODE_CONNECTOR_VGA 1FAPPEND O_APPEND_IScntrlDRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)_SC_ATEXIT_MAX _SC_ATEXIT_MAX_DIRENT_HAVE_D_TYPE AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11INT_LEAST8_MAX (127)__THROW __attribute__ ((__nothrow__ __LEAF))__attribute_nonstring__ __attribute__ ((__nonstring__))_IO_codecvttoupper_l(c,locale) __toupper_l ((c), (locale))RADEON_TILING_MACRO 0x1_CS_POSIX_V6_LPBIG_OFFBIG_LINTFLAGS _CS_POSIX_V6_LPBIG_OFFBIG_LINTFLAGS_XOPEN_SOURCE_EXTENDED 1RADEON_INFO_VRAM_USAGE 0x1edrmCommandWriteDRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)__FLT_MANT_DIG__ 24S_IFDIR __S_IFDIR__RLIM_T_MATCHES_RLIM64_T 1_IONBF 2__uid_t_defined DRM_MODE_PROP_ENUM (1<<3)__undef_NR_OPENAMDGPU_VRAM_TYPE_GDDR1 1__bos(ptr) __builtin_object_size (ptr, __USE_FORTIFY_LEVEL > 1)AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block)DRM_DEV_UID 0__W_CONTINUED 0xffffSYNC_FILE_RANGE_WAIT_BEFORE 1drm_amdgpu_infoAMDGPU_INFO_VRAM_GTT 0x14htobe64(x) __bswap_64 (x)_POSIX_MAX_CANON 255open64_DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)DRM_RADEON_FULLSCREEN 0x06__clock_t_defined 1RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf__FSID_T_TYPE struct { int __val[2]; }_DIRENT_HAVE_D_OFF _CS_POSIX_V6_LPBIG_OFFBIG_LDFLAGS _CS_POSIX_V6_LPBIG_OFFBIG_LDFLAGS_SC_LOGIN_NAME_MAX _SC_LOGIN_NAME_MAX_PC_MAX_CANON _PC_MAX_CANONAMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4F_OFD_SETLK 37RADEON_INFO_NUM_GB_PIPES 0x01RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81DRM_RADEON_IRQ_EMIT 0x16_POSIX_SEMAPHORES 200809LO_DSYNC __O_DSYNC__time_t_defined 1DRM_MODE_CONNECTOR_HDMIB 12O_RDONLY 00DRM_MODE_CONNECTOR_USB 20DRM_IOCTL_DROP_MASTER DRM_IO(0x1f)_SC_TRACE_EVENT_FILTER _SC_TRACE_EVENT_FILTERDRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties)_SC_SIGQUEUE_MAX _SC_SIGQUEUE_MAXmax_gs_waves_per_vgt__S_IFREG 0100000R300_CMD_WAIT 7_SC_LEVEL1_ICACHE_SIZE _SC_LEVEL1_ICACHE_SIZEfourcc_mod_get_vendor(modifier) (((modifier) >> 56) & 0xff)F_TLOCK 2__STDC_HOSTED__ 1AMDGPU_FAMILY_NV 143_POSIX_SOURCEGBM_FORMAT_XBGR1555 __gbm_fourcc_code('X', 'B', '1', '5')__struct_FILE_defined 1ARG_MAX 131072pos_buf_size_ASM_GENERIC_INT_LL64_H try_drm_devices__USE_XOPEN_EXTENDED_ALLOCA_H 1drmPlatformBusInfoPtrAMDGPU_INFO_VIS_VRAM_USAGE 0x17_SC_XOPEN_UNIX _SC_XOPEN_UNIXAMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10AMDGPU_VM_MTYPE_NC (1 << 5)RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)DRM_MODE_DITHERING_ON 1DRM_MODE_UNKNOWNCONNECTION__USE_POSIXAMDGPU_HW_IP_VCN_DEC 6__HAVE_FLOAT128_UNLIKE_LDBL (__HAVE_DISTINCT_FLOAT128 && __LDBL_MANT_DIG__ != 113)O_NDELAY O_NONBLOCKDRM_AMDGPU_GEM_WAIT_IDLE 0x07LOCK_UN 8EREMOTEIO 121minigbm_create_default_device_POSIX_V6_ILP32_OFFBIG -1_shortbufDRM_MODE_DITHERING_AUTO 2requestDRM_DEV_GID 0AMDGPU_VA_OP_MAP 1F_GETLK F_GETLK64DRM_MODE_SUBPIXEL_UNKNOWN__INT_FAST8_MAX__ 0x7f_DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))__ORDER_LITTLE_ENDIAN__ 1234_SC_WORD_BIT _SC_WORD_BIT__ctype_b_locINT16_MAX (32767)AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)DRM_MODE_CONTENT_TYPE_GAME 4AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)__DBL_DENORM_MIN__ ((double)4.94065645841246544176568792868221372e-324L)F_OFD_GETLK 36AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2)DRM_MODE_PICTURE_ASPECT_NONE 0R200_EMIT_MATRIX_SELECT_0 33FD_CLOEXEC 1__WALL 0x40000000_drmPciBusInfo__field64(type,type64,name) type64 nameX_OK 1_SC_CLOCK_SELECTION _SC_CLOCK_SELECTIONfloatECOMM 70_IOC_NRMASK ((1 << _IOC_NRBITS)-1)DRM_CAS(lock,old,new,ret) do { ret=1; } while (0)GBM_FORMAT_BGR888 __gbm_fourcc_code('B', 'G', '2', '4')AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0)__STD_TYPE typedef_SC_XBS5_LPBIG_OFFBIG _SC_XBS5_LPBIG_OFFBIG_SC_THREAD_PROCESS_SHARED _SC_THREAD_PROCESS_SHARED__FLT128_HAS_DENORM__ 1F_LOCK 1_SC_SINGLE_PROCESS _SC_SINGLE_PROCESS__USE_XOPEN2KDRM_IOCTL_SYNCOBJ_QUERY DRM_IOWR(0xCB, struct drm_syncobj_timeline_array)DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)DRM_MODE_OBJECT_CRTC 0xccccccccR200_EMIT_TCL_LIGHT_MODEL_CTL_0 29_SC_DELAYTIMER_MAX _SC_DELAYTIMER_MAXgbm_get_default_device_fd_SC_THREAD_PRIO_INHERIT _SC_THREAD_PRIO_INHERIT_SC_XOPEN_XCU_VERSION _SC_XOPEN_XCU_VERSIONDRM_RADEON_IRQ_WAIT 0x17DRM_RADEON_GEM_USERPTR 0x2dRADEON_TILING_MICRO_SQUARE 0x20_FEATURES_H 1DRM_IOCTL_SYNCOBJ_DESTROY DRM_IOWR(0xC0, struct drm_syncobj_destroy)_POSIX_PRIORITIZED_IO 200809L_SC_PII _SC_PII__key_t_defined __UINT_LEAST8_MAX__ 0xff__UINT_LEAST64_MAX__ 0xffffffffffffffffULAMDGPU_VM_DELAY_UPDATE (1 << 0)DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va)__FLT16_DIG__ 3__socklen_t_defined DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct drm_mode_get_lease)DRM_MODE_ENCODER_NONE 0F_OFD_SETLKW 38radeon_igp_idsDRM_MODE_PROP_BLOB (1<<4)drmGetDevices2__PIC__ 2GBM_FORMAT_NV61 __gbm_fourcc_code('N', 'V', '6', '1')RADEON_INFO_NUM_Z_PIPES 0x02DRM_MODE_FB_INTERLACED (1<<0)R200_EMIT_PP_TXCTLALL_0 88__DEC32_MIN__ 1E-95DF_SC_EXPR_NEST_MAX _SC_EXPR_NEST_MAXR200_EMIT_PP_TXFILTER_5 41DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)__WCHAR_MIN__ 0UDRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res)DRM_RADEON_GEM_MMAP 0x1eDRM_RADEON_VERTEX 0x09EBADE 52__UINT_LEAST32_TYPE__ unsigned int__GLIBC_USE_IEC_60559_TYPES_EXT 1return_sizeDRM_MODE_CONNECTOR_DVID 3available_nodesRADEON_LINE_STRIP 0x3__GXX_ABI_VERSION 1013DRM_MODE_DPMS_ON 0AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1)_XF86DRM_H_ ENAVAIL 119_ISOC11_SOURCE_IOC_DIRBITS 2UINT_FAST32_WIDTH __WORDSIZEAT_SYMLINK_NOFOLLOW 0x100R200_EMIT_RE_SCISSOR_TL_2 56DRM_MODE_LINK_STATUS_GOOD 0AMDGPU_INFO_SENSOR 0x1D__ARM_ARCH_8A 1count_props__FLT64X_MAX_10_EXP__ 4932_SC_USER_GROUPS_R _SC_USER_GROUPS_RRADEON_NR_TEX_REGIONS 64GBM_DEV_TYPE_FLAG_ARMSOC (1u << 3)RADEON_CMD_PACKET 1DRM_MODE_PICTURE_ASPECT_4_3 1ENOSR 63S_IRUSR __S_IREAD_ISgraph_BITS_STDIO_H 1_WCHAR_T_DECLARED ____mbstate_t_defined 1_SC_FILE_LOCKING _SC_FILE_LOCKING_ISOC95_SOURCE_POSIX_C_SOURCE 200809L_CS_V5_WIDTH_RESTRICTED_ENVS _CS_V5_WIDTH_RESTRICTED_ENVSDRM_MODE_REFLECT_X (1<<4)__GNUC_VA_LIST DN_RENAME 0x00000010DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut)__S_TYPEISMQ(buf) ((buf)->st_mode - (buf)->st_mode)F_GET_FILE_RW_HINT 1037DRM_IOC_VOID _IOC_NONE_SC_ASYNCHRONOUS_IO _SC_ASYNCHRONOUS_IO_ISOC95_SOURCE 1__DBL_MIN__ ((double)2.22507385850720138309023271733240406e-308L)RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09_BITS_STDINT_UINTN_H 1AMDGPU_FAMILY_KV 125__PRAGMA_REDEFINE_EXTNAME 1_SC_HOST_NAME_MAX _SC_HOST_NAME_MAXhsync_startfread_unlocked(ptr,size,n,stream) (__extension__ ((__builtin_constant_p (size) && __builtin_constant_p (n) && (size_t) (size) * (size_t) (n) <= 8 && (size_t) (size) != 0) ? ({ char *__ptr = (char *) (ptr); FILE *__stream = (stream); size_t __cnt; for (__cnt = (size_t) (size) * (size_t) (n); __cnt > 0; --__cnt) { int __c = getc_unlocked (__stream); if (__c == EOF) break; *__ptr++ = __c; } ((size_t) (size) * (size_t) (n) - __cnt) / (size_t) (size); }) : (((__builtin_constant_p (size) && (size_t) (size) == 0) || (__builtin_constant_p (n) && (size_t) (n) == 0)) ? ((void) (ptr), (void) (stream), (void) (size), (void) (n), (size_t) 0) : fread_unlocked (ptr, size, n, stream))))_SC_MULTI_PROCESS _SC_MULTI_PROCESS_BSD_PTRDIFF_T_ RWH_WRITE_LIFE_LONG 4RADEON_RELOC_PRIO_MASK (0xf << 0)__AARCH64_CMODEL_TINY___SC_PII_OSI_CLTS _SC_PII_OSI_CLTSL_cuserid 9_SC_PII_INTERNET _SC_PII_INTERNETR200_EMIT_PP_CUBIC_OFFSETS_3 68DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map)encoder_id__isblank_l(c,l) __isctype_l((c), _ISblank, (l))__SIZE_T _PC_2_SYMLINKS _PC_2_SYMLINKSENOLCK 37RADEON_CMD_VECTORS 3DRM_MODE_PICTURE_ASPECT_64_27 3AMDGPU_VRAM_TYPE_HBM 6MAX_HANDLE_SZ 128__REDIRECT_NTHNL(name,proto,alias) name proto __asm__ (__ASMNAME (#alias)) __THROWNLDRM_MODE_FLAG_DBLCLK (1<<12)_XBS5_LP64_OFF64 1__off_t__stub_fchflags DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN)_drmHost1xBusInfo_DIRENT_MATCHES_DIRENT64 1_POSIX_QLIMIT 1SPLICE_F_GIFT 8DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)INT64_MAX (__INT64_C(9223372036854775807))CLEAR_X1 0__USE_EXTERN_INLINES 1__AARCH64_CMODEL_SMALL__ 1R300_WAIT_2D_CLEAN 0x3__isxdigit_l(c,l) __isctype_l((c), _ISxdigit, (l))_POSIX_LOGIN_NAME_MAX 9R200_EMIT_PP_CUBIC_FACES_4 69RADEON_CMD_PACKET3 5_SC_2_UPE _SC_2_UPEDRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)dev_type_flags_IOC_SIZEBITS 14__O_DIRECT 0200000_SC_CHAR_MAX _SC_CHAR_MAXAMDGPU_VM_MTYPE_MASK (0xf << 5)_XOPEN_REALTIME 1_SC_AVPHYS_PAGES _SC_AVPHYS_PAGES__FLT128_DENORM_MIN__ 6.47517511943802511092443895822764655e-4966F128gbm_detect_device_info__USE_LARGEFILE 1__SIZEOF_LONG_DOUBLE__ 16drmModeGetConnectorDRM_MODE_OBJECT_PLANE 0xeeeeeeee__FLT_MAX_EXP__ 128INTMAX_MAX (__INT64_C(9223372036854775807))_CS_POSIX_V7_LP64_OFF64_LDFLAGS _CS_POSIX_V7_LP64_OFF64_LDFLAGSLITTLE_ENDIAN __LITTLE_ENDIAN__FLT16_MANT_DIG__ 11__FLT_RADIX__ 2doneva_end(v) __builtin_va_end(v)__INT_FAST16_MAX__ 0x7fffffffffffffffL__undef_OPEN_MAX DRM_AMDGPU_INFO 0x05DIV_ROUND_UP(n,d) (((n) + (d)-1) / (d))DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP)cntl_sb_buf_gpu_addr_POSIX_V7_ILP32_OFFBIG -1__always_inline __inline __attribute__ ((__always_inline__))AMDGPU_INFO_VRAM_USAGE 0x10DRM_MODE_ROTATE_180 (1<<2)__INTMAX_MAX__ 0x7fffffffffffffffL_POSIX2_CHAR_TERM 200809LDRM_RADEON_GEM_OP 0x2c__ULONGWORD_TYPE unsigned long int__kernel_old_uid_t __kernel_old_uid_tR600_SCRATCH_REG_OFFSET 256__FP_FAST_FMA 1__attribute_malloc__ __attribute__ ((__malloc__))_SC_LEVEL2_CACHE_LINESIZE _SC_LEVEL2_CACHE_LINESIZE__ATOMIC_CONSUME 1_POSIX_V6_LP64_OFF64 1_ASM_GENERIC_ERRNO_BASE_H _SC_SSIZE_MAX _SC_SSIZE_MAX_PC_REC_MIN_XFER_SIZE _PC_REC_MIN_XFER_SIZEAMDGPU_INFO_FW_GFX_MEC 0x08DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd)O_ACCMODE 0003_BITS_STDIO_LIM_H 1RADEON_UPLOAD_SETUP 0x00000040AMDGPU_INFO_FW_DMCU 0x12__BYTE_ORDER __LITTLE_ENDIAN_SC_LONG_BIT _SC_LONG_BITRAND_MAX 2147483647AMDGPU_INFO_FW_VERSION 0x0eDRM_MODE_CONTENT_TYPE_NO_DATA 0DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling)ALIGN(A,B) (((A) + (B)-1) & ~((B)-1))DRM_MODE_ENCODER_TMDS 2pos_buf_gpu_addrRADEON_VM_PAGE_SNOOPED (1 << 4)__BLKCNT64_T_TYPE __SQUAD_TYPEDRM_MODE_PROP_SIGNED_RANGE DRM_MODE_PROP_TYPE(2)_SC_LEVEL1_DCACHE_LINESIZE _SC_LEVEL1_DCACHE_LINESIZE__ATOMIC_ACQUIRE 2_XOPEN_LEGACY 1DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD DRM_IOWR(0xC1, struct drm_syncobj_handle)_POSIX_THREAD_ATTR_STACKSIZE 200809L__LDBL_MIN_10_EXP__ (-4931)__ATOMIC_ACQ_REL 4DRM_MODE_CONTENT_PROTECTION_UNDESIRED 0UTIME_OMIT ((1l << 30) - 2l)WEXITED 4POSIX_FADV_WILLNEED 3__FLT32_MAX__ 3.40282346638528859811704183484516925e+38F32DRM_MODE_SUBPIXEL_HORIZONTAL_BGR__tolower_l(c,locale) __tobody (c, __tolower_l, (locale)->__ctype_tolower, (c, locale))AMDGPU_INFO_FW_GFX_RLC 0x07AMDGPU_VRAM_TYPE_GDDR3 3_IOC_DIRMASK ((1 << _IOC_DIRBITS)-1)__BLKCNT_T_TYPE __SLONGWORD_TYPEDRM_MODE_FLAG_PIC_AR_16_9 (DRM_MODE_PICTURE_ASPECT_16_9<<19)ESPIPE 29DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc)valueDRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth)__KERNEL_STRICT_NAMEScount_encodersEMLINK 31AMDGPU_INFO_NUM_BYTES_MOVED 0x0fGBM_FORMAT_RGBA5551 __gbm_fourcc_code('R', 'A', '1', '5')__FLT32X_MAX_10_EXP__ 308__DEC32_MIN_EXP__ (-94)_SC_C_LANG_SUPPORT _SC_C_LANG_SUPPORTRADEON_EMIT_SE_CNTL_STATUS 10DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT DRM_IOWR(0xCA, struct drm_syncobj_timeline_wait)__POSIX2_THIS_VERSION 200809L__fortify_function __extern_always_inline __attribute_artificial__SI_TILE_MODE_COLOR_2D_8BPP 14__INT_FAST32_TYPE__ long intDRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int)__aligned_u64 __u64 __attribute__((aligned(8)))__f128(x) x ##f128_SC_TRACE_NAME_MAX _SC_TRACE_NAME_MAXGBM_FORMAT_AYUV __gbm_fourcc_code('A', 'Y', 'U', 'V')__DBL_MIN_EXP__ (-1021)INT_FAST16_MIN (-9223372036854775807L-1)__ATOMIC_SEQ_CST 5GBM_FORMAT_UYVY __gbm_fourcc_code('U', 'Y', 'V', 'Y')R200_EMIT_PP_TAM_DEBUG3 50IOC_OUT (_IOC_READ << _IOC_DIRSHIFT)DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)__GLIBC_USE_DEPRECATED_GETS 0STRINGIZE(x) STRINGIZE_NO_EXPANSION(x)FASYNC O_ASYNC__va_arg_pack_len() __builtin_va_arg_pack_len ()EADV 68AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f_POSIX_THREAD_PRIO_PROTECT 200809L__LONG_WIDTH__ 64P_PIDR200_EMIT_PP_TXCBLEND_4 25__FLT128_HAS_QUIET_NAN__ 1WSTOPSIG(status) __WSTOPSIG (status)DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc)version_majorfw_type_PC_SOCK_MAXBUF _PC_SOCK_MAXBUFDRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)RADEON_OFFSET_SHIFT 10hsync_end_T_SIZE _DEFAULT_SOURCEFD_ZERO(fdsetp) __FD_ZERO (fdsetp)AMDGPU_INFO_FW_GFX_PFP 0x05DT_UNKNOWN DT_UNKNOWNDRM_MODE_PAGE_FLIP_TARGET_RELATIVE 0x8__blkcnt_t_defined GBM_FORMAT_ABGR8888 __gbm_fourcc_code('A', 'B', '2', '4')F_GETLEASE 1025__ARM_FEATURE_QRDMXR200_EMIT_PP_TXOFFSET_5 47__INT_LEAST32_MAX__ 0x7fffffff_PC_CHOWN_RESTRICTED _PC_CHOWN_RESTRICTEDSI_TILE_MODE_COLOR_2D_32BPP 16__WCHAR_WIDTH__ 32IFTODT(mode) (((mode) & 0170000) >> 12)RADEON_INFO_MAX_PIPES 0x10RADEON_PARAM_LAST_FRAME 2_CS_POSIX_V7_WIDTH_RESTRICTED_ENVS _CS_V7_WIDTH_RESTRICTED_ENVSRADEON_CMD_DMA_DISCARD 4host1xGBM_DEV_TYPE_FLAG_DISPLAY (1u << 1)AMDGPU_CTX_NO_RESET 0DRM_RADEON_GEM_INFO 0x1cDRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)__O_TMPFILE (020000000 | __O_DIRECTORY)AMDGPU_INFO_FW_TA 0x13ENOMEM 12DN_CREATE 0x00000004__UINTPTR_MAX__ 0xffffffffffffffffUL__OPEN_NEEDS_MODE(oflag) (((oflag) & O_CREAT) != 0 || ((oflag) & __O_TMPFILE) == __O_TMPFILE)AT_STATX_FORCE_SYNC 0x2000_SC_STREAMS _SC_STREAMSDRM_HOST1X_DEVICE_NAME_LEN 512DRM_CAP_DUMB_PREFER_SHADOW 0x4__SIZEOF_PTRDIFF_T__ 8RADEON_INFO_RING_WORKING 0x15DRM_CLIENT_CAP_ATOMIC 3__S16_TYPE short intAMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07_SC_NGROUPS_MAX _SC_NGROUPS_MAX_T_PTRDIFF _IOC_TYPECHECK(t) (sizeof(t))INT_FAST32_MIN (-9223372036854775807L-1)mode_crtc_SIZE_T_DECLARED RADEON_GEM_USERPTR_REGISTER (1 << 3)_CS_LFS64_LINTFLAGS _CS_LFS64_LINTFLAGS_POSIX_MEMORY_PROTECTION 200809L_POSIX2_LOCALEDEF __POSIX2_THIS_VERSION__size_t__ _CS_XBS5_ILP32_OFFBIG_CFLAGS _CS_XBS5_ILP32_OFFBIG_CFLAGSDRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)__FLT64_DIG__ 15_CS_LFS_LDFLAGS _CS_LFS_LDFLAGSstdout stdout_STDINT_H 1BYTE_ORDER __BYTE_ORDER_D_EXACT_NAMLEN(d) (strlen ((d)->d_name))__ARM_ARCH_ISA_A64 1RADEON_PARAM_REGISTER_HANDLE 7F_ULOCK 0__AARCH64EL__ 1S_IFMT __S_IFMTDRM_MODE_PROP_RANGE (1<<1)opterr_SC_MQ_OPEN_MAX _SC_MQ_OPEN_MAXS_IFSOCK __S_IFSOCK_SC_THREAD_THREADS_MAX _SC_THREAD_THREADS_MAXDRM_MODE_CONNECTOR_DisplayPort 10EMULTIHOP 72RADEON_UPLOAD_BUMPMAP 0x00000008O_RDWR 02F_SETOWN_EX __F_SETOWN_EXXATTR_NAME_MAX 255__DBL_MANT_DIG__ 53LOCK_MAND 32__UINT_FAST64_MAX__ 0xffffffffffffffffULR200_EMIT_PP_TXOFFSET_4 46DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle)AMDGPU_INFO_SENSOR_GFX_MCLK 0x2FALLOC_FL_ZERO_RANGE 0x10__ispunct_l(c,l) __isctype_l((c), _ISpunct, (l))S_IRWXU (__S_IREAD|__S_IWRITE|__S_IEXEC)GBM_FORMAT_RGB332 __gbm_fourcc_code('R', 'G', 'B', '8')F_SET_FILE_RW_HINT 1038max_memory_clockDRM_NODE_CONTROL 1SPLICE_F_MOVE 1DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer)__UINT_LEAST16_MAX__ 0xffff_ANSI_STDDEF_H GBM_FORMAT_ABGR1555 __gbm_fourcc_code('A', 'B', '1', '5')deviceinfoRADEON_VA_RESULT_VA_EXIST 2_toupper(c) ((int) (*__ctype_toupper_loc ())[(int) (c)])__FLT_EVAL_METHOD_C99__ 0_SC_ULONG_MAX _SC_ULONG_MAXAMDGPU_GEM_USERPTR_REGISTER (1 << 3)_SC_SCHAR_MAX _SC_SCHAR_MAX_IO_save_end_CS_XBS5_ILP32_OFFBIG_LINTFLAGS _CS_XBS5_ILP32_OFFBIG_LINTFLAGSAMDGPU_CTX_STABLE_PSTATE_STANDARD 1RADEON_INFO_SI_CP_DMA_COMPUTE 0x17FNDELAY O_NDELAYUINT64_WIDTH 64GBM_FORMAT_YVYU __gbm_fourcc_code('Y', 'V', 'Y', 'U')_SC_CHARCLASS_NAME_MAX _SC_CHARCLASS_NAME_MAX__isascii_l(c,l) ((l), __isascii (c))O_PATH __O_PATH__CFLOAT128 _Complex _Float128DRM_PLANE_TYPE_PRIMARY 1SIG_ATOMIC_WIDTH 32isxdigit_l(c,l) __isxdigit_l ((c), (l))DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control)virtual_address_max__DEV_T_TYPE __UQUAD_TYPE__PTRDIFF_WIDTH__ 64_CS_XBS5_LPBIG_OFFBIG_LIBS _CS_XBS5_LPBIG_OFFBIG_LIBS__INT_FAST64_TYPE__ long intAIO_PRIO_DELTA_MAX 20__HAVE_FLOATN_NOT_TYPEDEF 1_SC_AIO_LISTIO_MAX _SC_AIO_LISTIO_MAXDRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6<<14)__ARM_NEON 1_SC_SAVED_IDS _SC_SAVED_IDSAMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)optarg__FLT32X_HAS_INFINITY__ 1__attribute_deprecated__ __attribute__ ((__deprecated__))AMDGPU_HW_IP_UVD 3EPROTONOSUPPORT 93DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2<<14)_ISOC99_SOURCE__FLT32_EPSILON__ 1.19209289550781250000000000000000000e-7F32isspace_l(c,l) __isspace_l ((c), (l))__flexarr []__FP_FAST_FMAF 1DRM_RADEON_CLEAR 0x08__INT32_TYPE__ intR_OK 4_STRUCT_TIMESPEC 1_STAT_VER_LINUX 0RADEON_INFO_NUM_TILE_PIPES 0x0bRADEON_CS_RING_UVD 3RADEON_GEM_OP_SET_INITIAL_DOMAIN 1DRM_DISPLAY_MODE_LEN 32_SC_AIO_MAX _SC_AIO_MAX__have_pthread_attr_t 1DRM_MODE_FLAG_3D_NONE (0<<14)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2_XF86DRMMODE_H_ DRM_RADEON_SURF_ALLOC 0x1adri_node_numR200_EMIT_PP_TXFILTER_1 37DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)ENOTCONN 107gbm_device_info__UINT8_MAX__ 0xffDRM_MODE_CURSOR_FLAGS 0x03__ATOMIC_RELAXED 0__DBL_HAS_DENORM__ 1__FLT64X_MIN_EXP__ (-16381)_SC_LEVEL2_CACHE_ASSOC _SC_LEVEL2_CACHE_ASSOC__S_ISVTX 01000__MODE_T_TYPE __U32_TYPERADEON_INFO_SI_BACKEND_ENABLED_MASK 0x19__FLT128_HAS_INFINITY__ 1version_patchlevel_SC_MQ_PRIO_MAX _SC_MQ_PRIO_MAXplatformS_IXOTH (S_IXGRP >> 3)AMDGPU_INFO_FW_GMC 0x03__F_SETSIG 10__bool_true_false_are_defined 1__GBM__ 1ENOSPC 28_CS_POSIX_V6_ILP32_OFF32_LINTFLAGS _CS_POSIX_V6_ILP32_OFF32_LINTFLAGSrevision_id_SC_ARG_MAX _SC_ARG_MAXENOTTY 25DRM_MODE_ROTATE_270 (1<<3)GBM_FORMAT_ARGB8888 __gbm_fourcc_code('A', 'R', '2', '4')_DRM_LOCK_CONT 0x40000000U_SYS_SELECT_H 1__ASM_POSIX_TYPES_H _BSD_WCHAR_T_ DRM_PLATFORM_DEVICE_NAME_LEN 512SIG_ATOMIC_MIN (-2147483647-1)DRM_EVENT_CONTEXT_VERSION 4SI_TILE_MODE_COLOR_LINEAR_ALIGNED 8AMDGPU_GEM_DOMAIN_VRAM 0x4__FLT_MIN__ 1.17549435082228750796873653722224568e-38F_SC_2_C_BIND _SC_2_C_BINDETIME 62_pad1AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0_POSIX_VDISABLE '\0'DRM_CAP_PRIME 0x5AMDGPU_CTX_PRIORITY_LOW -512RADEON_UPLOAD_TEX0 0x00000200__STD_TYPEUINT_FAST64_WIDTH 64gbm_device__SIZEOF_PTHREAD_ATTR_T 64DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)R300_CMD_VPU 2DRM_AMDGPU_GEM_CREATE 0x00R200_EMIT_PP_AFS_0 85bool _Bool__INT_FAST8_TYPE__ signed char_CS_GNU_LIBC_VERSION _CS_GNU_LIBC_VERSIONRADEON_VM_PAGE_VALID (1 << 0)STDERR_FILENO 2DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res)__ARM_FEATURE_SM3__ARM_FEATURE_SM4_DRM_POST_MODESET 2EOVERFLOW 75_IO_read_base_CS_POSIX_V7_ILP32_OFFBIG_LINTFLAGS _CS_POSIX_V7_ILP32_OFFBIG_LINTFLAGSDRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info)RADEON_EMIT_PP_BORDER_COLOR_1 15_POSIX_RAW_SOCKETS 200809LEPIPE 32_SC_EQUIV_CLASS_MAX _SC_EQUIV_CLASS_MAXRADEON_EMIT_PP_MISC 0AMDGPU_BO_LIST_OP_UPDATE 2__UINT32_TYPE__ unsigned intAMDGPU_FAMILY_CZ 135__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)DRM_MODE_PROP_OBJECT DRM_MODE_PROP_TYPE(1)__FLT_HAS_DENORM__ 1_STDDEF_H_ AMDGPU_VM_OP_UNRESERVE_VMID 2DRM_MODE_TYPE_ALL (DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_USERDEF | DRM_MODE_TYPE_DRIVER)__FLT16_EPSILON__ 9.76562500000000000000000000000000000e-4F16RADEON_INFO_NUM_BYTES_MOVED 0x1dAMDGPU_INFO_VBIOS 0x1B__GLIBC_USE_IEC_60559_TYPES_EXTfd_path_IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1)__ARM_ARCH 8_WCHAR_T_DEFINED_ pa_sc_tile_steering_overrideENOMEDIUM 123RADEON_LOG_TEX_GRANULARITY 16DRM_IOCTL_SYNCOBJ_WAIT DRM_IOWR(0xC3, struct drm_syncobj_wait)DN_ATTRIB 0x00000020_POSIX_THREAD_SAFE_FUNCTIONS 200809LRADEON_INFO_ACCEL_WORKING2 0x05_CS_XBS5_LPBIG_OFFBIG_LINTFLAGS _CS_XBS5_LPBIG_OFFBIG_LINTFLAGSDRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map)RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28GBM_DEV_TYPE_FLAG_USB (1u << 4)AMDGPU_VM_MTYPE_DEFAULT (0 << 5)__USE_XOPEN2K8XSIDRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer)max_heightEISCONN 106_SC_BC_BASE_MAX _SC_BC_BASE_MAX_SC_THREAD_PRIORITY_SCHEDULING _SC_THREAD_PRIORITY_SCHEDULING__DEC32_SUBNORMAL_MIN__ 0.000001E-95DF_IO_write_ptr_VA_LIST_T_H DRM_NODE_RENDER 2ce_ram_sizeDRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc)UINT_LEAST16_WIDTH 16AMDGPU_VRAM_TYPE_GDDR5 5DRM_MODE_TYPE_DRIVER (1<<6)UINT_LEAST64_WIDTH 64__LDBL_REDIR1(name,proto,alias) name proto__DEC128_MIN__ 1E-6143DL_SC_CLK_TCK _SC_CLK_TCK__toascii(c) ((c) & 0x7f)pte_fragment_size__SIZEOF_PTHREAD_RWLOCK_T 56__SIZEOF_PTHREAD_MUTEXATTR_T 8_POSIX_TTY_NAME_MAX 9_CS_POSIX_V6_ILP32_OFFBIG_LINTFLAGS _CS_POSIX_V6_ILP32_OFFBIG_LINTFLAGSAMDGPU_VRAM_TYPE_DDR2 2RADEON_INFO_TILING_CONFIG 0x06__SIZEOF_PTHREAD_RWLOCKATTR_T 8AMDGPU_CTX_STABLE_PSTATE_NONE 0DRM_MODE_FLAG_DBLSCAN (1<<5)R200_EMIT_SE_VTX_STATE_CNTL 58AMDGPU_VM_PAGE_READABLE (1 << 1)R200_EMIT_VAP_PVS_CNTL 94EFBIG 27_SC_OPEN_MAX _SC_OPEN_MAXRADEON_PARAM_CARD_TYPE 12R200_EMIT_PP_CUBIC_FACES_0 61__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__RADEON_EMIT_PP_CUBIC_FACES_0 78DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)DRM_MODE_PROP_PENDING (1<<0)AMDGPU_INFO_GTT_USAGE 0x11_ISxdigit__exctype(name) extern int name (int) __THROWUINT_FAST8_MAX (255)__CLOCKID_T_TYPE __S32_TYPE_POSIX_V7_LP64_OFF64 1_IOWR_BAD(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size))DRM_RADEON_VBLANK_CRTC2 2_UNISTD_H 1_POSIX_DELAYTIMER_MAX 32PTRDIFF_MIN (-9223372036854775807L-1)__LONG_LONG_PAIR(HI,LO) LO, HI__isascii(c) (((c) & ~0x7f) == 0)__ARM_FEATURE_CRC32_SIGSET_NWORDS (1024 / (8 * sizeof (unsigned long int)))_ASM_GENERIC_IOCTL_H AMDGPU_HW_IP_VCE 4DRM_MODE_ENCODER_TVDAC 4_sys_nerrRADEON_TILING_EG_BANKW_MASK 0xf_POSIX_REALTIME_SIGNALS 200809LRADEON_SETPARAM_PCIGART_TABLE_SIZE 5_SC_TYPED_MEMORY_OBJECTS _SC_TYPED_MEMORY_OBJECTSETXTBSY 26__FLT32_MIN_EXP__ (-125)EOF (-1)STDOUT_FILENO 1__FP_FAST_FMAF32x 1GBM_FORMAT_NV21 __gbm_fourcc_code('N', 'V', '2', '1')AMDGPU_CTX_OP_ALLOC_CTX 1_T_WCHAR_ DRM_MODE_PROP_IMMUTABLE (1<<2)_SC_GETPW_R_SIZE_MAX _SC_GETPW_R_SIZE_MAXRADEON_CS_RING_VCE 4ENFILE 23opendirDRM_IOCTL_SYNCOBJ_SIGNAL DRM_IOWR(0xC5, struct drm_syncobj_array)_SC_SELECT _SC_SELECTR200_EMIT_PP_TXCTLALL_3 91F_SETFD 2INT_LEAST32_MIN (-2147483647-1)__ARM_ARCH_PROFILE 65__stub_putmsg __INTPTR_WIDTH__ 64_SC_JOB_CONTROL _SC_JOB_CONTROL_ISOC99_SOURCE 1FALLOC_FL_NO_HIDE_STALE 0x04_POSIX_THREAD_CPUTIME 0_IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)hskewRADEON_INFO_IB_VM_MAX_SIZE 0x0fUINT_LEAST32_WIDTH 32name_lenvbios_infoINT_FAST64_MAX (__INT64_C(9223372036854775807))_DIRENT_HAVE_D_NAMLEN__UINT_FAST16_MAX__ 0xffffffffffffffffULAMDGPU_TILING_PIPE_CONFIG_SHIFT 4__W_STOPCODE(sig) ((sig) << 8 | 0x7f)__REDIRECT_NTH(name,proto,alias) name proto __asm__ (__ASMNAME (#alias)) __THROWENOTEMPTY 39__KERNEL_STRICT_NAMES INT_FAST16_MAX (9223372036854775807L)compatibleRADEON_GEM_OP_GET_INITIAL_DOMAIN 0_POSIX2_SW_DEV __POSIX2_THIS_VERSIONR300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8__P(args) argsRTSIG_MAX 32RADEON_EMIT_PP_TEX_SIZE_2 75_SC_LEVEL1_DCACHE_SIZE _SC_LEVEL1_DCACHE_SIZEDRM_RADEON_GEM_BUSY 0x2a_CS_V7_WIDTH_RESTRICTED_ENVS _CS_V7_WIDTH_RESTRICTED_ENVSAT_STATX_SYNC_AS_STAT 0x0000_markersRADEON_INFO_CURRENT_GPU_SCLK 0x22__FINITE_MATH_ONLY__ 0_filenoUINT_LEAST8_MAX (255)__UINTMAX_TYPE__ long unsigned intDRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create)DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map)DRM_IOCTL_MODE_REVOKE_LEASE DRM_IOWR(0xC9, struct drm_mode_revoke_lease)DRM_CAP_CURSOR_HEIGHT 0x9DRM_MODE_FLAG_PHSYNC (1<<0)DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)__CFLOAT32X _Complex _Float32x__GLIBC_USE_IEC_60559_FUNCS_EXT 1__INO_T_MATCHES_INO64_T 1AMDGPU_INFO_MEMORY 0x19__FLT32_DECIMAL_DIG__ 9POSIX_FADV_NORMAL 0_SC_PII_SOCKET _SC_PII_SOCKET__isgraph_l(c,l) __isctype_l((c), _ISgraph, (l))DRM_MODE_PROP_LEGACY_TYPE ( DRM_MODE_PROP_RANGE | DRM_MODE_PROP_ENUM | DRM_MODE_PROP_BLOB | DRM_MODE_PROP_BITMASK)DRM_MODE_PROP_ATOMIC 0x80000000DRM_RADEON_SETPARAM 0x19INT64_MIN (-__INT64_C(9223372036854775807)-1)__pic__ 2SI_TILE_MODE_COLOR_2D_16BPP 15DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid)AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1RADEON_WAIT_3D 0x2__PID_T_TYPE __S32_TYPEDRM_MODE_CONNECTOR_Unknown 0DRM_IOCTL_MODE_GETFB2 DRM_IOWR(0xCE, struct drm_mode_fb_cmd2)__FLT64_MIN__ 2.22507385850720138309023271733240406e-308F64AMDGPU_TILING_NUM_BANKS_MASK 0x3WEXITSTATUS(status) __WEXITSTATUS (status)GBM_FORMAT_BGRX4444 __gbm_fourcc_code('B', 'X', '1', '2')__FLT128_EPSILON__ 1.92592994438723585305597794258492732e-34F128__SCHAR_WIDTH__ 8DRM_AGP_NO_HANDLE 0F_GET_SEALS 1034_SC_TIMEOUTS _SC_TIMEOUTSgart_page_size_POSIX_SOURCE 1_SC_DEVICE_IO _SC_DEVICE_IOETOOMANYREFS 109__f64x(x) x ##f64xhtobe32(x) __bswap_32 (x)va_arg(v,l) __builtin_va_arg(v,l)AMDGPU_CTX_STABLE_PSTATE_PEAK 4DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map)SI_TILE_MODE_DEPTH_STENCIL_1D 4__sigset_t_defined 1WIFSIGNALED(status) __WIFSIGNALED (status)__LDBL_HAS_DENORM__ 1__WCHAR_T _SYS_TYPES_H 1__USE_LARGEFILE64 1__ssize_tLOCK_WRITE 128O_EXCL 0200_SC_NL_LANGMAX _SC_NL_LANGMAX_IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)DRM_CAP_SYNCOBJ_TIMELINE 0x14__SQUAD_TYPE long intO_DIRECTORY __O_DIRECTORYDRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET)R200_EMIT_PP_TXCBLEND_0 21EXIT_FAILURE 1F_GETFD 1__DEC128_MIN_EXP__ (-6142)__USE_FILE_OFFSET64EPROTOTYPE 91__undef_LINK_MAX __gid_t_defined __HAVE_DISTINCT_FLOAT32 0__CLOCK_T_TYPE __SLONGWORD_TYPEd_reclenAMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8__toupper_l(c,locale) __tobody (c, __toupper_l, (locale)->__ctype_toupper, (c, locale))DRM_CAP_PAGE_FLIP_TARGET 0x11__tobody(c,f,a,args) (__extension__ ({ int __res; if (sizeof (c) > 1) { if (__builtin_constant_p (c)) { int __c = (c); __res = __c < -128 || __c > 255 ? __c : (a)[__c]; } else __res = f args; } else __res = (a)[(int) (c)]; __res; }))DRM_CONTROL_DEV_NAME "%s/" DRM_CONTROL_MINOR_NAME "%d"DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock)_drmModeResDRM_CAP_DUMB_BUFFER 0x1AMDGPU_FAMILY_UNKNOWN 0_SC_SHRT_MAX _SC_SHRT_MAXDRM_PRINTFLIKE(f,a) __attribute__ ((format(__printf__, f, a)))DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane)__U64_TYPE unsigned long intAMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5)__gnu_linux__ 1__undef_ARG_MAXAT_EACCESS 0x200RADEON_CHUNK_ID_IB 0x02AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property)XATTR_SIZE_MAX 65536__builtin_memsetAMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8EDQUOT 122__FLT32_DENORM_MIN__ 1.40129846432481707092372958328991613e-45F32DRM_RADEON_VERTEX2 0x0FDRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd)_BITS_FLOATN_COMMON_H __attribute_noinline__ __attribute__ ((__noinline__))connectedvdisplayDRM_MODE_FLAG_PIC_AR_MASK (0x0F<<19)d_typeRADEON_PARAM_VBLANK_CRTC 13O_DIRECT __O_DIRECTUINT_FAST16_MAX (18446744073709551615UL)__isctype(c,type) ((*__ctype_b_loc ())[(int) (c)] & (unsigned short int) type)R200_EMIT_RE_AUX_SCISSOR_CNTL 53F_DUPFD_CLOEXEC 1030GBM_FORMAT_BIG_ENDIAN (1<<31)_SC_PRIORITIZED_IO _SC_PRIORITIZED_IO__GLIBC_USE_DEPRECATED_GETSGBM_FORMAT_YVU422 __gbm_fourcc_code('Y', 'V', '1', '6')DRM_MODE_CONNECTOR_SVIDEO 6_SC_SYMLOOP_MAX _SC_SYMLOOP_MAX_SC_MEMLOCK_RANGE _SC_MEMLOCK_RANGE__WCHAR_T__ _POSIX_FD_SETSIZE _POSIX_OPEN_MAXDRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx)_LARGEFILE_SOURCE 1EKEYEXPIRED 127AMDGPU_VRAM_TYPE_UNKNOWN 0GBM_FORMAT_YUV444 __gbm_fourcc_code('Y', 'U', '2', '4')SEEK_END 2__ARM_FEATURE_AES_SC_SEM_VALUE_MAX _SC_SEM_VALUE_MAX_SC_XOPEN_REALTIME_THREADS _SC_XOPEN_REALTIME_THREADSDRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread)_SC_DEVICE_SPECIFIC_R _SC_DEVICE_SPECIFIC_R__WIFCONTINUED(status) ((status) == __W_CONTINUED)O_WRONLY 01__ARM_FEATURE_SVE_CS_XBS5_ILP32_OFF32_CFLAGS _CS_XBS5_ILP32_OFF32_CFLAGSAMDGPU_INFO_RAS_ENABLED_SEM (1 << 10)_POSIX_HIWAT _POSIX_PIPE_BUF_SC_REGEXP _SC_REGEXP__USE_LARGEFILE64AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4)__isalpha_l(c,l) __isctype_l((c), _ISalpha, (l))__USE_POSIX199309sensor_infoAMDGPU_IB_FLAG_PREAMBLE (1<<1)RADEON_CHUNK_ID_FLAGS 0x03__glibc_clang_has_extension(ext) 0dri_node_PC_SYMLINK_MAX _PC_SYMLINK_MAX_IO_write_baseUINT8_MAX (255)AMDGPU_TILING_TILE_SPLIT_SHIFT 9DRM_MODE_CONNECTOR_DPI 17_SC_FD_MGMT _SC_FD_MGMTva_start(v,l) __builtin_va_start(v,l)count_connectorsDRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor)_SC_MAPPED_FILES _SC_MAPPED_FILES__FLT16_MIN__ 6.10351562500000000000000000000000000e-5F16_IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS)UINT16_WIDTH 16__U32_TYPE unsigned intO_TMPFILE __O_TMPFILE__GCC_ATOMIC_LLONG_LOCK_FREE 2SI_TILE_MODE_COLOR_1D_SCANOUT 9_LFS_LARGEFILE 1AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f__HAVE_FLOAT64 1_POSIX_ADVISORY_INFO 200809LR200_EMIT_PP_TXOFFSET_0 42R200_EMIT_PP_TXCBLEND_7 28DRM_RADEON_NOT_USED __DEC128_MAX__ 9.999999999999999999999999999999999E6144DLDRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth)__pid_t_defined _SC_THREAD_ATTR_STACKSIZE _SC_THREAD_ATTR_STACKSIZEreaddir64htole32(x) __uint32_identity (x)__CFLOAT64 _Complex _Float64__DBL_DIG__ 15__O_LARGEFILE 0RADEON_UPLOAD_ZBIAS 0x00020000S_ISUID __S_ISUID__LDBL_EPSILON__ 1.92592994438723585305597794258492732e-34LENOKEY 126__INT64_MAX__ 0x7fffffffffffffffLSPLICE_F_MORE 4DRM_RAM_PERCENT 10DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open)AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2AMDGPU_BO_LIST_OP_DESTROY 1__attribute_artificial__ __attribute__ ((__artificial__))__SSP_STRONG__ 3DRM_MODE_DIRTY_ON 1RADEON_EMIT_RB3D_COLORPITCH 2DRM_IOCTL_RADEON_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_OP, struct drm_radeon_gem_op)L_ctermid 9GBM_DEV_TYPE_FLAG_BLOCKED (1u << 5)ENOTBLK 15_SC_NPROCESSORS_ONLN _SC_NPROCESSORS_ONLNAMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13)__USE_GNUINT_LEAST64_MIN (-__INT64_C(9223372036854775807)-1)UINT_LEAST8_WIDTH 8EBUSY 16DT_FIFO DT_FIFODRM_MODE_CONTENT_TYPE_GRAPHICS 1__need_size_t high_va_offsetFD_SET(fd,fdsetp) __FD_SET (fd, fdsetp)__GLIBC_PREREQ(maj,min) ((__GLIBC__ << 16) + __GLIBC_MINOR__ >= ((maj) << 16) + (min))__aligned_le64 __le64 __attribute__((aligned(8)))__WIFSTOPPED(status) (((status) & 0xff) == 0x7f)__USE_MISC 1__S64_TYPE long int_CS_POSIX_V6_ILP32_OFFBIG_CFLAGS _CS_POSIX_V6_ILP32_OFFBIG_CFLAGSDRM_MODE_TYPE_DEFAULT (1<<4)__F_GETSIG 11RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79RADEON_EMIT_PP_TXFILTER_2 16RADEON_POINTS 0x1__SIZEOF_INT__ 4_SC_PII_INTERNET_STREAM _SC_PII_INTERNET_STREAMDRM_CAP_ASYNC_PAGE_FLIP 0x7__ORDER_PDP_ENDIAN__ 3412__FLT_DECIMAL_DIG__ 9_SC_XBS5_ILP32_OFF32 _SC_XBS5_ILP32_OFF32ERANGE 34__LONG_LONG_MAX__ 0x7fffffffffffffffLLAMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11)EIDRM 43__USE_ISOCXX11__WORDSIZE 64DRM_MODE_FLAG_PIC_AR_4_3 (DRM_MODE_PICTURE_ASPECT_4_3<<19)DRM_AMDGPU_VM 0x13__stub___compat_create_module DRM_MODE_ROTATE_MASK ( DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270)RADEON_MAX_TEXTURE_LEVELS 12EDOTDOT 73_MINIGBM_HELPERS_H_ DRM_MODE_CONNECTOR_HDMIA 11_SC_SS_REPL_MAX _SC_SS_REPL_MAX_POSIX_ARG_MAX 4096UINT_FAST16_WIDTH __WORDSIZE__SIZEOF_PTHREAD_BARRIER_T 32LOCK_RW 192_POSIX_THREAD_PRIORITY_SCHEDULING 200809L_drmPlatformDeviceInfoFD_SETSIZE __FD_SETSIZEAMDGPU_VRAM_TYPE_DDR4 8_XBS5_ILP32_OFF32 -1_POSIX_MESSAGE_PASSING 200809L__need_NULL __FLOAT_WORD_ORDER __BYTE_ORDER__f64(x) x ##f64__UQUAD_TYPE unsigned long int__OFF_T_MATCHES_OFF64_T 1AMDGPU_INFO_VIDEO_CAPS_ENCODE 1AMDGPU_HW_IP_NUM 9__ARM_FEATURE_FP16_VECTOR_ARITHMETICF_UNLCK 2GBM_FORMAT_BGRA4444 __gbm_fourcc_code('B', 'A', '1', '2')AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5_ASM_GENERIC_TYPES_H RADEON_TILING_SWAP_32BIT 0x8_cur_columnAMDGPU_INFO_FW_GFX_ME 0x04high_va_maxAMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7_POSIX_JOB_CONTROL 1O_FSYNC O_SYNCF_GETOWN_EX __F_GETOWN_EXDRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02__USE_XOPEN2K8XSI 1AT_EMPTY_PATH 0x1000_SC_FILE_ATTRIBUTES _SC_FILE_ATTRIBUTESEINVAL 22connectiondev_infoRADEON_PARAM_NUM_Z_PIPES 17ELNRNG 48INT_LEAST16_MIN (-32767-1)DRM_BUS_USB 1_POSIX_V7_LPBIG_OFFBIG -1_SC_TRACE_LOG _SC_TRACE_LOGDRM_MODE_ROTATE_90 (1<<1)DRM_MODE_CONTENT_TYPE_PHOTO 2DRM_MODE_ATOMIC_NONBLOCK 0x0200DRM_LIGHT_LOCK_COUNT(fd,lock,context,count) do { DRM_CAS_RESULT(__ret); DRM_CAS(lock,context,DRM_LOCK_HELD|context,__ret); if (__ret) drmGetLock(fd,context,0); else ++count; } while(0)AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3)AMDGPU_INFO_SENSOR_VDDNB 0x6__va_list__ RADEON_PARAM_NUM_GB_PIPES 15/source/platform/minigbm/minigbm_helpers.c__NTHNL(fct) __attribute__ ((__nothrow__)) fctAMDGPU_HW_IP_UVD_ENC 5_XOPEN_UNIX 1__PTRDIFF_TYPE__ long intEL2NSYNC 45R200_EMIT_TFACTOR_0 30__FLT64_MANT_DIG__ 53__FP_FAST_FMAF32 1__GNUC_PREREQ(maj,min) ((__GNUC__ << 16) + __GNUC_MINOR__ >= ((maj) << 16) + (min))R300_NEW_WAIT_2D_2D_CLEAN 0x4__undef_ARG_MAX isdigit(c) __isctype((c), _ISdigit)DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw)_STAT_VER _STAT_VER_KERNEL__isdigit_l(c,l) __isctype_l((c), _ISdigit, (l))__ORDER_BIG_ENDIAN__ 4321__SIZEOF_SIZE_T__ 8__LOCK_ALIGNMENT __FLT32X_DIG__ 15__DEC32_MAX__ 9.999999E96DFAMDGPU_INFO_MMR_SH_INDEX_SHIFT 8UINT64_MAX (__UINT64_C(18446744073709551615))_SC_CHAR_MIN _SC_CHAR_MIN_SC_SPORADIC_SERVER _SC_SPORADIC_SERVERstrndupa(s,n) (__extension__ ({ const char *__old = (s); size_t __len = strnlen (__old, (n)); char *__new = (char *) __builtin_alloca (__len + 1); __new[__len] = '\0'; (char *) memcpy (__new, __old, __len); }))_CS_LFS64_CFLAGS _CS_LFS64_CFLAGSAMDGPU_GEM_DOMAIN_GTT 0x2ENOTRECOVERABLE 131_D_ALLOC_NAMLEN(d) (((char *) (d) + (d)->d_reclen) - &(d)->d_name[0])AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFFSI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20__attribute_pure__ __attribute__ ((__pure__))count_modesprogram_invocation_short_nameF_TEST 3GBM_FORMAT_YVU411 __gbm_fourcc_code('Y', 'V', '1', '1')AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0_CS_POSIX_V7_ILP32_OFFBIG_LDFLAGS _CS_POSIX_V7_ILP32_OFFBIG_LDFLAGS__GNUC__ 8_SC_INT_MAX _SC_INT_MAXDRM_MODE_CURSOR_BO 0x01__FLT128_MANT_DIG__ 113_drmVersionAMDGPU_GEM_DOMAIN_CPU 0x1DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)_SC_TIMERS _SC_TIMERS__SLONG32_TYPE int_POSIX_SYMLINK_MAX 255AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1__INT_FAST32_MAX__ 0x7fffffffffffffffL__ID_T_TYPE __U32_TYPE_SC_TRACE_INHERIT _SC_TRACE_INHERIT__USE_POSIX199309 1__INT_FAST8_WIDTH__ 8DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2)DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version)_SC_USHRT_MAX _SC_USHRT_MAX__clockid_t_defined 1ECANCELED 125__GLIBC_USE_IEC_60559_BFP_EXT 1R300_CMD_PACKET3_CLEAR 0AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0)__FLT128_MIN_10_EXP__ (-4931)RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT)RADEON_GEM_CPU_ACCESS (1 << 3)_LARGEFILE64_SOURCE 1MINIGBM _POSIX_MQ_PRIO_MAX 32chip_revRADEON_EMIT_SE_VPORT_XSCALE 8EPFNOSUPPORT 96__off64_tRADEON_DEPTH 0x4__USE_XOPEN2KXSIDRM_MODE_FLAG_3D_MASK (0x1f<<14)drmIsMasterR200_EMIT_PP_TXFILTER_4 40drmDevicePtrFOPEN_MAXDRM_MODE_PAGE_FLIP_TARGET (DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE | DRM_MODE_PAGE_FLIP_TARGET_RELATIVE)F_SEAL_GROW 0x0004DRM_MODE_SUBPIXEL_VERTICAL_RGBRADEON_STENCIL 0x8EDOM 33AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3__ARM_64BIT_STATE 1DRM_IOCTL_SYNCOBJ_RESET DRM_IOWR(0xC4, struct drm_syncobj_array)F_SETOWN __F_SETOWNRADEON_INFO_DEVICE_ID 0x00_PC_NAME_MAX _PC_NAME_MAXAMDGPU_TILING_SCANOUT_MASK 0x1__DBL_MIN_10_EXP__ (-307)TTY_NAME_MAX 32R200_EMIT_RE_SCISSOR_TL_1 55DRM_MODE_REFLECT_Y (1<<5)EADDRNOTAVAIL 99__timer_t_defined 1DRM_AMDGPU_GEM_METADATA 0x06_IOW_BAD(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size))__WIFEXITED(status) (__WTERMSIG(status) == 0)WINT_MIN (0u)RADEON_GART_TEX_HEAP 1_CS_POSIX_V6_ILP32_OFFBIG_LDFLAGS _CS_POSIX_V6_ILP32_OFFBIG_LDFLAGSDRM_MODE_DIRTY_ANNOTATE 2RADEON_PARAM_GART_BASE 6DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink)EBADSLT 57__attribute_deprecated_msg__(msg) __attribute__ ((__deprecated__ (msg)))GBM_FORMAT_R8 __gbm_fourcc_code('R', '8', ' ', ' ')AMDGPU_VM_OP_RESERVE_VMID 1ECHRNG 44__dirstream_POSIX_TRACE_LOG -1_CS_POSIX_V7_ILP32_OFF32_LIBS _CS_POSIX_V7_ILP32_OFF32_LIBS__fsfilcnt_t_defined _PC_PIPE_BUF _PC_PIPE_BUF_ATFILE_SOURCEDRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7<<14)DRM_MODE_ENCODER_DPMST 7DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx)__attribute_warn_unused_result__ __attribute__ ((__warn_unused_result__))_POSIX2_C_DEV __POSIX2_THIS_VERSIONCLEAR_Y2 3__ARM_FEATURE_CLZ 1_BITS_STAT_H 1AMDGPU_INFO_READ_MMR_REG 0x15AMDGPU_CTX_INNOCENT_RESET 2_SC_PII_OSI_M _SC_PII_OSI_M__LEAF_ATTR __attribute__ ((__leaf__))__unix 1EACCES 13ENOENT 2_POSIX_HOST_NAME_MAX 255_SC_THREAD_DESTRUCTOR_ITERATIONS _SC_THREAD_DESTRUCTOR_ITERATIONS__USE_MISCWINT_MAX (4294967295u)DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane)num_shader_enginesip_instanceECONNRESET 104isalpha_l(c,l) __isalpha_l ((c), (l))_SC_2_PBS_TRACK _SC_2_PBS_TRACKRADEON_INFO_MAX_SE 0x12_POSIX_VERSION 200809LMB_CUR_MAX (__ctype_get_mb_cur_max ())DRM_RADEON_CS 0x26__AARCH64EB__R200_EMIT_PP_CUBIC_OFFSETS_2 66family__USE_FORTIFY_LEVEL_CS_POSIX_V7_ILP32_OFF32_CFLAGS _CS_POSIX_V7_ILP32_OFF32_CFLAGSENOTDIR 20__S_IFBLK 0060000AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7)DRM_MODE_PROP_EXTENDED_TYPE 0x0000ffc0DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL DRM_IOWR(0xCD, struct drm_syncobj_timeline_array)DRM_CAP_VBLANK_HIGH_CRTC 0x2DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx)_POSIX_SPAWN 200809LR200_EMIT_RB3D_DEPTHXY_OFFSET 52__f32x(x) x ##f32x__GLIBC_USE_LIB_EXT2 1__uint64_tDRM_CRTC_SEQUENCE_RELATIVE 0x00000001AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7F_SETLEASE 1024DN_MULTISHOT 0x80000000DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29_SC_SEMAPHORES _SC_SEMAPHORES_POSIX_V6_ILP32_OFF32 -1ELIBSCN 81DRM_MODE_SCALE_NONE 0__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1__FLT64_MAX_EXP__ 1024R200_EMIT_PP_CUBIC_FACES_3 67RADEON_INFO_VCE_FW_VERSION 0x1bRENAME_WHITEOUT (1 << 2)RADEON_EMIT_PP_LUM_MATRIX 5__REGISTER_PREFIX__ RADEON_TILING_EG_BANKW_SHIFT 8_CS_POSIX_V7_LPBIG_OFFBIG_LINTFLAGS _CS_POSIX_V7_LPBIG_OFFBIG_LINTFLAGSDRM_DEV_DIRMODE (S_IRUSR|S_IWUSR|S_IXUSR|S_IRGRP|S_IXGRP|S_IROTH|S_IXOTH)DRM_SPINLOCK_TAKE(spin,val) do { DRM_CAS_RESULT(__ret); int cur; do { cur = (*spin).lock; DRM_CAS(spin,cur,val,__ret); } while (__ret); } while(0)__LDBL_REDIR1_NTH(name,proto,alias) name proto __THROW_XOPEN_SHM 1drmFreeVersionRADEON_EMIT_PP_ROT_MATRIX_0 6ELIBMAX 82_XOPEN_XPG3 1DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd)conn_SC_XOPEN_XPG3 _SC_XOPEN_XPG3RADEON_INFO_VCE_FB_VERSION 0x1cEINPROGRESS 115AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1FILENAME_MAX 4096__USE_POSIX199506isspace(c) __isctype((c), _ISspace)GBM_FORMAT_BGRA8888 __gbm_fourcc_code('B', 'A', '2', '4')productDRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)__GCC_IEC_559_COMPLEX 2__PTHREAD_COMPAT_PADDING_MID __FLT32_HAS_INFINITY__ 1DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01__CHAR_BIT__ 8RADEON_GEM_DOMAIN_VRAM 0x4__INTPTR_MAX__ 0x7fffffffffffffffLDRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder)INT_LEAST64_MAX (__INT64_C(9223372036854775807))AMDGPU_INFO_CRTC_FROM_ID 0x01__FLT16_HAS_DENORM__ 1R200_EMIT_TEX_PROC_CTL_2 34DRM_CAS_RESULT(_result) char _result__HAVE_DISTINCT_FLOAT16 __HAVE_FLOAT16__glibc_macro_warning(message) __glibc_macro_warning1 (GCC warning message)__errordecl(name,msg) extern void name (void) __attribute__((__error__ (msg)))_FCNTL_H 1DRM_AMDGPU_GEM_VA 0x08vsync_start__glibc_macro_warning1(message) _Pragma (#message)__FLT32X_MIN_10_EXP__ (-307)GBM_FORMAT_BGRX8888 __gbm_fourcc_code('B', 'X', '2', '4')DRM_PRIME_CAP_IMPORT 0x1__glibc_unlikely(cond) __builtin_expect ((cond), 0)long long unsigned intR200_EMIT_ATF_TFACTOR 87_IOR_BAD(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size))RADEON_UPLOAD_TEX1IMAGES 0x00002000read_mmr_regDRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling)DRM_MIN_ORDER 5__INTMAX_WIDTH__ 64F_WRLCK 1__GCC_ATOMIC_BOOL_LOCK_FREE 2DRM_AMDGPU_CS 0x04AMDGPU_TILING_BANK_HEIGHT_MASK 0x3_drmModeConnectorDRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)RADEON_INFO_MAX_SH_PER_SE 0x13__LDBL_REDIR_NTH(name,proto) name proto __THROWDRM_MODE_CONNECTOR_WRITEBACK 18RWH_WRITE_LIFE_MEDIUM 3_SC_UCHAR_MAX _SC_UCHAR_MAXAMDGPU_BO_LIST_OP_CREATE 0RADEON_NR_TEX_HEAPS 2cu_ao_bitmapWINT_WIDTH 32__USE_POSIX 1count_fbsENOSYS 38DRM_MODE_OBJECT_PROPERTY 0xb0b0b0b0AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9)_SC_THREAD_STACK_MIN _SC_THREAD_STACK_MIN__ELF__ 1DRM_IOCTL_MODE_ATOMIC DRM_IOWR(0xBC, struct drm_mode_atomic)RADEON_MEM_REGION_GART 1__FLT128_MIN_EXP__ (-16381)_____fpos64_t_defined 1_POSIX_STREAM_MAX 8__INT64_TYPE__ long int__FSBLKCNT_T_TYPE __ULONGWORD_TYPERADEON_MEM_REGION_FB 2enabled_rb_pipes_maskDRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)__attribute_const__ __attribute__ ((__const__))__THROWNL __attribute__ ((__nothrow__))islower(c) __isctype((c), _ISlower)RADEON_GEM_NO_CPU_ACCESS (1 << 4)__stub_revoke __stub___compat_query_module F_SEAL_WRITE 0x0008__LDBL_REDIR_DECL(name) R200_EMIT_PP_CNTL_X 51DRM_RADEON_GEM_SET_TILING 0x28EBADR 53AMDGPU_VRAM_TYPE_DDR5 10__GLIBC_USE(F) __GLIBC_USE_ ## F_DRM_LOCK_HELD 0x80000000U__id_t_defined SI_TILE_MODE_DEPTH_STENCIL_2D_2AA 3DRM_MODE_DPMS_OFF 3_CS_LFS_LINTFLAGS _CS_LFS_LINTFLAGSELIBEXEC 83AMDGPU_INFO_FW_DMCUB 0x14AMDGPU_INFO_FW_SDMA 0x0b__NTH(fct) __attribute__ ((__nothrow__ __LEAF)) fct_VA_LIST_ _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)DRM_MODE_SCALE_CENTER 2DRM_MODE_SUBPIXEL_VERTICAL_BGR_PC_ALLOC_SIZE_MIN _PC_ALLOC_SIZE_MINDRM_MODE_CONNECTOR_Component 8__PTHREAD_MUTEX_USE_UNION 0_SC_READER_WRITER_LOCKS _SC_READER_WRITER_LOCKSRADEON_SETPARAM_NEW_MEMMAP 4__need___va_list cu_bitmap__dev_t_defined _CS_XBS5_ILP32_OFF32_LIBS _CS_XBS5_ILP32_OFF32_LIBSisalnum_l(c,l) __isalnum_l ((c), (l))__LP64__ 1_SC_XBS5_LP64_OFF64 _SC_XBS5_LP64_OFF64num_shader_visible_vgprs_POSIX_SPIN_LOCKS 200809LDRM_SPINLOCK_COUNT(spin,val,count,__ret) do { int __i; __ret = 1; for (__i = 0; __ret && __i < count; __i++) { DRM_CAS(spin,0,val,__ret); if (__ret) for (;__i < count && (spin)->lock; __i++); } } while(0)_SC_V7_ILP32_OFF32 _SC_V7_ILP32_OFF32__DBL_EPSILON__ ((double)2.22044604925031308084726333618164062e-16L)POSIX_FADV_SEQUENTIAL 2__ASM_GENERIC_POSIX_TYPES_H _ANSI_STDARG_H_ RADEON_INFO_GTT_USAGE 0x1fDRM_MODE_OBJECT_FB 0xfbfbfbfbTEMP_FAILURE_RETRY(expression) (__extension__ ({ long int __result; do __result = (long int) (expression); while (__result == -1L && errno == EINTR); __result; }))dirent_POSIX_CLOCK_SELECTION 200809LDRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding)RADEON_CHUNK_ID_RELOCS 0x01FD_ISSET(fd,fdsetp) __FD_ISSET (fd, fdsetp)DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)P_PGID_drmPciDeviceInfohdisplayINTPTR_MIN (-9223372036854775807L-1)__WEXITSTATUS(status) (((status) & 0xff00) >> 8)DRM_SPINLOCK(spin,val) do { DRM_CAS_RESULT(__ret); do { DRM_CAS(spin,0,val,__ret); if (__ret) while ((spin)->lock); } while (__ret); } while(0)SEEK_HOLE 4__ARM_FEATURE_NUMERIC_MAXMIN 1__FSBLKCNT64_T_TYPE __UQUAD_TYPE_DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)O_SYNC 04010000drmPciDeviceInfoPtr__restrict_arr __restrictEROFS 30__USE_UNIX98 1RADEON_INFO_WANT_HYPERZ 0x07RADEON_USE_HIERZ 0x40000000INT_FAST8_MAX (127)DRM_CLIENT_CAP_STEREO_3D 1_GBM_H_ _SC_C_LANG_SUPPORT_R _SC_C_LANG_SUPPORT_RAMDGPU_VM_PAGE_WRITEABLE (1 << 2)__LONG_MAX__ 0x7fffffffffffffffLAMDGPU_CTX_PRIORITY_HIGH 512RADEON_VM_PAGE_WRITEABLE (1 << 2)_IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS)__ARM_FEATURE_FP16_FMLDRM_ERR_NOT_ROOT (-1003)O_CREAT 0100__stub_getpmsg DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)_POSIX_THREAD_THREADS_MAX 64drmDropMaster__O_DSYNC 010000__INT_LEAST32_TYPE__ intFNONBLOCK O_NONBLOCKRADEON_VA_UNMAP 2_CS_POSIX_V7_ILP32_OFF32_LINTFLAGS _CS_POSIX_V7_ILP32_OFF32_LINTFLAGS__RADEON_DRM_H__ long long intDRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)_CS_POSIX_V7_ILP32_OFF32_LDFLAGS _CS_POSIX_V7_ILP32_OFF32_LDFLAGSF_OK 0___int_wchar_t_h LOGIN_NAME_MAX 256_SC_LEVEL1_ICACHE_ASSOC _SC_LEVEL1_ICACHE_ASSOCRADEON_UPLOAD_MISC 0x00000100PTHREAD_STACK_MIN 131072__gbm_fourcc_code(a,b,c,d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24))AMDGPU_TILING_NUM_BANKS_SHIFT 21resourcesF_GETOWN __F_GETOWNhtole16(x) __uint16_identity (x)DRM_MODE_FLAG_INTERLACE (1<<4)GBM_FORMAT_RGBX8888 __gbm_fourcc_code('R', 'X', '2', '4')__need_wchar_t _POSIX_TRACE_EVENT_FILTER -1_vtable_offset_XOPEN_VERSION 700DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)d_offDRM_RADEON_VBLANK_CRTC1 1_PC_PRIO_IO _PC_PRIO_IOgc_double_offchip_lds_buf_STDARG_H RADEON_TILING_R600_NO_SCANOUT RADEON_TILING_SWAP_16BITDRM_MODE_FB_DIRTY_FLAGS 0x03_CS_POSIX_V7_ILP32_OFFBIG_CFLAGS _CS_POSIX_V7_ILP32_OFFBIG_CFLAGS__getc_unlocked_body(_fp) (__glibc_unlikely ((_fp)->_IO_read_ptr >= (_fp)->_IO_read_end) ? __uflow (_fp) : *(unsigned char *) (_fp)->_IO_read_ptr++)__BIT_TYPES_DEFINED__ 1_BITS_POSIX1_LIM_H 1__FDS_BITS(set) ((set)->fds_bits)min_width_FILE_OFFSET_BITS 64RADEON_GEM_DOMAIN_GTT 0x2GBM_FORMAT_ABGR16161616F __gbm_fourcc_code('A', 'B', '4', 'H')R200_EMIT_PP_TXOFFSET_3 45dev_node_ISdigit_SC_PAGESIZE _SC_PAGESIZE__POSIX_FADV_DONTNEED 4DRM_RENDER_DEV_NAME "%s/" DRM_RENDER_MINOR_NAME "%d"_SC_CHAR_BIT _SC_CHAR_BIT_POSIX_TZNAME_MAX 6connector_id__daddr_t_defined _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size)))ENOTSUP EOPNOTSUPP__FSFILCNT64_T_TYPE __UQUAD_TYPEAMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4)_BITS_PTHREADTYPES_COMMON_H 1_SC_REALTIME_SIGNALS _SC_REALTIME_SIGNALSO_NOCTTY 0400UINT16_MAX (65535)GBM_FORMAT_RGBX4444 __gbm_fourcc_code('R', 'X', '1', '2')DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN)WSTOPPED 2NULL ((void *)0)RADEON_CS_RING_DMA 2DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector)_SC_TIMER_MAX _SC_TIMER_MAX__va_copy(d,s) __builtin_va_copy(d,s)DT_BLK DT_BLKDRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle)__glibc_has_attribute(attr) __has_attribute (attr)INT8_MAX (127)drmModeFreeConnectorSYNC_FILE_RANGE_WAIT_AFTER 4__CHAR_UNSIGNED__ 1__LDBL_MIN__ 3.36210314311209350626267781732175260e-4932LF_RDLCK 0O_LARGEFILE __O_LARGEFILESI_TILE_MODE_COLOR_2D_SCANOUT_32BPP 12DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock)__FLT_EVAL_METHOD___GCC_SIZE_T subvendor_idGBM_FORMAT_P010 __gbm_fourcc_code('P', '0', '1', '0')AMDGPU_INFO_VBIOS_IMAGE 0x2PTRDIFF_WIDTH __WORDSIZEO_CLOEXEC __O_CLOEXEC__va_arg_pack() __builtin_va_arg_pack ()__need_wchar_tRADEON_EMIT_SE_LINE_WIDTH 4__UINT64_MAX__ 0xffffffffffffffffULDRM_MODE_DPMS_SUSPEND 2DN_DELETE 0x00000008__GCC_IEC_559 2RADEON_VA_RESULT_ERROR 1__FLT32_MANT_DIG__ 24max_engine_clockGBM_FORMAT_YVU410 __gbm_fourcc_code('Y', 'V', 'U', '9')_DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)POSIX_FADV_DONTNEED __POSIX_FADV_DONTNEED_CS_XBS5_ILP32_OFF32_LDFLAGS _CS_XBS5_ILP32_OFF32_LDFLAGSLINK_MAX 127__S32_TYPE int__undef_NR_OPEN __HAVE_FLOAT64X_LONG_DOUBLE __HAVE_FLOAT128AMDGPU_HW_IP_DMA 2__F_SETOWN_EX 15__FLT64X_DECIMAL_DIG__ 36num_hw_gfx_contexts_SYS_SIZE_T_H __SHRT_WIDTH__ 16_SC_BASE _SC_BASE_SC_RAW_SOCKETS _SC_RAW_SOCKETSEUNATCH 49__ARM_SIZEOF_MINIMAL_ENUM 4EXDEV 18_SC_THREAD_SAFE_FUNCTIONS _SC_THREAD_SAFE_FUNCTIONS__STDC_IEC_559__ 1_PC_ASYNC_IO _PC_ASYNC_IO_SC_SCHAR_MIN _SC_SCHAR_MIN_SC_LINE_MAX _SC_LINE_MAX_POSIX2_VERSION __POSIX2_THIS_VERSION__DBL_DECIMAL_DIG__ 17__RADEON_SAREA_DEFINES__ asprintf__GCC_ATOMIC_CHAR_LOCK_FREE 2__INT_LEAST64_WIDTH__ 64subdevice_idRADEON_INFO_FASTFB_WORKING 0x14iscntrl(c) __isctype((c), _IScntrl)_XBS5_LPBIG_OFFBIG -1__FLT64X_HAS_QUIET_NAN__ 1AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock)POSIX_FADV_RANDOM 1__stub_sysctl _SC_BC_DIM_MAX _SC_BC_DIM_MAXAMDGPU_CTX_OP_SET_STABLE_PSTATE 6_LINUX_POSIX_TYPES_H L_INCR SEEK_CUR__PMTvce_harvest_config_SC_COLL_WEIGHTS_MAX _SC_COLL_WEIGHTS_MAXLOCK_NB 4FORMAT_BLOB_CURRENT 1__FSFILCNT_T_TYPE __ULONGWORD_TYPEAMDGPU_TILING_BANK_WIDTH_SHIFT 15__VERSION__ "8.3.0"AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff__DEC128_SUBNORMAL_MIN__ 0.000000000000000000000000000000001E-6143DLDRM_IOCTL_NR(n) _IOC_NR(n)_SC_XOPEN_CRYPT _SC_XOPEN_CRYPT__CONCAT(x,y) x ## yAMDGPU_CTX_PRIORITY_VERY_HIGH 1023__S_ISGID 02000_POSIX_THREAD_ATTR_STACKADDR 200809L__OPTIMIZE__ 1__AMDGPU_DRM_H__ AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0GNU C99 8.3.0 -mlittle-endian -mabi=lp64 -ggdb3 -O2 -std=c99 -fno-strict-aliasing -fstack-protector-strong -fvisibility=internal -fPIC_PC_FILESIZEBITS _PC_FILESIZEBITS_T_SIZE_ GBM_FORMAT_XRGB8888 __gbm_fourcc_code('X', 'R', '2', '4')openGBM_DEV_TYPE_FLAG_DISCRETE (1u << 0)EPROTO 71_SC_USER_GROUPS _SC_USER_GROUPSAMDGPU_INFO_RAS_ENABLED_DF (1 << 8)RADEON_EMIT_PP_BORDER_COLOR_0 13AMDGPU_HW_IP_GFX 0AMDGPU_INFO_GDS_CONFIG 0x13_chain_POSIX_LINK_MAX 8AMDGPU_TILING_SCANOUT_SHIFT 63DRM_MODE_TYPE_USERDEF (1<<5)DRM_MAX_MINOR 16EKEYREJECTED 129DRM_MODE_PROP_BITMASK (1<<5)_SC_TRACE_USER_EVENT_MAX _SC_TRACE_USER_EVENT_MAXAMDGPU_GEM_OP_SET_PLACEMENT 1EBADMSG 74RADEON_CS_RING_GFX 0EKEYREVOKED 128S_IFBLK __S_IFBLKRADEON_PARAM_FB_LOCATION 14RADEON_MAX_STATE_PACKETS 95DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)AMDGPU_GEM_USERPTR_VALIDATE (1 << 2)__drm_dummy_lock(lock) (*(__volatile__ unsigned int *)lock)DT_SOCK DT_SOCKAMDGPU_VM_MTYPE_CC (3 << 5)__KEY_T_TYPE __S32_TYPE_IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size)))_SC_SHRT_MIN _SC_SHRT_MIN__WCHAR_MIN __WCHAR_MIN__DTTOIF(dirtype) ((dirtype) << 12)O_TRUNC 01000__need_ptrdiff_tDRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info)__S_IWRITE 0200AMDGPU_HW_IP_COMPUTE 1_POSIX_SYMLOOP_MAX 8__FLT128_MAX_EXP__ 16384__FLT64X_DIG__ 33NFDBITS __NFDBITS_POSIX_SAVED_IDS 1ENETDOWN 100__USE_XOPEN2K8 1ELOOP 40ENXIO 6__LDBL_DENORM_MIN__ 6.47517511943802511092443895822764655e-4966L_LFS_ASYNCHRONOUS_IO 1__COMPAR_FN_T tolower(c) __tobody (c, tolower, *__ctype_tolower_loc (), (c))R300_WAIT_2D 0x1RADEON_UPLOAD_TEX0IMAGES 0x00001000_SC_XOPEN_VERSION _SC_XOPEN_VERSIONAMDGPU_INFO_FW_SOS 0x0c__DBL_MAX_EXP__ 1024IOCSIZE_SHIFT (_IOC_SIZESHIFT)dev_count__PTHREAD_SPINS 0RADEON_INFO_BACKEND_MAP 0x0d_SC_SEM_NSEMS_MAX _SC_SEM_NSEMS_MAX_POSIX2_C_VERSION __POSIX2_THIS_VERSION_SC_NPROCESSORS_CONF _SC_NPROCESSORS_CONF_SC_BC_SCALE_MAX _SC_BC_SCALE_MAX_____fpos_t_defined 1_DRM_PRE_MODESET 1INT_FAST32_MAX (9223372036854775807L)RADEON_INFO_READ_REG 0x24_DEFAULT_SOURCE 1__GCC_ATOMIC_POINTER_LOCK_FREE 2__UID_T_TYPE __U32_TYPENGROUPS_MAX 65536_tolower(c) ((int) (*__ctype_tolower_loc ())[(int) (c)])_POSIX_AIO_MAX 1_SC_THREAD_ATTR_STACKADDR _SC_THREAD_ATTR_STACKADDR__PMT(args) args__isprint_l(c,l) __isctype_l((c), _ISprint, (l))ENOPROTOOPT 92ERFKILL 132DRM_RADEON_FREE 0x14__SIZE_WIDTH__ 64DRM_NAME "drm"PTHREAD_DESTRUCTOR_ITERATIONS _POSIX_THREAD_DESTRUCTOR_ITERATIONS_SC_BARRIERS _SC_BARRIERSDRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb)__ATOMIC_RELEASE 3_IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1)__unix__ 1_SC_IPV6 _SC_IPV6__exctype_l(name) extern int name (int, locale_t) __THROWRADEON_GEM_USERPTR_ANONONLY (1 << 1)DRM_MODE_FLAG_PIC_AR_256_135 (DRM_MODE_PICTURE_ASPECT_256_135<<19)__iscntrl_l(c,l) __isctype_l((c), _IScntrl, (l))R200_EMIT_PP_TXCTLALL_2 90_CS_POSIX_V7_LPBIG_OFFBIG_LIBS _CS_POSIX_V7_LPBIG_OFFBIG_LIBSENONET 64_SC_POLL _SC_POLLDRM_AMDGPU_WAIT_CS 0x09AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFFRADEON_GEM_USERPTR_READONLY (1 << 0)__DEC_EVAL_METHOD__ 2_freeres_list__DADDR_T_TYPE __S32_TYPE_SC_VERSION _SC_VERSIONDRM_LIGHT_LOCK(fd,lock,context) do { DRM_CAS_RESULT(__ret); DRM_CAS(lock,context,DRM_LOCK_HELD|context,__ret); if (__ret) drmGetLock(fd,context,0); } while(0)DRM_RADEON_CP_START 0x01RADEON_PARAM_GART_TEX_HANDLE 10isblank(c) __isctype((c), _ISblank)_SC_TZNAME_MAX _SC_TZNAME_MAXUINTPTR_MAX (18446744073709551615UL)F_SEAL_SEAL 0x0001UINT_LEAST64_MAX (__UINT64_C(18446744073709551615))__O_NOFOLLOW 0100000GBM_FORMAT_RGBX5551 __gbm_fourcc_code('R', 'X', '1', '5')__GCC_HAVE_DWARF2_CFI_ASM 1__DEC64_EPSILON__ 1E-15DDAMDGPU_FAMILY_VI 130__attribute_format_strfmon__(a,b) __attribute__ ((__format__ (__strfmon__, a, b)))RADEON_CARD_PCIE 2EREMCHG 78_IO_FILE__stack_chk_fail__attribute_format_arg__(x) __attribute__ ((__format_arg__ (x)))DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info)DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma)AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8)MAX(A,B) ((A) > (B) ? (A) : (B))S_IRGRP (S_IRUSR >> 3)__USE_FORTIFY_LEVEL 0_SC_REGEX_VERSION _SC_REGEX_VERSIONDRM_UNLOCK(fd,lock,context) do { DRM_CAS_RESULT(__ret); DRM_CAS(lock,DRM_LOCK_HELD|context,context,__ret); if (__ret) drmUnlock(fd,context); } while(0)DRM_RADEON_CP_RESET 0x03_IOC_WRITE 1UENOCSI 50DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map)_SC_T_IOV_MAX _SC_T_IOV_MAXF_SETLKW F_SETLKW64__DECIMAL_DIG__ 36__INT16_MAX__ 0x7fffAMDGPU_INFO_FW_ASD 0x0d__ONCE_ALIGNMENT gpu_counter_freqDRM_BUS_PCI 0__ARM_ALIGN_MAX_PWR 28AMDGPU_VA_OP_REPLACE 4AMDGPU_IB_FLAG_PREEMPT (1<<2)F_GETLK64 5_POSIX_SHARED_MEMORY_OBJECTS 200809LAMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2GBM_FORMAT_ARGB2101010 __gbm_fourcc_code('A', 'R', '3', '0')__ARM_PCS_AAPCS64 1GBM_FORMAT_YUV420 __gbm_fourcc_code('Y', 'U', '1', '2')_SC_2_CHAR_TERM _SC_2_CHAR_TERMRADEON_GEM_GTT_UC (1 << 1)AMDGPU_INFO_ACCEL_WORKING 0x00_T_WCHAR GBM_FORMAT_NV16 __gbm_fourcc_code('N', 'V', '1', '6')_SC_PII_XTI _SC_PII_XTIR200_EMIT_SE_VAP_CNTL_STATUS 57optind__HAVE_DISTINCT_FLOAT64 0_CS_POSIX_V6_WIDTH_RESTRICTED_ENVS _CS_V6_WIDTH_RESTRICTED_ENVSstrlenUINTMAX_MAX (__UINT64_C(18446744073709551615))EXFULL 54_SC_2_PBS_ACCOUNTING _SC_2_PBS_ACCOUNTING__HAVE_FLOAT128X 0O_NOFOLLOW __O_NOFOLLOW_XOPEN_XPG2 1__AARCH64_CMODEL_SMALL___pad_BITS_BYTESWAP_H 1_IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS)RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)__size_t __UINT16_C(c) cdrm_radeon_infoAMDGPU_GEM_USERPTR_ANONONLY (1 << 1)AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19__WTERMSIG(status) ((status) & 0x7f)__warndecl(name,msg) extern void name (void) __attribute__((__warning__ (msg)))_LINUX_TYPES_H __u32DRM_MODE_CONNECTOR_DVII 2__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2_CS_LFS_CFLAGS _CS_LFS_CFLAGS__FLT32X_HAS_DENORM__ 1__stub_putpmsg __FLT16_MIN_EXP__ (-13)DRM_IOC_READ _IOC_READEHWPOISON 133AMDGPU_FAMILY_YC 146_PC_REC_XFER_ALIGN _PC_REC_XFER_ALIGNRWH_WRITE_LIFE_EXTREME 5_STDC_PREDEF_H 1BUFSIZ 8192DRM_MODE_CONNECTOR_TV 13_SC_PHYS_PAGES _SC_PHYS_PAGESDRM_CLIENT_CAP_WRITEBACK_CONNECTORS 5UINT_FAST64_MAX (__UINT64_C(18446744073709551615))_BITS_ERRNO_H 1PATH_MAX 4096DRM_RADEON_GEM_SET_DOMAIN 0x23isprint(c) __isctype((c), _ISprint)__FLT32_MAX_EXP__ 128UINT_FAST8_WIDTH 8drmModeFreeResources_CS_PATH _CS_PATH__intptr_t_defined _STAT_VER_KERNEL 0_LARGEFILE_SOURCE_POSIX_MEMLOCK_RANGE 200809LEL3HLT 46R200_EMIT_PP_TXCBLEND_2 23_DIRENT_H 1R300_CMD_SCRATCH 8_POSIX_REENTRANT_FUNCTIONS 1drm_amdgpu_query_fw__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2_SC_UIO_MAXIOV _SC_UIO_MAXIOVtrue 1AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)cntl_sb_buf_sizeAMDGPU_VA_OP_CLEAR 3_CS_LFS_LIBS _CS_LFS_LIBSAMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43__WCHAR_TYPE__ unsigned int__DEC64_MIN__ 1E-383DD__ARM_FEATURE_DOTPROD__FD_ELT(d) ((d) / __NFDBITS)DRM_MODE_CONNECTOR_9PinDIN 9_BITS_TYPES_H 1P_tmpdir "/tmp"DT_CHR DT_CHR_POSIX_THREAD_PROCESS_SHARED 200809L__USE_ISOC95 1prim_buf_size__DEC64_MAX__ 9.999999999999999E384DDDRM_AMDGPU_CTX 0x02AT_FDCWD -100DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain)__GLIBC_USE_IEC_60559_BFP_EXT_freeres_buf__F_GETOWN_EX 16AMDGPU_CTX_OP_QUERY_STATE 3_BITS_PTHREADTYPES_ARCH_H 1cu_ao_maskF_GET_RW_HINT 1035DRM_PROC_NAME "/proc/dri/"GBM_FORMAT_C8 __gbm_fourcc_code('C', '8', ' ', ' ')RADEON_CS_END_OF_FRAME 0x04_CS_POSIX_V6_LPBIG_OFFBIG_LIBS _CS_POSIX_V6_LPBIG_OFFBIG_LIBSDRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04__alignCLONE_VFORK 0x00004000STA_FREQHOLD 0x0080MESA_LLVMPIPE_MAX_TEXTURE_2D_LEVELS 15DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)__pthread_mutex_sDRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)AMD_FMT_MOD_RB_SHIFT 30DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8')DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17AMLOGIC_FBC_LAYOUT_SCATTER (2ULL)STA_CLK 0x8000__sched_priority sched_priorityVIRTGPU_BLOB_FLAG_USE_MAPPABLE 0x0001PTHREAD_ADAPTIVE_MUTEX_INITIALIZER_NP { { 0, 0, 0, 0, PTHREAD_MUTEX_ADAPTIVE_NP, __PTHREAD_SPINS, { 0, 0 } } }drv_loge(format,...) _drv_log(DRV_LOGE, format, ##__VA_ARGS__)DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4')CPU_ISSET_S(cpu,setsize,cpusetp) __CPU_ISSET_S (cpu, setsize, cpusetp)AMD_FMT_MOD_TILE_SHIFT 8CLOCK_REALTIME_COARSE 5PARAM(x) (struct virtgpu_param) { x, #x, 0 }CPU_XOR_S(setsize,destset,srcset1,srcset2) __CPU_OP_S (setsize, destset, srcset1, srcset2, ^)DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09AMD_FMT_MOD_TILE_VERSION_MASK 0xFFDRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2')VIRTGPU_PARAM_RESOURCE_BLOB 3BO_USE_NON_GPU_HW (BO_USE_SCANOUT | BO_USE_CAMERA_WRITE | BO_USE_CAMERA_READ | BO_USE_HW_VIDEO_ENCODER | BO_USE_HW_VIDEO_DECODER | BO_USE_SENSOR_DIRECT_DATA)AMD_FMT_MOD_TILE_GFX9_64K_D 10DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) fourcc_mod_broadcom_code(2, v)PTHREAD_CANCEL_DISABLE PTHREAD_CANCEL_DISABLEDRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1')__CPU_ZERO_S(setsize,cpusetp) do __builtin_memset (cpusetp, '\0', setsize); while (0)DRM_FORMAT_FLEX_YCbCr_420_888 fourcc_code('9', '9', '9', '9')PTHREAD_CANCELED ((void *) -1)AFBC_FORMAT_MOD_USM (1ULL << 12)__PTHREAD_RWLOCK_INT_FLAGS_SHARED 1DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode)DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2')AFRC_FORMAT_MOD_CU_SIZE_24 (2ULL)AFRC_FORMAT_MOD_CU_SIZE_16 (1ULL)DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0')DRM_IOCTL_VIRTGPU_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT, struct drm_virtgpu_3d_wait)_BITS_TYPES_STRUCT_SCHED_PARAM 1SCHED_RR 2rectDRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0')compressionDRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0')DRM_FORMAT_NONE fourcc_code('0', '0', '0', '0')DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4')DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8')DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8')BO_USE_CAMERA_READ (1ull << 7)DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6')DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4')ADJ_OFFSET_SS_READ 0xa001VIRTGPU_BLOB_MEM_GUEST 0x0001AMD_FMT_MOD_SET(field,value) ((uint64_t)(value) << AMD_FMT_MOD_ ##field ##_SHIFT)DRM_FORMAT_MOD_NONE 0virtgpu_virglI915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)__int64_tAMD_FMT_MOD_TILE_MASK 0x1Fdrv_import_fd_dataDRV_LOGEADJ_MAXERROR 0x0004CLONE_NEWUTS 0x04000000DRV_PRIV_H mappingBO_MAP_NONE 0DRV_LOGVAMD_FMT_MOD fourcc_mod_code(AMD, 0)MESA_LLVMPIPE_MAX_TEXTURE_2D_SIZE (1 << (MESA_LLVMPIPE_MAX_TEXTURE_2D_LEVELS - 1))DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0')DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5')fourcc_mod_broadcom_code(val,params) fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val))DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)__ownerDRM_FORMAT_MTISP_SXYZW10 fourcc_code('M', 'B', '1', '0')CPU_AND_S(setsize,destset,srcset1,srcset2) __CPU_OP_S (setsize, destset, srcset1, srcset2, &)VIRTGPU_PARAM_HOST_VISIBLE 4CLONE_SIGHAND 0x00000800DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2)CLOCK_TAI 11AMD_FMT_MOD_TILE_GFX9_64K_S 9__struct_tm_defined 1DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')__tzname__lockAMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24AFBC_FORMAT_MOD_SPARSE (1ULL << 6)drv_logv(format,...) _drv_log(DRV_LOGV, format, ##__VA_ARGS__)__pthread_list_tPTHREAD_RECURSIVE_MUTEX_INITIALIZER_NP { { 0, 0, 0, 0, PTHREAD_MUTEX_RECURSIVE_NP, __PTHREAD_SPINS, { 0, 0 } } }DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL)AFBC_FORMAT_MOD_YTR (1ULL << 4)DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4')DRM_IOCTL_VIRTGPU_MAP DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)CPU_CLR(cpu,cpusetp) __CPU_CLR_S (cpu, sizeof (cpu_set_t), cpusetp)DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0')AFRC_FORMAT_MOD_CU_SIZE_32 (3ULL)ADJ_ESTERROR 0x0008DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8')STA_PPSTIME 0x0004DRM_FORMAT_MOD_BROADCOM_SAND64 DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0)DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4')CPU_SETSIZE __CPU_SETSIZECLOCK_BOOTTIME 7AMD_FMT_MOD_DCC_BLOCK_128B 1DRM_FORMAT_MOD_VENDOR_INTEL 0x01BO_USE_HW_MASK (BO_USE_GPU_HW | BO_USE_NON_GPU_HW)DRM_VIRTGPU_GETPARAM 0x03AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3VIRTGPU_RESOURCE_INFO_TYPE_DEFAULT 0DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0')fourcc_code(a,b,c,d) ((__u32)(a) | ((__u32)(b) << 8) | ((__u32)(c) << 16) | ((__u32)(d) << 24))CLOCK_MONOTONIC_RAW 4DRM_FORMAT_MOD_VENDOR_QCOM 0x05MOD_TAI ADJ_TAIDRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0')STA_DEL 0x0020__dataVIRTGPU_EXECBUF_RING_IDX 0x04CLONE_NEWPID 0x20000000CLONE_SYSVSEM 0x00040000DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) fourcc_mod_broadcom_code(3, v)DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06fourcc_mod_code(vendor,val) ((((__u64)DRM_FORMAT_MOD_VENDOR_ ## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)PTHREAD_CANCEL_ASYNCHRONOUS PTHREAD_CANCEL_ASYNCHRONOUSAMLOGIC_FBC_LAYOUT_BASIC (1ULL)DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4')DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6')pthread_mutex_tADJ_NANO 0x2000DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2')DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5')drm_virtgpu_getparamBO_USE_SCANOUT (1ull << 0)__NCPUBITS (8 * sizeof (__cpu_mask))PTHREAD_CANCEL_ENABLE PTHREAD_CANCEL_ENABLEAMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1AMD_FMT_MOD_TILE_VER_GFX10 2AMD_FMT_MOD_DCC_RETILE_SHIFT 14BO_USE_HW_VIDEO_DECODER (1ull << 13)VIRTGPU_CONTEXT_PARAM_NUM_RINGS 0x0002PTHREAD_COND_INITIALIZER { { {0}, {0}, {0, 0}, {0, 0}, 0, 0, {0, 0} } }ADJ_TAI 0x0080PTHREAD_EXPLICIT_SCHED PTHREAD_EXPLICIT_SCHEDDRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8')__kindVIRTGPU_EXECBUF_FLAGS ( VIRTGPU_EXECBUF_FENCE_FD_IN | VIRTGPU_EXECBUF_FENCE_FD_OUT | VIRTGPU_EXECBUF_RING_IDX | 0)I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)SCHED_OTHER 0CLONE_NEWIPC 0x08000000MESA_LLVMPIPE_TILE_SIZE (1 << MESA_LLVMPIPE_TILE_ORDER)DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5')MOD_STATUS ADJ_STATUSVIRTGPU_PARAM_SUPPORTED_CAPSET_IDs 7DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8')VIRTGPU_PARAM_CONTEXT_INIT 6__fourcc_mod_broadcom_param_shift 8DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8')drv_log_levelDRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0')CPU_XOR(destset,srcset1,srcset2) __CPU_OP_S (sizeof (cpu_set_t), destset, srcset1, srcset2, ^)bo_metadataDRV_LOGDDRV_LOGICLOCKS_PER_SEC ((__clock_t) 1000000)ADJ_TICK 0x4000VIRTGPU_PARAM_GUEST_VRAM 10DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2)_PTHREAD_H 1DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8')rectangleCPU_EQUAL_S(setsize,cpusetp1,cpusetp2) __CPU_EQUAL_S (setsize, cpusetp1, cpusetp2)bo_compute_metadata__CPU_SET_S(cpu,setsize,cpusetp) (__extension__ ({ size_t __cpu = (cpu); __cpu / 8 < (setsize) ? (((__cpu_mask *) ((cpusetp)->__bits))[__CPUELT (__cpu)] |= __CPUMASK (__cpu)) : 0; }))DRM_FORMAT_MOD_BROADCOM_SAND32 DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0)virtgpu_cross_domainDRM_FORMAT_MOD_ARM_CODE(__type,__val) fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL))DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1')BO_USE_CURSOR (1ull << 1)BO_USE_TEXTURE_MASK (BO_USE_LINEAR | BO_USE_RENDERSCRIPT | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN | BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY | BO_USE_TEXTURE | BO_USE_FRONT_RENDERING)VIRTGPU_CONTEXT_PARAM_CAPSET_ID 0x0001CPU_ISSET(cpu,cpusetp) __CPU_ISSET_S (cpu, sizeof (cpu_set_t), cpusetp)__sizeCLONE_PARENT 0x00008000__isleap(year) ((year) % 4 == 0 && ((year) % 100 != 0 || (year) % 400 == 0))VIRTGPU_PARAM_RESOURCE_SYNC 9MESA_LLVMPIPE_TILE_ORDER 6DRM_FORMAT_MOD_BROADCOM_SAND256 DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0)drv_logd(format,...) _drv_log(DRV_LOGD, format, ##__VA_ARGS__)STA_CLOCKERR 0x1000PTHREAD_MUTEX_INITIALIZER { { 0, 0, 0, 0, 0, __PTHREAD_SPINS, { 0, 0 } } }MOD_MICRO ADJ_MICROCLONE_NEWNS 0x00020000get_paramDRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2')CPU_EQUAL(cpusetp1,cpusetp2) __CPU_EQUAL_S (sizeof (cpu_set_t), cpusetp1, cpusetp2)CLOCK_REALTIME_ALARM 8_BITS_TIMEX_H 1drv_logi(format,...) _drv_log(DRV_LOGI, format, ##__VA_ARGS__)__countDRM_FORMAT_P010 fourcc_code('P', '0', '1', '0')pthread_cleanup_pop(execute) do { } while (0); } while (0); __pthread_unregister_cancel (&__cancel_buf); if (execute) __cancel_routine (__cancel_arg); } while (0)DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v))DRM_FOURCC_H AMD_FMT_MOD_TILE_GFX9_64K_R_X 27VIRTGPU_BLOB_FLAG_USE_SHAREABLE 0x0002virtgpu_initDRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5')STA_UNSYNC 0x0040backend_virtgpuCLONE_NEWNET 0x40000000TIME_UTC 1DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4')__CPU_CLR_S(cpu,setsize,cpusetp) (__extension__ ({ size_t __cpu = (cpu); __cpu / 8 < (setsize) ? (((__cpu_mask *) ((cpusetp)->__bits))[__CPUELT (__cpu)] &= ~__CPUMASK (__cpu)) : 0; }))BO_USE_CURSOR_64X64 BO_USE_CURSORDRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0)AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7offsetsBO_USE_GPU_HW (BO_USE_RENDERING | BO_USE_TEXTURE | BO_USE_GPU_DATA_BUFFER)bo_create_from_metadataPTHREAD_ONCE_INIT 0VIRTGPU_PARAM_CREATE_GUEST_HANDLE 8AMD_FMT_MOD_TILE_VER_GFX9 1VIRTGPU_PARAM_CAPSET_QUERY_FIX 2DRM_IOCTL_VIRTGPU_EXECBUFFER DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER, struct drm_virtgpu_execbuffer)DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2')DRM_FORMAT_MOD_VENDOR_AMD 0x02CLONE_SETTLS 0x00080000CPU_ALLOC(count) __CPU_ALLOC (count)__pthread_internal_list__prevDRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5)AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21BO_USE_LINEAR (1ull << 4)refcountis_test_bufferDRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9')CLOCK_MONOTONIC_COARSE 6AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1VIRTGPU_EXECBUF_FENCE_FD_OUT 0x02DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5')sizesPTHREAD_CREATE_JOINABLE PTHREAD_CREATE_JOINABLE__fourcc_mod_amlogic_layout_mask 0xffDRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2')BO_USE_SW_WRITE_OFTEN (1ull << 11)AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0)AMD_FMT_MOD_DCC_SHIFT 13DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0')DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0')DRV_MAX_PLANES 4BO_USE_GPU_DATA_BUFFER (1ull << 18)__timezoneDRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4')BO_USE_SW_READ_OFTEN (1ull << 9)CLONE_VM 0x00000100BO_USE_HW_VIDEO_ENCODER (1ull << 14)CPU_SET_S(cpu,setsize,cpusetp) __CPU_SET_S (cpu, setsize, cpusetp)DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1')PTHREAD_CREATE_DETACHED PTHREAD_CREATE_DETACHEDADJ_FREQUENCY 0x0002AFRC_FORMAT_MOD_CU_SIZE_P12(__afrc_cu_size) ((__afrc_cu_size) << 4)CLOCK_BOOTTIME_ALARM 9DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0')MOD_CLKB ADJ_TICKDRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) fourcc_mod_broadcom_code(4, v)pthread_cleanup_push(routine,arg) do { __pthread_unwind_buf_t __cancel_buf; void (*__cancel_routine) (void *) = (routine); void *__cancel_arg = (arg); int __not_first_call = __sigsetjmp ((struct __jmp_buf_tag *) (void *) __cancel_buf.__cancel_jmp_buf, 0); if (__glibc_unlikely (__not_first_call)) { __cancel_routine (__cancel_arg); __pthread_unwind_next (&__cancel_buf); } __pthread_register_cancel (&__cancel_buf); do {DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V')CLONE_PTRACE 0x00002000VIRTGPU_WAIT_NOWAIT 1BO_USE_TEXTURE (1ull << 5)VIRTGPU_PARAM_3D_FEATURES 1DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V')CPU_ZERO(cpusetp) __CPU_ZERO_S (sizeof (cpu_set_t), cpusetp)__nextDRM_IOCTL_VIRTGPU_RESOURCE_CREATE_BLOB DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE_BLOB, struct drm_virtgpu_resource_create_blob)AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8)AFBC_FORMAT_MOD_DB (1ULL << 10)__fourcc_mod_amlogic_options_mask 0xffDRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H')DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0')AMD_FMT_MOD_PIPE_MASK 0x7ADJ_TIMECONST 0x0020metaMOD_OFFSET ADJ_OFFSETBO_USE_CAMERA_WRITE (1ull << 6)CLOCK_MONOTONIC 1DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ')_BITS_CPU_SET_H 1DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2')VIRTGPU_RESOURCE_INFO_TYPE_EXTENDED 1AMD_FMT_MOD_GET(field,value) (((value) >> AMD_FMT_MOD_ ##field ##_SHIFT) & AMD_FMT_MOD_ ##field ##_MASK)BO_QUIRK_DUMB32BPP (1ull << 0)VIRTGPU_PARAM_CROSS_DEVICE 5DRM_IOCTL_VIRTGPU_RESOURCE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE, struct drm_virtgpu_resource_create)CPU_OR_S(setsize,destset,srcset1,srcset2) __CPU_OP_S (setsize, destset, srcset1, srcset2, |)PTHREAD_SCOPE_SYSTEM PTHREAD_SCOPE_SYSTEMDRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')STA_PLL 0x0001PTHREAD_CANCEL_DEFERRED PTHREAD_CANCEL_DEFERREDVIRTGPU_BLOB_MEM_HOST3D 0x0002DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6')I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)memory_idx__cleanup_fct_attribute DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2')_drv_log(level,format,...) do { drv_log_prefix(level, "minigbm", __FILE__, __LINE__, format, ##__VA_ARGS__); } while (0)DRM_FORMAT_RESERVED ((1ULL << 56) - 1)LINEAR_METADATA (struct format_metadata) { 1, 0, DRM_FORMAT_MOD_LINEAR }AFBC_FORMAT_MOD_TILED (1ULL << 8)DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD)DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2')I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)STA_PPSJITTER 0x0200PTHREAD_PROCESS_SHARED PTHREAD_PROCESS_SHAREDDRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H')ADJ_STATUS 0x0010DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4')STA_PPSFREQ 0x0002I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7BO_USE_NONE 0VIRTGPU_DRM_H __CPU_SETSIZE 1024DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2')drv_log_prefixAFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL)BO_MAP_READ_WRITE (BO_MAP_READ | BO_MAP_WRITE)DRM_FORMAT_MOD_ARM_AFRC(__afrc_mode) DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFRC, __afrc_mode)DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6')MOD_TIMECONST ADJ_TIMECONSTAMD_FMT_MOD_DCC_MASK 0x1CPU_OR(destset,srcset1,srcset2) __CPU_OP_S (sizeof (cpu_set_t), destset, srcset1, srcset2, |)PTHREAD_PROCESS_PRIVATE PTHREAD_PROCESS_PRIVATE/source/platform/minigbm/virtgpu.cmap_flagsDRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6')I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)AFBC_FORMAT_MOD_SC (1ULL << 9)BO_USE_ARC_SCREEN_CAP_PROBED (1ull << 63)SCHED_FIFO 1__CPU_OP_S(setsize,destset,srcset1,srcset2,op) (__extension__ ({ cpu_set_t *__dest = (destset); const __cpu_mask *__arr1 = (srcset1)->__bits; const __cpu_mask *__arr2 = (srcset2)->__bits; size_t __imax = (setsize) / sizeof (__cpu_mask); size_t __i; for (__i = 0; __i < __imax; ++__i) ((__cpu_mask *) __dest->__bits)[__i] = __arr1[__i] op __arr2[__i]; __dest; }))BO_USE_SENSOR_DIRECT_DATA (1ull << 19)getdate_errAMD_FMT_MOD_TILE_VERSION_SHIFT 0AFBC_FORMAT_MOD_BCH (1ULL << 11)DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4)__CPU_EQUAL_S(setsize,cpusetp1,cpusetp2) (__builtin_memcmp (cpusetp1, cpusetp2, setsize) == 0)ADJ_OFFSET_SINGLESHOT 0x8001CPU_AND(destset,srcset1,srcset2) __CPU_OP_S (sizeof (cpu_set_t), destset, srcset1, srcset2, &)DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0')BO_USE_SW_READ_RARELY (1ull << 10)BO_MAP_WRITE (1 << 1)CPU_ALLOC_SIZE(count) __CPU_ALLOC_SIZE (count)DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3SCHED_IDLE 5BO_USE_PROTECTED (1ull << 8)__fourcc_mod_broadcom_param_bits 48SCHED_RESET_ON_FORK 0x40000000STA_PPSSIGNAL 0x0100CSIGNAL 0x000000ffDRM_FORMAT_YVU420_ANDROID fourcc_code('9', '9', '9', '7')DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07fourcc_mod_broadcom_param(m) ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))AFRC_FORMAT_MOD_CU_SIZE_MASK 0xfAMD_FMT_MOD_PACKERS_MASK 0x7DRM_VIRTGPU_TRANSFER_TO_HOST 0x07DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2')virtgpu_paramDRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0')BO_USE_RENDERING (1ull << 2)STA_FLL 0x0008map_infoAFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)__fourcc_mod_amlogic_options_shift 8BO_USE_RENDER_MASK (BO_USE_LINEAR | BO_USE_RENDERING | BO_USE_RENDERSCRIPT | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN | BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY | BO_USE_TEXTURE | BO_USE_FRONT_RENDERING)DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6')TIMER_ABSTIME 1AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1DRM_IOCTL_VIRTGPU_RESOURCE_INFO_CROS DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, struct drm_virtgpu_resource_info_cros)MOD_MAXERROR ADJ_MAXERROR__nusersCLOCK_THREAD_CPUTIME_ID 3AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15__itimerspec_defined 1DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2')STA_INS 0x0010SCHED_BATCH 3drmIoctlDRM_VIRTGPU_CONTEXT_INIT 0x0bBO_USE_FRONT_RENDERING (1ull << 16)CLONE_DETACHED 0x00400000DRM_IOCTL_VIRTGPU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM, struct drm_virtgpu_getparam)CPU_FREE(cpuset) __CPU_FREE (cpuset)CLONE_NEWCGROUP 0x02000000DRM_IOCTL_VIRTGPU_RESOURCE_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, struct drm_virtgpu_resource_info)DRM_VIRTGPU_RESOURCE_INFO 0x05DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H')CLONE_IO 0x80000000AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2')CLOCK_REALTIME 0DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5')_BITS_SETJMP_H 1CPU_CLR_S(cpu,setsize,cpusetp) __CPU_CLR_S (cpu, setsize, cpusetp)CPU_COUNT_S(setsize,cpusetp) __CPU_COUNT_S (setsize, cpusetp)DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL)I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)CLONE_FILES 0x00000400PTHREAD_INHERIT_SCHED PTHREAD_INHERIT_SCHEDDRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST, struct drm_virtgpu_3d_transfer_from_host)MOD_FREQUENCY ADJ_FREQUENCYDRV_H_ DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5')DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ')DRM_VIRTGPU_GET_CAPS 0x09VIRTGPU_BLOB_FLAG_CREATE_GUEST_HANDLE 0x0008MOD_CLKA ADJ_OFFSET_SINGLESHOTDRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1')DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST, struct drm_virtgpu_3d_transfer_to_host)VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK 0x0003DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2')DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0')STA_PPSWANDER 0x0400DRM_VIRTGPU_WAIT 0x08VIRTGPU_EXECBUF_FENCE_FD_IN 0x01DRM_FORMAT_BIG_ENDIAN (1U<<31)DRM_FORMAT_MOD_BROADCOM_SAND128 DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0)__int32_tDRM_VIRTGPU_RESOURCE_CREATE_BLOB 0x0aCLONE_UNTRACED 0x00800000__daylightDRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4')fourcc_mod_broadcom_mod(m) ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << __fourcc_mod_broadcom_param_shift))CPU_COUNT(cpusetp) __CPU_COUNT_S (sizeof (cpu_set_t), cpusetp)SCHED_DEADLINE 6AMD_FMT_MOD_RB_MASK 0x7_BITS_SCHED_H 1CLOCK_PROCESS_CPUTIME_ID 2DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2')DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0')SCHED_ISO 4MOD_ESTERROR ADJ_ESTERRORDRM_VIRTGPU_TRANSFER_FROM_HOST 0x06DRM_FORMAT_MOD_ARM_TYPE_AFRC 0x02ADJ_SETOFFSET 0x0100STA_NANO 0x2000AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL)physical_device_idx__CPUELT(cpu) ((cpu) / __NCPUBITS)DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1)DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c,s,g,k,h) fourcc_mod_code(NVIDIA, (0x10 | ((h) & 0xf) | (((k) & 0xff) << 12) | (((g) & 0x3) << 20) | (((s) & 0x1) << 22) | (((c) & 0x7) << 23)))pthread_cleanup_push_defer_np(routine,arg) do { __pthread_unwind_buf_t __cancel_buf; void (*__cancel_routine) (void *) = (routine); void *__cancel_arg = (arg); int __not_first_call = __sigsetjmp ((struct __jmp_buf_tag *) (void *) __cancel_buf.__cancel_jmp_buf, 0); if (__glibc_unlikely (__not_first_call)) { __cancel_routine (__cancel_arg); __pthread_unwind_next (&__cancel_buf); } __pthread_register_cancel_defer (&__cancel_buf); do {DRM_IOCTL_VIRTGPU_GET_CAPS DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, struct drm_virtgpu_get_caps)lengthAMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18DRM_VIRTGPU_MAP 0x01DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILEAMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16AMD_FMT_MOD_DCC_BLOCK_64B 0__listSTA_RONLY (STA_PPSSIGNAL | STA_PPSJITTER | STA_PPSWANDER | STA_PPSERROR | STA_CLOCKERR | STA_NANO | STA_MODE | STA_CLK)AFBC_FORMAT_MOD_SPLIT (1ULL << 5)PTHREAD_SCOPE_PROCESS PTHREAD_SCOPE_PROCESSCLONE_CHILD_SETTID 0x01000000DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2')BO_QUIRK_NONE 0CLONE_THREAD 0x00010000DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03DRM_VIRTGPU_EXECBUFFER 0x02VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H')I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)AMD_FMT_MOD_TILE_GFX9_64K_D_X 26AFRC_FORMAT_MOD_CU_SIZE_P0(__afrc_cu_size) (__afrc_cu_size)ADJ_MICRO 0x1000DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1')PTHREAD_ERRORCHECK_MUTEX_INITIALIZER_NP { { 0, 0, 0, 0, PTHREAD_MUTEX_ERRORCHECK_NP, __PTHREAD_SPINS, { 0, 0 } } }CLONE_CHILD_CLEARTID 0x00200000DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4')_BITS_TIME_H 1pthread_cleanup_pop_restore_np(execute) do { } while (0); } while (0); __pthread_unregister_cancel_restore (&__cancel_buf); if (execute) __cancel_routine (__cancel_arg); } while (0)AFBC_FORMAT_MOD_CBR (1ULL << 7)__CPU_ALLOC(count) __sched_cpualloc (count)ADJ_OFFSET 0x0001__CPU_FREE(cpuset) __sched_cpufree (cpuset)virtgpu_backendsDRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0aDRM_VIRTGPU_RESOURCE_CREATE 0x04map_strides__CPU_COUNT_S(setsize,cpusetp) __sched_cpucount (setsize, cpusetp)DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3)DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6')DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2')DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V')__CPU_ISSET_S(cpu,setsize,cpusetp) (__extension__ ({ size_t __cpu = (cpu); __cpu / 8 < (setsize) ? ((((const __cpu_mask *) ((cpusetp)->__bits))[__CPUELT (__cpu)] & __CPUMASK (__cpu))) != 0 : 0; }))CLONE_FS 0x00000200AMD_FMT_MOD_PIPE_SHIFT 33DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5')AMD_FMT_MOD_DCC_BLOCK_256B 2STA_PPSERROR 0x0800DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4')DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8')DRM_FORMAT_MOD_AMLOGIC_FBC(__layout,__options) fourcc_mod_code(AMLOGIC, ((__layout) & __fourcc_mod_amlogic_layout_mask) | (((__options) & __fourcc_mod_amlogic_options_mask) << __fourcc_mod_amlogic_options_shift))DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED fourcc_code('9', '9', '9', '8')PTHREAD_RWLOCK_INITIALIZER { { 0, 0, 0, 0, 0, 0, 0, 0, __PTHREAD_RWLOCK_ELISION_EXTRA, 0, 0 } }DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6')I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9)DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0')DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9')AMD_FMT_MOD_TILE_GFX9_64K_S_X 25DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2')AMD_FMT_MOD_CLEAR(field) (~((uint64_t)AMD_FMT_MOD_ ##field ##_MASK << AMD_FMT_MOD_ ##field ##_SHIFT))DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0')DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4')AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xfDRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6')DRM_FORMAT_MOD_VENDOR_ARM 0x08PTHREAD_BARRIER_SERIAL_THREAD -1PTHREAD_RWLOCK_WRITER_NONRECURSIVE_INITIALIZER_NP { { 0, 0, 0, 0, 0, 0, 0, 0, __PTHREAD_RWLOCK_ELISION_EXTRA, 0, PTHREAD_RWLOCK_PREFER_WRITER_NONRECURSIVE_NP } }AMD_FMT_MOD_PACKERS_SHIFT 27DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ')CPU_ZERO_S(setsize,cpusetp) __CPU_ZERO_S (setsize, cpusetp)DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4')BO_USE_TEST_ALLOC (1ull << 15)DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5')DRM_FORMAT_INVALID 0DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y')DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)AMD_FMT_MOD_DCC_RETILE_MASK 0x1DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8')DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y')DRM_FORMAT_MOD_VENDOR_NONE 0DRM_IOCTL_VIRTGPU_CONTEXT_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_CONTEXT_INIT, struct drm_virtgpu_context_init)BO_USE_SW_WRITE_RARELY (1ull << 12)DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2')DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00combosVIRTGPU_BLOB_MEM_HOST3D_GUEST 0x0003__CPU_ALLOC_SIZE(count) ((((count) + __NCPUBITS - 1) / __NCPUBITS) * sizeof (__cpu_mask))STA_MODE 0x4000VIRTGPU_BLOB_FLAG_CREATE_GUEST_CONTIG 0x0010CPU_SET(cpu,cpusetp) __CPU_SET_S (cpu, sizeof (cpu_set_t), cpusetp)BO_USE_SW_MASK (BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN | BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY | BO_USE_FRONT_RENDERING)BO_MAP_READ (1 << 0)CLONE_NEWUSER 0x10000000DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) fourcc_mod_broadcom_code(5, v)DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')__CPUMASK(cpu) ((__cpu_mask) 1 << ((cpu) % __NCPUBITS))CLONE_PARENT_SETTID 0x00100000DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U')drv_arrayMOD_NANO ADJ_NANOBO_USE_RENDERSCRIPT (1ull << 17)plane_widthMCL_CURRENT 1MAP_HUGETLB 0x40000MREMAP_FIXED 2MAP_TYPE 0x0fdrv_num_planes_from_formatPROT_EXEC 0x4MADV_DOFORK 11POSIX_MADV_SEQUENTIAL 2drv_modify_linear_combinationsPOSIX_MADV_WILLNEED 3MADV_KEEPONFORK 19drv_vertical_subsampling_from_formatout_formatdrv_height_from_formatMS_SYNC 4drv_num_planes_from_modifierdrv_add_combinationdrm_mode_create_dumbMADV_DONTDUMP 16PROT_GROWSUP 0x02000000drm_prime_handledrv_dumb_bo_create_exmmap64MADV_DODUMP 17out_use_flagsPKEY_DISABLE_ACCESS 0x1MLOCK_ONFAULT 1Ustatic_assertMADV_DONTFORK 10PROT_NONE 0x0MADV_MERGEABLE 12PROT_READ 0x1MCL_FUTURE 2drv_gem_bo_destroybiplanar_yuv_p010_layoutdrv_add_combinationsMAP_HUGE_SHIFT 26packed_3bpp_layoutMAP_PRIVATE 0x02assert_perror(errnum) (!(errnum) ? __ASSERT_VOID_CAST (0) : __assert_perror_fail ((errnum), __FILE__, __LINE__, __ASSERT_FUNCTION))MAP_GROWSDOWN 0x00100MAP_STACK 0x20000PAGE_SIZE 0x1000drv_pick_modifierMAP_FIXED 0x10drv_array_at_idxMAP_NORESERVE 0x04000drv_has_modifierdrv_size_from_formatnum_formatsquirksMADV_REMOVE 9__s32drv_dumb_bo_createMAP_ANON MAP_ANONYMOUSMADV_FREE 8drm_gem_closedrv_bo_from_formatdrv_stride_from_formatMADV_HWPOISON 100pitchMAP_FAILED ((void *) -1)MAP_FILE 0MAP_DENYWRITE 0x00800DRV_ARRAY_HELPERS_H MAP_FIXED_NOREPLACE 0x100000POSIX_MADV_RANDOM 1MADV_HUGEPAGE 14biplanar_yuv_420_layout__assert_failMAP_HUGE_MASK 0x3fsubsample_strideassert(expr) ((expr) ? __ASSERT_VOID_CAST (0) : __assert_fail (#expr, __FILE__, __LINE__, __ASSERT_FUNCTION))MS_ASYNC 1_ASSERT_H_DECLS PKEY_DISABLE_WRITE 0x2drv_array_appendMCL_ONFAULT 4static_assert _Static_assertdrv_prime_bo_importdrm_mode_destroy_dumbcomboMAP_SYNC 0x80000stride_alignMAP_POPULATE 0x08000drv_bo_munmapmodifier_orderMAP_SHARED_VALIDATE 0x03drm_mode_map_dumbhorizontal_subsamplingdrv_resolve_format_and_use_flags_helperDRV_HELPERS_H MAP_EXECUTABLE 0x01000aligned_widthMS_INVALIDATE 2MREMAP_MAYMOVE 1/source/platform/minigbm/drv_helpers.cMFD_CLOEXEC 1UMFD_ALLOW_SEALING 2UMADV_UNMERGEABLE 13bytes_per_pixelpacked_4bpp_layoutPOSIX_MADV_DONTNEED 4MADV_NOHUGEPAGE 15drv_array_size_ASSERT_H 1MAP_NONBLOCK 0x10000planar_layoutPROT_WRITE 0x2drv_modify_combinationaligned_heighttriplanar_yuv_420_layoutMADV_WIPEONFORK 18drv_get_protdrv_dumb_bo_mapMFD_HUGETLB 4Upacked_2bpp_layout__ASSERT_VOID_CAST (void)drv_bytes_per_pixel_from_formatlayout_from_formatMAP_ANONYMOUS 0x20vertical_subsampling__ASSERT_FUNCTION __extension__ __PRETTY_FUNCTION__MAP_SHARED 0x01drv_dumb_bo_destroyPOSIX_MADV_NORMAL 0format_metadatadrv_bo_from_format_and_paddingpacked_1bpp_layoutorder_countMAP_LOCKED 0x02000_SYS_MMAN_H 1PROT_GROWSDOWN 0x01000000mmappacked_8bpp_layout/source/platform/minigbm/dri.cdrv_dataGBM_BO_FORMAT_ARGB8888drv_bo_mapgbm_bo_mapdrv_bo_get_widthgbm_bo_newgbm_surface_has_free_buffersdrv_bo_get_plane_stridecallocGBM_BO_TRANSFER_READ_WRITEGBM_BO_USE_SENSOR_DIRECT_DATAdrv_get_combinationgbm_surface_create_with_modifiersdrv_bo_get_plane_handlegbm_bo_get_stride_for_planedrv_bo_destroygbm_format_name_descgbm_bo_unmapgbm_device_destroygbm_format_canonicalizedrv_bo_importgbm_bo_createGBM_BO_USE_CAMERA_READgbm_surface_destroyGBM_BO_USE_GPU_DATA_BUFFERgbm_surface_release_buffermap_datamallocGBM_BO_USE_FRONT_RENDERINGgbm_bo_get_plane_sizeGBM_BO_USE_PROTECTEDGBM_BO_USE_SW_READ_RARELYGBM_BO_USE_LINEARdrv_bo_creategbm_bo_formatgbm_bo_get_offsetGBM_BO_FORMAT_XRGB8888GBM_BO_TRANSFER_WRITEgbm_convert_usageGBM_BO_USE_HW_VIDEO_ENCODERGBM_BO_USE_TEXTURINGgbm_bo_set_user_datagbm_bo_transfer_flagsGBM_BO_USE_SW_READ_OFTENGBM_BO_USE_CURSORGBM_PRIV_H gbm_formatgbm_bo_flagsGBM_BO_USE_WRITEdrv_createGBM_HELPERS_H gbm_bo_get_user_datagbm_bo_get_plane_countgbm_bo_destroyGBM_BO_USE_SW_WRITE_RARELYgbm_bo_get_widthgbm_bo_get_handleGBM_BO_USE_CAMERA_WRITEnum_fdsgbm_bo_map2drv_get_fddrv_bo_get_formatgbm_bo_get_formatgbm_bo_get_fd_for_plane/source/platform/minigbm/gbm.cgbm_device_get_format_modifier_plane_countdrv_bo_get_heightgbm_bo_importgbm_bo_get_devicegbm_bo_get_heightgbm_device_get_fdGBM_BO_USE_SW_WRITE_OFTENgbm_bo_get_handle_for_planedrv_bo_get_num_planesGBM_BO_USE_CURSOR_64X64GBM_BO_TRANSFER_READGBM_TEST_ALLOCdrv_bo_get_plane_fdGBM_BO_USE_SCANOUTdrv_bo_get_format_modifiergbm_bo_handlegbm_surface_createdestroy_user_datagbm_surfacegbm_bo_get_bppgbm_bo_get_modifierdrv_bo_get_plane_sizedrv_bo_flush_or_unmapgbm_bo_get_stridegbm_bodrv_destroygbm_format_get_namegbm_device_get_backend_nameGBM_BO_USE_RENDERINGgbm_import_fd_modifier_datagbm_import_fd_datagbm_surface_lock_front_bufferdrv_bo_get_plane_offsetgbm_bo_create_with_modifiersgbm_bo_get_plane_fdgbm_device_is_format_supportedgbm_bo_get_fddrv_get_namedrv_bo_create_with_modifiersGBM_BO_USE_HW_VIDEO_DECODER/source/platform/minigbm/vc4.c/source/platform/minigbm/i915.cdrv_bo_get_use_flagsdrv_resource_infobackend_rockchipfree_buffer_table_lockbasenamedrv_array_initbackend_vkmsdrv_preloaddrv_bo_get_tilingdrv_bo_newbackend_synapticsminigbm_debugdrv_get_backendbest/source/platform/minigbm/drv.ccurrbackend_mediatek__gnuc_va_listpthread_mutex_destroy__gr_offsis_test_allocpthread_mutex_lockbackend_nouveaudrmHashCreatedrv_array_destroyfree_driverdrv_bo_releasedrv_bo_acquiredrmHashLookupbackend_mesonexact_matchdrv_bo_get_total_sizedrmHashDestroydrm_versionfiledrmPrimeHandleToFDfree_mappingsstrerrordrv_get_max_texture_2d_sizefree_mappings_locksuccessvfprintflseekbackend_udlbackend_sun4i_drmdrv_resolve_format_and_use_flagsfourcc_internalfree_buffer_tabledrv_bo_flush__stackbackend_komedadrv_bo_unmapdrv_array_removeseek_end__vr_topdrv_bo_invalidate__gr_topbackend_marvelllseek64pthread_mutex_initbackend_evdidrv_get_standard_fourccdrv_bo_mapping_destroygetenv__vr_offsdrv_backend_listpthread_mutex_unlockbackend_radeonpriordrmHashInsertdrmHashDeletestrcmpdestroy_bodrv_num_buffers_per_boVIRGL_FORMAT_R16G16B16A16_FLOATVIRGL_SET_BLEND_COLOR(x) ((x) + 1)VIRGL_PIPE_RES_CREATE_DEPTH 6VIRGL_FORMAT_L16_FLOATVIRGL_OBJ_SHADER_SO_OUTPUT_STREAM(x) (((x) & 0x03) << 0)VIRGL_SET_UNIFORM_BUFFER_RES_HANDLE 5VIRGL_OBJ_SHADER_HDR_SIZE(nso) (5 + ((nso) ? (2 * nso) + 4 : 0))VIRGL_FORMAT_L16A16_SNORMVIRGL_OBJ_SAMPLER_STATE_BORDER_COLOR(x) ((x) + 6)readVIRGL_FORMAT_R8G8B8A8_UNORMVIRGL_SET_SAMPLER_VIEWS_V0_HANDLE 3cur_blob_idVIRGL_QUERY_STATE_WAIT_HOST 2virgl_context_cmdVIRGL_FORMAT_R16_SNORMtexture_buffer_offset_alignmentVIRGL_FORMAT_R32G32B32A32_FLOATVIRGL_FORMAT_R8G8B8X8_SNORMVIRGL_COPY_TRANSFER3D_SRC_RES_HANDLE 12VIRGL_CAP_COMPUTE_SHADER (1 << 7)VIRGL_SET_VERTEX_BUFFER_STRIDE(x) (((x) * 3) + 1)VIRGL_OBJ_RS_S3_LINE_STIPPLE_PATTERN(x) (((x) & 0xffff) << 0)VIRGL_RENDER_CONDITION_HANDLE 1VIRGL_CMD_RCR_DST_LEVEL 2VIRGL_OBJ_RS_S0_FLATSHADE_FIRST(x) (((x) & 0x1) << 4)VIRGL_CMD_RCR_SRC_LEVEL 7VIRGL_CCMD_CREATE_OBJECTmin_smooth_line_widthVIRGL_DRAW_VBO_START 1VIRGL_OBJ_SAMPLER_VIEW_FORMAT 3VIRGL_DRAW_VBO_INDIRECT_STRIDE 17VIRGL_FORMAT_A4B4G4R4_UNORMatomic_flag_test_and_set(PTR) __atomic_test_and_set ((PTR), __ATOMIC_SEQ_CST)VIRGL_OBJ_VERTEX_ELEMENTS_V0_VERTEX_BUFFER_INDEX(x) (((x) * 4) + 4)VIRGL_DRAW_VBO_INDIRECT_DRAW_COUNT_HANDLE 20VIRGL_FORMAT_B4G4R4X4_UNORMVIRGL_DRAW_VBO_COUNT 2VIRGL_OBJ_RS_LINE_WIDTH 6transfer_boxsample_locationsVIRGL_OBJ_RS_S0_OFFSET_POINT(x) (((x) & 0x1) << 19)VIRGL_FORMAT_S8_UINT_Z24_UNORMVIRGL_OBJ_RS_S3_LINE_STIPPLE_FACTOR(x) (((x) & 0xff) << 16)VIRGL_TRANSFER3D_DIRECTION 13VIRGL_OBJ_RS_S0_BOTTOM_EDGE_RULE(x) (((x) & 0x1) << 30)VIRGL_FORMAT_L16_SINTVIRGL_FORMAT_A32_UINTmax_smooth_point_sizeVIRGL_PIPE_RES_CREATE_BLOB_ID 11MIN(a,b) ((a) < (b) ? (a) : (b))xfer_paramsVIRGL_TEXTURE_ARRAY_C 11max_uniform_blocksVIRGL_OBJ_CLEAR_DEPTH_1 7VIRGL_RESOURCE_IW_STRIDE 4virgl_formatsVIRGL_OBJ_RS_S0_FRONT_CCW(x) (((x) & 0x1) << 15)VIRGL_SET_ATOMIC_BUFFER_LENGTH(x) ((x) * VIRGL_SET_ATOMIC_BUFFER_ELEMENT_SIZE + 3)VIRGL_FORMAT_L32_UINThost_feature_check_versionVIRGL_OBJ_SHADER_SO_STRIDE(x) (6 + (x))VIRGL_OBJ_QUERY_OFFSET 3VIRGL_SET_VIEWPORT_STATE_SCALE_2(x) (4 + (x * 6))max_dual_source_render_targetsVIRGL_FORMAT_L16A16_UINTVIRGL_OBJ_VERTEX_ELEMENTS_V0_SRC_FORMAT(x) (((x) * 4) + 5)VIRGL_CAP_COPY_TRANSFER (1 << 26)max_versioncapability_bitsmin_texture_gather_offsetmax_combined_atomic_countersVIRGL_SET_FRAMEBUFFER_STATE_CBUF_HANDLE(x) ((x) + 3)VIRGL_OBJ_SHADER_NUM_TOKENS 4VIRGL_FORMAT_R8_UNORMVIRGL_FORMAT_R8_SRGBVIRGL_CCMD_SET_UNIFORM_BUFFERVIRGL_RENDER_CONDITION_CONDITION 2atomic_signal_fence(MO) __atomic_signal_fence (MO)VIRGL_CAP_BIND_COMMAND_ARGS (1 << 20)VIRGL_CCMD_CLEARVIRGL_FORMAT_R32G32_UINTVIRGL_FORMAT_A8B8G8R8_UNORMVIRGL_OBJ_SAMPLER_VIEW_BUFFER_FIRST_ELEMENT 4VIRGL_OBJ_BLEND_S2(cbuf) (4 + (cbuf))VIRGL_FORMAT_DXT1_SRGBVIRGL_RESOURCE_IW_DATA_START 12min_texel_offsetVIRGL_OBJ_RS_S3_CLIP_PLANE_ENABLE(x) (((x) & 0xff) << 24)VIRGL_TEXTURE_ARRAY_A 9virgl_bo_invalidateVIRGL_FORMAT_A16_SNORMVIRGL_FORMAT_B8G8R8X8_UNORMVIRGL_FORMAT_A8_UINTvirgl_bo_destroyVIRGL_OBJ_SURFACE_BUFFER_FIRST_ELEMENT 4atomic_thread_fence(MO) __atomic_thread_fence (MO)VIRGL_BIND_CONSTANT_BUFFER (1 << 6)VIRGL_OBJ_DSA_S0_DEPTH_ENABLE(x) (((x) & 0x1) << 0)VIRGL_OBJ_RS_OFFSET_UNITS 7VIRGL_BIND_STAGING (1 << 19)VIRGL_FORMAT_Z32_FLOAT_S8X24_UINTVIRGL_FORMAT_MAXtexture_multisampleVIRGL_OBJ_RS_S0_OFFSET_TRI(x) (((x) & 0x1) << 20)VIRGL_FORMAT_Z24X8_UNORMdrm_virtgpu_3d_transfer_from_hostVIRGL_FORMAT_R8G8B8_SINTVIRGL_BIND_CURSOR (1 << 16)VIRGL_SET_VIEWPORT_STATE_SCALE_1(x) (3 + (x * 6))VIRGL_FORMAT_NV21param_supported_capset_idsVIRGL_FORMAT_L8_SNORMtranslate_formatVIRGL_FORMAT_R16G16_SINTVIRGL_OBJ_STREAMOUT_HANDLE 1VIRGL_COPY_TRANSFER3D_SIZE 14bitmask_indexVIRGL_SET_CLIP_STATE_SIZE 32VIRGL_SET_SAMPLER_VIEWS_START_SLOT 2VIRGL_FORMAT_R16G16_SNORMVIRGL_BIND_VERTEX_BUFFER (1 << 4)VIRGL_CMD_BLIT_DST_Y 8virgl_capsblob_memvirgl_3d_bo_mapVIRGL_FORMAT_B5G5R5X1_UNORMATOMIC_LLONG_LOCK_FREE __GCC_ATOMIC_LLONG_LOCK_FREEVIRGL_OBJ_SAMPLER_STATE_HANDLE 1ATOMIC_CHAR32_T_LOCK_FREE __GCC_ATOMIC_CHAR32_T_LOCK_FREEshader_buffer_offset_alignmentVIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_SIZE 2VIRGL_LAUNCH_GRID_Y 5VIRGL_QUERY_RESULT_WAIT 2VIRGL_PIPE_RES_CREATE_FORMAT 2VIRGL_OBJ_BLEND_S2_RT_ALPHA_DST_FACTOR(x) (((x) & 0x1f) << 22)VIRGL_OBJ_SHADER_SO_OUTPUT_START_COMPONENT(x) (((x) & 0x3) << 8)VIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_LAYERS(x) (x & 0xffff)VIRGL_CCMD_SET_CONSTANT_BUFFERVIRGL_OBJ_SHADER_TYPE 2VIRGL_OBJ_SAMPLER_STATE_SIZE 9VIRGL_TEXTURE_BARRIER_FLAGS 1VIRGL_CCMD_SET_INDEX_BUFFERVIRGL_DRAW_VBO_DRAWID 14VIRGL_CCMD_DESTROY_OBJECTVIRGL_FORMAT_L32A32_SINTVIRGL_CAP_3D_ASTC (1 << 24)VIRGL_FORMAT_L8_UINTVIRGL_OBJ_BLEND_S1 3VIRGL_SET_TWEAKS_SIZE 2VIRGL_OBJ_DSA_S1_STENCIL_FUNC(x) (((x) & 0x7) << 1)VIRGL_QUERY_STATE_DONE 1VIRGL_FORMAT_R16G16B16X16_SINTVIRGL_RESOURCE_IW_W 9VIRGL_FORMAT_R32G32B32_UINTVIRGL_QUERY_RESULT_SIZE 2VIRGL_CCMD_SET_SAMPLE_MASKmax_aliased_point_sizeVIRGL_SET_STENCIL_REF 1VIRGL_SET_SCISSOR_MINX_MINY(x) (2 + (x * 2))VIRGL_FORMAT_RGTC2_SNORMVIRGL_OBJ_DSA_S1_STENCIL_ENABLED(x) (((x) & 0x1) << 0)VIRGL_OBJ_DSA_S0_DEPTH_WRITEMASK(x) (((x) & 0x1) << 1)VIRGL_FORMAT_L8A8_UNORMVIRGL_MAX_CLIP_PLANES 8VIRGL_CMD_BLIT_DST_RES_HANDLE 4atomic_fetch_sub_explicit(PTR,VAL,MO) __atomic_fetch_sub ((PTR), (VAL), (MO))VIRGL_DRAW_VBO_INDIRECT_DRAW_COUNT 18atomic_store_explicit(PTR,VAL,MO) __extension__ ({ __auto_type __atomic_store_ptr = (PTR); __typeof__ (*__atomic_store_ptr) __atomic_store_tmp = (VAL); __atomic_store (__atomic_store_ptr, &__atomic_store_tmp, (MO)); })atomic_init(PTR,VAL) atomic_store_explicit (PTR, VAL, __ATOMIC_RELAXED)VIRGL_CCMD_DRAW_VBOatomic_fetch_or_explicit(PTR,VAL,MO) __atomic_fetch_or ((PTR), (VAL), (MO))VIRGL_BIND_SAMPLER_STATES_S0_HANDLE 3VIRGL_SET_SHADER_IMAGE_ACCESS(x) ((x) * VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE + 4)VIRGL_OBJ_RS_OFFSET_CLAMP 9VIRGL_OBJ_DSA_S0 2compute_virgl_bind_flagsVIRGL_SET_ATOMIC_BUFFER_RES_HANDLE(x) ((x) * VIRGL_SET_ATOMIC_BUFFER_ELEMENT_SIZE + 4)VIRGL_OBJ_RS_S3 5VIRGL_CMD_BLIT_S0_MASK(x) (((x) & 0xff) << 0)bit_indexVIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_WIDTH(x) (x & 0xffff)VIRGL_SET_VERTEX_BUFFERS_SIZE(num_buffers) ((num_buffers) * 3)VIRGL_SET_SHADER_BUFFER_OFFSET(x) ((x) * VIRGL_SET_SHADER_BUFFER_ELEMENT_SIZE + 3)VIRGL_OBJ_BLEND_S0_ALPHA_TO_COVERAGE(x) (((x) & 0x1) << 3)max_compute_block_sizeVIRGL_OBJ_RS_HANDLE 1ATOMIC_POINTER_LOCK_FREE __GCC_ATOMIC_POINTER_LOCK_FREEVIRGL_FORMAT_R8_SINTatomic_compare_exchange_weak_explicit(PTR,VAL,DES,SUC,FAIL) __extension__ ({ __auto_type __atomic_compare_exchange_ptr = (PTR); __typeof__ (*__atomic_compare_exchange_ptr) __atomic_compare_exchange_tmp = (DES); __atomic_compare_exchange (__atomic_compare_exchange_ptr, (VAL), &__atomic_compare_exchange_tmp, 1, (SUC), (FAIL)); })VIRGL_BIND_MINIGBM_HW_VIDEO_ENCODER (1 << 27)bsetVIRGL_CCMD_SET_SCISSOR_STATEVIRGL_LAUNCH_INDIRECT_HANDLE 7VIRGL_OBJ_SAMPLE_STATE_S0_SEAMLESS_CUBE_MAP(x) (((x) & 0x1) << 19)VIRGL_OBJ_SAMPLER_VIEW_TEXTURE_LEVEL 5VIRGL_CMD_RCR_SRC_X 8VIRGL_CCMD_MEMORY_BARRIERvirgl_bindgem_mapseamless_cube_mapVIRGL_SET_ATOMIC_BUFFER_START_SLOT 1max_shader_image_frag_computeVIRGL_SET_SHADER_IMAGE_LAYER_OFFSET(x) ((x) * VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE + 5)atomic_fetch_or(PTR,VAL) __atomic_fetch_or ((PTR), (VAL), __ATOMIC_SEQ_CST)VIRGL_SET_SAMPLER_VIEWS_SHADER_TYPE 1ATOMIC_INT_LOCK_FREE __GCC_ATOMIC_INT_LOCK_FREEVIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_LAYERS_SAMPLES 2VIRGL_CAP_SRGB_WRITE_CONTROL (1 << 15)max_compute_shared_memory_sizepolygon_offset_clampparam_maxcolor_clampingVIRGL_CCMD_SET_SHADER_IMAGESmax_combined_atomic_counter_buffersVIRGL_CCMD_SET_SHADER_BUFFERSc_plane_heightVIRGL_CMD_BLIT_DST_X 7drm_virtgpu_mapVIRGL_OBJ_DSA_S1_STENCIL_ZFAIL_OP(x) (((x) & 0x7) << 10)max_geom_total_output_componentsATOMIC_WCHAR_T_LOCK_FREE __GCC_ATOMIC_WCHAR_T_LOCK_FREEVIRGL_FORMAT_R16G16B16X16_UNORMdrm_virtgpu_3d_waitVIRGL_PIPE_RES_CREATE_LAST_LEVEL 8max_shader_buffer_frag_computeVIRGL_CCMD_NOPVIRGL_CCMD_SET_SUB_CTXVIRGL_DRAW_VBO_VERTICES_PER_PATCH 13VIRGL_OBJ_DSA_S1_STENCIL_VALUEMASK(x) (((x) & 0xff) << 13)VIRGL_SET_VERTEX_BUFFER_HANDLE(x) (((x) * 3) + 3)nr_samplesVIRGL_RESOURCE_IW_D 11VIRGL_POLYGON_STIPPLE_P0 1VIRGL_OBJ_CREATE_HEADER 0VIRGL_SET_SHADER_IMAGE_FORMAT(x) ((x) * VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE + 3)VIRGL_PIPE_RES_CREATE_TARGET 1VIRGL_OBJ_BLEND_S0_INDEPENDENT_BLEND_ENABLE(x) ((x) & 0x1 << 0)VIRGL_FORMAT_R8G8_SNORMVIRGL_OBJ_CLEAR_COLOR_2 4VIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_HEIGHT(x) ((x >> 16) & 0xffff)VIRGL_FORMAT_B8G8R8A8_UNORM_EMULATEDmax_texture_3d_sizeVIRGL_BIND_MINIGBM_HW_VIDEO_DECODER (1 << 26)VIRGL_FORMAT_A8_SNORMparam_guest_vramVIRGL_FORMAT_B10G10R10A2_UINTVIRGL_FORMAT_RGTC1_SNORMVIRGL_RESOURCE_IW_Y 7VIRGL_FORMAT_R32_SINTVIRGL_OBJ_QUERY_SIZE 4VIRGL_QUERY_END_HANDLE 1atomic_fetch_add_explicit(PTR,VAL,MO) __atomic_fetch_add ((PTR), (VAL), (MO))VIRGL_CCMD_BIND_OBJECTVIRGL_OBJ_QUERY_INDEX(x) ((x & 0xffff) << 16)VIRGL_OBJ_DESTROY_HANDLE 1drm_virtgpu_resource_info_crosVIRGL_CCMD_DESTROY_SUB_CTXVIRGL_SET_SAMPLER_VIEWS_SIZE(num_views) ((num_views) + 2)VIRGL_LAUNCH_BLOCK_X 1VIRGL_FORMAT_R16G16B16A16_UINTtimer_queryVIRGL_SET_SHADER_IMAGE_START_SLOT 2VIRGL_FORMAT_DXT1_RGBvirgl_3d_get_max_texture_2d_sizeconditional_render_invertedVIRGL_OBJ_DSA_S1_STENCIL_FAIL_OP(x) (((x) & 0x7) << 4)has_tessellation_shadersparam_create_guest_handleparam_resource_blobVIRGL_FORMAT_R8G8_SRGBVIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_SAMPLES(x) ((x >> 16) & 0xff)VIRGL_FORMAT_DXT1_RGBAVIRGL_MEMORY_BARRIER_FLAGS 1max_texture_cube_sizeVIRGL_FORMAT_L16A16_UNORMVIRGL_OBJ_RS_S0_HALF_PIXEL_CENTER(x) (((x) & 0x1) << 29)xfers_neededmin_smooth_point_sizemax_viewportsVIRGL_CAP_TGSI_PRECISE (1 << 4)VIRGL_FORMAT_R16_UNORMVIRGL_QUERY_RESULT_QBO_HANDLE 1VIRGL_CAP_SHADER_CLOCK (1 << 11)VIRGL_FORMAT_R8G8B8X8_SINTVIRGL_FORMAT_R8G8B8X8_UNORMmax_texture_array_layersVIRGL_CCMD_SET_STENCIL_REFVIRGL_DRAW_VBO_INDIRECT_DRAW_COUNT_OFFSET 19VIRGL_FORMAT_BPTC_RGB_UFLOATVIRGL_FORMAT_R9G9B9E5_FLOATVIRGL_CCMD_RESOURCE_INLINE_WRITEVIRGL_BIND_COMMAND_ARGS (1 << 8)VIRGL_CCMD_SET_ATOMIC_BUFFERSVIRGL_FORMAT_R8G8B8A8_SRGBVIRGL_OBJ_SAMPLER_STATE_MIN_LOD 4VIRGL_FORMAT_R32_FLOATvirtio_transfers_paramsVIRGL_OBJ_RS_S0_LIGHT_TWOSIZE(x) (((x) & 0x1) << 5)VIRGL_TEXTURE_ARRAY_B 10atomic_compare_exchange_strong(PTR,VAL,DES) atomic_compare_exchange_strong_explicit (PTR, VAL, DES, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST)render_target_formatsdumb_texture_source_formatsVIRGL_CMD_BLIT_DST_Z 9VIRGL_HW_H VIRGL_OBJ_RS_S0_CLAMP_FRAGMENT_COLOR(x) (((x) & 0x1) << 17)VIRGL_CAP_MEMORY_BARRIER (1 << 6)VIRGL_SET_SAMPLE_MASK_SIZE 1VIRGL_SET_SHADER_BUFFER_START_SLOT 2VIRGL_OBJ_BLEND_S2_RT_ALPHA_SRC_FACTOR(x) (((x) & 0x1f) << 17)VIRGL_PIPE_RES_CREATE_FLAGS 10VIRGL_OBJ_RS_S0_SCISSOR(x) (((x) & 0x1) << 14)VIRGL_TEXTURE_SRC_X 3VIRGL_PROTOCOL_H VIRGL_FORMAT_B10G10R10A2_UNORMVIRGL_DRAW_VBO_SIZE_INDIRECT 20VIRGL_SET_VIEWPORT_START_SLOT 1VIRGL_CMD_BLIT_DST_W 10drm_virtgpu_3d_boxvirgl_supports_combination_through_emulationVIRGL_OBJ_SAMPLER_VIEW_SIZE 6atomic_fetch_xor_explicit(PTR,VAL,MO) __atomic_fetch_xor ((PTR), (VAL), (MO))VIRGL_QUERY_RESULT_QBO_INDEX 6VIRGL_RESOURCE_IW_RES_HANDLE 1VIRGL_CMD_RCR_DST_RES_HANDLE 1VIRGL_FORMAT_R8G8B8X8_SRGBatomic_compare_exchange_strong_explicit(PTR,VAL,DES,SUC,FAIL) __extension__ ({ __auto_type __atomic_compare_exchange_ptr = (PTR); __typeof__ (*__atomic_compare_exchange_ptr) __atomic_compare_exchange_tmp = (DES); __atomic_compare_exchange (__atomic_compare_exchange_ptr, (VAL), &__atomic_compare_exchange_tmp, 0, (SUC), (FAIL)); })VIRGL_FORMAT_R16G16B16X16_FLOATVIRGL_SET_INDEX_BUFFER_OFFSET 3VIRGL_CAP_COPY_IMAGE (1 << 3)VIRGL_OBJ_SAMPLE_STATE_S0_MIN_MIP_FILTER(x) (((x) & 0x3) << 11)atomic_fetch_and_explicit(PTR,VAL,MO) __atomic_fetch_and ((PTR), (VAL), (MO))VIRGL_BIND_DEPTH_STENCIL (1 << 0)virgl_3d_resolve_format_and_use_flagsVIRGL_CAP_TGSI_COMPONENTS (1 << 13)VIRGL_CAP_TRANSFER (1 << 17)VIRGL_CMD_BLIT_SCISSOR_MAXX_MAXY 3VIRGL_CMD_RCR_SRC_D 13VIRGL_FORMAT_L8A8_SRGBVIRGL_SET_ATOMIC_BUFFER_ELEMENT_SIZE 3VIRGL_CMD_BLIT_SRC_FORMAT 15uniform_buffer_offset_alignmentVIRGL_CMD_BLIT_SRC_Z 18VIRGL_LAUNCH_BLOCK_Z 3VIRGL_QUERY_STATE_NEW 0max_streamout_buffersVIRGL_BIND_PREFER_EMULATED_BGRA (1 << 21)VIRGL_CAP_APP_TWEAK_SUPPORT (1 << 28)VIRGL_DRAW_VBO_PRIMITIVE_RESTART 8atomic_fetch_add(PTR,VAL) __atomic_fetch_add ((PTR), (VAL), __ATOMIC_SEQ_CST)VIRGL_CCMD_GET_QUERY_RESULTVIRGL_OBJ_QUERY_TYPE_INDEX 2VIRGL_CAP_TEXTURE_BARRIER (1 << 12)VIRGL_FORMAT_A16_UNORMVIRGL_CMD_BLIT_SRC_W 19VIRGL_FORMAT_X24S8_UINTVIRGL_OBJ_VERTEX_ELEMENTS_HANDLE 1atomic_intVIRGL_FORMAT_R16G16B16_SINTVIRGL_SET_SHADER_IMAGE_LEVEL_SIZE(x) ((x) * VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE + 6)VIRGL_OBJ_RS_S0_FILL_BACK(x) (((x) & 0x3) << 12)VIRGL_BIND_QUERY_BUFFER (1 << 15)VIRGL_OBJ_RS_S0_RASTERIZER_DISCARD(x) (((x) & 0x1) << 3)VIRGL_FORMAT_BPTC_SRGBAVIRGL_FORMAT_A32_FLOATVIRGL_2D_MAX_TEXTURE_2D_SIZE MIN(ANGLE_ON_SWIFTSHADER_MAX_TEXTURE_2D_SIZE, MESA_LLVMPIPE_MAX_TEXTURE_2D_SIZE)VIRGL_CAP_CLIP_HALFZ (1 << 27)VIRGL_CMD_RESOURCE_COPY_REGION_SIZE 13VIRGL_TESS_STATE_SIZE 6VIRGL_FORMAT_A8_UNORMVIRGL_CCMD_PIPE_RESOURCE_CREATEVIRGL_DRAW_VBO_MIN_INDEX 10VIRGL_SET_CONSTANT_BUFFER_DATA_START 3max_texture_gather_componentskill_dependency(Y) __extension__ ({ __auto_type __kill_dependency_tmp = (Y); __kill_dependency_tmp; })VIRGL_TEXTURE_SRC_D 8VIRGL_SET_FRAMEBUFFER_STATE_NR_ZSURF_HANDLE 2VIRGL_OBJ_RS_S0_CULL_FACE(x) (((x) & 0x3) << 8)max_atomic_countersVIRGL_FORMAT_L16A16_FLOATVIRGL_CMD_RCR_SRC_Z 10VIRGL_SET_FRAMEBUFFER_STATE_SIZE(nr_cbufs) (nr_cbufs + 2)VIRGL_FORMAT_MAX_EXTENDEDVIRGL_CMD_RCR_DST_X 3VIRGL_CCMD_BEGIN_QUERYVIRGL_FORMAT_R8G8_SINTATOMIC_BOOL_LOCK_FREE __GCC_ATOMIC_BOOL_LOCK_FREEVIRGL_FORMAT_L8_UNORMVIRGL_SET_SHADER_IMAGE_SIZE(x) (VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE * (x)) + 2VIRGL_SET_ATOMIC_BUFFER_OFFSET(x) ((x) * VIRGL_SET_ATOMIC_BUFFER_ELEMENT_SIZE + 2)VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_R(x) (((x) & 0x7) << 6)VIRGL_TEXTURE_SRC_Y 4VIRGL_FORMAT_R16_FLOATVIRGL_FORMAT_R16G16_UNORMatomic_flag_test_and_set_explicit(PTR,MO) __atomic_test_and_set ((PTR), (MO))VIRGL_PIPE_RES_CREATE_HEIGHT 5max_texture_gather_offsetVIRGL_CCMD_LAUNCH_GRIDVIRGL_CCMD_BIND_SHADERVIRGL_OBJ_RS_S0_SPRITE_COORD_MODE(x) (((x) & 0x1) << 6)VIRGL_SET_VIEWPORT_STATE_TRANSLATE_2(x) (7 + (x * 6))VIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_MODE(x) (((x) & 0x1) << 15)VIRGL_CCMD_COPY_TRANSFER3DVIRGL_OBJ_RS_S0_POLY_SMOOTH(x) (((x) & 0x1) << 21)VIRGL_SET_UNIFORM_BUFFER_OFFSET 3VIRGL_CAP_TGSI_INVARIANT (1 << 0)VIRGL_OBJ_QUERY_RES_HANDLE 4VIRGL_FORMAT_R8G8B8A8_SINTVIRGL_SET_SHADER_BUFFER_SHADER_TYPE 1VIRGL_FORMAT_B2G3R3_UNORMVIRGL_BIND_SCANOUT (1 << 18)next_blob_idvirgl_get_max_texture_2d_sizeVIRGL_FORMAT_A16_UINTis_arc_screen_capture_boVIRGL_SET_INDEX_BUFFER_HANDLE 1VIRGL_OBJ_RS_S0_POINT_QUAD_RASTERIZATION(x) (((x) & 0x1) << 7)max_tbo_sizesupported_readback_formatsVIRGL_OBJ_RS_S0_LINE_LAST_PIXEL(x) (((x) & 0x1) << 28)ATOMIC_VAR_INIT(VALUE) (VALUE)VIRGL_SET_INDEX_BUFFER_INDEX_SIZE 2VIRGL_FORMAT_Z32_UNORM/source/platform/minigbm/virtgpu_virgl.cVIRGL_QUERY_RESULT_HANDLE 1waitcmdmax_texture_lod_biasVIRGL_BIND_DISPLAY_TARGET (1 << 7)VIRGL_OBJ_DSA_ALPHA_REF 5VIRGL_FORMAT_R16G16B16_FLOATvirgl_bitmask_supports_formatVIRGL_OBJ_SAMPLER_STATE_MAX_LOD 5virgl_resource_infoVIRGL_OBJ_SHADER_SO_NUM_OUTPUTS 5VIRGL_SET_SHADER_IMAGE_RES_HANDLE(x) ((x) * VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE + 7)VIRGL_CCMD_SET_BLEND_COLORVIRGL_CMD_BLIT_SRC_H 20VIRGL_PIPE_RES_CREATE_ARRAY_SIZE 7VIRGL_FORMAT_L16_UINTtexture_query_lodVIRGL_SET_TWEAKS_ID 1VIRGL_LAUNCH_GRID_SIZE 8virgl_bo_create_with_modifiersVIRGL_FORMAT_RGTC2_UNORMVIRGL_OBJ_RS_S0_FORCE_PERSAMPLE_INTERP(x) (((x) & 0x1) << 31)VIRGL_SET_SAMPLE_MASK_MASK 1VIRGL_OBJ_RS_S0_LINE_SMOOTH(x) (((x) & 0x1) << 26)VIRGL_OBJ_RS_S0_LINE_STIPPLE_ENABLE(x) (((x) & 0x1) << 27)atomic_fetch_xor(PTR,VAL) __atomic_fetch_xor ((PTR), (VAL), __ATOMIC_SEQ_CST)VIRGL_FORMAT_R32G32B32A32_UINTvertex_element_instance_divisorVIRGL_CCMD_SET_TESS_STATEVIRGL_FORMAT_L8A8_SINTparam_capset_fixVIRGL_OBJ_QUERY_HANDLE 1VIRGL_SET_TWEAKS_VALUE 2VIRGL_CMD_RCR_SRC_W 11ATOMIC_LONG_LOCK_FREE __GCC_ATOMIC_LONG_LOCK_FREEVIRGL_BIND_RENDER_TARGET (1 << 1)VIRGL_OBJ_BLEND_S0_LOGICOP_ENABLE(x) (((x) & 0x1) << 1)VIRGL_FORMAT_R32G32B32_FLOATVIRGL_BIND_SHADER_BUFFER (1 << 14)VIRGL_OBJ_RS_S0_CLIP_HALFZ(x) (((x) & 0x1) << 2)VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_G(x) (((x) & 0x7) << 3)VIRGL_OBJ_RS_S0_POLY_STIPPLE_ENABLE(x) (((x) & 0x1) << 22)atomic_exchange_explicit(PTR,VAL,MO) __extension__ ({ __auto_type __atomic_exchange_ptr = (PTR); __typeof__ (*__atomic_exchange_ptr) __atomic_exchange_val = (VAL); __typeof__ (*__atomic_exchange_ptr) __atomic_exchange_tmp; __atomic_exchange (__atomic_exchange_ptr, &__atomic_exchange_val, &__atomic_exchange_tmp, (MO)); __atomic_exchange_tmp; })VIRGL_TRANSFER3D_SIZE 13virgl_initVIRGL_FORMAT_A16_FLOATVIRGL_BIND_MINIGBM_SW_WRITE_OFTEN (1 << 30)VIRGL_OBJ_VERTEX_ELEMENTS_SIZE(num_elements) (((num_elements) * 4) + 1)xfer_boxesVIRGL_OBJ_BLEND_S0 2VIRGL_CMD_RCR_DST_Z 5VIRGL_OBJ_BLEND_S2_RT_RGB_FUNC(x) (((x) & 0x7) << 1)VIRGL_SET_STREAMOUT_TARGETS_H0 2atomic_fetch_sub(PTR,VAL) __atomic_fetch_sub ((PTR), (VAL), __ATOMIC_SEQ_CST)param_context_initVIRGL_FORMAT_A8R8G8B8_UNORMVIRGL_CMD_BLIT_SIZE 21VIRGL_BIND_SHARED (1 << 20)VIRGL_CMD_BLIT_SRC_RES_HANDLE 13VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_A(x) (((x) & 0x7) << 9)VIRGL_CCMD_SET_SAMPLER_VIEWSmax_vertex_attrib_stridevirgl_get_emulated_metadataPIPE_TEXTURE_2D 2VIRGL_FORMAT_A16_SINTstart_instanceVIRGL_OBJ_SHADER_HANDLE 1VIRGL_OBJ_SHADER_SO_OUTPUT_NUM_COMPONENTS(x) (((x) & 0x7) << 10)VIRGL_OBJ_CLEAR_COLOR_1 3VIRGL_OBJ_SHADER_OFFSET_VAL(x) (((x) & 0x7fffffff) << 0)should_use_blobVIRGL_RESOURCE_IW_H 10VIRGL_CCMD_SET_FRAMEBUFFER_STATE_NO_ATTACHlayer_strideVIRGL_CCMD_SET_FRAMEBUFFER_STATEmax_vertex_attribsVIRGL_OBJ_SHADER_SO_OUTPUT_BUFFER(x) (((x) & 0x7) << 13)VIRGL_FORMAT_R32G32B32A32_SINTVIRGL_CCMD_RESOURCE_COPY_REGIONVIRGL_FORMAT_R16_UINTvirtgpu_param_idVIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_FUNC(x) (((x) & 0x7) << 16)VIRGL_COPY_TRANSFER3D_SRC_RES_OFFSET 13shader_stencil_exportVIRGL_OBJ_SURFACE_HANDLE 1VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE 5VIRGL_CCMD_SET_STREAMOUT_TARGETSVIRGL_CCMD_BLITVIRGL_FORMAT_DXT5_RGBAVIRGL_OBJ_RS_S0 2drm_formatsVIRGL_OBJ_BLEND_S2_RT_RGB_DST_FACTOR(x) (((x) & 0x1f) << 9)VIRGL_FORMAT_S8_UINTVIRGL_FORMAT_R8G8_UNORMVIRGL_FORMAT_R16G16_UINTVIRGL_FORMAT_L16_SNORMVIRGL_DRAW_VBO_INSTANCE_COUNT 5VIRGL_CAP_TGSI_FBFETCH (1 << 10)VIRGL_OBJ_DSA_S0_DEPTH_FUNC(x) (((x) & 0x7) << 2)VIRGL_OBJ_SAMPLE_STATE_S0_MIN_IMG_FILTER(x) (((x) & 0x3) << 9)VIRGL_CMD0_MAX_DWORDS (((1ULL << 16) - 1) / 4) * 4VIRGL_FORMAT_R16G16B16A16_SNORMVIRGL_OBJ_STREAMOUT_RES_HANDLE 2VIRGL_CMD_BLIT_DST_H 11VIRGL_OBJ_BLEND_S2_RT_ALPHA_FUNC(x) (((x) & 0x7) << 14)VIRGL_OBJ_SHADER_SO_OUTPUT0_SO(x) (11 + (x * 2))VIRGL_FORMAT_Z16_UNORMVIRGL_FORMAT_R8G8B8_SNORMVIRGL_FORMAT_RGTC1_UNORMVIRGL_OBJ_BIND_HEADER 0VIRGL_TEXTURE_BARRIER_SIZE 1VIRGL_BIND_MINIGBM_SW_READ_OFTEN (1 << 28)VIRGL_SET_VIEWPORT_STATE_SIZE(num_viewports) ((6 * num_viewports) + 1)VIRGL_OBJ_STREAMOUT_BUFFER_SIZE 4atomic_load_explicit(PTR,MO) __extension__ ({ __auto_type __atomic_load_ptr = (PTR); __typeof__ (*__atomic_load_ptr) __atomic_load_tmp; __atomic_load (__atomic_load_ptr, &__atomic_load_tmp, (MO)); __atomic_load_tmp; })occlusion_queryVIRGL_BIND_SAMPLER_STATES_START_SLOT 2VIRGL_FORMAT_R8G8B8_UINTVIRGL_SET_SCISSOR_START_SLOT 1VIRGL_CLEAR_TEXTURE_SIZE 12VIRGL_SET_SCISSOR_STATE_SIZE(x) (1 + 2 * x)VIRGL_FORMAT_Z32_FLOATVIRGL_FORMAT_L32A32_UINTVIRGL_PIPE_RES_CREATE_NR_SAMPLES 9VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_R(x) (((x) & 0x7) << 0)virgl_add_combinationsinstanceidVIRGL_FORMAT_P010VIRGL_FORMAT_P012virgl_bo_flushVIRGL_FORMAT_P016VIRGL_BIND_SHADER_SIZE 2VIRGL_BIND_SHARED_SUBFLAGS (0xff << 24)VIRGL_BIND_SAMPLER_VIEW (1 << 3)VIRGL_FORMAT_L8_SRGBVIRGL_OBJ_DSA_S1_STENCIL_ZPASS_OP(x) (((x) & 0x7) << 7)VIRGL_OBJ_BLEND_S2_RT_RGB_SRC_FACTOR(x) (((x) & 0x1f) << 4)VIRGL_RESOURCE_IW_LAYER_STRIDE 5VIRGL_CMD_BLIT_SRC_D 21VIRGL_FORMAT_A32_SINTVIRGL_TEXTURE_SRC_Z 5VIRGL_OBJ_STREAMOUT_BUFFER_OFFSET 3VIRGL_OBJ_BLEND_S0_DITHER(x) (((x) & 0x1) << 2)VIRGL_FORMAT_R16G16B16X16_UINTblob_flagstargetbitmaskVIRGL_SET_SHADER_BUFFER_RES_HANDLE(x) ((x) * VIRGL_SET_SHADER_BUFFER_ELEMENT_SIZE + 5)atomic_fetch_and(PTR,VAL) __atomic_fetch_and ((PTR), (VAL), __ATOMIC_SEQ_CST)VIRGL_FORMAT_DXT3_SRGBAVIRGL_MEMORY_BARRIER_SIZE 1has_sample_shadingVIRGL_FORMAT_R16_SINTVIRGL_FORMAT_L32_SINTVIRGL_DRAW_VBO_INDIRECT_OFFSET 16VIRGL_LAUNCH_BLOCK_Y 2VIRGL_OBJ_DSA_S2 4VIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_WIDTH_HEIGHT 1VIRGL_OBJ_RS_S0_FLATSHADE(x) (((x) & 0x1) << 0)seamless_cube_map_per_textureparam_resource_syncVIRGL_BIND_MINIGBM_CAMERA_READ (1 << 25)virgl_3d_bo_createVIRGL_FORMAT_L16A16_SINThas_indirect_drawVIRGL_CMD_BLIT_SCISSOR_MINX_MINY 2VIRGL_FORMAT_R10G10B10A2_UNORMVIRGL_CMD_BLIT_S0_SCISSOR_ENABLE(x) (((x) & 0x1) << 10)VIRGL_CAP_FAKE_FP64 (1 << 19)fragment_coord_conventionsVIRGL_FORMAT_R8_UINTVIRGL_QUERY_RESULT_QBO_QBO_HANDLE 2VIRGL_SET_SHADER_BUFFER_SIZE(x) (VIRGL_SET_SHADER_BUFFER_ELEMENT_SIZE * (x)) + 2VIRGL_OBJ_CLEAR_STENCIL 8param_host_visibleVIRGL_FORMAT_B8G8R8A8_SRGBVIRGL_SET_INDEX_BUFFER_SIZE(ib) (((ib) ? 2 : 0) + 1)VIRGL_FORMAT_BPTC_RGB_FLOATVIRGL_FORMAT_R32G32_SINTsamplerVIRGL_LAUNCH_GRID_X 4VIRGL_OBJ_SAMPLER_STATE_S0 2drm_fourccVIRGL_SET_VIEWPORT_STATE_TRANSLATE_1(x) (6 + (x * 6))VIRGL_CCMD_CREATE_SUB_CTXVIRGL_OBJ_SHADER_SO_OUTPUT0(x) (10 + (x * 2))VIRGL_FORMAT_B10G10R10X2_UNORMATOMIC_SHORT_LOCK_FREE __GCC_ATOMIC_SHORT_LOCK_FREEVIRGL_SET_MIN_SAMPLES_SIZE 1VIRGL_FORMAT_A8_SINTVIRGL_TRANSFER_FROM_HOST 2VIRGL_CCMD_SET_VERTEX_BUFFERSatomic_compare_exchange_weak(PTR,VAL,DES) atomic_compare_exchange_weak_explicit (PTR, VAL, DES, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST)max_geom_output_verticesres_infovirgl_supported_format_maskVIRGL_CAP_TRANSFORM_FEEDBACK3 (1 << 23)virgl_supports_combination_nativelyVIRGL_OBJ_BLEND_SIZE (VIRGL_MAX_COLOR_BUFS + 3)max_atomic_counter_buffersVIRGL_CMD_BLIT_S0_FILTER(x) (((x) & 0x3) << 8)VIRGL_PIPE_RES_CREATE_SIZE 11last_levelVIRGL_DRAW_VBO_START_INSTANCE 7VIRGL_BIND_SAMPLER_STATES(num_states) ((num_states) + 2)glsl_levelVIRGL_SET_CLIP_STATE_C0 1VIRGL_OBJ_RS_SIZE 9host_write_flagsparam_3datomic_flag_clear_explicit(PTR,MO) __atomic_clear ((PTR), (MO))VIRGL_FORMAT_R16G16_FLOATVIRGL_DRAW_VBO_MAX_INDEX 11VIRGL_OBJ_BLEND_S1_LOGICOP_FUNC(x) (((x) & 0xf) << 0)min_aliased_line_widthVIRGL_CMD_BLIT_SRC_Y 17virgl_2d_resolve_format_and_use_flagsVIRGL_FORMAT_R8G8B8A8_SNORMVIRGL_OBJ_BLEND_S2_RT_COLORMASK(x) (((x) & 0xf) << 27)VIRGL_CAP_FBO_MIXED_COLOR_FORMATS (1 << 18)VIRGL_FORMAT_B8G8R8X8_SRGBVIRGL_QUERY_RESULT_QBO_SIZE 6VIRGL_SET_STENCIL_REF_SIZE 1VIRGL_SET_UNIFORM_BUFFER_SHADER_TYPE 1VIRGL_TRANSFER_TO_HOST 1conditional_renderVIRGL_OBJ_DSA_SIZE 5VIRGL_SET_ATOMIC_BUFFER_SIZE(x) (VIRGL_SET_ATOMIC_BUFFER_ELEMENT_SIZE * (x)) + 1VIRGL_OBJ_BLEND_HANDLE 1VIRGL_FORMAT_R32_UINTcap_set_idVIRGL_LAUNCH_INDIRECT_OFFSET 8VIRGL_OBJ_RS_S0_MULTISAMPLE(x) (((x) & 0x1) << 25)VIRGL_OBJ_SHADER_OFFSET_CONT (0x1u << 31)VIRGL_OBJ_SHADER_SO_OUTPUT_REGISTER_INDEX(x) (((x) & 0xff) << 0)virgl_add_combinationmax_compute_grid_sizemax_samplesVIRGL_FORMAT_R10G10B10A2_UINTVIRGL_OBJ_SAMPLER_VIEW_SWIZZLE 6VIRGL_TEXTURE_LEVEL 2VIRGL_OBJ_CLEAR_COLOR_0 2VIRGL_BIND_MINIGBM_SW_WRITE_RARELY (1 << 31)VIRGL_FORMAT_B4G4R4A4_UNORMVIRGL_OBJ_SAMPLER_VIEW_TEXTURE_LAYER 4VIRGL_OBJ_RS_POINT_SIZE 3VIRGL_CAP_QBO (1 << 16)VIRGL_DRAW_VBO_SIZE_TESS 14ATOMIC_CHAR16_T_LOCK_FREE __GCC_ATOMIC_CHAR16_T_LOCK_FREEstreamout_pause_resumeVIRGL_RESOURCE_IW_X 6VIRGL_QUERY_RESULT_QBO_WAIT 3VIRGL_DRAW_VBO_COUNT_FROM_SO 12VIRGL_CCMD_TEXTURE_BARRIERVIRGL_OBJ_DSA_S1_STENCIL_WRITEMASK(x) (((x) & 0xff) << 21)VIRGL_FORMAT_L8_SINTVIRGL_BIND_MINIGBM_SW_READ_RARELY (1 << 29)primitive_restartVIRGL_SET_VIEWPORT_STATE_TRANSLATE_0(x) (5 + (x * 6))VIRGL_CCMD_SET_DEBUG_FLAGSvirgl_bo_mapVIRGL_FORMAT_R32G32B32_SINTvirgl_privvirgl_init_params_and_capsVIRGL_MAX_COLOR_BUFS 8VIRGL_DRAW_VBO_SIZE 12VIRGL_CAP_GUEST_MAY_INIT_LOG (1 << 14)VIRGL_TEXTURE_SRC_H 7drm_formatVIRGL_OBJ_RS_S0_POINT_SIZE_PER_VERTEX(x) (((x) & 0x1) << 24)virgl_formatVIRGL_OBJ_DSA_S1 3host_gbm_enabledVIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_B(x) (((x) & 0x7) << 6)VIRGL_LAUNCH_GRID_Z 6VIRGL_OBJ_SURFACE_FORMAT 3caps_is_v2VIRGL_CCMD_SET_TWEAKSVIRGL_OBJ_STREAMOUT_SIZE 4VIRGL_OBJ_QUERY_TYPE(x) (x & 0xffff)VIRGL_QUERY_BEGIN_HANDLE 1VIRGL_RENDER_CONDITION_SIZE 3y_plane_heightVIRGL_CCMD_END_QUERYVIRGL_OBJ_SAMPLE_STATE_S0_WRAP_T(x) (((x) & 0x7) << 3)VIRGL_CCMD_TRANSFER3Dmax_smooth_line_widthVIRGL_FORMAT_IYUVVIRGL_OBJ_SAMPLER_STATE_LOD_BIAS 3VIRGL_OBJ_SURFACE_TEXTURE_LEVEL 4VIRGL_BIND_SHADER_TYPE 2VIRGL_CMD_BLIT_S0_RENDER_CONDITION_ENABLE(x) (((x) & 0x1) << 11)VIRGL_CMD_RCR_SRC_Y 9VIRGL_TEXTURE_ARRAY_D 12VIRGL_OBJ_SHADER_SO_OUTPUT_DST_OFFSET(x) (((x) & 0xffff) << 16)VIRGL_OBJ_RS_S0_POINT_SMOOTH(x) (((x) & 0x1) << 23)VIRGL_OBJ_SURFACE_SIZE 5scanoutVIRGL_FORMAT_R8_SNORMVIRGL_DRAW_VBO_RESTART_INDEX 9check_flagANGLE_ON_SWIFTSHADER_MAX_TEXTURE_2D_SIZE 8192VIRGL_FORMAT_L32A32_FLOATVIRGL_PIPE_RES_CREATE_WIDTH 4VIRGL_BIND_INDEX_BUFFER (1 << 5)VIRGL_PIPE_RES_CREATE_BIND 3VIRGL_SET_CONSTANT_BUFFER_SHADER_TYPE 1VIRGL_SET_VIEWPORT_STATE_SCALE_0(x) (2 + (x * 6))VIRGL_FORMAT_B8G8R8A8_UNORMVIRGL_OBJ_CREATE_HANDLE 1indep_blend_enableVIRGL_CCMD_SET_POLYGON_STIPPLEVIRGL_CAP_TEXTURE_VIEW (1 << 1)VIRGL_FORMAT_DXT1_SRGBAVIRGL_FORMAT_Z24_UNORM_S8_UINTVIRGL_DRAW_VBO_INDIRECT_HANDLE 15max_shader_patch_varyingsVIRGL_FORMAT_X8R8G8B8_UNORMparam_cross_deviceVIRGL_CMD_RCR_SRC_H 12VIRGL_SET_UNIFORM_BUFFER_LENGTH 4max_combined_shader_buffersVIRGL_CCMD_GET_QUERY_RESULT_QBOVIRGL_DRAW_VBO_MODE 3VIRGL_DRAW_VBO_INDEX_BIAS 6virgl_caps_bool_set1VIRGL_SET_SHADER_IMAGE_SHADER_TYPE 1has_fp64VIRGL_CAP_SET_MIN_SAMPLES (1 << 2)VIRGL_OBJ_CLEAR_COLOR_3 5depthstencilVIRGL_OBJ_CLEAR_SIZE 8VIRGL_OBJ_SURFACE_RES_HANDLE 2virgl_get_emulated_transfers_paramsVIRGL_QUERY_RESULT_QBO_OFFSET 5VIRGL_OBJ_DSA_S0_ALPHA_ENABLED(x) (((x) & 0x1) << 8)VIRGL_BIND_SAMPLER_STATES_SHADER_TYPE 1VIRGL_SET_MIN_SAMPLES_MASK 1VIRGL_RESOURCE_IW_Z 8VIRGL_OBJ_BLEND_S0_ALPHA_TO_ONE(x) (((x) & 0x1) << 4)VIRGL_OBJ_SAMPLER_VIEW_HANDLE 1VIRGL_SET_SCISSOR_MAXX_MAXY(x) (3 + (x * 2))VIRGL_BIND_SHADER_HANDLE 1VIRGL_FORMAT_B5G5R5A1_UNORMVIRGL_CAP_ROBUST_BUFFER_ACCESS (1 << 9)VIRGL_CAP_TXQS (1 << 5)VIRGL_OBJ_BLEND_S2_RT_BLEND_ENABLE(x) (((x) & 0x1) << 0)VIRGL_CAP_FB_NO_ATTACH (1 << 8)VIRGL_FORMAT_B8G8R8X8_UNORM_EMULATEDVIRGL_SET_SHADER_BUFFER_LENGTH(x) ((x) * VIRGL_SET_SHADER_BUFFER_ELEMENT_SIZE + 4)atomic_exchange(PTR,VAL) atomic_exchange_explicit (PTR, VAL, __ATOMIC_SEQ_CST)cap_argshas_cullVIRGL_CMD_BLIT_S0_ALPHA_BLEND(x) (((x) & 0x1) << 12)VIRGL_SET_FRAMEBUFFER_STATE_NR_CBUFS 1VIRGL_RESOURCE_IW_USAGE 3VIRGL_FORMAT_R16G16B16_UINTVIRGL_CMD_BLIT_SRC_X 16VIRGL_OBJ_SAMPLER_VIEW_RES_HANDLE 2drm_virtgpu_resource_create_blobVIRGL_DRAW_VBO_INDEXED 4VIRGL_OBJ_DSA_HANDLE 1blend_eq_sepVIRGL_SET_CONSTANT_BUFFER_INDEX 2virgl_get_capsVIRGL_FORMAT_R16G16B16A16_SINTVIRGL_OBJ_CLEAR_DEPTH_0 6VIRGL_OBJ_SURFACE_BUFFER_LAST_ELEMENT 5VIRGL_BIND_CUSTOM (1 << 17)VIRGL_CCMD_SET_VIEWPORT_STATEvirgl_caps_v1virgl_caps_v2VIRGL_CCMD_END_TRANSFERSVIRGL_FORMAT_R11G11B10_FLOATvirgl_closeVIRGL_CMD_BLIT_DST_FORMAT 6VIRGL_FORMAT_S8X24_UINTVIRGL_RESOURCE_IW_LEVEL 2poly_stippleVIRGL_CMD_RCR_SRC_RES_HANDLE 6VIRGL_OBJ_RS_S0_CLAMP_VERTEX_COLOR(x) (((x) & 0x1) << 16)VIRGL_CCMD_SET_MIN_SAMPLESVIRGL_SET_SHADER_BUFFER_ELEMENT_SIZE 3VIRGL_SET_UNIFORM_BUFFER_INDEX 2original_widthVIRGL_FORMAT_R8G8_UINTVIRGL_CAP_NONE 0VIRGL_FORMAT_L16_UNORMVIRGL_CCMD_SET_RENDER_CONDITIONVIRGL_FORMAT_R16G16B16A16_UNORMVIRGL_OBJ_SHADER_OFFSET 3VIRGL_CAP_MULTI_DRAW_INDIRECT (1 << 21)VIRGL_CCMD_BIND_SAMPLER_STATESVIRGL_FORMAT_L8A8_SNORMVIRGL_SET_UNIFORM_BUFFER_SIZE 5VIRGL_OBJ_BIND_HANDLE 1VIRGL_COPY_TRANSFER3D_SYNCHRONIZED 14VIRGL_FORMAT_R8G8B8_UNORMres_handleVIRGL_FORMAT_L32_FLOATvertexbuffermax_aliased_line_widthVIRGL_FORMAT_YV12max_shader_image_other_stagesVIRGL_FORMAT_YV16VIRGL_FORMAT_R8G8B8A8_UINTVIRGL_BIND_MINIGBM_PROTECTED (0xf << 28)VIRGL_TRANSFER3D_DATA_OFFSET 12xferprim_maskres_createmax_shader_buffer_other_stagesatomic_is_lock_free(OBJ) __atomic_is_lock_free (sizeof (*(OBJ)), (OBJ))VIRGL_OBJ_RS_S0_FILL_FRONT(x) (((x) & 0x3) << 10)ATOMIC_FLAG_INIT { 0 }VIRGL_OBJ_DSA_S0_ALPHA_FUNC(x) (((x) & 0x7) << 9)atomic_store(PTR,VAL) atomic_store_explicit (PTR, VAL, __ATOMIC_SEQ_CST)virgl_resolve_format_and_use_flagsVIRGL_FORMAT_R32G32_FLOATVIRGL_OBJ_RS_S0_DEPTH_CLIP(x) (((x) & 0x1) << 1)original_heightVIRGL_BIND_STREAM_OUTPUT (1 << 11)max_render_targetsVIRGL_RESOURCE_Y_0_TOP (1 << 0)max_compute_work_group_invocationsVIRGL_SET_STREAMOUT_TARGETS_APPEND_BITMASK 1VIRGL_BIND_MINIGBM_CAMERA_WRITE (1 << 24)VIRGL_SET_BLEND_COLOR_SIZE 4strstrVIRGL_FORMAT_R8G8B8X8_UINTderivative_controlmax_texel_offsetVIRGL_FORMAT_BPTC_RGBA_UNORMVIRGL_STENCIL_REF_VAL(f,s) ((f & 0xff) | (((s & 0xff) << 8)))cmd_sizedepth_clip_disableVIRGL_OBJ_VERTEX_ELEMENTS_V0_SRC_OFFSET(x) (((x) * 4) + 2)VIRGL_SET_VERTEX_BUFFER_OFFSET(x) (((x) * 3) + 2)VIRGL_QUERY_RESULT_QBO_RESULT_TYPE 4VIRGL_FORMAT_DXT3_RGBAVIRGL_CMD_BLIT_S0 1VIRGL_FORMAT_L8A8_UINTVIRGL_FORMAT_R16G16B16X16_SNORMVIRGL_CMD_BLIT_SRC_LEVEL 14indep_blend_funcdrm_rc_blobVIRGL_CCMD_CLEAR_TEXTUREVIRGL_OBJ_SAMPLE_STATE_S0_MAG_IMG_FILTER(x) (((x) & 0x3) << 13)VIRGL_OBJ_VERTEX_ELEMENTS_V0_INSTANCE_DIVISOR(x) (((x) * 4) + 3)VIRGL_CAP_INDIRECT_INPUT_ADDR (1 << 25)VIRGL_OBJ_CLEAR_BUFFERS 1max_vertex_outputsmax_image_samplesVIRGL_CMD_BLIT_DST_LEVEL 5VIRGL_CAP_BGRA_SRGB_IS_EMULATED (1 << 29)VIRGL_CMD_BLIT_DST_D 12transform_feedback_overflow_queryhandle_flagVIRGL_FORMAT_R10G10B10X2_UNORMVIRGL_CCMD_SET_CLIP_STATEatomic_load(PTR) atomic_load_explicit (PTR, __ATOMIC_SEQ_CST)_STDATOMIC_H VIRGL_TEXTURE_HANDLE 1VIRGL_FORMAT_DXT5_SRGBAvirgl_bo_createcube_map_arrayVIRGL_OBJ_SAMPLER_VIEW_BUFFER_LAST_ELEMENT 5VIRGL_TEXTURE_SRC_W 6VIRGL_OBJ_RS_OFFSET_SCALE 8VIRGL_POLYGON_STIPPLE_SIZE 32VIRGL_OBJ_SURFACE_TEXTURE_LAYERS 5virgl_bo_create_blobmirror_clampdrm_virtgpu_resource_createVIRGL_OBJ_SAMPLE_STATE_S0_WRAP_S(x) (((x) & 0x7) << 0)drm_virtgpu_3d_transfer_to_hostvirgl_2d_dumb_bo_createcap_set_verVIRGL_OBJ_RS_SPRITE_COORD_ENABLE 4VIRGL_FORMAT_B5G6R5_UNORMVIRGL_CMD_RCR_DST_Y 4ATOMIC_CHAR_LOCK_FREE __GCC_ATOMIC_CHAR_LOCK_FREEVIRGL_OBJ_RS_S0_OFFSET_LINE(x) (((x) & 0x1) << 18)atomic_flag_clear(PTR) __atomic_clear ((PTR), __ATOMIC_SEQ_CST)min_aliased_point_sizeVIRGL_BIND_LINEAR (1 << 22)VIRGL_CMD0(cmd,obj,len) ((cmd) | ((obj) << 8) | ((len) << 16))VIRGL_CAP_INDIRECT_PARAMS (1 << 22)VIRGL_FORMAT_NV12drm_virtgpu_get_capsVIRGL_RENDER_CONDITION_MODE 3new_itemsrealloc__builtin_memcpyallocationsitemitem_size/source/platform/minigbm/drv_array_helpers.c/source/platform/minigbm/msm.c/source/platform/minigbm/mediatek.cdumb_driver_initscanout_render_formatsINIT_DUMB_DRIVER(driver) INIT_DUMB_DRIVER_WITH_NAME(driver, #driver)INIT_DUMB_DRIVER_WITH_NAME(driver,_name) const struct backend backend_ ##driver = { .name = _name, .init = dumb_driver_init, .bo_create = drv_dumb_bo_create, .bo_create_with_modifiers = dumb_bo_create_with_modifiers, .bo_destroy = drv_dumb_bo_destroy, .bo_import = drv_prime_bo_import, .bo_map = drv_dumb_bo_map, .bo_unmap = drv_bo_munmap, .resolve_format_and_use_flags = drv_resolve_format_and_use_flags_helper, };/source/platform/minigbm/dumb_driver.cdumb_bo_create_with_modifierstexture_only_formats/source/platform/minigbm/gbm_helpers.c/source/platform/minigbm/rockchip.c/source/platform/minigbm/amdgpu.ccmd_initout_unlockring_handleCAPSET_CROSS_FAKE 30cross_domain_bo_createfree_privatenum_bo_handlesCROSS_DOMAIN_ID_TYPE_VIRTGPU_SYNC 2cachedCROSS_DOMAIN_CHANNEL_RING 1/source/platform/minigbm/virtgpu_cross_domain.cCROSS_DOMAIN_CMD_SEND 4execcross_domain_privateVIRTGPU_CROSS_DOMAIN_PROTOCOL_H ring_addrcross_domain_get_emulated_metadatasupports_external_gpu_memoryCROSS_DOMAIN_CHANNEL_TYPE_WAYLAND 0x0001CROSS_DOMAIN_QUERY_RING 0ring_idCROSS_DOMAIN_ID_TYPE_WRITE_PIPE 4fence_fdcross_domain_submit_cmdCROSS_DOMAIN_CMD_RECEIVE 5channel_typedrm_virtgpu_execbufferCROSS_DOMAIN_CMD_INIT 1CROSS_DOMAIN_CMD_POLL 3CAPSET_CROSS_DOMAIN 5CrossDomainGetImageRequirementsfence_ctx_idxdrm_virtgpu_context_set_paramwait_3dcross_domain_metadata_queryCROSS_DOMAIN_ID_TYPE_VIRTGPU_BLOB 1CROSS_DOMAIN_ID_TYPE_READ_PIPE 3num_paramscurrentremaining_sizecross_domain_capsmetadata_cache_lockcross_domain_initCROSS_DOMAIN_RING_NONE 0xffffffffsupported_channelsCROSS_DOMAIN_CHANNEL_TYPE_CAMERA 0x0002CrossDomainCapabilitiessupports_dmabufCROSS_DOMAIN_CMD_READ 6cross_domain_closeCrossDomainHeaderCrossDomainInitcross_domain_release_privatecmd_get_reqscommandctx_set_paramsCROSS_DOMAIN_CMD_WRITE 7drm_virtgpu_context_initcross_domain_bo_mapCROSS_DOMAIN_CMD_GET_IMAGE_REQUIREMENTS 2cached_datametadata_equalmetadata_cacheCROSS_DOMAIN_MAX_IDENTIFIERS 4P4 i4 < P< i P $ c$ < Pl x P P c P c P P cPQ f fX ` c` x e ePf< X fx { P fPXPhlPlc< X c c ece< P eP X  x  e  4P4;pm;hmPpPc|PpQ|QpR$g$<R<TgTdRd|gpS$h$<S<ThTdSd|hp0PxPe<PePTTdSd|ePk<@P@\k\hPh|kPfPfQQQQR`e`ReReRHXPX[Q[hdPd`dPdhePePPPPQdQQQRcRRRHPHcPcpP,Q,XfXdQdpf@R@TdTdRdpdP\P\<hdhPphdlPle0cP`hPPPpPSPPQPPDdDlPT\P`lPP0c044Dc$P$eP eP0PPPP`0`lPP001PlP0R04t48R8lRPPQqQ0XlPlXXl0lWwl0PLeLTPTXe HPHdP HQHeQ HRHfR HSHgS H0H\c\gQhcQhPpPeP epQ QpRr RpS g S gpTi T0@P@lPDQDKqKlQ0R0lRKSKlSPPQQPcPc,Q,eQeRfRfDPPPH\0\|P||f P dPd Q iQi PXP 0cx P t jt P j8 @ P P V 0 T l l l 0 T c c 0  P  P 0 d0 8 P8 t d  P8 \ P P P Q Q R R S S T T P g P g ? Q? Q  Q < Q< | Q| Q R h  R  f < h< | R| h S d S d ? T? T  T < T< | T| T ? U? U  U < U< | U| U| P c|  P c 0 ( Q( P cX | c  Q $ c$ , A, < c< X QX \ c\ | Q 4 R4 f  R ( f( 0 A0 < f< x Rx f d h 1 \ g@tPthhhlhlX h@wQwdpQ d 4 Q4 X d@wRweeR e4 X e@wSw`i`lSlX i@wTwdkdlTlX k@wUw`j`lUlX j0 e<Xel0e 4 e\glg X gp0dldlVll 0 4 l4 X 0pwTwkxP el0e 4 e klk 4 ktc e i c khPeP ehQcpQ chRdR dPPp"11Q"111Ppq#P#hP#Q#4c4DQDhc$8PDTPPPQcQcPPP d (P(0d08P8DdDKPKLPQ$|$(|(4|48|8H|HL|R c (R(0c08R8DcDKRKLR(P8@PQ|(4|48|P(,PPUPUPPPPPgPgPPgQg|c|QcPgRgxdxRdhPPPcd+P+<P$Q$4c4<Q(R(+Q+<R+S+<SX P PX Q QX R RX S SX T TPP`P@f@HPH`f`QhqPQPXhX`Q`RlPRPXRX`R`SpPSPXSX`S`TtPTPXTX`T`UPUPXUX`U`VhHVHLhLPVPXVX`V`WgHWHLgLPWPXWX`W`DDHH`P e dp " Pu1u3R U3PTPTXPPWQWXQHLPLPPHOQOPQPP,PPP,PPPPPQQPPQQPPQQ`lPlxP`oQoxQHTPT`PX_P_`PxPP@DPDHP8<P<@P$P$4PPPPP P PPPPPPPQQQQ`sPsP`sQsQ`sRsR`sSsS`sTsT`sUsU`sVsV`sWsW P hfhtPtfQded|Q|eQRctRtcR3S3lgltStg$<c<?PctRtcRctRtcRdDet|eepPpt|PPPpp~xVt|V$e$fP$cPcPP8P8ePe<Q<fQfGRG|||GSGdSdGTGpppGUGxxx`xccP0GSG`d08P8`eL\P\`c0cPcfPfP0\Q\gQgQg0`R`hRhRh0cScdddSd0cTceTeTecccPhdhfxPc(+P+,P $P$(PPPPPP PQQ QRR RSS STT TUU UPPQQRRSSTTPcPPpPdPdPccPhlPlpP P PPP4P4TcT\P\`P`dP7Q7TdT\Q\dQ7R7\R\dR47R7PR07Q7Pd,4P4Pc8DPDGR`oPopPptPtxPSPSTPTXPX\PSQSTQT\QSRSTRT\RSSSTST\S0(T(,tP@d@PdPQ(}(Ws}W}}s}}RRS(}(Ws}W}}s}}TfTfPP000|W000|S0P0P`Q`lQPPP PQQQ QRRR RSSS STT T  TPPPPPPPPPPPP@TPTXPXpPpP@PQPXQXlQlQ P P(P(<PQQ$Q$<QPLcLxPxcPcPcP@Q@QQQHLPx|PPcPPQqpPP P P P P PP$P$8P8HPH\P\lPlPPP Q Q Q Q Q Q Q 8Q8DQD\Q\hQhQQQ P P  P P  P 0 P0 @ P@ T PT d Pd x Px P P Q Q  Q 0 Q0 < Q< T QT ` Q` x Qx Q Q@PPPPPPPPPP P  P@QQQQQQQQ Q  Q@lPlhP4h4<P@oQoeQ0e0<Qdd,d,0c,cd0PggP4g4<P d Pd e P H eH ` P` e P e @ Q@ f Q f ` Q` t ft  Q f Q f Q X RX h R h S S  S \ k\ ` S` k S k  S  S 8 S8 < S< ` S` d Sd S S S k T T  T  j 7 T7 8 T8 _ T_ ` T` T T T T jx d d c  c` c c@ ` c P c P  c c4 P` t P Px x e| | e@ D j j@ D e eCPCdPdP8Q8cQcQ\dPPt0 d4dH[P[eP `4ePPePP i4iPiPcPP+P+c+P+ccff8P0Pjjx0dcf0tdd0hti8<P<`ggPPLPLdPdP@dPQPeQeQ@edRdfRfRR@f`S`gSgSS@g\T\hThTT@hXUXiUiUU@ix ꟠PP < <@PtPccP ;P;@c?P?ePePe?Q?gQgQg?R?hRhRh?S?iSiSiTd T}d T}d T}Hp pPPP  P DoPocPcP P cP( t 0.( T 0.PfPf0ehe<T0Txdxdd`PhPh`QgQg`RfRf`SdSd`Txxx`UeUPccPdPHdHPPP\PQeQHeH\QRfRHfH\RPHP g PHgcQcQ,c,88HcptPt|PhlPlpP/P/`c`gPghPhPd PP(c<cPc hPPPPg<Dg0P0\e\dP40PPPPPPPPQQQQP@P@TPTPQ4f4@Q@fR8g8@R@gS@S@LSLhSt|P|etPtP<P<LPLP PTQTpQpQQ QDRD\t\pRpRRRR RSS STcT T,pTTcT,pSSS,DRD\t\pRRR,TQTpQQQ,pP<P<LPLPPpT TpS SpRR RpQ Q P e P e Q i Q i P Pd h P # P 0  d( , d 0 ( # P ePe Q iQi P PPP 0 dhp0 # ,  D, d8pddLdXde08e$@PlkTgPgj04P48j`P`dPPP d (PXQXfQQQf(QhRheRRRe(R\ff Q\hRhee RT`P`d d|PPPPPPP4d4HPHdPdPdQ(g(HQH`g`hAhQgQgR(h(HRHdhdlAlRhRhS(e(HSHtSteSeSeTHcHHTHpTpcT4c4TcTHcHHT4c4TcS8e8;P4eeHhhRhhHggg4d4HPdd (P(HcPc0$P$'Q@c4c@H@@$HL Le4e@L8@L@L @LLX2LXLX4LXXd@>$XdXd1Xddp@<$dpdp2dpp|@B$p|p|@p||@B$||@?$|@B$@>$@B$@<$@H$ @D$@@E$@F$ @G$ @8H@I$8H8H 8HHT@J$HTHT HTT`@H$T`T` T``p@K$`p`p `p$40HpTpcHtSteHdhdlAlhH`g`hAhgHdPcPHPH$c$0P0cL`P`f0fPhpc0cchpf0ff0Xcc0tfff0@@XQXohotQ3h3ptP4?PPP 4i5 xc0,P 0,Pi,P8,P ,Pc,00 5i5 xc0 0 0 0i 08 0  0c 0(P(`d`kPklPldPd8Q8dedkQklQleUQQe8R8dfdkRklRlfRRf8S8`c`kSlcScPPSPlPlSPSxPxPPPQPlQlQQPRPlRlR~RSLPLxts1%Lp1%Lxt1%PP lSSP3U3@P@U P P P $P P P P P p PP#(PQPleltQt{Q{eQQe(PRPhchtRt{R{cRRc(PPP`dtxPxdPd{t{Q{etxpx|Pp5%pOePp5%pOePp5%pO 8 Q8 p cp x Qx c Q c Q ? R? R P$ ? PH x R RH p cp x Q c(TPTXPX_P_`P(_Q_`Q(_R_`R(_S_`S(@T@`T(8U8@u@`U(@0X`TX`UX_S_`SX_R_`RX_Q_`QX_P_`PPdPP0ccPPXhPhpPpPPXQQ 8P8dPdP0d0@P@XP WQWceQceQ c Q0c0<Q<XQdQ0PhPcPchQgQgP0PPdPLdLTPTdd (P(DcT\c\_POPOcPc$P$(P(/P/0P/Q/0Q/R/0R/S/0ST0TUu0U0(0T(0U(/S/0S(/R/0R(/Q/0Q(/P/0P ȍPȍЍP 0 p1 $p3$ЍQPPPcxPL cL x c xQ QwRwR' R' RwSwS' S' SwTwT' T' TPp d 0 0D G P dPh2hg g g0 p      p j  j j j 0 P p d  0 P d d 8 0H P PP c Q  Q p f  f f f p i  i i i  0 ( R( L QL T R 0 T S S( d  dH P PP c Q QH l  P P DPDfPfPe P heh|P|ePjPj@PPe$e$'P'`edgPgePjeP,j,0e0ljlpeP dddpdpxPfPdP0e2$"e0clRloXoPRoSoPSoToPTpP PPcPLePeP|P|dP@dPxQxfQ@fPtRteR@ePP4d4f4e P VpcPc <DHXd| <DHXd|< X \ ` x  8DP 8DPdl l 4 ||h004<DPTX\`$,<Xtx<D<D  ( ` t  0 4 8 < @ H 8xt(LPT$(,p@Lp@L H l 0TH48@4Pdhp00t $(,P $(4P 00T$T\\$  Ѝ  p   ( l H X !#$.(1=  !" "#$$ %h%)&'G(|qTL|)*"+$,$_-+$._$˝+$$/G%'05&$1Q&a&<2&=3L&&4H<5@'(=((6s+$)7)'8*`*B** 9:;<$=+Y,u&V0> \#?.=@&A...B2F22KCNDP+$23 o4 J? @@EP@@!@#f$F@'G H(Ia)Je* e+ @.KALeAAMA:0EP@A@#~'NB(OTBB7P ,B_Qr),B|CRC~STHUlVLC@WcCXY D!ZL"[%D%\(5D{D]*v^M_D E?2`"E@2EGabBEEP@RE!@bEctE@EdEe+$~GG@Gf4Hg,;u"#i#%FXP'h PEP@iP+$%P `(cS%,(-jT.T U!UWk:W0{[3uF= ʀ9PlLNgq8ltP7 lBZ%"CB8./ :AGߍs,)%k!b?) `D|nHnR*qm"ޏM!f?,f16m29 `gLE }ZZdL,?!T_n]J $>g3c0zbz+zNg=C~St4vN 7HG]a#&[~/.{hZ[u*8# eqADxE3ZYLEJ~Qk_h[ V7$x+ mx3"Q5 ~C.0< [W{'>sNѬ7(ZeAOA<NdVkUnkM}F^a_IpXHť 4U bB9]y' jWql tՒ|p@C9vxp ="gAXBGc;֐[$n$I2)V<64xGo?V%_~hGibD"\13+4ej.# K.YwP21J-b\E h}R=MXwLy<kpz^PvYAwh-Î,PPFx4ny:'ua?Qya-t@&}.: $;/+,H-.7?Pݫ $ '( )*,/^-ӗ.n/0:p>BEKS)KTTUAV}uW ^XLY~\#]R ^_aecUde;fagBӋC^DSE4G\dHIJ`KI{"l!&TZh] 8kZ3%4w I#6m${X>^A|!%%]gTc-3L./ջ1L23v4!5767}9 GHI{JK\qLHMNaOPΌQ9RJS8TYcJZJ[4\]6m^R_`aObe%fOgahi%lmp6n/?opAs)tXLv9xzI|=1ps{d)V&e"AvEN4MpO~?:OLL->= <дO-Uy\4t+:e:]X}L/9`%mLC^Sw %q16 ɤ`i;|gZ=r|F vMUt!0J]M?}EoQCoW6nH$i!c=~>,N!4<('2tuC T6TB,?OE4yB,yr&hwo:i/=VfP@'tƓ'X0֔)[Vw$pX6) >2>)Q8' A-(MHay\}j K<\Go#Sa[u )v*+a,Ɛ-C_./L01\2&304F5x?69748:;J?G@A3A=SBɸCDEC*FGHGUIEbFcDdefAg6hprtG1vJx6z@|uSYazs`4 '* 8:O@P:I^a<&@)[x zmme(!N di`v&Tpd-1/=(=r V_ysKp( E*>UEGx::L(T2Hš/V#m6 7 7D|s@(K<x^oVp9=yM)/ʔ.'vH._[3w&1Zp=Ԫe, eS_tѼ~d\˃Pv6@kYr X>zdrWn"iJ{L@QV(BGQEQ~v'\ўsA.Y9P5=m<Fހ CZX, *d9V;U"d } `YX4 =eT$&_D5 $E{Nwx{xyWz9{t|P} /~YK-aRJ  .*$Q:6S +xA;dZo1ZO!/P^;- ΩItzObtUZO!/P`[#HW͇zObB1,lś4,͇!>gW"l7s>;{,RZ6l"__P#"*a+P78c9"e:@^c/cJdOijWmYuYvOd{%|ǘ \7Z{27ȈwEb)9KNO)- 4h 1O zl]5xD9+<5GX `cqJ]=\Η  9  cYEp\^MqnzUocU%P:lpm(nl|o.1pk5qug#4<b{lGF{7z' aI!."5#$b%&N'y({H)e*+,9b-l./u0z1G2$3 4 ,5v67)8K9|:5;<=+>TY? ES<HQKQ/V6h  !i<-r.>/B04/zz,P;Jh@VA;qBCE!F3GMH3J*K[L)qMe_+9/XW*cNd fQ%EJ~ACcD *Q"YV"]+a@dqh+ke n-qytw^fz b}G[|sIug.k{|L$ #Ae(& _| K - k e}(^Y+,0/1q5J6-=:~;'?6A(D?FInKO?SqpV^YsL\p_=b4eG6y }ۂStpy.FnyM *Y>?z*Q6 TK  $ y *1hq QH5W6o}=XS,mr>= !"l#$ %kK&(9:0 {`އ}/p9N,AL>]} # !"d#5$~%.y&@N(L*-+,- .m/ 0C 1!)23 4756I78:9˄:;s<ݠ=k>9y?@VAXBdCklD ~EwnF} GmH0-IdyJ>$KLM!NJoO'JP+QzrRLSTGUǻVjWRXl;YGZF[-\{!] 4^D_O>`abPYck&deRWfgh&i(k> lTmHn3oH,pqMtuDwyޙHkT3#$v4%d6Y>?*<+,--A/dn2"5rv8ކ;$+>c:ADlF=H"ZUm[i^tandmn>o$y}#|sz*[F1Z+0$/!Pa$K'q8|'/ZK=U!{*ax_<gLe"E;"\{y /U$ȃ&KcXo!Y`&'0V oEtRh{ax*uC3lp +e)+B<_Nu9 +5>~t-}'(T3.'<AF2$%&QB)4,OV]PZQM_]@-T/8Iq(PcSA+C'W+ER4? tP]QRlwSTDyVHZY\a3bpAfivjKk?~mopiq|sB#uzv:5wyB~LoG&,,C2)E"so.a~31 4D5A[6 7i89_:);Sp<=>>?@M^A{BECCDd3E{F NL MKN4O6PzQVRXScT JUJVWufXYZ [z \B8]^a_K`<`a#bfcd7e|fgh2i:j8Ak xlmDn[omp3qrWswtJu<v1wxEytz{|d}3~c|T*ZLS~e+AYY#'R{Vkqo5 qf nEG87MЛx]l^*);u 4Κf!Ifg# %k=#A %'`&AJXKtm#R/_8!qByIFvx~}IIyM`L }:wi}ImZ]U42Eas})ڎȠm'I:~V(6 wR..cݝYs^,^Wgr#F:oj_ lf7x$cWByo \db  "-k0ɊZё~^x;C5 cT !lP25X4FTul/M$O{) v@L>a\b.E-/bfISRrABtZIyIgcj*@rG=_.W h p~KA  Ioi>{ٱmB'j'H/Idݟքϧw<LɭA lrrV1G}fR_~:j" ,b}V0Yz 1hrCq*Z^{1O-by,"3dC-E.>'( *6#k2~k2#:Y:+ eA&")% zkokezzE?w>?Ǯ:0zY%A(T/1I8:/A C'6 ;YzE?w>?Ǯ" 'if?sjiolpVFrbsuuT5N]3`^:@_ȾcQhmGn&,o,qrkx۝KڵYy5 $J%-dSAVI7$6q;Ӎw X![$ڦ&n'S,B0ʛ1v2jk"w%=M( ,`71-5C@8N9 :Ϳ;<+I ,^-.`/a"0V 2((«-3|>G"`# #$1%py&i4\5o$67+n8VB9?FU]#i#<qT}!F(3}GzQZV[#\}.`R"(67 :g;c*oX;N2f .ΒʀtC^bQ&!nSu? ^'FR+Ӂ%5EeQG>#p=lV/J.z*]]W|̌=}9hxt:::Ԅ{,–R 2pidoD} e .%|ftlRgz \ *p7MDv%)нSoO-or1Fr2"S ̍"W Gr h" /!001!4w6wiVelorui@:0"u*j=Ck t>u`vAwyhxz{|)/vMP,C.>96օOo[kn7[rƘ"m4{6.*Nj Us]&R;kMQS7P?CS6P THH11R$Q$WVD6C6ONRQed ; ;}k|kZz8ѷ`/<4F56Ǚ7 r8]>9.HIKjWMOUVNWH,XY\];&^t`Uh0hi9jKnkelan!t&I]d[m?FkWlg7Xot>E44r!"#Ʃ4E FFMQmVpY*\_NbqefOijwkvlt n o`mp{q<sthuv]xI)yz{ }>~ 3Js,{qV]kYOQsCD\tpf't$F0vz~{%E5<+s,@v˟qudCI:$F 5   e  ZN'P "$$_$_$ !$"+Y,u&V0#$T @@%P@@!\#f$&@&˝$$'G%'( )(*a)+e*e+@.,j]-eAA.A /BE%P@RE!]0H<1@bE2tE. E3E4$~GG]]54H6,; u"G^ #%&XP&7n^~89H:l;L^. cC<5&$=Q&a&<>&=?L&@A D!BL"C%D%D('E5D{D *v MFD E?2'G P%P@HP$%P `(I$.(JKL1=  MN" OP$Q Rh%)STGU|qITLcSF V\W^]+X^JY,Z__`]![`I\a']`0^b_$b `:0%P@Ab#~'aB(bTBB7c B_dr)B|Ce"E.2EGfg4hjc%jkiki:Wǣy }ۂStpy.FnyM *YE?w>?5CGN]3`^:@_ȾcQhmGn&,o,qrkx۝YE?w>?^$ѾM2~LoY C2)E#i"(37f@B5E}9:;< =E>?E@ABXCDEHIJKBLMTN;OPŵQR VWXUYb[0\]^y`babFceJfg;hk$A7$&kW^Z\^m#d(TJ,Y:+ eA&")% zkokezzE?w>?]/`cifpixl.obpisht#w̩x{|V}~o|5<f GwWTh{3'ӼBI ?M zX&DkR +t~v-[(յ9a"Uƪ.d7yR Nٶ .t;ҭT"t%[SKjMr¿h~#Gzda>nler    " H ķ  ~ q   t  B   D      w    p  "    P ̡ A Q   K    = [  : T b  0  (߸E 6!"#G$[%=&'()t* +9,l.1<225Z6D7j8>j?@AFTܢa lptwhy|Ou()*+,,-\./[01 2V4q5y67NOPʤQRQSTUVWʴG2Kֹ߱@n\4^LH T 4$.(1=  !" "#$$ %h%)&'G|qTLwr( )P*zY!+,"-$.$_/-$0_$,y˝-$$1G%2P-$"c%`y `3:0*P@A{#~'4B(5TBB76 .B_7r).B|C8H<9@: }~;<H=l>LC.C?5&$@Q&a&nler    " H ķ  ~ q   t  B   D      w    p  "    P ̡ A Q   K    = [  : T b  0  %A(T/1I8:/A C'Xj=Ck t>u`vAwyhxz{|)/vMP,C.>96օOo[kn7[rƘ"m4{6.*Nj Us]&R;kMQS7P?CS6P THH11R$Q$WVD6C6ONRQed ; ;}k|kZz8ѷ`y }ۂStpy.FnyM *Y:+ eA&")% zkokezzE?w>?"(371BC DPH`I NOPC Qz RST U V. W XYZ [4 ] ^_ `befg= ht in o q! & '~LoY '("+#"$$_$_$\˝$$G%#.=&.*.2F22KNP 5&$!Q&a&<"&=#L&$23 $ %P&P@'P$"c%`y ` @@&P@@!]#f$(@') *(+a),e*e+@.-A.eAA /A :0&P@Ab#~'0B(1TBB72 B_3r)B|C4H<5@6~78H9l:LC.C;< D!=L">%D%?(5D{D@*vAMBD E?2C"E.2EGDE FBE&P@RE!]bEGtE. H}.)I~0JJ~uKh,zL#%(XP(M$.(NOP1=   QR" ST$U Vh%)WXGY|qMTLcS 4Zjc[T%j[  U!+U\:W(AaUu o "(37?Ǯ5>66"+#" $!$_" $#_$$%&'$(+Y,u&V0)\˝ $$*G%#+.=,&-.*..2F22K/N0P15&$2Q&a&<3&=4L& $23 \5^]6l+7^J8,9__`]!:`I;}<(%='>`.?H/@L0A?E@ABXCDEHIJKBLMTN;OPŵQR VWXUYb[0\]^y`babFceJfg;hk$"(37(?a)@e*e+@.AABeAA CA BE:P@RE!]DH<E@bEFtE.}.)G~0HJ~uIh,z EJEK"$~GG]L4HM,; u"#i#%<XP&N8~OPHQlRL^.CST D!UL"V%D%W(5D{D*v MXD E?2($.(YZ[1=  \]" ^_$` ah%)bcGd|qTLcS eT 4fjc:0:P@Ab#~'gB(hTBB7i #B_jr)#B|Ck"E.2EGlm%j nN F o\p^]+q^Jr,s__`]!t`Iua'v`0wbx"$bkr iky:WfȄ!'#TϗO\Rg7UU]-_d+`kbWcיd~eF1f@@gvhv>iRaj0k:y6.=mbM)J:pw7:`0MqO% Y<y^$ѾM~LoY "(37~P!{yt+o2x3f0*TQ.Papx0.-g]1IaS/v[..eQos]C<<lVd}+ILQF4"op5kst5vAwytlz|D~x\|dmBa4q=:.3Cz1,(eopikK2z{b8-5jfrZ54 F7p?9Ax]y:i6sb T$IY \VSL(*K &.Zb3|__t\]G^'q_j~%9$',y&.n8$}BgB֌R(90"Ayӈ(n8{4Eœg!nhn5UMy$_Wd $=ăV;aPeH79xAtZsP5͖?0JLkf/QzlQR^pD aR.Dr)ZS,D4.]1nY$A+9Ml(p C~4gAn,n5edK_0yAoj2Fl.3Q |j=:X(8h{Gt ~~M{7wd@'/#i3 _"axNB1OYY!^@nK'nݗ}3LXpXRV,J&(ڃ*j  P zY!  "$$_$_$,y˝$$G%P$"c%`y `q} :0 P@A{#~'B(TBB7 B_r)B|CH<@ }~Hl LC.C!5&$"Q&a&<#&=$L&%& D!'L"(%D%)('*5D{D+*v,M-D E?2."E.2EG/0 1BE P@RE!]bE2tE. 3:Wnpp-q"$$_$_$$+Y,u&V0  T 4$.( 1=  !"" #$$% &h%)'(G)|qTLwr* +P,P@˝$$-G%.P$"c%`y `/:0,P@A{#~'0B(1TBB72 B_3r)B|C4H<5@6 }~78H9l:LC.C;5&$<Q&a&<=&=>L&?@ D!AL"B%D%C('D5D{D *vMED E?2F"E.2EGGH%j IN  F J\K^]+L^JM,N__ `]!O`IPa'Q`0RbS$bk T:W r-w @@ zY!  "$$_$_$,y@!@#f$@&˝$$G%' (a)e*e+@.j]eAAA 4$.( 1=!  "#" $%$& 'h%)()G*|qTLwr+T, -P P@.P$"/c%`y `0:0 P@A@#~'1B(2TBB73 B_4r)B|C5H<6@7~89H:l;LC@C<5&$=Q&a&<>&=?L&@A D!BL"C%D%D('E5D{DF*vGMHD E?2I"E@2EGJK%j  U!U'( *6#k2~k2#:y }ۂStpy.FnyM *Y:+ eA&")% zkokezzE?w>?Ǯ"(37 ?P%P@@P$%`y `( $.(ABC1=   DE" FG$H Ih%)JKGL|q TLcS  MT 4Njc:0%P@Ab#~'OB(PTBB7Q B_Rr)B|CS"E.2EGTU%j N  F \V^]+W^JX,Y__ `]!Z`I[a'\`0]b^$bkik_:WR!&.'r h" 'i/!001!4w6wiVeloorui@"(37 ta v Hw (z ~t    8 8 8. HG `` x{ v 8 ЦpD ȩ ȩ   D  ! 8 p? pV  x5D HkvD Ѝ ЍP    `  ? V ( `)7`F W\R Dh z GLh HL 0\( 8K\ e<  MX  e+  xZ6  eQ f  Yq  (ft  (K  Y  xm  d  K   DL  ?(  F,  cB  eZ  Ly  x@h  m\  (YX  8B,    eD  X]    M@! 8/ @  [N  g`] j  d  d  @X  d$   hB  e  Y'  l; 8K  d c  bp  e  F  X  P   0j   K  T  H&  W1  8_< 0N  d]  eo (  X^  8AX  ?|  HD 0  f0 #5B J R XeDj A + N| 8XD 0+ S 0T  <O Ocr O" @T.<Q Sc xQq P U  T S N XO( O7J (T\ T t O `S8 OP 8Q< S 2Gd T O  S 78-@U Tk 8T 6 T S T2GUdy HT O N 6T& OQbp NT PT 1N Sb S~ O/usr/lib/gcc/aarch64-linux-gnu/8/../../../aarch64-linux-gnu/crti.o$xcall_weak_fn/usr/lib/gcc/aarch64-linux-gnu/8/../../../aarch64-linux-gnu/crtn.ocrtstuff.cderegister_tm_clones$d__do_global_dtors_auxcompleted.8216__do_global_dtors_aux_fini_array_entryframe_dummy__frame_dummy_init_array_entryminigbm_helpers.cdri_node_numfd_node_numtry_drm_devicesradeon_igp_idsvirtgpu.cvirtgpu_initdrv_helpers.clayout_from_formatpacked_8bpp_layouttriplanar_yuv_420_layoutbiplanar_yuv_420_layoutbiplanar_yuv_p010_layoutpacked_1bpp_layoutpacked_3bpp_layoutpacked_4bpp_layoutpacked_2bpp_layout__PRETTY_FUNCTION__.7892__PRETTY_FUNCTION__.7898__PRETTY_FUNCTION__.7904__PRETTY_FUNCTION__.7911__PRETTY_FUNCTION__.7950__PRETTY_FUNCTION__.7930dri.cgbm.c__PRETTY_FUNCTION__.6737__PRETTY_FUNCTION__.6759vc4.ci915.cdrv.cdrv_bo_acquiredrv_bo_get_plane_offset.part.0__PRETTY_FUNCTION__.8175__PRETTY_FUNCTION__.8138__PRETTY_FUNCTION__.8109__PRETTY_FUNCTION__.8144__PRETTY_FUNCTION__.8150__PRETTY_FUNCTION__.8180__PRETTY_FUNCTION__.8185__PRETTY_FUNCTION__.8211__PRETTY_FUNCTION__.8170drv_backend_listvirtgpu_virgl.cvirgl_get_emulated_metadatavirgl_get_emulated_transfers_paramsvirgl_resource_infotranslate_formatvirgl_bo_destroyvirgl_closevirgl_get_max_texture_2d_sizevirgl_supports_combination_natively.isra.3virgl_resolve_format_and_use_flagsvirgl_supports_combination_through_emulation.isra.4virgl_bo_flushvirgl_bo_invalidatevirgl_bo_createvirgl_add_combinationvirgl_initvirgl_bo_mapvirgl_bo_create_with_modifiers__PRETTY_FUNCTION__.8750__PRETTY_FUNCTION__.8736__PRETTY_FUNCTION__.8610render_target_formatsdumb_texture_source_formatsdrv_array_helpers.c__PRETTY_FUNCTION__.4174__PRETTY_FUNCTION__.4180__PRETTY_FUNCTION__.4189msm.cmediatek.cdumb_driver.cdumb_driver_initdumb_bo_create_with_modifiersscanout_render_formatstexture_only_formatsrockchip.camdgpu.cvirtgpu_cross_domain.ccross_domain_submit_cmd.isra.0cross_domain_bo_mapcross_domain_release_private.isra.2cross_domain_closecross_domain_initcross_domain_bo_create__FRAME_END__backend_radeondrv_preloaddrv_dumb_bo_create_exgbm_convert_usagedrv_gem_bo_destroybackend_rockchipdrv_modify_combinationdrv_bo_create_with_modifiersdrv_add_combinationdrv_resolve_format_and_use_flagsdrv_pick_modifierdrv_bo_get_formatdrv_bo_newdrv_bo_get_format_modifiervirtgpu_cross_domaindrv_get_fddrv_num_buffers_per_bodrv_get_protdrv_get_namedrv_get_max_texture_2d_sizedrv_bo_get_heightdrv_add_combinations_finidrv_bo_from_formatdrv_num_planes_from_formatdrv_dumb_bo_createdrv_bo_flush_or_unmapdrv_get_standard_fourccdrv_modify_linear_combinationsdrv_height_from_formatdrv_resource_infodrv_destroydrv_size_from_formatbackend_udlbackend_komedadrv_bo_get_plane_sizedrv_bo_unmapdrv_array_sizedrv_has_modifiervirtgpu_virglbackend_mediatekdrv_bo_createdrv_bo_destroy__dso_handledrv_bo_get_num_planesdrv_bo_get_widthdrv_vertical_subsampling_from_formatdrv_bo_get_plane_offsetbackend_nouveaudrv_bo_from_format_and_paddingdrv_bo_get_total_sizedrv_get_combinationdrv_bo_get_plane_fdbackend_virtgpudrv_bo_get_plane_handledrv_bo_flushdrv_bo_get_use_flagsdrv_dumb_bo_destroydrv_array_appendcross_domain_get_emulated_metadata_DYNAMICdrv_bo_importbackend_mesondrv_bo_munmapdrv_array_destroydrv_prime_bo_importdrv_createdrv_bo_mapbackend_synapticsdrv_array_initdrv_bo_get_tilingbackend_marvelldrv_bo_invalidatedrv_bytes_per_pixel_from_formatdrv_num_planes_from_modifierdrv_array_at_idx__GNU_EH_FRAME_HDRdrv_log_prefix__TMC_END___GLOBAL_OFFSET_TABLE_backend_sun4i_drmbackend_vkmsdrv_dumb_bo_mapdrv_bo_get_plane_stridedrv_stride_from_formatdrv_resolve_format_and_use_flags_helperdrv_array_removebackend_evdimemcpy@@GLIBC_2.17strlen@@GLIBC_2.17gbm_bo_get_plane_countgbm_bo_get_stride_for_plane_ITM_deregisterTMCloneTabledrmPrimeHandleToFDgbm_surface_destroydrmFreeVersiongbm_surface_createreadlink@@GLIBC_2.17__cxa_finalize@@GLIBC_2.17opendir@@GLIBC_2.17gbm_bo_set_user_datadrmModeGetResourcesstderr@@GLIBC_2.17drmModeGetConnectorasprintf@@GLIBC_2.17drmDropMastersnprintf@@GLIBC_2.17gbm_bo_get_devicegbm_bo_importdrmHashDestroygbm_bo_create_with_modifiersmalloc@@GLIBC_2.17gbm_bo_mapgbm_bo_get_plane_fdgbm_bo_get_formatstrncmp@@GLIBC_2.17gbm_device_get_fdgbm_device_destroygbm_surface_has_free_buffersstdout@@GLIBC_2.17gbm_bo_get_offsetgbm_bo_get_fd_for_planememset@@GLIBC_2.17gbm_surface_lock_front_buffergbm_bo_unmaplseek64@@GLIBC_2.17gbm_create_devicegbm_bo_destroygbm_bo_get_bppcalloc@@GLIBC_2.17realloc@@GLIBC_2.17closedir@@GLIBC_2.17strerror@@GLIBC_2.17__stack_chk_fail@@GLIBC_2.17pthread_mutex_init@@GLIBC_2.17close@@GLIBC_2.17gbm_bo_get_handlegbm_surface_release_buffer__gmon_start__gbm_bo_get_height__stack_chk_guard@@GLIBC_2.17minigbm_create_default_devicedrmHashLookupstrcmp@@GLIBC_2.17basename@@GLIBC_2.17gbm_bo_get_plane_size__ctype_b_loc@@GLIBC_2.17gbm_bo_get_stridestrtol@@GLIBC_2.17drmGetVersiondrmIsMastergbm_detect_device_info_pathgbm_bo_map2gbm_bo_get_widthfree@@GLIBC_2.17gbm_bo_get_fdreaddir64@@GLIBC_2.17drmModeFreeResourcesdrmHashInsertdrmFreeDevicesdrmModeFreeConnectordrmHashDeletegbm_bo_get_user_datagbm_surface_create_with_modifiersgbm_device_get_backend_namemunmap@@GLIBC_2.17pthread_mutex_destroy@@GLIBC_2.17gbm_detect_device_infogbm_device_get_format_modifier_plane_countread@@GLIBC_2.17drmHashCreateopen64@@GLIBC_2.17gbm_device_is_format_supportedstrstr@@GLIBC_2.17drmGetDevices2gbm_format_get_namedrmCommandWrite_ITM_registerTMCloneTablevfprintf@@GLIBC_2.17__assert_fail@@GLIBC_2.17__errno_location@@GLIBC_2.17gbm_bo_get_modifiergbm_bo_get_handle_for_planemmap64@@GLIBC_2.17getenv@@GLIBC_2.17pthread_mutex_lock@@GLIBC_2.17drmCommandWriteReadpthread_mutex_unlock@@GLIBC_2.17drmIoctlgbm_bo_create.symtab.strtab.shstrtab.note.gnu.build-id.gnu.hash.dynsym.dynstr.gnu.version.gnu.version_r.rela.dyn.rela.plt.init.text.fini.rodata.eh_frame_hdr.eh_frame.init_array.fini_array.data.rel.ro.dynamic.got.got.plt.data.bss.comment.debug_aranges.debug_info.debug_abbrev.debug_line.debug_str.debug_loc.debug_ranges.debug_macro$.h8X @H HU@d n%x+s0+ ~P/Tjx0ȰD((0(8(P ((`(((0 (v-g%#RL/0)C:lEm` Spyx.0$" Ri`