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Y Y ruY ^ Y WuY OXtXttVtXttVtXttXXtXttX Muv <Y Gzt.tW.tW.tW.t  MYuh <Y Ev GwX.t\.tW.tW.tW.t==KgKf PgK!.tgK!.tK==KKL/+!tXttX P -"i J.Y0t KJ\ 47J X $g<'jtKJ.xJt6}tk=I=  =Y0YW/<)I;JJX X.;JJg<Lfr JgI <5<Z ~= K;=Y\=  X;IJfpgXQvt& <<Jz4z<X>J;Z!YWK f.8 5(GK%\(<4kJkJ*[qK*XLk$JJ7X0 =-Ytf&gY #.XftiX[PKz& <KX0 uXU.tXt$XK$XJHfJ> <Y Y y /source/platform/minigbm/usr/include/usr/include/x86_64-linux-gnu/bits/usr/lib/gcc/x86_64-linux-gnu/8/include/usr/include/x86_64-linux-gnu/bits/types/usr/include/asm-generic/working/usr/include/libdrm/source/platform/minigbm/external/working/usr/include/usr/include/x86_64-linux-gnu/sys/usr/include/x86_64-linux-gnu/gnu/usr/include/linux/usr/include/x86_64-linux-gnu/asmvirtgpu_virgl.cerrno.htypes.hstddef.hstdint-intn.hstdint-uintn.hstruct_FILE.hFILE.hstdio.hsys_errlist.hunistd.hgetopt_core.hthread-shared-types.hpthreadtypes.hint-ll64.hdrm.hdrv.htime.hdrv_priv.hvirgl_hw.hvirgl_protocol.hvirtgpu_drm.hvirtgpu.hxf86drm.h string.hassert.hfcntl.hdrv_helpers.hmman.h stdlib.hstdc-predef.hfeatures.hcdefs.h wordsize.hlong-double.hstubs.h stubs-64.h errno.herrno.h errno.h errno.herrno-base.herror_t.htypesizes.hfcntl.hfcntl-linux.hstruct_iovec.hfalloc.h struct_timespec.hstat.hstdatomic.hstdint.hstdint.hlibc-header-start.hwchar.hstdarg.h__fpos_t.h__mbstate_t.h__fpos64_t.h__FILE.hcookie_io_functions_t.hstdio_lim.hstdio.hlocale_t.h__locale_t.hstrings.hmman.hmman-linux.hmman-shared.hposix_opt.henvironments.hconfname.hgetopt_posix.htypes.h clock_t.hclockid_t.htime_t.htimer_t.hendian.hendian.hbyteswap.huintn-identity.hselect.h select.hsigset_t.h__sigset_t.hstruct_timeval.hpthreadtypes-arch.htypes.h types.h types.hbitsperlong.h bitsperlong.hposix_types.h stddef.h posix_types.h posix_types_64.h posix_types.hioctl.h ioctl.hdrm_mode.hstdbool.hdrm_fourcc.hwaitflags.hwaitstatus.hfloatn.hfloatn-common.halloca.hstdlib-bsearch.hstdlib-float.hdrv_array_helpers.hpthread.hsched.hsched.hstruct_sched_param.hcpu-set.htime.htimex.hstruct_tm.hstruct_itimerspec.hsetjmp.hutil.h 0 = >u<>7*-:5*p( <u</%(3:AA*@t<@/Ar.??/=>*KIX>,4%9D(9u<( v<?*x<u?=>*K*ty)/J <2fN#xv.*= =. <=2$<=3%<?. .=2 <=2$<='Nv.*= =. <=2$<=3%<?. .=2 X=&<'. .=2pX<C..=&'3C\XXZ$[U u$M5X(0H ])X(rhtj)h%. f 1.. q<X ~M 00 r0>#.l  ~M 00 r0>7. t<.K ?<g  X8 V <un.Lf2gg t .0)u<M8<N J)L9J WX f/g z V . ot <XX tJ5)K  v . W7g7)<.)1G/)off(J3x J>s JL3 YX 6t-yJJ@ zfKuuu KX a+XJ  >v  Cf.V.v.-/VvX3 SX   XXf֑XO#IXYbg "0u ~=;X1u ~C;X0  )5Jt[5Jt[1Jt[0Jt[3Jt[;JtJ&"-cX3 z Y. XX..tu}dM<ULKXYO KsK XJ<e X}<X0 f YJsX Y s 5 /source/platform/minigbm/usr/include/x86_64-linux-gnu/bits/usr/include/usr/lib/gcc/x86_64-linux-gnu/8/include/usr/include/x86_64-linux-gnu/sys/usr/include/x86_64-linux-gnu/gnu/usr/include/x86_64-linux-gnu/bits/typesdrv_array_helpers.ctypes.hstdint-uintn.hstdlib.hassert.hstdc-predef.hdrv_array_helpers.hstdint.hstdint.hlibc-header-start.hfeatures.hcdefs.hwordsize.hlong-double.hstubs.hstubs-64.htypesizes.hwchar.hstdint-intn.hstddef.hwaitflags.hwaitstatus.hfloatn.hfloatn-common.hlocale_t.h__locale_t.htypes.hclock_t.hclockid_t.htime_t.htimer_t.hendian.hendian.hbyteswap.huintn-identity.hselect.hselect.hsigset_t.h__sigset_t.hstruct_timeval.hstruct_timespec.hpthreadtypes.hthread-shared-types.hpthreadtypes-arch.halloca.hstdlib-bsearch.hstdlib-float.hstring.hstrings.hutil.h P #U 1U [\u=]=zt =-Y n G?<<YY<Yt Y K wt @ Mג< YK t p1G! st/K"Y*K'Y<(J !=K PHZy Z6yXY[u!N? KuMZYKUYKY }[LK JO(f QfXXp<xX"XX X ~!MG?X ,i;KVL 07JfK *1Gz<*q[*GL<YKZY+J'YfIX /.\ ~<y. J ~X FKYsYB<K' kO*.Q/JQJ/@Y~XJMSXqXXs[z<YJ uXL v" XuJKJKvuu v .5fYK2JK5+.f_K!tuQN 9 u XX. ~& ~AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1PTHREAD_KEYS_MAX 1024GBM_FORMAT_RGB565 __gbm_fourcc_code('R', 'G', '1', '6')pci_rev_CS_POSIX_V7_LP64_OFF64_LINTFLAGS _CS_POSIX_V7_LP64_OFF64_LINTFLAGS__u64AT_REMOVEDIR 0x200DRM_CAP_CURSOR_WIDTH 0x8_POSIX_V6_LPBIG_OFFBIG -1version_minor_BITS_TYPES___LOCALE_T_H 1INT_FAST8_MIN (-128)AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04AMDGPU_TILING_SET(field,value) (((__u64)(value) & AMDGPU_TILING_ ##field ##_MASK) << AMDGPU_TILING_ ##field ##_SHIFT)_drmPlatformBusInfoDRM_MODE_REFLECT_MASK ( DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y)AMDGPU_CTX_PRIORITY_UNSET -2048__REDIRECT(name,proto,alias) name proto __asm__ (__ASMNAME (#alias))_SC_THREAD_PRIO_PROTECT _SC_THREAD_PRIO_PROTECTDRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob)RADEON_CMD_WAIT 8RADEON_BUFFER_SIZE 65536AMDGPU_FAMILY_SI 110DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw)RADEON_CS_KEEP_TILING_FLAGS 0x01SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP 11DRM_MODE_ENCODER_VIRTUAL 5DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP)DRM_MODE_PAGE_FLIP_ASYNC 0x02ENOTUNIQ 76_CS_POSIX_V7_ILP32_OFFBIG_LIBS _CS_POSIX_V7_ILP32_OFFBIG_LIBSDRM_BUS_PLATFORM 2__FLT_MAX_10_EXP__ 38__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1DRM_CAP_SYNCOBJ 0x13DRM_MODE_FEATURE_KMS 1R200_EMIT_PP_TXCBLEND_3 24__UINT_LEAST16_TYPE__ short unsigned intAMDGPU_INFO_SENSOR_GPU_LOAD 0x4RADEON_CMD_VECLINEAR 9GBM_FORMAT_BGRA1010102 __gbm_fourcc_code('B', 'A', '3', '0')R200_EMIT_PP_TXCBLEND_6 27_CS_POSIX_V7_LPBIG_OFFBIG_LDFLAGS _CS_POSIX_V7_LPBIG_OFFBIG_LDFLAGS__INT32_C(c) cDRM_IOCTL_CRTC_GET_SEQUENCE DRM_IOWR(0x3b, struct drm_crtc_get_sequence)_STDLIB_H 1_CTYPE_H 1ELIBBAD 80__pad5__STDC_IEC_559_COMPLEX__ 1AT_NO_AUTOMOUNT 0x800EPERM 1cu_active_numberRADEON_TILING_MICRO 0x2vrefresh__INT_LEAST64_MAX__ 0x7fffffffffffffffL__wchar_t__ GNU C99 8.3.0 -mtune=generic -march=x86-64 -ggdb3 -O2 -std=c99 -fno-strict-aliasing -fstack-protector-strong -fvisibility=internal -fPICAMDGPU_INFO_VRAM_LOST_COUNTER 0x1F__SIZEOF_WCHAR_T__ 4S_IFLNK __S_IFLNK_POSIX_MEMLOCK 200809LDRM_MODE_DITHERING_OFF 0_SC_2_C_DEV _SC_2_C_DEV__FLT32X_MIN__ 2.22507385850720138309023271733240406e-308F32xDRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb)__DEC32_MAX_EXP__ 97DRM_RADEON_CP_STOP 0x02_STDBOOL_H LOCK_EX 2R300_CMD_PACKET3 3SEEK_DATA 3__CLOCK_T_TYPE __SYSCALL_SLONG_TYPEF_SETPIPE_SZ 1031_CS_XBS5_LPBIG_OFFBIG_LDFLAGS _CS_XBS5_LPBIG_OFFBIG_LDFLAGS__LDBL_DECIMAL_DIG__ 21AMDGPU_CTX_OP_FREE_CTX 2_CS_XBS5_ILP32_OFF32_LIBS _CS_XBS5_ILP32_OFF32_LIBS_SIZET_ FFSYNC O_FSYNC_POSIX_RTSIG_MAX 8_SC_2_PBS_ACCOUNTING _SC_2_PBS_ACCOUNTING_POSIX_REGEXP 1__FLT32X_MAX__ 1.79769313486231570814527423731704357e+308F32xR200_EMIT_ATF_TFACTOR 87R200_EMIT_RB3D_BLENDCOLOR 76__UINT64_C(c) c ## ULRADEON_UPLOAD_CONTEXT 0x00000001_IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)_LFS64_STDIO 1AMDGPU_TILING_BANK_HEIGHT_SHIFT 17DRM_PRIME_CAP_EXPORT 0x2RADEON_EMIT_PP_TEX_SIZE_0 73DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap)__LITTLE_ENDIAN 1234EUSERS 87RADEON_EMIT_PP_TXFILTER_1 14L_XTND SEEK_END_CS_V6_WIDTH_RESTRICTED_ENVS _CS_V6_WIDTH_RESTRICTED_ENVS_BITS_FLOATN_H _SC_SPIN_LOCKS _SC_SPIN_LOCKSGBM_FORMAT_BGRA5551 __gbm_fourcc_code('B', 'A', '1', '5')WIFSTOPPED(status) __WIFSTOPPED (status)DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb)FALLOC_FL_KEEP_SIZE 0x01DRM_MODE_OBJECT_ENCODER 0xe0e0e0e0AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0DRM_EVENT_CRTC_SEQUENCE 0x03_CS_V6_ENV _CS_V6_ENV__SIZEOF_POINTER__ 8isgraph(c) __isctype((c), _ISgraph)__extern_inline extern __inline __attribute__ ((__gnu_inline__))__USE_XOPEN2K8__WIFSIGNALED(status) (((signed char) (((status) & 0x7f) + 1) >> 1) > 0)RADEON_INFO_NUM_BACKENDS 0x0a__cookie_io_functions_t_defined 1RENAME_EXCHANGE (1 << 1)DRM_CAP_DUMB_PREFERRED_DEPTH 0x3RADEON_UPLOAD_ALL 0x003effff__UINT_FAST8_MAX__ 0xffDRM_MODE_PRESENT_TOP_FIELD (1<<0)__suseconds_t_defined _POSIX_THREAD_PRIO_INHERIT 200809LRADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18_POSIX_READER_WRITER_LOCKS 200809L_GCC_WRAP_STDINT_H uintptr_tDRM_RADEON_SURF_FREE 0x1b__DEC32_EPSILON__ 1E-6DFUINT_LEAST32_MAX (4294967295U)DRM_MODE_FLAG_NVSYNC (1<<3)DRM_EVENT_VBLANK 0x01_POSIX_BARRIERS 200809Lprop_valuesdrmVersionPtrDRM_MODE_TYPE_BUILTIN (1<<0)S_IWGRP (S_IWUSR >> 3)__SIZEOF_PTHREAD_MUTEXATTR_T 4F_ADD_SEALS 1033PTHREAD_THREADS_MAXRADEON_TILING_SWAP_16BIT 0x4__FLT_EVAL_METHOD__ 0DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)_ISspaceHOST_NAME_MAX 64_LP64 1drmPciBusInfoPtrDRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE (1 << 2)GBM_FORMAT_XBGR16161616F __gbm_fourcc_code('X', 'B', '4', 'H')_SC_SPAWN _SC_SPAWNDRM_RADEON_GEM_PWRITE 0x22__bos0(ptr) __builtin_object_size (ptr, 0)RADEON_PARAM_IRQ_NR 5DRM_MODE_ATOMIC_FLAGS ( DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_PAGE_FLIP_ASYNC | DRM_MODE_ATOMIC_TEST_ONLY | DRM_MODE_ATOMIC_NONBLOCK | DRM_MODE_ATOMIC_ALLOW_MODESET)RADEON_UPLOAD_VIEWPORT 0x00000020_SC_2_VERSION _SC_2_VERSION_SC_2_PBS_MESSAGE _SC_2_PBS_MESSAGE__USE_XOPEN__FLT32X_DENORM_MIN__ 4.94065645841246544176568792868221372e-324F32x_SC_SYSTEM_DATABASE _SC_SYSTEM_DATABASEGBM_FORMAT_XRGB1555 __gbm_fourcc_code('X', 'R', '1', '5')external_revDRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)RADEON_CMD_SCALARS2 7__LDBL_MAX_10_EXP__ 4932__UINT_FAST8_TYPE__ unsigned charF_SET_RW_HINT 1036__INT_LEAST16_TYPE__ short int__PTHREAD_MUTEX_HAVE_PREV 1__S_IFSOCK 0140000EDEADLK 35RADEON_UPLOAD_CLIPRECTS 0x00008000__nlink_t_defined __BIG_ENDIAN 4321DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)_POSIX_UIO_MAXIOV 16R300_NEW_WAIT_3D_3D_CLEAN 0x6_POSIX_PRIORITY_SCHEDULING 200809Lhtole64(x) __uint64_identity (x)S_IXGRP (S_IXUSR >> 3)DRM_MODE_TYPE_DEFAULT (1<<4)ENOLINK 67DRM_PLANE_TYPE_CURSOR 2_PC_MAX_INPUT _PC_MAX_INPUT__stub_setlogin DRM_IOCTL_MODE_DESTROYPROPBLOB DRM_IOWR(0xBE, struct drm_mode_destroy_blob)__INT_LEAST64_TYPE__ long int__LDBL_EPSILON__ 1.08420217248550443400745280086994171e-19L__isalnum_l(c,l) __isctype_l((c), _ISalnum, (l))_CS_POSIX_V6_ILP32_OFF32_CFLAGS _CS_POSIX_V6_ILP32_OFF32_CFLAGSAMDGPU_VM_PAGE_EXECUTABLE (1 << 3)DRM_SYNCOBJ_QUERY_FLAGS_LAST_SUBMITTED (1 << 0)isprint_l(c,l) __isprint_l ((c), (l))F_SETFL 4__glibc_c99_flexarr_available 1S_IROTH (S_IRGRP >> 3)AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5__toascii_l(c,l) ((l), __toascii (c))GBM_BO_IMPORT_FD_PLANAR 0x5504__FLT64_DECIMAL_DIG__ 17UTIME_NOW ((1l << 30) - 1l)DRM_RADEON_CP_INIT 0x00strncmp__FLT64X_DIG__ 18DRM_MAX_ORDER 22RADEON_CS_USE_VM 0x02_XOPEN_XCU_VERSION 4__S_ISUID 04000AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9_CS_POSIX_V6_LPBIG_OFFBIG_CFLAGS _CS_POSIX_V6_LPBIG_OFFBIG_CFLAGSR300_CMD_R500FP 9DRM_MODE_FLAG_BCAST (1<<10)IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT)_CS_XBS5_LP64_OFF64_LIBS _CS_XBS5_LP64_OFF64_LIBS__FLT32_HAS_QUIET_NAN__ 1INT32_MAX (2147483647)__bitwise __bitwise__SYNC_FILE_RANGE_WRITE 2RADEON_CMD_PACKET3_CLIP 6__SIG_ATOMIC_TYPE__ intAMDGPU_INFO_VIDEO_CAPS 0x21R200_EMIT_PP_TXFILTER_3 39__SIZEOF_FLOAT__ 4F_SHLCK 8le16toh(x) __uint16_identity (x)EUCLEAN 117freeDRM_RADEON_INIT_HEAP 0x15AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12)_drmUsbDeviceInfo__SSIZE_T_TYPE __SWORD_TYPE_CS_XBS5_LPBIG_OFFBIG_CFLAGS _CS_XBS5_LPBIG_OFFBIG_CFLAGSPTHREAD_STACK_MIN 16384RADEON_EMIT_PP_TEX_SIZE_2 75DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip)_IO_USER_LOCK 0x8000RADEON_MAX_SURFACES 8_XOPEN_XPG4 1__ILP32_OFF32_CFLAGS "-m32"_SC_XOPEN_ENH_I18N _SC_XOPEN_ENH_I18NF_GETPIPE_SZ 1032_BSD_SIZE_T_DEFINED_ CLEAR_Y1 1DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8<<14)DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx)RADEON_LINES 0x2RADEON_INFO_ACTIVE_CU_COUNT 0x20DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map)__DEC64_MANT_DIG__ 16__FD_CLR(d,set) ((void) (__FDS_BITS (set)[__FD_ELT (d)] &= ~__FD_MASK (d)))connector_type_idAMDGPU_INFO_VIDEO_CAPS_DECODE 0R200_EMIT_RE_SCISSOR_TL_0 54drmModeConnection__glibc_likely(cond) __builtin_expect ((cond), 1)FALLOC_FL_UNSHARE_RANGE 0x40_DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)EL2HLT 51_XOPEN_SOURCE 700__S_IEXEC 0100isascii_l(c,l) __isascii_l ((c), (l))_ISpunct_CS_LFS64_LIBS _CS_LFS64_LIBSDRM_IOC_READ _IOC_READ__GCC_ASM_FLAG_OUTPUTS__ 1virtual_address_offsetDRM_MODE_CURSOR_MOVE 0x02DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)__UINT_FAST64_TYPE__ long unsigned intDRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4ESOCKTNOSUPPORT 94DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0)F_GETFL 3CLEAR_X2 2DRM_MODE_TYPE_PREFERRED (1<<3)__GCC_ATOMIC_LONG_LOCK_FREE 2__BIGGEST_ALIGNMENT__ 16_POSIX_OPEN_MAX 20ispunct(c) __isctype((c), _ISpunct)_GETOPT_CORE_H 1_CS_POSIX_V7_LP64_OFF64_LIBS _CS_POSIX_V7_LP64_OFF64_LIBS__ASM_GENERIC_BITS_PER_LONG DN_ACCESS 0x00000001DRM_MODE_SCALE_ASPECT 3__HAVE_FLOAT32 1drmHost1xDeviceInfoPtr_GCC_PTRDIFF_T S_IRWXG (S_IRWXU >> 3)R200_EMIT_PP_CUBIC_OFFSETS_1 64DT_LNK DT_LNKR300_CMD_END3D 4__f32(x) x ##f32__INT_FAST64_MAX__ 0x7fffffffffffffffLRADEON_USE_COMP_ZBUF 0x20000000DRM_IOCTL_SYNCOBJ_TRANSFER DRM_IOWR(0xCC, struct drm_syncobj_transfer)__LDBL_MIN_EXP__ (-16381)UINT32_WIDTH 32__F_GETOWN 9__DEC128_MAX_EXP__ 6145__BITS_PER_LONG 64ispunct_l(c,l) __ispunct_l ((c), (l))DRM_COMMAND_END 0xA0DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property)DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0)__stub_sigreturn STDIN_FILENO 0_CS_POSIX_V6_LP64_OFF64_LINTFLAGS _CS_POSIX_V6_LP64_OFF64_LINTFLAGS_SC_V6_ILP32_OFF32 _SC_V6_ILP32_OFF32DRM_MODE_PICTURE_ASPECT_256_135 4_IO_wide_dataNR_OPEN 1024__FD_MASK(d) ((__fd_mask) (1UL << ((d) % __NFDBITS)))ESTALE 116AMDGPU_GEM_USERPTR_READONLY (1 << 0)_POSIX_THREAD_ROBUST_PRIO_PROTECT -1RADEON_BACK 0x2DRM_MODE_SCALE_FULLSCREEN 1AMDGPU_INFO_TIMESTAMP 0x05R200_EMIT_PP_CUBIC_FACES_2 65_ISlower__mode_t_defined DRM_IOCTL_CRTC_QUEUE_SEQUENCE DRM_IOWR(0x3c, struct drm_crtc_queue_sequence)_POSIX_ASYNCHRONOUS_IO 200809LAMDGPU_IB_FLAGS_SECURE (1 << 5)DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique)DRM_RADEON_GEM_CREATE 0x1d__U16_TYPE unsigned short intEPROTO 71__S_IFDIR 0040000__timeval_defined 1vtotal_POSIX_CHOWN_RESTRICTED 0_SC_IOV_MAX _SC_IOV_MAXAMDGPU_HW_IP_VCN_ENC 7drmHost1xBusInfoPtrEREMOTE 66__CHAR32_TYPE__ unsigned intGBM_FORMAT_ARGB1555 __gbm_fourcc_code('A', 'R', '1', '5')RADEON_UPLOAD_TCL 0x00000080__DEC128_EPSILON__ 1E-33DL__UINT16_TYPE__ short unsigned intAMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4)__FLT_MIN_EXP__ (-125)__UINT_LEAST64_TYPE__ long unsigned intDRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)AMDGPU_VRAM_TYPE_GDDR4 4R200_EMIT_PP_TXCTLALL_5 93RADEON_GEM_USERPTR_VALIDATE (1 << 2)AT_SYMLINK_FOLLOW 0x400O_APPEND 02000__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1__S_TYPEISSEM(buf) ((buf)->st_mode - (buf)->st_mode)__LP64_OFF64_LDFLAGS "-m64"R200_EMIT_RE_POINTSIZE 59__SYSCALL_SLONG_TYPE __SLONGWORD_TYPEEAFNOSUPPORT 97__INT_LEAST8_WIDTH__ 8_POSIX_RE_DUP_MAX 255__USECONDS_T_TYPE __U32_TYPESEEK_CUR 1__USE_XOPEN_EXTENDED 1DRM_CONTROL_MINOR_NAME "controlD"date_lenGBM_FORMAT_XBGR8888 __gbm_fourcc_code('X', 'B', '2', '4')__GNU_LIBRARY__ 6AMDGPU_INFO_FW_SMC 0x0a_old_offset__USE_UNIX98__wur EDESTADDRREQ 89AMDGPU_TILING_ARRAY_MODE_SHIFT 0EBFONT 59DRM_MODE_CONTENT_PROTECTION_DESIRED 1FOPEN_MAX 16RADEON_SETPARAM_SWITCH_TILING 2_POSIX_MAX_INPUT 255_POSIX_SEM_NSEMS_MAX 256DRM_RADEON_INFO 0x27EXIT_SUCCESS 0INT_LEAST8_MIN (-128)AMDGPU_IDS_FLAGS_PREEMPTION 0x2__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__RADEON_SETPARAM_PCIGART_LOCATION 3htotal_ISbit(bit) ((bit) < 8 ? ((1 << (bit)) << 8) : ((1 << (bit)) >> 8))EWOULDBLOCK EAGAINF_SETSIG __F_SETSIGDRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding)__FD_SETSIZE 1024_POSIX_NO_TRUNC 1ENAMETOOLONG 36DRM_AMDGPU_GEM_OP 0x10O_RSYNC O_SYNC__GLIBC_INTERNAL_STARTING_HEADER_IMPLEMENTATION DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite)__STDC__ 1_SC_THREAD_KEYS_MAX _SC_THREAD_KEYS_MAX_POSIX_SYNCHRONIZED_IO 200809LEBADF 9_ASM_GENERIC_INT_LL64_H /workingAMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)_ISOC11_SOURCE 1RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83DRM_MODE_FLAG_ALL (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLSCAN | DRM_MODE_FLAG_CSYNC | DRM_MODE_FLAG_PCSYNC | DRM_MODE_FLAG_NCSYNC | DRM_MODE_FLAG_HSKEW | DRM_MODE_FLAG_DBLCLK | DRM_MODE_FLAG_CLKDIV2 | DRM_MODE_FLAG_3D_MASK)_CS_GNU_LIBPTHREAD_VERSION _CS_GNU_LIBPTHREAD_VERSIONprim_buf_gpu_addrGBM_FORMAT_BGR565 __gbm_fourcc_code('B', 'G', '1', '6')DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)gs_prim_buffer_depthR200_EMIT_OUTPUT_VTX_COMP_SEL 49le32toh(x) __uint32_identity (x)ETIMEDOUT 110DRM_MODE_FLAG_3D_FRAME_PACKING (1<<14)devsDRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx)F_SETLK64 6__STRICT_ANSI__ 1DRM_MODE_CONNECTOR_Composite 5MQ_PRIO_MAX 32768_MKNOD_VER_LINUX 0alloca(size) __builtin_alloca (size)DRM_AMDGPU_FENCE_TO_HANDLE 0x14num_shader_arrays_per_engineS_IWOTH (S_IWGRP >> 3)__SLONGWORD_TYPE long int__INO64_T_TYPE __UQUAD_TYPER200_EMIT_PP_CUBIC_OFFSETS_5 72__NLINK_T_TYPE __SYSCALL_ULONG_TYPERADEON_CARD_AGP 1_SC_V6_LP64_OFF64 _SC_V6_LP64_OFF64__ILP32_OFFBIG_LDFLAGS "-m32"RADEON_EMIT_RE_LINE_PATTERN 3DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0_ENDIAN_H 1_SC_MB_LEN_MAX _SC_MB_LEN_MAX__isupper_l(c,l) __isctype_l((c), _ISupper, (l))__GNUC_STDC_INLINE__ 1DRM_RADEON_GEM_PREAD 0x21_PC_SYNC_IO _PC_SYNC_IO_POSIX_THREAD_KEYS_MAX 128__BLKCNT_T_TYPE __SYSCALL_SLONG_TYPE__ASMNAME(cname) __ASMNAME2 (__USER_LABEL_PREFIX__, cname)__SIZEOF_LONG_LONG__ 8__PTHREAD_MUTEX_LOCK_ELISION 1ESRMNT 69AMDGPU_VM_MTYPE_RW (5 << 5)fwrite_unlocked(ptr,size,n,stream) (__extension__ ((__builtin_constant_p (size) && __builtin_constant_p (n) && (size_t) (size) * (size_t) (n) <= 8 && (size_t) (size) != 0) ? ({ const char *__ptr = (const char *) (ptr); FILE *__stream = (stream); size_t __cnt; for (__cnt = (size_t) (size) * (size_t) (n); __cnt > 0; --__cnt) if (putc_unlocked (*__ptr++, __stream) == EOF) break; ((size_t) (size) * (size_t) (n) - __cnt) / (size_t) (size); }) : (((__builtin_constant_p (size) && (size_t) (size) == 0) || (__builtin_constant_p (n) && (size_t) (n) == 0)) ? ((void) (ptr), (void) (stream), (void) (size), (void) (n), (size_t) 0) : fwrite_unlocked (ptr, size, n, stream))))DRM_RADEON_CP_RESUME 0x18O_NONBLOCK 04000_SC_V7_LP64_OFF64 _SC_V7_LP64_OFF64__USE_ATFILEAMDGPU_CTX_OP_QUERY_STATE2 4_unused2__stub_stty _SC_V7_LPBIG_OFFBIG _SC_V7_LPBIG_OFFBIG_SC_XBS5_ILP32_OFFBIG _SC_XBS5_ILP32_OFFBIG_GETOPT_POSIX_H 1__USE_GNU 1drmCommandWriteRead_XOPEN_SOURCEENOBUFS 105DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy)IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)_POSIX_AIO_LISTIO_MAX 2GBM_DEV_TYPE_FLAG_ARMSOC (1u << 3)__WORDSIZE_TIME64_COMPAT32 1__WCOREFLAG 0x80__FLT64_MIN_EXP__ (-1021)DRM_IOCTL_MODE_CREATE_LEASE DRM_IOWR(0xC6, struct drm_mode_create_lease)__USER_LABEL_PREFIX__ ENODEV 19__GNUC_MINOR__ 3__undef_OPEN_MAXDRM_MODE_PRESENT_BOTTOM_FIELD (1<<1)DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client)AMDGPU_TILING_TILE_SPLIT_MASK 0x7__FLT64X_HAS_INFINITY__ 1EMFILE 24R300_WAIT_3D_CLEAN 0x4dri_node_sizeBIG_ENDIAN __BIG_ENDIANCIK_TILE_MODE_DEPTH_STENCIL_1D 5EHOSTDOWN 112DRM_IOC_READWRITE _IOC_READ|_IOC_WRITERADEON_UPLOAD_TEX2 0x00000800DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd)DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version)desc_len__WINT_WIDTH__ 32__need_NULLgbm_create_devicegbm_detect_device_info_pathDRM_AMDGPU_WAIT_FENCES 0x12readdir_POSIX_THREAD_DESTRUCTOR_ITERATIONS 4__linux__ 1_POSIX_SHELL 1__has_include(STR) __has_include__(STR)islower_l(c,l) __islower_l ((c), (l))_IOLBF 1__WCOREDUMP(status) ((status) & __WCOREFLAG)ENOPKG 65AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)AMDGPU_INFO_NUM_EVICTIONS 0x18_POSIX_PATH_MAX 256DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2)RADEON_TILING_EG_TILE_SPLIT_MASK 0xfS_ISGID __S_ISGIDAMDGPU_GEM_DOMAIN_GWS 0x10__GLIBC_USE_LIB_EXT2__S_IFIFO 0010000RADEON_INFO_CRTC_FROM_ID 0x04__FLT_HAS_QUIET_NAN__ 1INT32_MIN (-2147483647-1)AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1Eprogram_invocation_name__HAVE_DISTINCT_FLOAT64X 0RADEON_TRIANGLE_FAN 0x5S_IRWXO (S_IRWXG >> 3)PDP_ENDIAN __PDP_ENDIAN__ENUM_IDTYPE_T 1video_capSSIZE_MAX LONG_MAXRADEON_VM_PAGE_SYSTEM (1 << 3)RADEON_REQUIRE_QUIESCENCE 0x00010000__S_IFLNK 0120000_SC_SIGNALS _SC_SIGNALS__INT64_C(c) c ## LDRM_IOCTL_BASE 'd'GBM_MAX_PLANES 4SPLICE_F_NONBLOCK 2SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3__SIZEOF_PTHREAD_BARRIERATTR_T 4__FLT64X_MIN__ 3.36210314311209350626267781732175260e-4932F64x_POSIX_TYPED_MEMORY_OBJECTS -1_SC_SHARED_MEMORY_OBJECTS _SC_SHARED_MEMORY_OBJECTS__UINT64_TYPE__ long unsigned intAMDGPU_FAMILY_CI 120ECONNREFUSED 111RADEON_UPLOAD_VERTFMT 0x00000002GBM_FORMAT_ABGR2101010 __gbm_fourcc_code('A', 'B', '3', '0')__DBL_MAX_10_EXP__ 308DRM_BUS_HOST1X 3RADEON_SETPARAM_FB_LOCATION 1__SIZE_MAX__ 0xffffffffffffffffULR200_EMIT_TCL_POINT_SPRITE_CNTL 77R200_EMIT_PP_TXOFFSET_2 44AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f__stub_fattach __S_TYPEISSHM(buf) ((buf)->st_mode - (buf)->st_mode)CLEAR_Y2 3_SC_BARRIERS _SC_BARRIERSDRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap)RADEON_PARAM_GART_BUFFER_OFFSET 1__feof_unlocked_body(_fp) (((_fp)->_flags & _IO_EOF_SEEN) != 0)__CFLOAT32 _Complex _Float32wave_front_sizeDRM_AMDGPU_GEM_USERPTR 0x11GBM_DEV_TYPE_FLAG_3D (1u << 2)DRM_MODE_FEATURE_DIRTYFB 1SEEK_SET 0_SC_PRIORITY_SCHEDULING _SC_PRIORITY_SCHEDULING_SC_AIO_PRIO_DELTA_MAX _SC_AIO_PRIO_DELTA_MAXENETUNREACH 101_CS_V7_ENV _CS_V7_ENV__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1__DEC64_MIN_EXP__ (-382)SEM_VALUE_MAX (2147483647)__REDIRECT_NTH_LDBL(name,proto,alias) __REDIRECT_NTH (name, proto, alias)AMDGPU_IDS_FLAGS_FUSION 0x1AMDGPU_GEM_METADATA_OP_SET_METADATA 1__FLT128_MAX_10_EXP__ 4932DRM_AMDGPU_WAIT_CS 0x09AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3EFAULT 14__aligned_be64 __be64 __attribute__((aligned(8)))_IOW_BAD(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size))iscntrl_l(c,l) __iscntrl_l ((c), (l))UINT8_WIDTH 8RADEON_VA_MAP 1_DRM_VBLANK_HIGH_CRTC_SHIFT 1__PTHREAD_RWLOCK_ELISION_EXTRA 0, { 0, 0, 0, 0, 0, 0, 0 }__S_IFMT 0170000RADEON_LOCAL_TEX_HEAP 0__GID_T_TYPE __U32_TYPERADEON_TRIANGLE_STRIP 0x6RADEON_GEM_NO_BACKING_STORE (1 << 0)RADEON_CHUNK_ID_CONST_IB 0x04DRM_MODE_FLAG_PIC_AR_64_27 (DRM_MODE_PICTURE_ASPECT_64_27<<19)DRM_MODE_FLAG_PIXMUX (1<<11)param_buf_gpu_addrisalnum(c) __isctype((c), _ISalnum)__ILP32_OFFBIG_CFLAGS "-m32 -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64"AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)_SC_LEVEL3_CACHE_ASSOC _SC_LEVEL3_CACHE_ASSOC_IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0)EIO 5RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19RADEON_EMIT_PP_CNTL 1__ino64_tS_IWUSR __S_IWRITEAMDGPU_HW_IP_VCN_JPEG 8EL3RST 47DRM_MODE_CONNECTOR_DSI 16DRM_CONNECTOR_NAME_LEN 32_IO_lock_tDRM_MODE_FLAG_PIC_AR_NONE (DRM_MODE_PICTURE_ASPECT_NONE<<19)EDEADLOCK EDEADLKRADEON_PARAM_DEVICE_ID 16_BITS_UINTN_IDENTITY_H 1__FD_ZERO_STOS "stosq"W_OK 2LOCK_SH 1DRM_PLANE_TYPE_OVERLAY 0__FSWORD_T_TYPE __SYSCALL_SLONG_TYPE__HAVE_FLOAT64X 1_BITS_TYPES_LOCALE_T_H 1_SC_MESSAGE_PASSING _SC_MESSAGE_PASSING__FLT64_HAS_DENORM__ 1__LDBL_DIG__ 18AMDGPU_IB_FLAG_CE (1<<0)DRM_MODE_PAGE_FLIP_EVENT 0x01__useconds_t_defined _SC_NETWORKING _SC_NETWORKINGRADEON_UPLOAD_CONTEXT_ALL 0x003e01ffDRM_MODE_DIRTY_OFF 0__INO_T_TYPE __SYSCALL_ULONG_TYPEUINT_FAST32_MAX (18446744073709551615UL)__FLT64_MIN_10_EXP__ (-307)__W_EXITCODE(ret,sig) ((ret) << 8 | (sig))__OFF64_T_TYPE __SQUAD_TYPEAMDGPU_CTX_OP_GET_STABLE_PSTATE 5__extern_always_inline extern __always_inline __attribute__ ((__gnu_inline__))out_fd_POSIX_FSYNC 200809LRADEON_PARAM_STATUS_HANDLE 8INT_LEAST32_MAX (2147483647)GBM_FORMAT_XRGB2101010 __gbm_fourcc_code('X', 'R', '3', '0')vram_type__S_IFCHR 0020000_POSIX_C_SOURCE__ATOMIC_HLE_ACQUIRE 65536_IOC_NRBITS 8UINT32_MAX (4294967295U)DRM_EVENT_CONTEXT_VERSION 4__bswap_constant_32(x) ((((x) & 0xff000000u) >> 24) | (((x) & 0x00ff0000u) >> 8) | (((x) & 0x0000ff00u) << 8) | (((x) & 0x000000ffu) << 24))_SC_SYSTEM_DATABASE_R _SC_SYSTEM_DATABASE_R__uint8_t__DBL_MAX__ ((double)1.79769313486231570814527423731704357e+308L)__S_IREAD 0400WCHAR_MIN __WCHAR_MINtoupper(c) __tobody (c, toupper, *__ctype_toupper_loc (), (c))_SC_MEMLOCK _SC_MEMLOCK__POSIX_FADV_NOREUSE 5__GLIBC__ 2_SC_THREAD_ROBUST_PRIO_PROTECT _SC_THREAD_ROBUST_PRIO_PROTECTDRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL (4<<14)RADEON_SETPARAM_VBLANK_CRTC 6DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)_CS_POSIX_V7_LPBIG_OFFBIG_CFLAGS _CS_POSIX_V7_LPBIG_OFFBIG_CFLAGS__UINT8_C(c) c_POSIX2_C_BIND __POSIX2_THIS_VERSIONUINTPTR_WIDTH __WORDSIZEEMEDIUMTYPE 124__SIZEOF_PTHREAD_COND_T 48_STATBUF_ST_BLKSIZE drmGetVersion__INTMAX_C(c) c ## LDRM_NODE_NAME_MAX (sizeof(DRM_DIR_NAME) + 1 + MAX3(sizeof(DRM_PRIMARY_MINOR_NAME), sizeof(DRM_CONTROL_MINOR_NAME), sizeof(DRM_RENDER_MINOR_NAME)) + sizeof("144") + 1)AMDGPU_VRAM_TYPE_GDDR6 9__FLT64_MAX__ 1.79769313486231570814527423731704357e+308F64__USE_ISOC11 1DRV_RADEON 1errno (*__errno_location ())AMDGPU_VRAM_TYPE_DDR3 7AMDGPU_INFO_SENSOR_VDDGFX 0x7AMDGPU_CHUNK_ID_DEPENDENCIES 0x03__WCHAR_TYPE__ intAMDGPU_VA_OP_UNMAP 2htobe16(x) __bswap_16 (x)DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)__blksize_t_defined R200_EMIT_PP_TXFILTER_2 38toascii_l(c,l) __toascii_l ((c), (l))ENOTNAM 118DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)AMDGPU_INFO_VBIOS_SIZE 0x1DRM_MODE_CONNECTOR_eDP 14DRM_SPINUNLOCK(spin,val) do { DRM_CAS_RESULT(__ret); if ((*spin).lock == val) { do { DRM_CAS(spin,val,0,__ret); } while (__ret); } } while(0)_POSIX_MEMORY_PROTECTION 200809L_SC_NZERO _SC_NZEROEOWNERDEAD 130__GNUC__ 8_SC_HOST_NAME_MAX _SC_HOST_NAME_MAX__SIZEOF_PTHREAD_CONDATTR_T 4__SYSCALL_ULONG_TYPE __ULONGWORD_TYPE__GLIBC_INTERNAL_STARTING_HEADER_IMPLEMENTATION_LFS64_ASYNCHRONOUS_IO 1__ptr_t void *__BEGIN_DECLS L_SET SEEK_SET__lldiv_t_defined 1O_ASYNC 020000AMDGPU_INFO_FW_UVD 0x2S_IFIFO __S_IFIFO__INT_WIDTH__ 32DRM_CAP_ADDFB2_MODIFIERS 0x10__GLIBC_MINOR__ 28drmUsbDeviceInfoPtrst_mtime st_mtim.tv_secF_GETSIG __F_GETSIGAMDGPU_INFO_MMR_SH_INDEX_MASK 0xff_POSIX_TIMERS 200809LWNOWAIT 0x01000000toascii(c) __toascii (c)RADEON_UPLOAD_LINE 0x00000004_POSIX_MAPPED_FILES 200809L__STDC_VERSION__ 199901L__USE_POSIX2 1__DBL_HAS_INFINITY__ 1__FLT_EVAL_METHOD_TS_18661_3__ 0_PC_VDISABLE _PC_VDISABLER200_EMIT_PP_CUBIC_FACES_1 63DRM_IOCTL_MODE_LIST_LESSEES DRM_IOWR(0xC7, struct drm_mode_list_lessees)_SC_CPUTIME _SC_CPUTIMEAMDGPU_INFO_FW_TOC 0x15__SSE_MATH__ 1_SC_NL_TEXTMAX _SC_NL_TEXTMAX_SC_LEVEL4_CACHE_SIZE _SC_LEVEL4_CACHE_SIZEst_atime st_atim.tv_sec__SIG_ATOMIC_MAX__ 0x7fffffffDRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_PAGE_FLIP_ASYNC | DRM_MODE_PAGE_FLIP_TARGET)DRM_RADEON_RESET 0x05_SC_2_PBS_LOCATE _SC_2_PBS_LOCATE_IOC_NRSHIFT 0DRM_CLIENT_CAP_ASPECT_RATIO 4__stub_fdetach R200_EMIT_PP_TXCTLALL_1 89_SC_PIPE _SC_PIPEXATTR_LIST_MAX 65536AMDGPU_CHUNK_ID_FENCE 0x02SI_TILE_MODE_COLOR_1D 13AMDGPU_IDS_FLAGS_TMZ 0x4_SC_NL_MSGMAX _SC_NL_MSGMAXst_ctime st_ctim.tv_secle64toh(x) __uint64_identity (x)FALLOC_FL_INSERT_RANGE 0x20_XOPEN_ENH_I18N 1_SC_XOPEN_REALTIME _SC_XOPEN_REALTIMERADEON_TILING_SURFACE 0x10AMDGPU_INFO_FW_VCN 0x0efd_node_num_IOFBF 0RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2INT16_MIN (-32767-1)_POSIX_NAME_MAX 14RADEON_FRONT 0x1drmModeSubPixel__HAVE_FLOAT16 0_drmHost1xDeviceInfoDRM_MODE_PICTURE_ASPECT_16_9 2_SC_XOPEN_LEGACY _SC_XOPEN_LEGACYDRM_RADEON_STIPPLE 0x0C__INT_FAST32_WIDTH__ 64__linux 1_SC_RE_DUP_MAX _SC_RE_DUP_MAXDRM_MODE_FLAG_PCSYNC (1<<7)DRM_ERR_NO_FD (-1005)POSIX_FADV_NOREUSE __POSIX_FADV_NOREUSEDRM_COMMAND_BASE 0x40__FLT32X_MANT_DIG__ 53DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)dir_entSI_TILE_MODE_COLOR_2D_64BPP 17_ATFILE_SOURCE 1__GCC_ATOMIC_SHORT_LOCK_FREE 2_IO_ERR_SEEN 0x0020DRM_IOCTL_RADEON_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_USERPTR, struct drm_radeon_gem_userptr)max_widthDRM_CRTC_SEQUENCE_NEXT_ON_MISS 0x00000002_SC_2_LOCALEDEF _SC_2_LOCALEDEFRADEON_EMIT_RB3D_STENCILREFMASK 7DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)__END_DECLS DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)FD_CLR(fd,fdsetp) __FD_CLR (fd, fdsetp)stdin stdinquery_hw_ipd_fileno d_ino__errno_location_STAT_VER _STAT_VER_LINUX_GCC_WCHAR_T __SIZEOF_INT128__ 16FALLOC_FL_PUNCH_HOLE 0x02_SC_V6_LPBIG_OFFBIG _SC_V6_LPBIG_OFFBIGAMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf_LINUX_LIMITS_H DT_DIR DT_DIR_STAT_VER_LINUX 1____FILE_defined 1mmWidthARRAY_SIZE(A) (sizeof(A) / sizeof(*(A)))__RLIM64_T_TYPE __UQUAD_TYPER300_CMD_PACKET3_RAW 1__has_include_next(STR) __has_include_next__(STR)_POSIX_SSIZE_MAX 32767RADEON_EMIT_RE_MISC 11__INTPTR_TYPE__ long intDRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)__INT_LEAST32_WIDTH__ 32_SC_PII_OSI_COTS _SC_PII_OSI_COTSdrmModeModeInfoPtr_CS_XBS5_LP64_OFF64_CFLAGS _CS_XBS5_LP64_OFF64_CFLAGS__USE_XOPEN2KXSI 1F_EXLCK 4__DEC32_MANT_DIG__ 7DRM_MODE_FB_MODIFIERS (1<<1)__u_intN_t(N,MODE) typedef unsigned int u_int ##N ##_t __attribute__ ((__mode__ (MODE)))DRM_ERR_NO_DEVICE (-1001)__bswap_constant_64(x) ((((x) & 0xff00000000000000ull) >> 56) | (((x) & 0x00ff000000000000ull) >> 40) | (((x) & 0x0000ff0000000000ull) >> 24) | (((x) & 0x000000ff00000000ull) >> 8) | (((x) & 0x00000000ff000000ull) << 8) | (((x) & 0x0000000000ff0000ull) << 24) | (((x) & 0x000000000000ff00ull) << 40) | (((x) & 0x00000000000000ffull) << 56))__O_NOATIME 01000000__PDP_ENDIAN 3412ids_flagsRADEON_UPLOAD_MASKS 0x00000010RADEON_VA_RESULT_OK 0__FLT32X_EPSILON__ 2.22044604925031308084726333618164062e-16F32xstrdupa(s) (__extension__ ({ const char *__old = (s); size_t __len = strlen (__old) + 1; char *__new = (char *) __builtin_alloca (__len); (char *) memcpy (__new, __old, __len); }))DRM_MODE_DISCONNECTED___int_ptrdiff_t_h R300_WAIT_3D 0x2DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)R200_EMIT_PP_CUBIC_OFFSETS_4 70__FLT64_MAX_10_EXP__ 308_T_PTRDIFF_ __INT_WCHAR_T_H _POSIX_CLOCKRES_MIN 20000000DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)__RLIM_T_TYPE __SYSCALL_ULONG_TYPEEILSEQ 84RADEON_PARAM_LAST_CLEAR 4_SC_LEVEL1_DCACHE_ASSOC _SC_LEVEL1_DCACHE_ASSOC_SYS_CDEFS_H 1_IO_EOF_SEEN 0x0010__SIZEOF_DOUBLE__ 8_CS_XBS5_ILP32_OFFBIG_LIBS _CS_XBS5_ILP32_OFFBIG_LIBSEISDIR 21DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3<<14)GBM_FORMAT_ABGR4444 __gbm_fourcc_code('A', 'B', '1', '2')UTIL_H ENOTSOCK 88_IO_backup_baseDRM_RADEON_ALLOC 0x13R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35_POSIX_TIMEOUTS 200809L__UINT_LEAST8_TYPE__ unsigned char__HAVE_DISTINCT_FLOAT32X 0___int_size_t_h AMDGPU_INFO_SENSOR_GFX_SCLK 0x1ESTRPIPE 86UINT_LEAST16_MAX (65535)_SC_PII_INTERNET_DGRAM _SC_PII_INTERNET_DGRAMDRM_CAP_CURSOR_HEIGHT 0x9__FLT64_EPSILON__ 2.22044604925031308084726333618164062e-16F64_SC_FILE_SYSTEM _SC_FILE_SYSTEM__DECIMAL_BID_FORMAT__ 1EOPNOTSUPP 95RWF_WRITE_LIFE_NOT_SET 0R200_EMIT_PP_CUBIC_FACES_5 71__LDBL_DENORM_MIN__ 3.64519953188247460252840593361941982e-4951L__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1EEXIST 17DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode)RADEON_TILING_EG_BANKH_MASK 0xf_CS_POSIX_V6_ILP32_OFF32_LDFLAGS _CS_POSIX_V6_ILP32_OFF32_LDFLAGS_FALLOC_H_ _IOC_NONE 0U_CS_POSIX_V5_WIDTH_RESTRICTED_ENVS _CS_V5_WIDTH_RESTRICTED_ENVSRADEON_EMIT_PP_MISC 0be64toh(x) __bswap_64 (x)RADEON_INFO_CURRENT_GPU_TEMP 0x21__FLT_HAS_INFINITY__ 1_DRM_MODE_H RADEON_EMIT_PP_TEX_SIZE_1 74__undef_LINK_MAXEAGAIN 11__INT_FAST16_TYPE__ long int__x86_64__ 1_POSIX_PIPE_BUF 512DT_REG DT_REG__WCHAR_MAX__ 0x7fffffff_sys_errlistDRM_IOC_WRITE _IOC_WRITEDT_WHT DT_WHTDRM_DEVICE_GET_PCI_REVISION (1 << 0)AMDGPU_INFO_VCE_CLOCK_TABLE 0x1AEADDRINUSE 98RADEON_INFO_FUSION_GART_WORKING 0x0cAMDGPU_TILING_BANK_WIDTH_MASK 0x3_CS_POSIX_V7_LP64_OFF64_CFLAGS _CS_POSIX_V7_LP64_OFF64_CFLAGSconnector_typeDRM_RADEON_INDIRECT 0x0D_ISprint__FLT32_MIN_10_EXP__ (-37)__FLT64X_MAX__ 1.18973149535723176502126385303097021e+4932F64xDRM_RADEON_GEM_VA 0x2bDRM_MODE_DPMS_STANDBY 1SIG_ATOMIC_MAX (2147483647)GBM_FORMAT_BGRX1010102 __gbm_fourcc_code('B', 'X', '3', '0')__FLT64X_MIN_10_EXP__ (-4931)GBM_FORMAT_VYUY __gbm_fourcc_code('V', 'Y', 'U', 'Y')_drmUsbBusInfo__SIZEOF_LONG__ 8AT_STATX_SYNC_TYPE 0x6000RADEON_CLEAR_FASTZ 0x80000000__O_PATH 010000000_CS_XBS5_ILP32_OFFBIG_LDFLAGS _CS_XBS5_ILP32_OFFBIG_LDFLAGS_SC_2_PBS _SC_2_PBSGBM_BO_IMPORT_FD_MODIFIER 0x5505_PC_PATH_MAX _PC_PATH_MAXoptoptDRM_EVENT_FLIP_COMPLETE 0x02vsync_endDRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free)__WCHAR_MAX __WCHAR_MAX____FLT_DIG__ 6__FLT128_DECIMAL_DIG__ 36RADEON_CMD_SCALARS 2__ferror_unlocked_body(_fp) (((_fp)->_flags & _IO_ERR_SEEN) != 0)num_cu_per_sh__UINT_LEAST32_MAX__ 0xffffffffUAMDGPU_INFO_DEV_INFO 0x16AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0GBM_BO_IMPORT_WL_BUFFER 0x5501GBM_FORMAT_XBGR4444 __gbm_fourcc_code('X', 'B', '1', '2')_IO_read_endS_IFCHR __S_IFCHR_XOPEN_REALTIME_THREADS 1DRM_RADEON_GEM_WAIT_IDLE 0x24AMDGPU_INFO_HW_IP_COUNT 0x03snprintfRADEON_MAX_TEXTURE_UNITS 3__WSTOPSIG(status) __WEXITSTATUS(status)R200_EMIT_VTX_FMT_0 31DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)_SC_V7_ILP32_OFFBIG _SC_V7_ILP32_OFFBIGAMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44__LDBL_MAX_EXP__ 16384_SIZE_T_DEFINED _POSIX_SEM_VALUE_MAX 32767EBADRQC 56ELIBACC 79S_IFREG __S_IFREG_IO_save_baseEMSGSIZE 90__HAVE_FLOAT32X 1RADEON_GEM_GTT_WC (1 << 2)__FLT32X_MAX_EXP__ 1024ENOEXEC 8AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw)__INT16_C(c) c_SC_LEVEL3_CACHE_LINESIZE _SC_LEVEL3_CACHE_LINESIZE__INT_LEAST8_MAX__ 0x7f__bswap_constant_16(x) ((__uint16_t) ((((x) >> 8) & 0xff) | (((x) & 0xff) << 8)))_WCHAR_T_DEFINED SIZE_WIDTH __WORDSIZE__stub_gtty RADEON_PARAM_SAREA_HANDLE 9DRM_CLIENT_CAP_UNIVERSAL_PLANES 2__ULONG32_TYPE unsigned int__SWORD_TYPE long int__USE_ISOC11AMDGPU_FAMILY_VGH 144GBM_FORMAT_RGBA4444 __gbm_fourcc_code('R', 'A', '1', '2')tcc_disabled_mask__GNU_LIBRARY__DRM_MODE_FLAG_PVSYNC (1<<2)__TIMER_T_TYPE void *mmHeightreturn_pointerDRM_CLOEXEC O_CLOEXEC_SC_LEVEL4_CACHE_LINESIZE _SC_LEVEL4_CACHE_LINESIZE_IO_write_endnum_rb_pipes_SC_NL_ARGMAX _SC_NL_ARGMAX_POSIX_TIMER_MAX 32DRM_MODE_OBJECT_ANY 0__INT_LEAST8_TYPE__ signed charAMDGPU_VCE_CLOCK_TABLE_ENTRIES 6AT_STATX_DONT_SYNC 0x4000__LDBL_MAX__ 1.18973149535723176502126385303097021e+4932LRADEON_INFO_TIMESTAMP 0x11RADEON_INFO_MAX_SCLK 0x1a_SC_2_FORT_DEV _SC_2_FORT_DEVDRM_MODE_ATOMIC_ALLOW_MODESET 0x0400RADEON_NR_SAREA_CLIPRECTS 12DRM_MODE_CONNECTOR_VIRTUAL 15DRM_MODE_ROTATE_0 (1<<0)__PTRDIFF_T S_IXUSR __S_IEXECAMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3)RADEON_SCRATCH_REG_OFFSET 32RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK 0xfreadlinkDRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats)GBM_FORMAT_YVU420 __gbm_fourcc_code('Y', 'V', '1', '2')DRM_PRIMARY_MINOR_NAME "card"__SIZEOF_PTHREAD_MUTEX_T 40__O_DIRECT 040000F_NOTIFY 1026LOCK_NB 4RADEON_EMIT_PP_TXFILTER_0 12__DEC64_MAX_EXP__ 385DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)__ASMNAME2(prefix,cname) __STRING (prefix) cnameAMDGPU_GEM_DOMAIN_OA 0x20__stub_sstk _SC_RTSIG_MAX _SC_RTSIG_MAX__bitwise__ __UWORD_TYPE unsigned long int__FLT32X_DECIMAL_DIG__ 17_SC_MONOTONIC_CLOCK _SC_MONOTONIC_CLOCK__ino64_t_defined _IO_buf_baseAMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT)DRM_IOCTL_SET_CLIENT_CAP DRM_IOW( 0x0d, struct drm_set_client_cap)_SC_2_PBS_CHECKPOINT _SC_2_PBS_CHECKPOINTDRM_AMDGPU_GEM_MMAP 0x01__INT_MAX__ 0x7fffffffESHUTDOWN 108WCHAR_MAX __WCHAR_MAX_SC_TRACE _SC_TRACEDRM_ERR_INVALID (-1004)DRM_RADEON_TEXTURE 0x0ERADEON_EMIT_PP_CUBIC_FACES_2 82__uint16_t_SC_TTY_NAME_MAX _SC_TTY_NAME_MAXDRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)R200_EMIT_PP_TXFILTER_0 36__islower_l(c,l) __isctype_l((c), _ISlower, (l))_SC_XOPEN_SHM _SC_XOPEN_SHM_SC_NL_NMAX _SC_NL_NMAXR200_EMIT_VAP_CTL 32F_SEAL_SHRINK 0x0002_SC_XOPEN_XPG2 _SC_XOPEN_XPG2INTPTR_MAX (9223372036854775807L)_SC_XBS5_LP64_OFF64 _SC_XBS5_LP64_OFF64_SC_SYNCHRONIZED_IO _SC_SYNCHRONIZED_IO__FLT64_DENORM_MIN__ 4.94065645841246544176568792868221372e-324F64drmModeResPtr__LDBL_HAS_INFINITY__ 1_SC_TRACE_SYS_MAX _SC_TRACE_SYS_MAXdrmModeGetResources__SIZEOF_SHORT__ 2__ssize_t_defined count_crtcs__NFDBITS (8 * (int) sizeof (__fd_mask))_STDARG_H __INTMAX_TYPE__ long int__HAVE_FLOAT64X_LONG_DOUBLE 1INT_LEAST16_MAX (32767)__UINT_FAST32_TYPE__ long unsigned int_LFS64_LARGEFILE 1RADEON_GEM_DOMAIN_CPU 0x1O_NOATIME __O_NOATIME_SC_PII_OSI _SC_PII_OSIisalpha(c) __isctype((c), _ISalpha)DRM_MODE_SUBPIXEL_HORIZONTAL_RGB_SC_XOPEN_XPG4 _SC_XOPEN_XPG4R200_EMIT_PP_TXCBLEND_5 26_SC_PASS_MAX _SC_PASS_MAXisascii(c) __isascii (c)_PC_REC_MAX_XFER_SIZE _PC_REC_MAX_XFER_SIZE__FLT_MIN_10_EXP__ (-37)DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)DRM_MODE_FLAG_CLKDIV2 (1<<13)AMDGPU_VM_MTYPE_WC (2 << 5)_POSIX_CPUTIME 0F_SETLKW64 7__REDIRECT_LDBL(name,proto,alias) __REDIRECT (name, proto, alias)_POSIX_NGROUPS_MAX 8__attribute_alloc_size__(params) __attribute__ ((__alloc_size__ params))__u_char_defined drmModeConnectorPtr__PTHREAD_COMPAT_PADDING_END __stub_lchmod AMDGPU_INFO_VBIOS_INFO 0x3F_DUPFD 0__glibc_clang_prereq(maj,min) 0__isspace_l(c,l) __isctype_l((c), _ISspace, (l))gs_vgt_table_depthDRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)DN_MODIFY 0x00000002__isctype_l(c,type,locale) ((locale)->__ctype_b[(int) (c)] & (unsigned short int) type)DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle)INT8_MIN (-128)_drmDevice_SC_FSYNC _SC_FSYNCWNOHANG 1__FXSR__ 1PTRDIFF_MAX (9223372036854775807L)__nonnull(params) __attribute__ ((__nonnull__ params))__error_t_defined 1DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather)AMDGPU_CHUNK_ID_BO_HANDLES 0x06__need_size_t__PTRDIFF_MAX__ 0x7fffffffffffffffL__FLT64_HAS_QUIET_NAN__ 1__USE_ISOC99 1DRM_MODE_FLAG_HSKEW (1<<9)__GNUC_VA_LIST RADEON_TILING_EG_TILE_SPLIT_SHIFT 24DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc)_IO_marker__amd64 1GBM_FORMAT_YUYV __gbm_fourcc_code('Y', 'U', 'Y', 'V')WIFCONTINUED(status) __WIFCONTINUED (status)__MMX__ 1WUNTRACED 2__WINT_TYPE__ unsigned intRADEON_UPLOAD_TEX1 0x00000400__SIZEOF_FLOAT128__ 16__FLT32_HAS_DENORM__ 1R500FP_CONSTANT_CLAMP (1 << 2)__UINT32_C(c) c ## U_BITS_STDINT_INTN_H 1DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct drm_mode_create_blob)DRM_RADEON_CMDBUF 0x10GBM_FORMAT_RGBX1010102 __gbm_fourcc_code('R', 'X', '3', '0')__SIZEOF_WINT_T__ 4__USE_XOPEN 1__USE_POSIX2SIZE_MAX (18446744073709551615UL)DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)__UINT_FAST16_TYPE__ long unsigned int_GNU_SOURCE 1GBM_FORMAT_RGB888 __gbm_fourcc_code('R', 'G', '2', '4')fullnameRADEON_PARAM_LAST_DISPATCH 3__FLT32X_HAS_QUIET_NAN__ 1DRM_DEV_NAME "%s/" DRM_PRIMARY_MINOR_NAME "%d"min_heightDRM_AMDGPU_BO_LIST 0x03virtual_address_alignmentDRM_MODE_FLAG_3D_L_DEPTH (5<<14)DRM_RADEON_INDICES 0x0A__SCHAR_MAX__ 0x7f__GCC_ATOMIC_INT_LOCK_FREE 2__LEAF , __leaf____CHAR16_TYPE__ short unsigned intAMDGPU_INFO_FW_VCE 0x1DRM_MODE_ATOMIC_TEST_ONLY 0x0100_SC_MEMORY_PROTECTION _SC_MEMORY_PROTECTION_STRINGS_H 1R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60__UINT16_MAX__ 0xffffGBM_FORMAT_NV12 __gbm_fourcc_code('N', 'V', '1', '2')DRM_MODE_FB_DIRTY_MAX_CLIPS 256_BITS_TYPESIZES_H 1__UINTMAX_MAX__ 0xffffffffffffffffUL__FLT64X_MAX_EXP__ 16384__FLT32X_MIN_EXP__ (-1021)__FLT64X_HAS_DENORM__ 1RWH_WRITE_LIFE_SHORT 2businfoGBM_FORMAT_YVU444 __gbm_fourcc_code('Y', 'V', '2', '4')R200_EMIT_PP_AFS_1 86DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info)DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res)__always_inline_SC_PAGE_SIZE _SC_PAGESIZE_BITS_POSIX_OPT_H 1_IO_read_ptr__USE_ISOC95vram_bit_widthtolower_l(c,locale) __tolower_l ((c), (locale))__USE_ISOC99isupper_l(c,l) __isupper_l ((c), (l))DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut)AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5DRM_MODE_ENCODER_DAC 1__ASM_X86_BITSPERLONG_H RENAME_NOREPLACE (1 << 0)__O_CLOEXEC 02000000__ino_t_defined RADEON_EMIT_PP_BORDER_COLOR_2 17AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9)isdigit_l(c,l) __isdigit_l ((c), (l))__FLT64_HAS_INFINITY__ 1ENODATA 61__FLT_EPSILON__ 1.19209289550781250000000000000000000e-7Fsubpixel__environDRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property)_SC_THREAD_ROBUST_PRIO_INHERIT _SC_THREAD_ROBUST_PRIO_INHERITGBM_FORMAT_XRGB4444 __gbm_fourcc_code('X', 'R', '1', '2')DRM_MODE_CONNECTOR_LVDS 7_IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(size)))_ISupper_flags2RADEON_INFO_GPU_RESET_COUNTER 0x26__HAVE_GENERIC_SELECTION 1_VA_LIST_DEFINED GBM_FORMAT_RGBA8888 __gbm_fourcc_code('R', 'A', '2', '4')GBM_FORMAT_YUV422 __gbm_fourcc_code('Y', 'U', '1', '6')rendernode_nameDRM_IOCTL_SYNCOBJ_FD_TO_HANDLE DRM_IOWR(0xC2, struct drm_syncobj_handle)INT_FAST64_MIN (-__INT64_C(9223372036854775807)-1)__INT8_TYPE__ signed char_SC_2_SW_DEV _SC_2_SW_DEVisgraph_l(c,l) __isgraph_l ((c), (l))_DIRENT_HAVE_D_RECLEN RADEON_INFO_SI_TILE_MODE_ARRAY 0x16DRM_MODE_CONTENT_TYPE_CINEMA 3DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd)RADEON_INFO_VA_START 0x0e__warnattr(msg) __attribute__((__warning__ (msg)))DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather)__ldiv_t_defined 1bustype__SIZE_T__ be16toh(x) __bswap_16 (x)R300_CMD_PACKET0 1RADEON_WAIT_2D 0x1DRM_IOCTL_SYNCOBJ_CREATE DRM_IOWR(0xBF, struct drm_syncobj_create)_ASM_GENERIC_ERRNO_H __SIZE_TYPE__ long unsigned intDRM_RADEON_CP_IDLE 0x04__SYSCALL_WORDSIZE 64_SC_2_C_VERSION _SC_2_C_VERSION_SC_2_FORT_RUN _SC_2_FORT_RUN_SC_UINT_MAX _SC_UINT_MAXP_ALLR200_EMIT_PP_TRI_PERF_CNTL 84INTMAX_MIN (-__INT64_C(9223372036854775807)-1)AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6)_POSIX_SIGQUEUE_MAX 32_POSIX_THREAD_ROBUST_PRIO_INHERIT 200809LWTERMSIG(status) __WTERMSIG (status)GBM_FORMAT_YUV410 __gbm_fourcc_code('Y', 'U', 'V', '9')__INT_LEAST16_MAX__ 0x7fffparam_buf_size__DEC128_MANT_DIG__ 34ENOSTR 60RADEON_PARAM_SCRATCH_OFFSET 11DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0)DELAYTIMER_MAX 2147483647AMDGPU_CHUNK_ID_IB 0x01__always_inline __inline____ILP32_OFF32_LDFLAGS "-m32"DRM_RADEON_GEM_GET_TILING 0x29AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3_SC_ADVISORY_INFO _SC_ADVISORY_INFO_CS_POSIX_V6_ILP32_OFFBIG_LIBS _CS_POSIX_V6_ILP32_OFFBIG_LIBSUINTMAX_WIDTH 64__FLT_DENORM_MIN__ 1.40129846432481707092372958328991613e-45FAMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7)__F_SETOWN 8DRM_RENDER_MINOR_NAME "renderD"DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique)drmUsbBusInfoPtr__USE_FILE_OFFSET64 1ERESTART 85EALREADY 114DRM_RDWR O_RDWRGBM_BO_IMPORT_EGL_IMAGE 0x5502RADEON_EMIT_PP_CUBIC_FACES_1 80_POSIX_THREADS 200809LRADEON_TRIANGLES 0x4DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)R200_EMIT_VTE_CNTL 48_BSD_WCHAR_T_DRM_RADEON_SWAP 0x07__O_DIRECTORY 0200000EINTR 4R200_EMIT_PP_TXCTLALL_4 92DRM_RADEON_FLIP 0x12EBADFD 77AMDGPU_GEM_DOMAIN_GDS 0x8__DBL_HAS_QUIET_NAN__ 1AMDGPU_CTX_PRIORITY_NORMAL 0__SHRT_MAX__ 0x7fffRADEON_EMIT_SE_CNTL 9WIFEXITED(status) __WIFEXITED (status)RADEON_INFO_CURRENT_GPU_MCLK 0x23_SC_CHILD_MAX _SC_CHILD_MAX__k8 1AMDGPU_GEM_METADATA_OP_GET_METADATA 2__GLIBC_USE_IEC_60559_FUNCS_EXTR300_CMD_CP_DELAY 5__PTHREAD_SPINS_DATA short __spins; short __elision_IOC(dir,type,nr,size) (((dir) << _IOC_DIRSHIFT) | ((type) << _IOC_TYPESHIFT) | ((nr) << _IOC_NRSHIFT) | ((size) << _IOC_SIZESHIFT))_PC_NO_TRUNC _PC_NO_TRUNC_SC_GETGR_R_SIZE_MAX _SC_GETGR_R_SIZE_MAXDRM_DIR_NAME "/dev/dri"__LONG_LONG_WIDTH__ 64_SC_V6_ILP32_OFFBIG _SC_V6_ILP32_OFFBIG__UINT8_TYPE__ unsigned charAMDGPU_INFO_RAS_ENABLED_HDP (1 << 6)__STDIO_INLINE __extern_inline__HAVE_DISTINCT_FLOAT128X __HAVE_FLOAT128X__INT8_C(c) cisxdigit(c) __isctype((c), _ISxdigit)MAXNAMLEN NAME_MAX__UINTPTR_TYPE__ long unsigned int_SC_LEVEL1_ICACHE_LINESIZE _SC_LEVEL1_ICACHE_LINESIZE__USE_ATFILE 1_POSIX_CHILD_MAX 25__UINT32_MAX__ 0xffffffffU_SC_INT_MIN _SC_INT_MINDRM_MODE_OBJECT_MODE 0xdededede_CS_POSIX_V6_LP64_OFF64_LDFLAGS _CS_POSIX_V6_LP64_OFF64_LDFLAGSFALLOC_FL_COLLAPSE_RANGE 0x08DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)isupper(c) __isctype((c), _ISupper)__FLT128_MAX__ 1.18973149535723176508575932662800702e+4932F128__WINT_MAX__ 0xffffffffUAMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11)_STATBUF_ST_RDEV R200_EMIT_PP_CUBIC_OFFSETS_0 62RADEON_EMIT_SE_ZBIAS_FACTOR 18AMDGPU_VM_MTYPE_UC (4 << 5)AMDGPU_CTX_GUILTY_RESET 1GBM_DETECT_FLAG_CONNECTED (1u << 0)__WNOTHREAD 0x20000000vscan__attribute_used__ __attribute__ ((__used__))DRM_MODE_CONNECTOR_SPI 19DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx)_BSD_SIZE_T_ ENOANO 55_POSIX_TRACE_INHERIT -1_CS_POSIX_V7_ILP32_OFF32_LDFLAGS _CS_POSIX_V7_ILP32_OFF32_LDFLAGS_drmModeModeInfoRADEON_CS_RING_COMPUTE 1__INT16_TYPE__ short intAMDGPU_CTX_UNKNOWN_RESET 3_SC_FIFO _SC_FIFODRM_IOC(dir,group,nr,size) _IOC(dir, group, nr, size)AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2)AMDGPU_INFO_HW_IP_INFO 0x02GBM_FORMAT_BGR233 __gbm_fourcc_code('B', 'G', 'R', '8')__WINT_MIN__ 0UDRM_MODE_CONNECTEDDRM_MODE_FLAG_NCSYNC (1<<8)false 0_XOPEN_SOURCE_EXTENDED__USE_LARGEFILE_STATBUF_ST_NSEC RADEON_INFO_VA_UNMAP_WORKING 0x25__LDBL_REDIR(name,proto) name proto_SC_BC_STRING_MAX _SC_BC_STRING_MAX__CFLOAT64X _Complex _Float64xR300_CMD_DMA_DISCARD 6AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05AMDGPU_INFO_FW_GFX_CE 0x06DRM_MODE_PROP_TYPE(n) ((n) << 6)_LARGEFILE64_SOURCE__STDIO_INLINESI_TILE_MODE_DEPTH_STENCIL_2D 0__WCLONE 0x80000000__INT32_MAX__ 0x7fffffff__WCHAR_MIN__ (-__WCHAR_MAX__ - 1)DRM_DISPLAY_MODE_LEN 32__HAVE_DISTINCT_FLOAT128 1_IOC_TYPEBITS 8AMDGPU_FAMILY_AI 141DRM_AMDGPU_SCHED 0x15__FLT128_MIN__ 3.36210314311209350626267781732175260e-4932F128__STRING(x) #xR200_EMIT_PP_TXCBLEND_1 22__FLT_MAX__ 3.40282346638528859811704183484516925e+38F__INT_LEAST16_WIDTH__ 16__FLT32_MAX_10_EXP__ 38stderr stderrS_ISVTX __S_ISVTX_ISblankDRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl)drmFreeDevicesGBM_FORMAT_BGRX5551 __gbm_fourcc_code('B', 'X', '1', '5')_PC_LINK_MAX _PC_LINK_MAX__INT_FAST16_WIDTH__ 64RADEON_INFO_ACCEL_WORKING 0x03vendorDRM_NODE_PRIMARY 0DRM_MODE_FLAG_NHSYNC (1<<1)_SC_THREADS _SC_THREADSR300_NEW_WAIT_2D_3D 0x3DRM_MODE_OBJECT_BLOB 0xbbbbbbbb__fsblkcnt_t_defined GBM_BO_IMPORT_FD 0x5503_CS_POSIX_V6_LP64_OFF64_CFLAGS _CS_POSIX_V6_LP64_OFF64_CFLAGSoffsetof(TYPE,MEMBER) __builtin_offsetof (TYPE, MEMBER)__stub_chflags _Static_assert(expr,diagnostic) extern int (*__Static_assert_function (void)) [!!sizeof (struct { int __error_if_negative: (expr) ? 2 : -1; })]_PC_REC_INCR_XFER_SIZE _PC_REC_INCR_XFER_SIZE____sigset_t_defined DRM_MODE_CONTENT_PROTECTION_ENABLED 2_POSIX_TRACE -1__uint32_tE2BIG 7_SC_XOPEN_STREAMS _SC_XOPEN_STREAMSSTRINGIZE_NO_EXPANSION(x) #x_CS_XBS5_LP64_OFF64_LINTFLAGS _CS_XBS5_LP64_OFF64_LINTFLAGS_CS_POSIX_V6_ILP32_OFF32_LIBS _CS_POSIX_V6_ILP32_OFF32_LIBSGBM_FORMAT_RGBA1010102 __gbm_fourcc_code('R', 'A', '3', '0')__GNUC_PATCHLEVEL__ 0ESRCH 3__FD_ZERO(fdsp) do { int __d0, __d1; __asm__ __volatile__ ("cld; rep; " __FD_ZERO_STOS : "=c" (__d0), "=D" (__d1) : "a" (0), "0" (sizeof (fd_set) / sizeof (__fd_mask)), "1" (&__FDS_BITS (fdsp)[0]) : "memory"); } while (0)F_SETLK F_SETLK64__INT_FAST64_WIDTH__ 64_POSIX_THREAD_SPORADIC_SERVER -1__iovec_defined 1_CS_LFS64_LDFLAGS _CS_LFS64_LDFLAGS_THREAD_SHARED_TYPES_H 1RADEON_VM_PAGE_READABLE (1 << 1)DRM_MODE_ENCODER_DPI 8__off64_t_defined __INT8_MAX__ 0x7fAMDGPU_VM_PAGE_PRT (1 << 4)R500FP_CONSTANT_TYPE (1 << 1)ENOMSG 42AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10)DRM_CAP_TIMESTAMP_MONOTONIC 0x6_SC_LEVEL2_CACHE_SIZE _SC_LEVEL2_CACHE_SIZE__off_t_defined __SIG_ATOMIC_WIDTH__ 32__USE_XOPEN2K 1GBM_FORMAT_YUV411 __gbm_fourcc_code('Y', 'U', '1', '1')_SC_LEVEL4_CACHE_ASSOC _SC_LEVEL4_CACHE_ASSOCRWH_WRITE_LIFE_NONE 1_ISalpha_CS_POSIX_V6_LP64_OFF64_LIBS _CS_POSIX_V6_LP64_OFF64_LIBSDRM_NODE_MAX 3_POSIX_MQ_OPEN_MAX 8__UINT_FAST32_MAX__ 0xffffffffffffffffULstrtolallocaDRM_IOCTL_SET_MASTER DRM_IO(0x1e)RADEON_INDEX_PRIM_OFFSET 20_IOC_READ 2UDRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block)DRM_MODE_ENCODER_DSI 6DRM_MODE_ENCODER_LVDS 3__LDBL_HAS_QUIET_NAN__ 1__UINTMAX_C(c) c ## UL_SC_LEVEL3_CACHE_SIZE _SC_LEVEL3_CACHE_SIZERADEON_LOG_TEX_GRANULARITY 16dword_offsetRADEON_TILING_EG_BANKH_SHIFT 12AMDGPU_TILING_ARRAY_MODE_MASK 0xfDRM_MODE_SUBPIXEL_NONE__stub___compat_bdflush TMP_MAX 238328DRM_LOCK(fd,lock,context,flags) do { if (flags) drmGetLock(fd,context,flags); else DRM_LIGHT_LOCK(fd,lock,context); } while(0)radinfo_POSIX_IPV6 200809LdrmPlatformDeviceInfoPtr_CS_XBS5_ILP32_OFF32_LINTFLAGS _CS_XBS5_ILP32_OFF32_LINTFLAGS__HAVE_FLOAT128 1_PTRDIFF_T_DECLARED DRM_MODE_LINK_STATUS_BAD 1__PTHREAD_SPINS 0, 0RADEON_UPLOAD_TEX2IMAGES 0x00004000_STRING_H 1__LONG_LONG_PAIR(HI,LO) LO, HIEISNAM 120DRM_MODE_FLAG_CSYNC (1<<6)WCHAR_WIDTH 32_SC_TRACE_EVENT_NAME_MAX _SC_TRACE_EVENT_NAME_MAX__USE_POSIX199506 1_ISalnum_POSIX_ASYNC_IO 1_POSIX_SPORADIC_SERVER -1_IO_buf_end_SC_STREAM_MAX _SC_STREAM_MAXGBM_DEV_TYPE_FLAG_INTERNAL_LCD (1u << 6)R200_EMIT_PP_TXOFFSET_1 43DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)__PTHREAD_MUTEX_NUSERS_AFTER_KIND 0__stub_getmsg detect_flags__putc_unlocked_body(_ch,_fp) (__glibc_unlikely ((_fp)->_IO_write_ptr >= (_fp)->_IO_write_end) ? __overflow (_fp, (unsigned char) (_ch)) : (unsigned char) (*(_fp)->_IO_write_ptr++ = (_ch)))__FLT32_DIG__ 6__FLT32_MIN__ 1.17549435082228750796873653722224568e-38F32RADEON_INFO_WANT_CMASK 0x08isblank_l(c,l) __isblank_l ((c), (l))_POSIX_MONOTONIC_CLOCK 0_CS_XBS5_LP64_OFF64_LDFLAGS _CS_XBS5_LP64_OFF64_LDFLAGSCLEAR_DEPTH 4ECHILD 10AMDGPU_INFO_NUM_HANDLES 0x1CL_tmpnam 20closedirLOCK_READ 64ENETRESET 102DRM_PROP_NAME_LEN 32PIPE_BUF 4096num_tcc_blocks_BITS_WCHAR_H 1DRM_MODE_CONNECTOR_VGA 1FAPPEND O_APPEND_IScntrlDRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)_SC_ATEXIT_MAX _SC_ATEXIT_MAX__SSE__ 1_DIRENT_HAVE_D_TYPE AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11INT_LEAST8_MAX (127)__THROW __attribute__ ((__nothrow__ __LEAF))__attribute_nonstring__ __attribute__ ((__nonstring__))_IO_codecvttoupper_l(c,locale) __toupper_l ((c), (locale))RADEON_TILING_MACRO 0x1_CS_POSIX_V6_LPBIG_OFFBIG_LINTFLAGS _CS_POSIX_V6_LPBIG_OFFBIG_LINTFLAGS_XOPEN_SOURCE_EXTENDED 1RADEON_INFO_VRAM_USAGE 0x1edrmCommandWriteDRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)__FLT_MANT_DIG__ 24S_IFDIR __S_IFDIR__RLIM_T_MATCHES_RLIM64_T 1_IONBF 2__uid_t_defined __code_model_small__ 1DRM_MODE_PROP_ENUM (1<<3)__undef_NR_OPENAMDGPU_VRAM_TYPE_GDDR1 1__bos(ptr) __builtin_object_size (ptr, __USE_FORTIFY_LEVEL > 1)AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block)DRM_DEV_UID 0__W_CONTINUED 0xffffSYNC_FILE_RANGE_WAIT_BEFORE 1drm_amdgpu_infoAMDGPU_INFO_VRAM_GTT 0x14htobe64(x) __bswap_64 (x)_POSIX_MAX_CANON 255open64_DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)DRM_RADEON_FULLSCREEN 0x06__clock_t_defined 1RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf__FSID_T_TYPE struct { int __val[2]; }_DIRENT_HAVE_D_OFF DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP)_CS_POSIX_V6_LPBIG_OFFBIG_LDFLAGS _CS_POSIX_V6_LPBIG_OFFBIG_LDFLAGS_SC_LOGIN_NAME_MAX _SC_LOGIN_NAME_MAX_PC_MAX_CANON _PC_MAX_CANONAMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4F_OFD_SETLK 37RADEON_INFO_NUM_GB_PIPES 0x01RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81DRM_RADEON_IRQ_EMIT 0x16_POSIX_SEMAPHORES 200809LO_DSYNC __O_DSYNC__time_t_defined 1DRM_MODE_CONNECTOR_HDMIB 12O_RDONLY 00DRM_MODE_CONNECTOR_USB 20DRM_IOCTL_DROP_MASTER DRM_IO(0x1f)_SC_TRACE_EVENT_FILTER _SC_TRACE_EVENT_FILTERDRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties)_SC_SIGQUEUE_MAX _SC_SIGQUEUE_MAXmax_gs_waves_per_vgt__S_IFREG 0100000R300_CMD_WAIT 7_SC_LEVEL1_ICACHE_SIZE _SC_LEVEL1_ICACHE_SIZEfourcc_mod_get_vendor(modifier) (((modifier) >> 56) & 0xff)F_TLOCK 2__STDC_HOSTED__ 1AMDGPU_FAMILY_NV 143_POSIX_SOURCEGBM_FORMAT_XBGR1555 __gbm_fourcc_code('X', 'B', '1', '5')__struct_FILE_defined 1ARG_MAX 131072pos_buf_sizetry_drm_devices__USE_XOPEN_EXTENDED_ALLOCA_H 1drmPlatformBusInfoPtrAMDGPU_INFO_VIS_VRAM_USAGE 0x17_SC_XOPEN_UNIX _SC_XOPEN_UNIX__k8__ 1AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10AMDGPU_VM_MTYPE_NC (1 << 5)RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)DRM_MODE_DITHERING_ON 1DRM_MODE_UNKNOWNCONNECTION__USE_POSIXAMDGPU_HW_IP_VCN_DEC 6__HAVE_FLOAT128_UNLIKE_LDBL (__HAVE_DISTINCT_FLOAT128 && __LDBL_MANT_DIG__ != 113)O_NDELAY O_NONBLOCKLOCK_UN 8EREMOTEIO 121minigbm_create_default_device_shortbufDRM_MODE_DITHERING_AUTO 2requestDRM_DEV_GID 0AMDGPU_VA_OP_MAP 1F_GETLK F_GETLK64DRM_MODE_SUBPIXEL_UNKNOWN__INT_FAST8_MAX__ 0x7f_DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))__ORDER_LITTLE_ENDIAN__ 1234_SC_WORD_BIT _SC_WORD_BIT__ctype_b_locINT16_MAX (32767)AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)DRM_MODE_CONTENT_TYPE_GAME 4AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)__DBL_DENORM_MIN__ ((double)4.94065645841246544176568792868221372e-324L)F_OFD_GETLK 36AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2)DRM_MODE_PICTURE_ASPECT_NONE 0R200_EMIT_MATRIX_SELECT_0 33FD_CLOEXEC 1__WALL 0x40000000_drmPciBusInfoX_OK 1_SC_CLOCK_SELECTION _SC_CLOCK_SELECTIONfloatECOMM 70_IOC_NRMASK ((1 << _IOC_NRBITS)-1)GBM_FORMAT_BGR888 __gbm_fourcc_code('B', 'G', '2', '4')AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0)__STD_TYPE typedef_SC_XBS5_LPBIG_OFFBIG _SC_XBS5_LPBIG_OFFBIG_SC_THREAD_PROCESS_SHARED _SC_THREAD_PROCESS_SHARED__FLT128_HAS_DENORM__ 1F_LOCK 1_SC_SINGLE_PROCESS _SC_SINGLE_PROCESS_BITS_PTHREADTYPES_COMMON_H 1__USE_XOPEN2KDRM_IOCTL_SYNCOBJ_QUERY DRM_IOWR(0xCB, struct drm_syncobj_timeline_array)DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)DRM_MODE_OBJECT_CRTC 0xcccccccc__amd64__ 1R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29_SC_DELAYTIMER_MAX _SC_DELAYTIMER_MAXgbm_get_default_device_fd_SC_THREAD_PRIO_INHERIT _SC_THREAD_PRIO_INHERIT_SC_XOPEN_XCU_VERSION _SC_XOPEN_XCU_VERSIONDRM_RADEON_IRQ_WAIT 0x17DRM_RADEON_GEM_USERPTR 0x2dRADEON_TILING_MICRO_SQUARE 0x20_FEATURES_H 1DRM_IOCTL_SYNCOBJ_DESTROY DRM_IOWR(0xC0, struct drm_syncobj_destroy)_POSIX_PRIORITIZED_IO 200809L_SC_PII _SC_PII__key_t_defined __UINT_LEAST8_MAX__ 0xff__UINT_LEAST64_MAX__ 0xffffffffffffffffULAMDGPU_VM_DELAY_UPDATE (1 << 0)DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va)__socklen_t_defined DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct drm_mode_get_lease)DRM_MODE_ENCODER_NONE 0F_OFD_SETLKW 38radeon_igp_idsDRM_MODE_PROP_BLOB (1<<4)drmGetDevices2__PIC__ 2GBM_FORMAT_NV61 __gbm_fourcc_code('N', 'V', '6', '1')RADEON_INFO_NUM_Z_PIPES 0x02DRM_MODE_FB_INTERLACED (1<<0)R200_EMIT_PP_TXCTLALL_0 88__DEC32_MIN__ 1E-95DF_SC_EXPR_NEST_MAX _SC_EXPR_NEST_MAXR200_EMIT_PP_TXFILTER_5 41DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)__AMDGPU_DRM_H__ DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res)DRM_RADEON_GEM_MMAP 0x1eDRM_RADEON_VERTEX 0x09EBADE 52__UINT_LEAST32_TYPE__ unsigned int__GLIBC_USE_IEC_60559_TYPES_EXT 1return_sizeDRM_MODE_CONNECTOR_DVID 3available_nodesRADEON_LINE_STRIP 0x3__GXX_ABI_VERSION 1013DRM_MODE_DPMS_ON 0__FSBLKCNT_T_TYPE __SYSCALL_ULONG_TYPE_XF86DRM_H_ ENAVAIL 119_ISOC11_SOURCE_IOC_DIRBITS 2UINT_FAST32_WIDTH __WORDSIZEAT_SYMLINK_NOFOLLOW 0x100R200_EMIT_RE_SCISSOR_TL_2 56DRM_MODE_LINK_STATUS_GOOD 0AMDGPU_INFO_SENSOR 0x1Dcount_props__FLT64X_MAX_10_EXP__ 4932_SC_USER_GROUPS_R _SC_USER_GROUPS_RRADEON_NR_TEX_REGIONS 64RADEON_CMD_PACKET 1DRM_MODE_PICTURE_ASPECT_4_3 1ENOSR 63S_IRUSR __S_IREAD_ISgraph_BITS_STDIO_H 1_WCHAR_T_DECLARED ____mbstate_t_defined 1_ISOC95_SOURCE_POSIX_C_SOURCE 200809L_CS_V5_WIDTH_RESTRICTED_ENVS _CS_V5_WIDTH_RESTRICTED_ENVSDRM_MODE_REFLECT_X (1<<4)__PTHREAD_RWLOCK_INT_FLAGS_SHARED 1__kernel_old_dev_t __kernel_old_dev_tDN_RENAME 0x00000010DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut)__S_TYPEISMQ(buf) ((buf)->st_mode - (buf)->st_mode)F_GET_FILE_RW_HINT 1037DRM_IOC_VOID _IOC_NONE_SC_ASYNCHRONOUS_IO _SC_ASYNCHRONOUS_IO_ISOC95_SOURCE 1__DBL_MIN__ ((double)2.22507385850720138309023271733240406e-308L)RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09_BITS_STDINT_UINTN_H 1AMDGPU_FAMILY_KV 125__PRAGMA_REDEFINE_EXTNAME 1platformhsync_startfread_unlocked(ptr,size,n,stream) (__extension__ ((__builtin_constant_p (size) && __builtin_constant_p (n) && (size_t) (size) * (size_t) (n) <= 8 && (size_t) (size) != 0) ? ({ char *__ptr = (char *) (ptr); FILE *__stream = (stream); size_t __cnt; for (__cnt = (size_t) (size) * (size_t) (n); __cnt > 0; --__cnt) { int __c = getc_unlocked (__stream); if (__c == EOF) break; *__ptr++ = __c; } ((size_t) (size) * (size_t) (n) - __cnt) / (size_t) (size); }) : (((__builtin_constant_p (size) && (size_t) (size) == 0) || (__builtin_constant_p (n) && (size_t) (n) == 0)) ? ((void) (ptr), (void) (stream), (void) (size), (void) (n), (size_t) 0) : fread_unlocked (ptr, size, n, stream))))_SC_MULTI_PROCESS _SC_MULTI_PROCESS_BSD_PTRDIFF_T_ RWH_WRITE_LIFE_LONG 4RADEON_RELOC_PRIO_MASK (0xf << 0)DRM_MODE_DIRTY_ANNOTATE 2_SC_PII_OSI_CLTS _SC_PII_OSI_CLTSL_cuserid 9_SC_PII_INTERNET _SC_PII_INTERNETR200_EMIT_PP_CUBIC_OFFSETS_3 68DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map)encoder_id__isblank_l(c,l) __isctype_l((c), _ISblank, (l))__SIZE_T _PC_2_SYMLINKS _PC_2_SYMLINKSENOLCK 37RADEON_CMD_VECTORS 3DRM_MODE_PICTURE_ASPECT_64_27 3AMDGPU_VRAM_TYPE_HBM 6MAX_HANDLE_SZ 128__REDIRECT_NTHNL(name,proto,alias) name proto __asm__ (__ASMNAME (#alias)) __THROWNLDRM_MODE_FLAG_DBLCLK (1<<12)_XBS5_LP64_OFF64 1__off_t__stub_fchflags DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN)_drmHost1xBusInfo_DIRENT_MATCHES_DIRENT64 1DRV_VC4 1_POSIX_QLIMIT 1SPLICE_F_GIFT 8DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)INT64_MAX (__INT64_C(9223372036854775807))CLEAR_X1 0__USE_EXTERN_INLINES 1R300_WAIT_2D_CLEAN 0x3_POSIX_LOGIN_NAME_MAX 9R200_EMIT_PP_CUBIC_FACES_4 69RADEON_CMD_PACKET3 5_SC_2_UPE _SC_2_UPEDRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)dev_type_flags_IOC_SIZEBITS 14_SC_CHAR_MAX _SC_CHAR_MAXAMDGPU_VM_MTYPE_MASK (0xf << 5)_SC_NL_SETMAX _SC_NL_SETMAX_SC_AVPHYS_PAGES _SC_AVPHYS_PAGES__FLT64X_MANT_DIG__ 64__FLT128_DENORM_MIN__ 6.47517511943802511092443895822764655e-4966F128gbm_detect_device_info__USE_LARGEFILE 1__TIME_T_TYPE __SYSCALL_SLONG_TYPEAMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2__SIZEOF_LONG_DOUBLE__ 16drmModeGetConnectorDRM_MODE_OBJECT_PLANE 0xeeeeeeee__FLT_MAX_EXP__ 128INTMAX_MAX (__INT64_C(9223372036854775807))_CS_POSIX_V7_LP64_OFF64_LDFLAGS _CS_POSIX_V7_LP64_OFF64_LDFLAGSLITTLE_ENDIAN __LITTLE_ENDIAN__FLT_RADIX__ 2doneva_end(v) __builtin_va_end(v)__INT_FAST16_MAX__ 0x7fffffffffffffffL__undef_OPEN_MAX DRM_AMDGPU_INFO 0x05DIV_ROUND_UP(n,d) (((n) + (d)-1) / (d))DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP)cntl_sb_buf_gpu_addr__always_inline __inline __attribute__ ((__always_inline__))AMDGPU_INFO_VRAM_USAGE 0x10DRM_MODE_ROTATE_180 (1<<2)__INTMAX_MAX__ 0x7fffffffffffffffL_POSIX2_CHAR_TERM 200809LDRM_RADEON_GEM_OP 0x2c__ULONGWORD_TYPE unsigned long int__kernel_old_uid_t __kernel_old_uid_tR600_SCRATCH_REG_OFFSET 256__attribute_malloc__ __attribute__ ((__malloc__))_SC_LEVEL2_CACHE_LINESIZE _SC_LEVEL2_CACHE_LINESIZE__ATOMIC_CONSUME 1_POSIX_V6_LP64_OFF64 1_ASM_GENERIC_ERRNO_BASE_H _SC_SSIZE_MAX _SC_SSIZE_MAX_PC_REC_MIN_XFER_SIZE _PC_REC_MIN_XFER_SIZEAMDGPU_INFO_FW_GFX_MEC 0x08WCONTINUED 8DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd)O_ACCMODE 0003_BITS_STDIO_LIM_H 1RADEON_UPLOAD_SETUP 0x00000040AMDGPU_INFO_FW_DMCU 0x12__BYTE_ORDER __LITTLE_ENDIAN_SC_LONG_BIT _SC_LONG_BITRAND_MAX 2147483647AMDGPU_INFO_FW_VERSION 0x0eDRM_MODE_CONTENT_TYPE_NO_DATA 0DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling)ALIGN(A,B) (((A) + (B)-1) & ~((B)-1))DRM_MODE_ENCODER_TMDS 2pos_buf_gpu_addrRADEON_VM_PAGE_SNOOPED (1 << 4)__BLKCNT64_T_TYPE __SQUAD_TYPEDRM_MODE_PROP_SIGNED_RANGE DRM_MODE_PROP_TYPE(2)_SC_LEVEL1_DCACHE_LINESIZE _SC_LEVEL1_DCACHE_LINESIZE__ATOMIC_ACQUIRE 2_XOPEN_LEGACY 1DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD DRM_IOWR(0xC1, struct drm_syncobj_handle)_POSIX_THREAD_ATTR_STACKSIZE 200809L__LDBL_MIN_10_EXP__ (-4931)__ATOMIC_ACQ_REL 4DRM_MODE_CONTENT_PROTECTION_UNDESIRED 0UTIME_OMIT ((1l << 30) - 2l)WEXITED 4POSIX_FADV_WILLNEED 3__FLT32_MAX__ 3.40282346638528859811704183484516925e+38F32DRM_MODE_SUBPIXEL_HORIZONTAL_BGR__tolower_l(c,locale) __tobody (c, __tolower_l, (locale)->__ctype_tolower, (c, locale))AMDGPU_INFO_FW_GFX_RLC 0x07AMDGPU_VRAM_TYPE_GDDR3 3_IOC_DIRMASK ((1 << _IOC_DIRBITS)-1)__WORDSIZE 64DRM_MODE_FLAG_PIC_AR_16_9 (DRM_MODE_PICTURE_ASPECT_16_9<<19)ESPIPE 29DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc)valueDRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth)__KERNEL_STRICT_NAMEScount_encodersEMLINK 31AMDGPU_INFO_NUM_BYTES_MOVED 0x0fGBM_FORMAT_RGBA5551 __gbm_fourcc_code('R', 'A', '1', '5')__FLT32X_MAX_10_EXP__ 308__DEC32_MIN_EXP__ (-94)_SC_C_LANG_SUPPORT _SC_C_LANG_SUPPORTRADEON_EMIT_SE_CNTL_STATUS 10DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT DRM_IOWR(0xCA, struct drm_syncobj_timeline_wait)__POSIX2_THIS_VERSION 200809L__fortify_function __extern_always_inline __attribute_artificial__SI_TILE_MODE_COLOR_2D_8BPP 14__INT_FAST32_TYPE__ long intDRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int)__aligned_u64 __u64 __attribute__((aligned(8)))__f128(x) x ##f128_SC_TRACE_NAME_MAX _SC_TRACE_NAME_MAXGBM_FORMAT_AYUV __gbm_fourcc_code('A', 'Y', 'U', 'V')__DBL_MIN_EXP__ (-1021)INT_FAST16_MIN (-9223372036854775807L-1)__ATOMIC_SEQ_CST 5GBM_FORMAT_UYVY __gbm_fourcc_code('U', 'Y', 'V', 'Y')R200_EMIT_PP_TAM_DEBUG3 50IOC_OUT (_IOC_READ << _IOC_DIRSHIFT)DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)__GLIBC_USE_DEPRECATED_GETS 0STRINGIZE(x) STRINGIZE_NO_EXPANSION(x)FASYNC O_ASYNC__va_arg_pack_len() __builtin_va_arg_pack_len ()EADV 68AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f_POSIX_THREAD_PRIO_PROTECT 200809L__LONG_WIDTH__ 64P_PIDR200_EMIT_PP_TXCBLEND_4 25__FLT128_HAS_QUIET_NAN__ 1WSTOPSIG(status) __WSTOPSIG (status)DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc)version_majorfw_type_PC_SOCK_MAXBUF _PC_SOCK_MAXBUFDRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)RADEON_OFFSET_SHIFT 10hsync_end_T_SIZE _DEFAULT_SOURCEFD_ZERO(fdsetp) __FD_ZERO (fdsetp)AMDGPU_INFO_FW_GFX_PFP 0x05DT_UNKNOWN DT_UNKNOWNDRM_MODE_PAGE_FLIP_TARGET_RELATIVE 0x8__blkcnt_t_defined GBM_FORMAT_ABGR8888 __gbm_fourcc_code('A', 'B', '2', '4')F_GETLEASE 1025RADEON_INFO_IB_VM_MAX_SIZE 0x0fR200_EMIT_PP_TXOFFSET_5 47__INT_LEAST32_MAX__ 0x7fffffff_PC_CHOWN_RESTRICTED _PC_CHOWN_RESTRICTEDSI_TILE_MODE_COLOR_2D_32BPP 16__WCHAR_WIDTH__ 32IFTODT(mode) (((mode) & 0170000) >> 12)RADEON_INFO_MAX_PIPES 0x10RADEON_PARAM_LAST_FRAME 2_CS_POSIX_V7_WIDTH_RESTRICTED_ENVS _CS_V7_WIDTH_RESTRICTED_ENVSRADEON_CMD_DMA_DISCARD 4host1xGBM_DEV_TYPE_FLAG_DISPLAY (1u << 1)AMDGPU_CTX_NO_RESET 0DRM_RADEON_GEM_INFO 0x1cDRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)__O_TMPFILE (020000000 | __O_DIRECTORY)AMDGPU_INFO_FW_TA 0x13ENOMEM 12DN_CREATE 0x00000004__UINTPTR_MAX__ 0xffffffffffffffffUL__OPEN_NEEDS_MODE(oflag) (((oflag) & O_CREAT) != 0 || ((oflag) & __O_TMPFILE) == __O_TMPFILE)AT_STATX_FORCE_SYNC 0x2000__x86_64 1_SC_STREAMS _SC_STREAMSDRM_HOST1X_DEVICE_NAME_LEN 512DRM_CAP_DUMB_PREFER_SHADOW 0x4_SC_FILE_LOCKING _SC_FILE_LOCKINGRADEON_INFO_RING_WORKING 0x15DRM_CLIENT_CAP_ATOMIC 3__S16_TYPE short intAMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07_SC_NGROUPS_MAX _SC_NGROUPS_MAX_T_PTRDIFF _IOC_TYPECHECK(t) (sizeof(t))INT_FAST32_MIN (-9223372036854775807L-1)_ASM_X86_TYPES_H mode_crtc_SIZE_T_DECLARED RADEON_GEM_USERPTR_REGISTER (1 << 3)_CS_LFS64_LINTFLAGS _CS_LFS64_LINTFLAGSDRM_MODE_CONNECTOR_DVIA 4_POSIX2_LOCALEDEF __POSIX2_THIS_VERSION__size_t__ _CS_XBS5_ILP32_OFFBIG_CFLAGS _CS_XBS5_ILP32_OFFBIG_CFLAGSDRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)__FLT64_DIG__ 15_CS_LFS_LDFLAGS _CS_LFS_LDFLAGSstdout stdout_STDINT_H 1BYTE_ORDER __BYTE_ORDERAMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1)_D_EXACT_NAMLEN(d) (strlen ((d)->d_name))RADEON_PARAM_REGISTER_HANDLE 7F_ULOCK 0S_IFMT __S_IFMTDRM_MODE_PROP_RANGE (1<<1)opterr_SC_MQ_OPEN_MAX _SC_MQ_OPEN_MAXS_IFSOCK __S_IFSOCK_SC_THREAD_THREADS_MAX _SC_THREAD_THREADS_MAXDRM_MODE_CONNECTOR_DisplayPort 10EMULTIHOP 72RADEON_UPLOAD_BUMPMAP 0x00000008O_RDWR 02F_SETOWN_EX __F_SETOWN_EXXATTR_NAME_MAX 255__DBL_MANT_DIG__ 53LOCK_MAND 32__UINT_FAST64_MAX__ 0xffffffffffffffffULR200_EMIT_PP_TXOFFSET_4 46DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle)AMDGPU_INFO_SENSOR_GFX_MCLK 0x2FALLOC_FL_ZERO_RANGE 0x10__ispunct_l(c,l) __isctype_l((c), _ISpunct, (l))S_IRWXU (__S_IREAD|__S_IWRITE|__S_IEXEC)GBM_FORMAT_RGB332 __gbm_fourcc_code('R', 'G', 'B', '8')F_SET_FILE_RW_HINT 1038max_memory_clockDRM_NODE_CONTROL 1SPLICE_F_MOVE 1DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer)__UINT_LEAST16_MAX__ 0xffff_ANSI_STDDEF_H GBM_FORMAT_ABGR1555 __gbm_fourcc_code('A', 'B', '1', '5')deviceinfoRADEON_VA_RESULT_VA_EXIST 2_toupper(c) ((int) (*__ctype_toupper_loc ())[(int) (c)])_SC_ULONG_MAX _SC_ULONG_MAXAMDGPU_GEM_USERPTR_REGISTER (1 << 3)_SC_SCHAR_MAX _SC_SCHAR_MAX_IO_save_end_CS_XBS5_ILP32_OFFBIG_LINTFLAGS _CS_XBS5_ILP32_OFFBIG_LINTFLAGSAMDGPU_CTX_STABLE_PSTATE_STANDARD 1__LP64_OFF64_CFLAGS "-m64"RADEON_INFO_SI_CP_DMA_COMPUTE 0x17FNDELAY O_NDELAYUINT64_WIDTH 64GBM_FORMAT_YVYU __gbm_fourcc_code('Y', 'V', 'Y', 'U')_SC_CHARCLASS_NAME_MAX _SC_CHARCLASS_NAME_MAX__isascii_l(c,l) ((l), __isascii (c))O_PATH __O_PATH__CFLOAT128 _Complex _Float128DRM_PLANE_TYPE_PRIMARY 1SIG_ATOMIC_WIDTH 32isxdigit_l(c,l) __isxdigit_l ((c), (l))DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control)_SC_THREAD_CPUTIME _SC_THREAD_CPUTIME__DEV_T_TYPE __UQUAD_TYPE__PTRDIFF_WIDTH__ 64_CS_XBS5_LPBIG_OFFBIG_LIBS _CS_XBS5_LPBIG_OFFBIG_LIBS__INT_FAST64_TYPE__ long intAIO_PRIO_DELTA_MAX 20__HAVE_FLOATN_NOT_TYPEDEF 1_SC_AIO_LISTIO_MAX _SC_AIO_LISTIO_MAXDRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6<<14)_SC_SAVED_IDS _SC_SAVED_IDSAMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)optarg__FLT32X_HAS_INFINITY__ 1__attribute_deprecated__ __attribute__ ((__deprecated__))AMDGPU_HW_IP_UVD 3EPROTONOSUPPORT 93DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2<<14)_ISOC99_SOURCE__FLT32_EPSILON__ 1.19209289550781250000000000000000000e-7F32isspace_l(c,l) __isspace_l ((c), (l))__flexarr []RADEON_INFO_VCE_FB_VERSION 0x1cDRM_RADEON_CLEAR 0x08__INT32_TYPE__ intR_OK 4_STRUCT_TIMESPEC 1RADEON_INFO_NUM_TILE_PIPES 0x0bRADEON_CS_RING_UVD 3RADEON_GEM_OP_SET_INITIAL_DOMAIN 1_SC_AIO_MAX _SC_AIO_MAX__have_pthread_attr_t 1DRM_MODE_FLAG_3D_NONE (0<<14)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2_XF86DRMMODE_H_ DRM_RADEON_SURF_ALLOC 0x1adri_node_numR200_EMIT_PP_TXFILTER_1 37DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)ENOTCONN 107gbm_device_info__UINT8_MAX__ 0xffDRM_MODE_CURSOR_FLAGS 0x03__ATOMIC_RELAXED 0__DBL_HAS_DENORM__ 1__FLT64X_MIN_EXP__ (-16381)_SC_LEVEL2_CACHE_ASSOC _SC_LEVEL2_CACHE_ASSOC__S_ISVTX 01000__MODE_T_TYPE __U32_TYPERADEON_INFO_SI_BACKEND_ENABLED_MASK 0x19__FLT128_HAS_INFINITY__ 1version_patchlevel_SC_MQ_PRIO_MAX _SC_MQ_PRIO_MAX__SIZEOF_PTHREAD_ATTR_T 56S_IXOTH (S_IXGRP >> 3)AMDGPU_INFO_FW_GMC 0x03__F_SETSIG 10__bool_true_false_are_defined 1__GBM__ 1ENOSPC 28_CS_POSIX_V6_ILP32_OFF32_LINTFLAGS _CS_POSIX_V6_ILP32_OFF32_LINTFLAGSrevision_id_SC_ARG_MAX _SC_ARG_MAXENOTTY 25DRM_MODE_ROTATE_270 (1<<3)GBM_FORMAT_ARGB8888 __gbm_fourcc_code('A', 'R', '2', '4')_DRM_LOCK_CONT 0x40000000U_SYS_SELECT_H 1_BSD_WCHAR_T_ DRM_PLATFORM_DEVICE_NAME_LEN 512SIG_ATOMIC_MIN (-2147483647-1)__FLT64X_EPSILON__ 1.08420217248550443400745280086994171e-19F64xSI_TILE_MODE_COLOR_LINEAR_ALIGNED 8AMDGPU_GEM_DOMAIN_VRAM 0x4__FLT_MIN__ 1.17549435082228750796873653722224568e-38F_SC_2_C_BIND _SC_2_C_BINDETIME 62_pad1AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0DRM_CAP_PRIME 0x5AMDGPU_CTX_PRIORITY_LOW -512RADEON_UPLOAD_TEX0 0x00000200__STD_TYPEUINT_FAST64_WIDTH 64gbm_device_CS_POSIX_V6_ILP32_OFFBIG_LINTFLAGS _CS_POSIX_V6_ILP32_OFFBIG_LINTFLAGSDRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)R300_CMD_VPU 2DRM_AMDGPU_GEM_CREATE 0x00R200_EMIT_PP_AFS_0 85bool _Bool__INT_FAST8_TYPE__ signed char_CS_GNU_LIBC_VERSION _CS_GNU_LIBC_VERSIONRADEON_VM_PAGE_VALID (1 << 0)STDERR_FILENO 2DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res)_DRM_POST_MODESET 2EOVERFLOW 75_IO_read_base_CS_POSIX_V7_ILP32_OFFBIG_LINTFLAGS _CS_POSIX_V7_ILP32_OFFBIG_LINTFLAGSDRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info)RADEON_EMIT_PP_BORDER_COLOR_1 15_POSIX_RAW_SOCKETS 200809LEPIPE 32_SC_EQUIV_CLASS_MAX _SC_EQUIV_CLASS_MAXAMDGPU_BO_LIST_OP_UPDATE 2__UINT32_TYPE__ unsigned intAMDGPU_FAMILY_CZ 135__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)DRM_MODE_PROP_OBJECT DRM_MODE_PROP_TYPE(1)__FLT_HAS_DENORM__ 1_STDDEF_H_ AMDGPU_VM_OP_UNRESERVE_VMID 2DRM_MODE_TYPE_ALL (DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_USERDEF | DRM_MODE_TYPE_DRIVER)RADEON_INFO_NUM_BYTES_MOVED 0x1dAMDGPU_INFO_VBIOS 0x1B__GLIBC_USE_IEC_60559_TYPES_EXTfd_path_IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1)_CS_XBS5_ILP32_OFF32_CFLAGS _CS_XBS5_ILP32_OFF32_CFLAGS_WCHAR_T_DEFINED_ pa_sc_tile_steering_overrideENOMEDIUM 123_SC_SHELL _SC_SHELLDRM_IOCTL_SYNCOBJ_WAIT DRM_IOWR(0xC3, struct drm_syncobj_wait)DN_ATTRIB 0x00000020_POSIX_THREAD_SAFE_FUNCTIONS 200809LRADEON_INFO_ACCEL_WORKING2 0x05_CS_XBS5_LPBIG_OFFBIG_LINTFLAGS _CS_XBS5_LPBIG_OFFBIG_LINTFLAGSDRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map)RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28GBM_DEV_TYPE_FLAG_USB (1u << 4)AMDGPU_VM_MTYPE_DEFAULT (0 << 5)__USE_XOPEN2K8XSIDRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer)max_heightEISCONN 106_SC_BC_BASE_MAX _SC_BC_BASE_MAX_SC_THREAD_PRIORITY_SCHEDULING _SC_THREAD_PRIORITY_SCHEDULING__DEC32_SUBNORMAL_MIN__ 0.000001E-95DF_IO_write_ptr_VA_LIST_T_H DRM_NODE_RENDER 2ce_ram_sizeDRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc)UINT_LEAST16_WIDTH 16AMDGPU_VRAM_TYPE_GDDR5 5DRM_MODE_TYPE_DRIVER (1<<6)UINT_LEAST64_WIDTH 64__LDBL_REDIR1(name,proto,alias) name proto__DEC128_MIN__ 1E-6143DL_SC_CLK_TCK _SC_CLK_TCK_SC_FILE_ATTRIBUTES _SC_FILE_ATTRIBUTESpte_fragment_size__SIZEOF_PTHREAD_RWLOCK_T 56_POSIX_TTY_NAME_MAX 9AMDGPU_VRAM_TYPE_DDR2 2RADEON_INFO_TILING_CONFIG 0x06__SIZEOF_PTHREAD_RWLOCKATTR_T 8AMDGPU_CTX_STABLE_PSTATE_NONE 0DRM_MODE_FLAG_DBLSCAN (1<<5)R200_EMIT_SE_VTX_STATE_CNTL 58AMDGPU_VM_PAGE_READABLE (1 << 1)R200_EMIT_VAP_PVS_CNTL 94EFBIG 27RADEON_PARAM_CARD_TYPE 12R200_EMIT_PP_CUBIC_FACES_0 61__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__RADEON_EMIT_PP_CUBIC_FACES_0 78DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)DRM_MODE_PROP_PENDING (1<<0)AMDGPU_INFO_GTT_USAGE 0x11_ISxdigit__exctype(name) extern int name (int) __THROWUINT_FAST8_MAX (255)__CLOCKID_T_TYPE __S32_TYPE_POSIX_V7_LP64_OFF64 1_IOWR_BAD(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size))DRM_RADEON_VBLANK_CRTC2 2_UNISTD_H 1_POSIX_DELAYTIMER_MAX 32PTRDIFF_MIN (-9223372036854775807L-1)__FD_ISSET(d,set) ((__FDS_BITS (set)[__FD_ELT (d)] & __FD_MASK (d)) != 0)__isascii(c) (((c) & ~0x7f) == 0)_SIGSET_NWORDS (1024 / (8 * sizeof (unsigned long int)))_ASM_GENERIC_IOCTL_H AMDGPU_HW_IP_VCE 4DRM_MODE_ENCODER_TVDAC 4_sys_nerrRADEON_TILING_EG_BANKW_MASK 0xf_POSIX_REALTIME_SIGNALS 200809LRADEON_SETPARAM_PCIGART_TABLE_SIZE 5_SC_TYPED_MEMORY_OBJECTS _SC_TYPED_MEMORY_OBJECTSETXTBSY 26__FLT32_MIN_EXP__ (-125)EOF (-1)STDOUT_FILENO 1GBM_FORMAT_NV21 __gbm_fourcc_code('N', 'V', '2', '1')AMDGPU_CTX_OP_ALLOC_CTX 1_T_WCHAR_ DRM_MODE_PROP_IMMUTABLE (1<<2)_SC_GETPW_R_SIZE_MAX _SC_GETPW_R_SIZE_MAXRADEON_CS_RING_VCE 4ENFILE 23opendirDRM_IOCTL_SYNCOBJ_SIGNAL DRM_IOWR(0xC5, struct drm_syncobj_array)_SC_SELECT _SC_SELECTR200_EMIT_PP_TXCTLALL_3 91F_SETFD 2INT_LEAST32_MIN (-2147483647-1)__stub_putmsg __INTPTR_WIDTH__ 64_SC_JOB_CONTROL _SC_JOB_CONTROL_ISOC99_SOURCE 1FALLOC_FL_NO_HIDE_STALE 0x04_POSIX_THREAD_CPUTIME 0_IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)hskewUINT_LEAST32_WIDTH 32name_lenvbios_infoINT_FAST64_MAX (__INT64_C(9223372036854775807))_DIRENT_HAVE_D_NAMLEN__UINT_FAST16_MAX__ 0xffffffffffffffffULAMDGPU_TILING_PIPE_CONFIG_SHIFT 4__W_STOPCODE(sig) ((sig) << 8 | 0x7f)__REDIRECT_NTH(name,proto,alias) name proto __asm__ (__ASMNAME (#alias)) __THROWENOTEMPTY 39__KERNEL_STRICT_NAMES INT_FAST16_MAX (9223372036854775807L)compatibleRADEON_GEM_OP_GET_INITIAL_DOMAIN 0_POSIX2_SW_DEV __POSIX2_THIS_VERSIONR300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8__P(args) argsRTSIG_MAX 32RADEON_CARD_PCI 0_SC_LEVEL1_DCACHE_SIZE _SC_LEVEL1_DCACHE_SIZEDRM_RADEON_GEM_BUSY 0x2abe32toh(x) __bswap_32 (x)_CS_V7_WIDTH_RESTRICTED_ENVS _CS_V7_WIDTH_RESTRICTED_ENVSAT_STATX_SYNC_AS_STAT 0x0000_markers__FINITE_MATH_ONLY__ 0_filenoUINT_LEAST8_MAX (255)__UINTMAX_TYPE__ long unsigned intDRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create)DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map)DRM_IOCTL_MODE_REVOKE_LEASE DRM_IOWR(0xC9, struct drm_mode_revoke_lease)_POSIX_CLOCK_SELECTION 200809Lvirtual_address_maxDRM_MODE_FLAG_PHSYNC (1<<0)DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)__CFLOAT32X _Complex _Float32x__GLIBC_USE_IEC_60559_FUNCS_EXT 1__INO_T_MATCHES_INO64_T 1AMDGPU_INFO_MEMORY 0x19__FLT32_DECIMAL_DIG__ 9POSIX_FADV_NORMAL 0_SC_PII_SOCKET _SC_PII_SOCKET__isgraph_l(c,l) __isctype_l((c), _ISgraph, (l))DRM_MODE_PROP_LEGACY_TYPE ( DRM_MODE_PROP_RANGE | DRM_MODE_PROP_ENUM | DRM_MODE_PROP_BLOB | DRM_MODE_PROP_BITMASK)DRM_MODE_PROP_ATOMIC 0x80000000DRM_RADEON_SETPARAM 0x19INT64_MIN (-__INT64_C(9223372036854775807)-1)__pic__ 2SI_TILE_MODE_COLOR_2D_16BPP 15DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid)AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1__STDC_ISO_10646__ 201706L__PID_T_TYPE __S32_TYPEDRM_MODE_CONNECTOR_Unknown 0DRM_IOCTL_MODE_GETFB2 DRM_IOWR(0xCE, struct drm_mode_fb_cmd2)__BLKSIZE_T_TYPE __SYSCALL_SLONG_TYPE__FLT64_MIN__ 2.22507385850720138309023271733240406e-308F64AMDGPU_TILING_NUM_BANKS_MASK 0x3WEXITSTATUS(status) __WEXITSTATUS (status)GBM_FORMAT_BGRX4444 __gbm_fourcc_code('B', 'X', '1', '2')__FLT128_EPSILON__ 1.92592994438723585305597794258492732e-34F128__SCHAR_WIDTH__ 8DRM_AGP_NO_HANDLE 0F_GET_SEALS 1034_SC_TIMEOUTS _SC_TIMEOUTSgart_page_size_POSIX_SOURCE 1ETOOMANYREFS 109__f64x(x) x ##f64xhtobe32(x) __bswap_32 (x)va_arg(v,l) __builtin_va_arg(v,l)AMDGPU_CTX_STABLE_PSTATE_PEAK 4DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map)SI_TILE_MODE_DEPTH_STENCIL_1D 4__sigset_t_defined 1WIFSIGNALED(status) __WIFSIGNALED (status)__LDBL_HAS_DENORM__ 1__WCHAR_T _SYS_TYPES_H 1__USE_LARGEFILE64 1__ssize_tLOCK_WRITE 128O_EXCL 0200_SC_NL_LANGMAX _SC_NL_LANGMAX_IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)DRM_CAP_SYNCOBJ_TIMELINE 0x14__SQUAD_TYPE long intDRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close)DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET)R200_EMIT_PP_TXCBLEND_0 21EXIT_FAILURE 1F_GETFD 1__DEC128_MIN_EXP__ (-6142)__USE_FILE_OFFSET64EPROTOTYPE 91__FLT64X_DENORM_MIN__ 3.64519953188247460252840593361941982e-4951F64x__gid_t_defined __HAVE_DISTINCT_FLOAT32 0d_reclenAMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8__toupper_l(c,locale) __tobody (c, __toupper_l, (locale)->__ctype_toupper, (c, locale))DRM_CAP_PAGE_FLIP_TARGET 0x11__tobody(c,f,a,args) (__extension__ ({ int __res; if (sizeof (c) > 1) { if (__builtin_constant_p (c)) { int __c = (c); __res = __c < -128 || __c > 255 ? __c : (a)[__c]; } else __res = f args; } else __res = (a)[(int) (c)]; __res; }))DRM_CONTROL_DEV_NAME "%s/" DRM_CONTROL_MINOR_NAME "%d"DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock)_drmModeResDRM_CAP_DUMB_BUFFER 0x1AMDGPU_FAMILY_UNKNOWN 0_SC_SHRT_MAX _SC_SHRT_MAXDRM_PRINTFLIKE(f,a) __attribute__ ((format(__printf__, f, a)))DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane)__U64_TYPE unsigned long intAMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5)__gnu_linux__ 1__undef_ARG_MAXAT_EACCESS 0x200RADEON_CHUNK_ID_IB 0x02AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12AMDGPU_INFO_SENSOR_GPU_TEMP 0x3DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property)XATTR_SIZE_MAX 65536__DEC64_SUBNORMAL_MIN__ 0.000000000000001E-383DDAMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8EDQUOT 122__FLT32_DENORM_MIN__ 1.40129846432481707092372958328991613e-45F32DRM_RADEON_VERTEX2 0x0FDRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd)_BITS_FLOATN_COMMON_H __attribute_noinline__ __attribute__ ((__noinline__))connectedvdisplayDRM_MODE_FLAG_PIC_AR_MASK (0x0F<<19)d_typeRADEON_PARAM_VBLANK_CRTC 13O_DIRECT __O_DIRECTUINT_FAST16_MAX (18446744073709551615UL)__isctype(c,type) ((*__ctype_b_loc ())[(int) (c)] & (unsigned short int) type)R200_EMIT_RE_AUX_SCISSOR_CNTL 53F_DUPFD_CLOEXEC 1030GBM_FORMAT_BIG_ENDIAN (1<<31)_SC_PRIORITIZED_IO _SC_PRIORITIZED_IO__GLIBC_USE_DEPRECATED_GETSGBM_FORMAT_YVU422 __gbm_fourcc_code('Y', 'V', '1', '6')DRM_MODE_CONNECTOR_SVIDEO 6_SC_SYMLOOP_MAX _SC_SYMLOOP_MAX_SC_MEMLOCK_RANGE _SC_MEMLOCK_RANGE__WCHAR_T__ _POSIX_FD_SETSIZE _POSIX_OPEN_MAXDRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx)_LARGEFILE_SOURCE 1EKEYEXPIRED 127AMDGPU_VRAM_TYPE_UNKNOWN 0GBM_FORMAT_YUV444 __gbm_fourcc_code('Y', 'U', '2', '4')SEEK_END 2_SC_SEM_VALUE_MAX _SC_SEM_VALUE_MAX_SC_XOPEN_REALTIME_THREADS _SC_XOPEN_REALTIME_THREADSDRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread)_SC_DEVICE_SPECIFIC_R _SC_DEVICE_SPECIFIC_R__WIFCONTINUED(status) ((status) == __W_CONTINUED)O_WRONLY 01GBM_FORMAT_XBGR2101010 __gbm_fourcc_code('X', 'B', '3', '0')AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10)_POSIX_HIWAT _POSIX_PIPE_BUF_SC_REGEXP _SC_REGEXP__USE_LARGEFILE64AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4)__isalpha_l(c,l) __isctype_l((c), _ISalpha, (l))__USE_POSIX199309sensor_infoAMDGPU_IB_FLAG_PREAMBLE (1<<1)RADEON_CHUNK_ID_FLAGS 0x03__glibc_clang_has_extension(ext) 0dri_node_PC_SYMLINK_MAX _PC_SYMLINK_MAX_IO_write_baseRADEON_WAIT_3D 0x2UINT8_MAX (255)AMDGPU_TILING_TILE_SPLIT_SHIFT 9DRM_MODE_CONNECTOR_DPI 17_SC_FD_MGMT _SC_FD_MGMTva_start(v,l) __builtin_va_start(v,l)count_connectorsDRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor)_SC_MAPPED_FILES _SC_MAPPED_FILES__INTMAX_WIDTH__ 64_IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS)UINT16_WIDTH 16__U32_TYPE unsigned intO_TMPFILE __O_TMPFILE__GCC_ATOMIC_LLONG_LOCK_FREE 2SI_TILE_MODE_COLOR_1D_SCANOUT 9_LFS_LARGEFILE 1AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f__HAVE_FLOAT64 1_POSIX_ADVISORY_INFO 200809LR200_EMIT_PP_TXOFFSET_0 42R200_EMIT_PP_TXCBLEND_7 28DRM_RADEON_NOT_USED __DEC128_MAX__ 9.999999999999999999999999999999999E6144DLDRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth)__pid_t_defined _SC_THREAD_ATTR_STACKSIZE _SC_THREAD_ATTR_STACKSIZEreaddir64htole32(x) __uint32_identity (x)__CFLOAT64 _Complex _Float64__DBL_DIG__ 15__O_LARGEFILE 0RADEON_UPLOAD_ZBIAS 0x00020000S_ISUID __S_ISUIDENOKEY 126__INT64_MAX__ 0x7fffffffffffffffL_DRM_LOCK_HELD 0x80000000UDRM_RAM_PERCENT 10DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open)AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2AMDGPU_BO_LIST_OP_DESTROY 1__attribute_artificial__ __attribute__ ((__artificial__))__SSP_STRONG__ 3DRM_MODE_DIRTY_ON 1RADEON_EMIT_RB3D_COLORPITCH 2DRM_IOCTL_RADEON_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_OP, struct drm_radeon_gem_op)L_ctermid 9GBM_DEV_TYPE_FLAG_BLOCKED (1u << 5)ENOTBLK 15_SC_NPROCESSORS_ONLN _SC_NPROCESSORS_ONLNAMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13)__USE_GNUINT_LEAST64_MIN (-__INT64_C(9223372036854775807)-1)UINT_LEAST8_WIDTH 8EBUSY 16DT_FIFO DT_FIFODRM_MODE_CONTENT_TYPE_GRAPHICS 1__need_size_t high_va_offsetFD_SET(fd,fdsetp) __FD_SET (fd, fdsetp)__GLIBC_PREREQ(maj,min) ((__GLIBC__ << 16) + __GLIBC_MINOR__ >= ((maj) << 16) + (min))__aligned_le64 __le64 __attribute__((aligned(8)))__WIFSTOPPED(status) (((status) & 0xff) == 0x7f)__USE_MISC 1__S64_TYPE long int_CS_POSIX_V6_ILP32_OFFBIG_CFLAGS _CS_POSIX_V6_ILP32_OFFBIG_CFLAGS__F_GETSIG 11RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79RADEON_EMIT_PP_TXFILTER_2 16RADEON_POINTS 0x1__SIZEOF_INT__ 4_SC_PII_INTERNET_STREAM _SC_PII_INTERNET_STREAMDRM_CAP_ASYNC_PAGE_FLIP 0x7__ORDER_PDP_ENDIAN__ 3412__FLT_DECIMAL_DIG__ 9_SC_XBS5_ILP32_OFF32 _SC_XBS5_ILP32_OFF32ERANGE 34__LONG_LONG_MAX__ 0x7fffffffffffffffLLAMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11)EIDRM 43__USE_ISOCXX11_SC_DEVICE_IO _SC_DEVICE_IODRM_MODE_FLAG_PIC_AR_4_3 (DRM_MODE_PICTURE_ASPECT_4_3<<19)DRM_AMDGPU_VM 0x13__toascii(c) ((c) & 0x7f)DRM_MODE_ROTATE_MASK ( DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270)RADEON_MAX_TEXTURE_LEVELS 12EDOTDOT 73_MINIGBM_HELPERS_H_ DRM_MODE_CONNECTOR_HDMIA 11_SC_SS_REPL_MAX _SC_SS_REPL_MAX__SIZEOF_PTRDIFF_T__ 8_POSIX_ARG_MAX 4096UINT_FAST16_WIDTH __WORDSIZE__SIZEOF_PTHREAD_BARRIER_T 32LOCK_RW 192_POSIX_THREAD_PRIORITY_SCHEDULING 200809L_drmPlatformDeviceInfoFD_SETSIZE __FD_SETSIZEAMDGPU_VRAM_TYPE_DDR4 8GBM_FORMAT_GR88 __gbm_fourcc_code('G', 'R', '8', '8')_POSIX_MESSAGE_PASSING 200809L__need_NULL __FLOAT_WORD_ORDER __BYTE_ORDER__f64(x) x ##f64__UQUAD_TYPE unsigned long int__OFF_T_MATCHES_OFF64_T 1AMDGPU_INFO_VIDEO_CAPS_ENCODE 1AMDGPU_HW_IP_NUM 9__SUSECONDS_T_TYPE __SYSCALL_SLONG_TYPEF_UNLCK 2GBM_FORMAT_BGRA4444 __gbm_fourcc_code('B', 'A', '1', '2')AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5_ASM_GENERIC_TYPES_H RADEON_TILING_SWAP_32BIT 0x8_cur_columnIS_ALIGNED(A,B) (ALIGN((A), (B)) == (A))AMDGPU_INFO_FW_GFX_ME 0x04high_va_maxAMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7_POSIX_JOB_CONTROL 1O_FSYNC O_SYNCF_GETOWN_EX __F_GETOWN_EXDRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02__USE_XOPEN2K8XSI 1AT_EMPTY_PATH 0x1000EINVAL 22connectiondev_infoRADEON_PARAM_NUM_Z_PIPES 17ELNRNG 48INT_LEAST16_MIN (-32767-1)DRM_BUS_USB 1_POSIX_V7_LPBIG_OFFBIG -1_SC_TRACE_LOG _SC_TRACE_LOGDRM_MODE_ROTATE_90 (1<<1)DRM_MODE_CONTENT_TYPE_PHOTO 2DRM_MODE_ATOMIC_NONBLOCK 0x0200DRM_LIGHT_LOCK_COUNT(fd,lock,context,count) do { DRM_CAS_RESULT(__ret); DRM_CAS(lock,context,DRM_LOCK_HELD|context,__ret); if (__ret) drmGetLock(fd,context,0); else ++count; } while(0)AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3)AMDGPU_INFO_SENSOR_VDDNB 0x6__va_list__ RADEON_PARAM_NUM_GB_PIPES 15/source/platform/minigbm/minigbm_helpers.c__NTHNL(fct) __attribute__ ((__nothrow__)) fctAMDGPU_HW_IP_UVD_ENC 5_XOPEN_UNIX 1__PTRDIFF_TYPE__ long intEL2NSYNC 45R200_EMIT_TFACTOR_0 30__FLT64_MANT_DIG__ 53__GNUC_PREREQ(maj,min) ((__GNUC__ << 16) + __GNUC_MINOR__ >= ((maj) << 16) + (min))R300_NEW_WAIT_2D_2D_CLEAN 0x4__undef_ARG_MAX isdigit(c) __isctype((c), _ISdigit)DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw)__isdigit_l(c,l) __isctype_l((c), _ISdigit, (l))__ORDER_BIG_ENDIAN__ 4321__SIZEOF_SIZE_T__ 8__LOCK_ALIGNMENT __FLT32X_DIG__ 15__DEC32_MAX__ 9.999999E96DFAMDGPU_INFO_MMR_SH_INDEX_SHIFT 8UINT64_MAX (__UINT64_C(18446744073709551615))_SC_CHAR_MIN _SC_CHAR_MIN_SC_SPORADIC_SERVER _SC_SPORADIC_SERVERstrndupa(s,n) (__extension__ ({ const char *__old = (s); size_t __len = strnlen (__old, (n)); char *__new = (char *) __builtin_alloca (__len + 1); __new[__len] = '\0'; (char *) memcpy (__new, __old, __len); }))_CS_LFS64_CFLAGS _CS_LFS64_CFLAGSAMDGPU_GEM_DOMAIN_GTT 0x2PUBLIC __attribute__((visibility("default")))ENOTRECOVERABLE 131_D_ALLOC_NAMLEN(d) (((char *) (d) + (d)->d_reclen) - &(d)->d_name[0])AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFFSI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20__attribute_pure__ __attribute__ ((__pure__))count_modesprogram_invocation_short_nameF_TEST 3GBM_FORMAT_YVU411 __gbm_fourcc_code('Y', 'V', '1', '1')AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0_CS_POSIX_V7_ILP32_OFFBIG_LDFLAGS _CS_POSIX_V7_ILP32_OFFBIG_LDFLAGS_SC_INT_MAX _SC_INT_MAXDRM_MODE_CURSOR_BO 0x01__FLT128_MANT_DIG__ 113_drmVersionAMDGPU_GEM_DOMAIN_CPU 0x1DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)_SC_TIMERS _SC_TIMERS__SLONG32_TYPE int_POSIX_SYMLINK_MAX 255AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1__INT_FAST32_MAX__ 0x7fffffffffffffffL__ID_T_TYPE __U32_TYPE_SC_TRACE_INHERIT _SC_TRACE_INHERIT__USE_POSIX199309 1__INT_FAST8_WIDTH__ 8DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2)DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version)_SC_USHRT_MAX _SC_USHRT_MAX__clockid_t_defined 1ECANCELED 125__GLIBC_USE_IEC_60559_BFP_EXT 1R300_CMD_PACKET3_CLEAR 0AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0)__FLT128_MIN_10_EXP__ (-4931)RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT)RADEON_GEM_CPU_ACCESS (1 << 3)_LARGEFILE64_SOURCE 1MINIGBM _POSIX_MQ_PRIO_MAX 32chip_revRADEON_EMIT_SE_VPORT_XSCALE 8EPFNOSUPPORT 96__off64_tRADEON_DEPTH 0x4__USE_XOPEN2KXSIDRM_MODE_FLAG_3D_MASK (0x1f<<14)drmIsMasterR200_EMIT_PP_TXFILTER_4 40drmDevicePtrFOPEN_MAXDRM_MODE_PAGE_FLIP_TARGET (DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE | DRM_MODE_PAGE_FLIP_TARGET_RELATIVE)F_SEAL_GROW 0x0004DRM_MODE_SUBPIXEL_VERTICAL_RGBRADEON_STENCIL 0x8AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)EDOM 33AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3AMDGPU_TILING_GET(value,field) (((__u64)(value) >> AMDGPU_TILING_ ##field ##_SHIFT) & AMDGPU_TILING_ ##field ##_MASK)DRM_IOCTL_SYNCOBJ_RESET DRM_IOWR(0xC4, struct drm_syncobj_array)F_SETOWN __F_SETOWN_SC_RAW_SOCKETS _SC_RAW_SOCKETSRADEON_INFO_DEVICE_ID 0x00_PC_NAME_MAX _PC_NAME_MAXAMDGPU_TILING_SCANOUT_MASK 0x1__DBL_MIN_10_EXP__ (-307)TTY_NAME_MAX 32R200_EMIT_RE_SCISSOR_TL_1 55DRM_MODE_REFLECT_Y (1<<5)EADDRNOTAVAIL 99__timer_t_defined 1DRM_AMDGPU_GEM_METADATA 0x06O_DIRECTORY __O_DIRECTORY__WIFEXITED(status) (__WTERMSIG(status) == 0)WINT_MIN (0u)RADEON_GART_TEX_HEAP 1_CS_POSIX_V6_ILP32_OFFBIG_LDFLAGS _CS_POSIX_V6_ILP32_OFFBIG_LDFLAGSRADEON_PARAM_GART_BASE 6DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink)EBADSLT 57__attribute_deprecated_msg__(msg) __attribute__ ((__deprecated__ (msg)))GBM_FORMAT_R8 __gbm_fourcc_code('R', '8', ' ', ' ')AMDGPU_VM_OP_RESERVE_VMID 1ECHRNG 44__dirstream_POSIX_TRACE_LOG -1_CS_POSIX_V7_ILP32_OFF32_LIBS _CS_POSIX_V7_ILP32_OFF32_LIBS__fsfilcnt_t_defined _PC_PIPE_BUF _PC_PIPE_BUF_ATFILE_SOURCEDRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7<<14)DRM_MODE_ENCODER_DPMST 7DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx)__attribute_warn_unused_result__ __attribute__ ((__warn_unused_result__))_POSIX2_C_DEV __POSIX2_THIS_VERSION__FSFILCNT_T_TYPE __SYSCALL_ULONG_TYPE_BITS_STAT_H 1AMDGPU_INFO_READ_MMR_REG 0x15AMDGPU_CTX_INNOCENT_RESET 2_SC_PII_OSI_M _SC_PII_OSI_M__LEAF_ATTR __attribute__ ((__leaf__))__unix 1EACCES 13ENOENT 2_POSIX_HOST_NAME_MAX 255_SC_THREAD_DESTRUCTOR_ITERATIONS _SC_THREAD_DESTRUCTOR_ITERATIONS__USE_MISCWINT_MAX (4294967295u)DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane)num_shader_engines__need___va_listECONNRESET 104isalpha_l(c,l) __isalpha_l ((c), (l))_SC_2_PBS_TRACK _SC_2_PBS_TRACKRADEON_INFO_MAX_SE 0x12_POSIX_VERSION 200809LMB_CUR_MAX (__ctype_get_mb_cur_max ())DRM_RADEON_CS 0x26R200_EMIT_PP_CUBIC_OFFSETS_2 66family__USE_FORTIFY_LEVEL_CS_POSIX_V7_ILP32_OFF32_CFLAGS _CS_POSIX_V7_ILP32_OFF32_CFLAGSENOTDIR 20__S_IFBLK 0060000AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7)DRM_MODE_PROP_EXTENDED_TYPE 0x0000ffc0DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL DRM_IOWR(0xCD, struct drm_syncobj_timeline_array)DRM_CAP_VBLANK_HIGH_CRTC 0x2DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx)_POSIX_SPAWN 200809LR200_EMIT_RB3D_DEPTHXY_OFFSET 52__f32x(x) x ##f32x__GLIBC_USE_LIB_EXT2 1__uint64_tDRM_CRTC_SEQUENCE_RELATIVE 0x00000001AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7F_SETLEASE 1024DN_MULTISHOT 0x80000000DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29_SC_SEMAPHORES _SC_SEMAPHORESELIBSCN 81DRM_MODE_SCALE_NONE 0__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1__FLT64_MAX_EXP__ 1024R200_EMIT_PP_CUBIC_FACES_3 67RADEON_INFO_VCE_FW_VERSION 0x1bRENAME_WHITEOUT (1 << 2)RADEON_EMIT_PP_LUM_MATRIX 5__REGISTER_PREFIX__ RADEON_TILING_EG_BANKW_SHIFT 8_CS_POSIX_V7_LPBIG_OFFBIG_LINTFLAGS _CS_POSIX_V7_LPBIG_OFFBIG_LINTFLAGSDRM_DEV_DIRMODE (S_IRUSR|S_IWUSR|S_IXUSR|S_IRGRP|S_IXGRP|S_IROTH|S_IXOTH)DRM_SPINLOCK_TAKE(spin,val) do { DRM_CAS_RESULT(__ret); int cur; do { cur = (*spin).lock; DRM_CAS(spin,cur,val,__ret); } while (__ret); } while(0)__LDBL_REDIR1_NTH(name,proto,alias) name proto __THROW_XOPEN_SHM 1drmFreeVersionRADEON_EMIT_PP_ROT_MATRIX_0 6ELIBMAX 82_XOPEN_XPG3 1DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd)conn_SC_XOPEN_XPG3 _SC_XOPEN_XPG3EINPROGRESS 115AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1FILENAME_MAX 4096__USE_POSIX199506isspace(c) __isctype((c), _ISspace)GBM_FORMAT_BGRA8888 __gbm_fourcc_code('B', 'A', '2', '4')productDRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)__GCC_IEC_559_COMPLEX 2__PTHREAD_COMPAT_PADDING_MID __FLT32_HAS_INFINITY__ 1__SEG_GS 1DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01__CHAR_BIT__ 8RADEON_GEM_DOMAIN_VRAM 0x4__INTPTR_MAX__ 0x7fffffffffffffffLDRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder)INT_LEAST64_MAX (__INT64_C(9223372036854775807))AMDGPU_INFO_CRTC_FROM_ID 0x01R200_EMIT_TEX_PROC_CTL_2 34DRM_CAS_RESULT(_result) char _result__HAVE_DISTINCT_FLOAT16 __HAVE_FLOAT16__glibc_macro_warning(message) __glibc_macro_warning1 (GCC warning message)__errordecl(name,msg) extern void name (void) __attribute__((__error__ (msg)))_FCNTL_H 1DRM_AMDGPU_GEM_VA 0x08vsync_start__glibc_macro_warning1(message) _Pragma (#message)__FLT32X_MIN_10_EXP__ (-307)GBM_FORMAT_BGRX8888 __gbm_fourcc_code('B', 'X', '2', '4')RADEON_INFO_CURRENT_GPU_SCLK 0x22__glibc_unlikely(cond) __builtin_expect ((cond), 0)long long unsigned int_IOR_BAD(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size))RADEON_UPLOAD_TEX1IMAGES 0x00002000read_mmr_regDRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling)DRM_MIN_ORDER 5F_WRLCK 1__GCC_ATOMIC_BOOL_LOCK_FREE 2ip_instanceDRM_AMDGPU_CS 0x04__LDBL_MANT_DIG__ 64AMDGPU_TILING_BANK_HEIGHT_MASK 0x3_drmModeConnectorDRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)RADEON_INFO_MAX_SH_PER_SE 0x13__LDBL_REDIR_NTH(name,proto) name proto __THROW_XOPEN_REALTIME 1DRM_MODE_CONNECTOR_WRITEBACK 18RWH_WRITE_LIFE_MEDIUM 3_SC_UCHAR_MAX _SC_UCHAR_MAXAMDGPU_BO_LIST_OP_CREATE 0RADEON_NR_TEX_HEAPS 2cu_ao_bitmapWINT_WIDTH 32__SSE2_MATH__ 1__USE_POSIX 1count_fbsENOSYS 38DRM_MODE_OBJECT_PROPERTY 0xb0b0b0b0AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9)_SC_THREAD_STACK_MIN _SC_THREAD_STACK_MIN__ELF__ 1DRM_IOCTL_MODE_ATOMIC DRM_IOWR(0xBC, struct drm_mode_atomic)RADEON_MEM_REGION_GART 1__FLT128_MIN_EXP__ (-16381)_____fpos64_t_defined 1_POSIX_STREAM_MAX 8__INT64_TYPE__ long intRADEON_MEM_REGION_FB 2enabled_rb_pipes_maskDRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)__attribute_const__ __attribute__ ((__const__))__THROWNL __attribute__ ((__nothrow__))islower(c) __isctype((c), _ISlower)RADEON_GEM_NO_CPU_ACCESS (1 << 4)__stub_revoke F_SEAL_WRITE 0x0008__LDBL_REDIR_DECL(name) R200_EMIT_PP_CNTL_X 51DRM_RADEON_GEM_SET_TILING 0x28EBADR 53AMDGPU_VRAM_TYPE_DDR5 10__GLIBC_USE(F) __GLIBC_USE_ ## F__id_t_defined SI_TILE_MODE_DEPTH_STENCIL_2D_2AA 3DRM_MODE_DPMS_OFF 3__ATOMIC_HLE_RELEASE 131072_CS_LFS_LINTFLAGS _CS_LFS_LINTFLAGSELIBEXEC 83AMDGPU_INFO_FW_DMCUB 0x14AMDGPU_INFO_FW_SDMA 0x0b__NTH(fct) __attribute__ ((__nothrow__ __LEAF)) fct_VA_LIST_ _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)DRM_CAS(lock,old,new,__ret) do { int __dummy; __asm__ __volatile__( "lock ; cmpxchg %4,%1\n\t" "setnz %0" : "=d" (__ret), "=m" (__drm_dummy_lock(lock)), "=a" (__dummy) : "2" (old), "r" (new)); } while (0)DRM_MODE_SCALE_CENTER 2DRM_MODE_SUBPIXEL_VERTICAL_BGR_PC_ALLOC_SIZE_MIN _PC_ALLOC_SIZE_MINDRM_MODE_CONNECTOR_Component 8__PTHREAD_MUTEX_USE_UNION 0DRM_ERR_NO_ACCESS (-1002)_SC_READER_WRITER_LOCKS _SC_READER_WRITER_LOCKSRADEON_SETPARAM_NEW_MEMMAP 4__need___va_list cu_bitmap__dev_t_defined isalnum_l(c,l) __isalnum_l ((c), (l))__LP64__ 1num_shader_visible_vgprs_POSIX_SPIN_LOCKS 200809LDRM_SPINLOCK_COUNT(spin,val,count,__ret) do { int __i; __ret = 1; for (__i = 0; __ret && __i < count; __i++) { DRM_CAS(spin,0,val,__ret); if (__ret) for (;__i < count && (spin)->lock; __i++); } } while(0)_SC_V7_ILP32_OFF32 _SC_V7_ILP32_OFF32__DBL_EPSILON__ ((double)2.22044604925031308084726333618164062e-16L)POSIX_FADV_SEQUENTIAL 2__ASM_GENERIC_POSIX_TYPES_H _ANSI_STDARG_H_ RADEON_INFO_GTT_USAGE 0x1fDRM_MODE_OBJECT_FB 0xfbfbfbfbTEMP_FAILURE_RETRY(expression) (__extension__ ({ long int __result; do __result = (long int) (expression); while (__result == -1L && errno == EINTR); __result; }))dirent_SC_DEVICE_SPECIFIC _SC_DEVICE_SPECIFICDRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding)RADEON_CHUNK_ID_RELOCS 0x01FD_ISSET(fd,fdsetp) __FD_ISSET (fd, fdsetp)DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)P_PGID_drmPciDeviceInfohdisplayINTPTR_MIN (-9223372036854775807L-1)__WEXITSTATUS(status) (((status) & 0xff00) >> 8)DRM_SPINLOCK(spin,val) do { DRM_CAS_RESULT(__ret); do { DRM_CAS(spin,0,val,__ret); if (__ret) while ((spin)->lock); } while (__ret); } while(0)SEEK_HOLE 4drm_amdgpu_info_device__FSBLKCNT64_T_TYPE __UQUAD_TYPE_DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)O_SYNC 04010000drmPciDeviceInfoPtr__restrict_arr __restrictEROFS 30__USE_UNIX98 1RADEON_INFO_WANT_HYPERZ 0x07RADEON_USE_HIERZ 0x40000000INT_FAST8_MAX (127)DRM_CLIENT_CAP_STEREO_3D 1_GBM_H_ _SC_C_LANG_SUPPORT_R _SC_C_LANG_SUPPORT_RAMDGPU_VM_PAGE_WRITEABLE (1 << 2)__LONG_MAX__ 0x7fffffffffffffffLAMDGPU_CTX_PRIORITY_HIGH 512RADEON_VM_PAGE_WRITEABLE (1 << 2)_IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS)DRM_ERR_NOT_ROOT (-1003)O_CREAT 0100_SC_OPEN_MAX _SC_OPEN_MAX__FD_SET(d,set) ((void) (__FDS_BITS (set)[__FD_ELT (d)] |= __FD_MASK (d)))DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)_POSIX_THREAD_THREADS_MAX 64drmDropMaster__O_DSYNC 010000__INT_LEAST32_TYPE__ intFNONBLOCK O_NONBLOCKRADEON_VA_UNMAP 2_CS_POSIX_V7_ILP32_OFF32_LINTFLAGS _CS_POSIX_V7_ILP32_OFF32_LINTFLAGS__RADEON_DRM_H__ DRV_I915 1long long intDRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)F_OK 0___int_wchar_t_h LOGIN_NAME_MAX 256__OFF_T_TYPE __SYSCALL_SLONG_TYPE_SC_LEVEL1_ICACHE_ASSOC _SC_LEVEL1_ICACHE_ASSOCRADEON_UPLOAD_MISC 0x00000100__gbm_fourcc_code(a,b,c,d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24))AMDGPU_TILING_NUM_BANKS_SHIFT 21resourcesF_GETOWN __F_GETOWNhtole16(x) __uint16_identity (x)DRM_MODE_FLAG_INTERLACE (1<<4)GBM_FORMAT_RGBX8888 __gbm_fourcc_code('R', 'X', '2', '4')__need_wchar_t _POSIX_TRACE_EVENT_FILTER -1_vtable_offset_XOPEN_VERSION 700d_offDRM_RADEON_VBLANK_CRTC1 1_PC_PRIO_IO _PC_PRIO_IOgc_double_offchip_lds_bufRADEON_TILING_R600_NO_SCANOUT RADEON_TILING_SWAP_16BITDRM_MODE_FB_DIRTY_FLAGS 0x03_CS_POSIX_V7_ILP32_OFFBIG_CFLAGS _CS_POSIX_V7_ILP32_OFFBIG_CFLAGS__getc_unlocked_body(_fp) (__glibc_unlikely ((_fp)->_IO_read_ptr >= (_fp)->_IO_read_end) ? __uflow (_fp) : *(unsigned char *) (_fp)->_IO_read_ptr++)__BIT_TYPES_DEFINED__ 1_BITS_POSIX1_LIM_H 1__FDS_BITS(set) ((set)->fds_bits)min_width_FILE_OFFSET_BITS 64RADEON_GEM_DOMAIN_GTT 0x2GBM_FORMAT_ABGR16161616F __gbm_fourcc_code('A', 'B', '4', 'H')R200_EMIT_PP_TXOFFSET_3 45dev_node_ISdigit_SC_PAGESIZE _SC_PAGESIZE__POSIX_FADV_DONTNEED 4DRM_RENDER_DEV_NAME "%s/" DRM_RENDER_MINOR_NAME "%d"_SC_CHAR_BIT _SC_CHAR_BIT_POSIX_TZNAME_MAX 6connector_id__FLT64X_DECIMAL_DIG__ 21__daddr_t_defined _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size)))ENOTSUP EOPNOTSUPP__FSFILCNT64_T_TYPE __UQUAD_TYPEAMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4)_POSIX_VDISABLE '\0'_SC_REALTIME_SIGNALS _SC_REALTIME_SIGNALSO_NOCTTY 0400UINT16_MAX (65535)GBM_FORMAT_RGBX4444 __gbm_fourcc_code('R', 'X', '1', '2')DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN)WSTOPPED 2NULL ((void *)0)RADEON_CS_RING_DMA 2DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12__O_NOFOLLOW 0400000DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector)_SC_TIMER_MAX _SC_TIMER_MAX__va_copy(d,s) __builtin_va_copy(d,s)DT_BLK DT_BLKDRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle)__glibc_has_attribute(attr) __has_attribute (attr)INT8_MAX (127)drmModeFreeConnectorSYNC_FILE_RANGE_WAIT_AFTER 4__LDBL_MIN__ 3.36210314311209350626267781732175260e-4932LF_RDLCK 0O_LARGEFILE __O_LARGEFILESI_TILE_MODE_COLOR_2D_SCANOUT_32BPP 12DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock)_GCC_SIZE_T subvendor_idGBM_FORMAT_P010 __gbm_fourcc_code('P', '0', '1', '0')AMDGPU_INFO_VBIOS_IMAGE 0x2PTRDIFF_WIDTH __WORDSIZEO_CLOEXEC __O_CLOEXEC__va_arg_pack() __builtin_va_arg_pack ()__SIZEOF_FLOAT80__ 16__need_wchar_tRADEON_EMIT_SE_LINE_WIDTH 4__UINT64_MAX__ 0xffffffffffffffffULDRM_MODE_DPMS_SUSPEND 2DN_DELETE 0x00000008__GCC_IEC_559 2RADEON_VA_RESULT_ERROR 1__FLT32_MANT_DIG__ 24max_engine_clockGBM_FORMAT_YVU410 __gbm_fourcc_code('Y', 'V', 'U', '9')_DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)POSIX_FADV_DONTNEED __POSIX_FADV_DONTNEED_CS_XBS5_ILP32_OFF32_LDFLAGS _CS_XBS5_ILP32_OFF32_LDFLAGSLINK_MAX 127__S32_TYPE int_ASM_X86_POSIX_TYPES_64_H __undef_NR_OPEN AMDGPU_FAMILY_RV 142AMDGPU_HW_IP_DMA 2__F_SETOWN_EX 15num_hw_gfx_contexts__USE_FORTIFY_LEVEL 0_SYS_SIZE_T_H __SHRT_WIDTH__ 16_SC_BASE _SC_BASE__SSE2__ 1EUNATCH 49__CPU_MASK_TYPE __SYSCALL_ULONG_TYPEEXDEV 18_SC_THREAD_SAFE_FUNCTIONS _SC_THREAD_SAFE_FUNCTIONS__STDC_IEC_559__ 1_PC_ASYNC_IO _PC_ASYNC_IO_SC_SCHAR_MIN _SC_SCHAR_MIN_SC_LINE_MAX _SC_LINE_MAX_POSIX2_VERSION __POSIX2_THIS_VERSION__DBL_DECIMAL_DIG__ 17__RADEON_SAREA_DEFINES__ asprintf__GCC_ATOMIC_CHAR_LOCK_FREE 2__INT_LEAST64_WIDTH__ 64subdevice_idRADEON_INFO_FASTFB_WORKING 0x14iscntrl(c) __isctype((c), _IScntrl)_XBS5_LPBIG_OFFBIG -1__FLT64X_HAS_QUIET_NAN__ 1AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock)POSIX_FADV_RANDOM 1_SC_BC_DIM_MAX _SC_BC_DIM_MAXAMDGPU_CTX_OP_SET_STABLE_PSTATE 6_LINUX_POSIX_TYPES_H L_INCR SEEK_CUR__PMTvce_harvest_config_SC_COLL_WEIGHTS_MAX _SC_COLL_WEIGHTS_MAXFORMAT_BLOB_CURRENT 1DRM_AMDGPU_GEM_WAIT_IDLE 0x07AMDGPU_TILING_BANK_WIDTH_SHIFT 15__VERSION__ "8.3.0"AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff__DEC128_SUBNORMAL_MIN__ 0.000000000000000000000000000000001E-6143DLDRM_IOCTL_NR(n) _IOC_NR(n)SPLICE_F_MORE 4_SC_XOPEN_CRYPT _SC_XOPEN_CRYPT__CONCAT(x,y) x ## yAMDGPU_CTX_PRIORITY_VERY_HIGH 1023__S_ISGID 02000_POSIX_THREAD_ATTR_STACKADDR 200809L__OPTIMIZE__ 1AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0_PC_FILESIZEBITS _PC_FILESIZEBITS_T_SIZE_ GBM_FORMAT_XRGB8888 __gbm_fourcc_code('X', 'R', '2', '4')openGBM_DEV_TYPE_FLAG_DISCRETE (1u << 0)_SC_USER_GROUPS _SC_USER_GROUPSAMDGPU_INFO_RAS_ENABLED_DF (1 << 8)RADEON_EMIT_PP_BORDER_COLOR_0 13AMDGPU_HW_IP_GFX 0AMDGPU_INFO_GDS_CONFIG 0x13_chain_POSIX_LINK_MAX 8AMDGPU_TILING_SCANOUT_SHIFT 63DRM_MODE_TYPE_USERDEF (1<<5)DRM_MAX_MINOR 16EKEYREJECTED 129DRM_MODE_PROP_BITMASK (1<<5)_SC_TRACE_USER_EVENT_MAX _SC_TRACE_USER_EVENT_MAXAMDGPU_GEM_OP_SET_PLACEMENT 1EBADMSG 74RADEON_CS_RING_GFX 0EKEYREVOKED 128S_IFBLK __S_IFBLKRADEON_PARAM_FB_LOCATION 14RADEON_MAX_STATE_PACKETS 95DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)AMDGPU_GEM_USERPTR_VALIDATE (1 << 2)__drm_dummy_lock(lock) (*(__volatile__ unsigned int *)lock)DT_SOCK DT_SOCKAMDGPU_VM_MTYPE_CC (3 << 5)__KEY_T_TYPE __S32_TYPE_IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size)))_SC_SHRT_MIN _SC_SHRT_MIN__WCHAR_MIN __WCHAR_MIN__DTTOIF(dirtype) ((dirtype) << 12)O_TRUNC 01000__need_ptrdiff_tDRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info)__S_IWRITE 0200AMDGPU_HW_IP_COMPUTE 1_POSIX_SYMLOOP_MAX 8__FLT128_MAX_EXP__ 16384NFDBITS __NFDBITS_POSIX_SAVED_IDS 1ENETDOWN 100__USE_XOPEN2K8 1ELOOP 40ENXIO 6_LFS_ASYNCHRONOUS_IO 1__COMPAR_FN_T tolower(c) __tobody (c, tolower, *__ctype_tolower_loc (), (c))R300_WAIT_2D 0x1RADEON_UPLOAD_TEX0IMAGES 0x00001000_SC_XOPEN_VERSION _SC_XOPEN_VERSIONAMDGPU_INFO_FW_SOS 0x0c__DBL_MAX_EXP__ 1024IOCSIZE_SHIFT (_IOC_SIZESHIFT)dev_countRADEON_INFO_BACKEND_MAP 0x0d_SC_SEM_NSEMS_MAX _SC_SEM_NSEMS_MAX_POSIX2_C_VERSION __POSIX2_THIS_VERSION_SC_NPROCESSORS_CONF _SC_NPROCESSORS_CONF_SC_BC_SCALE_MAX _SC_BC_SCALE_MAX_____fpos_t_defined 1_DRM_PRE_MODESET 1INT_FAST32_MAX (9223372036854775807L)RADEON_INFO_READ_REG 0x24_DEFAULT_SOURCE 1__GCC_ATOMIC_POINTER_LOCK_FREE 2__UID_T_TYPE __U32_TYPENGROUPS_MAX 65536_tolower(c) ((int) (*__ctype_tolower_loc ())[(int) (c)])_POSIX_AIO_MAX 1_SC_THREAD_ATTR_STACKADDR _SC_THREAD_ATTR_STACKADDR__PMT(args) args__isprint_l(c,l) __isctype_l((c), _ISprint, (l))ENOPROTOOPT 92ERFKILL 132DRM_RADEON_FREE 0x14__SIZE_WIDTH__ 64DRM_NAME "drm"PTHREAD_DESTRUCTOR_ITERATIONS _POSIX_THREAD_DESTRUCTOR_ITERATIONSDRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb)__ATOMIC_RELEASE 3_IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1)__unix__ 1_SC_IPV6 _SC_IPV6__exctype_l(name) extern int name (int, locale_t) __THROWRADEON_GEM_USERPTR_ANONONLY (1 << 1)DRM_MODE_FLAG_PIC_AR_256_135 (DRM_MODE_PICTURE_ASPECT_256_135<<19)__iscntrl_l(c,l) __isctype_l((c), _IScntrl, (l))R200_EMIT_PP_TXCTLALL_2 90_CS_POSIX_V7_LPBIG_OFFBIG_LIBS _CS_POSIX_V7_LPBIG_OFFBIG_LIBSENONET 64_SC_POLL _SC_POLL__HAVE_DISTINCT_FLOAT64 0AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFFRADEON_GEM_USERPTR_READONLY (1 << 0)__DEC_EVAL_METHOD__ 2_freeres_list__DADDR_T_TYPE __S32_TYPE_SC_VERSION _SC_VERSIONDRM_LIGHT_LOCK(fd,lock,context) do { DRM_CAS_RESULT(__ret); DRM_CAS(lock,context,DRM_LOCK_HELD|context,__ret); if (__ret) drmGetLock(fd,context,0); } while(0)DRM_RADEON_CP_START 0x01RADEON_PARAM_GART_TEX_HANDLE 10isblank(c) __isctype((c), _ISblank)__DECIMAL_DIG__ 21_SC_TZNAME_MAX _SC_TZNAME_MAXUINTPTR_MAX (18446744073709551615UL)F_SEAL_SEAL 0x0001UINT_LEAST64_MAX (__UINT64_C(18446744073709551615))GBM_FORMAT_RGBX5551 __gbm_fourcc_code('R', 'X', '1', '5')__undef_LINK_MAX __GCC_HAVE_DWARF2_CFI_ASM 1__DEC64_EPSILON__ 1E-15DDAMDGPU_FAMILY_VI 130__attribute_format_strfmon__(a,b) __attribute__ ((__format__ (__strfmon__, a, b)))RADEON_CARD_PCIE 2EREMCHG 78_IO_FILE__stack_chk_fail__attribute_format_arg__(x) __attribute__ ((__format_arg__ (x)))DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info)DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma)AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8)MAX(A,B) ((A) > (B) ? (A) : (B))S_IRGRP (S_IRUSR >> 3)_SC_THREAD_SPORADIC_SERVER _SC_THREAD_SPORADIC_SERVER_SC_REGEX_VERSION _SC_REGEX_VERSIONDRM_UNLOCK(fd,lock,context) do { DRM_CAS_RESULT(__ret); DRM_CAS(lock,DRM_LOCK_HELD|context,context,__ret); if (__ret) drmUnlock(fd,context); } while(0)DRM_RADEON_CP_RESET 0x03_IOC_WRITE 1UENOCSI 50ECONNABORTED 103DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map)_SC_T_IOV_MAX _SC_T_IOV_MAXF_SETLKW F_SETLKW64__INT16_MAX__ 0x7fffAMDGPU_INFO_FW_ASD 0x0d__ONCE_ALIGNMENT gpu_counter_freqDRM_BUS_PCI 0AMDGPU_VA_OP_REPLACE 4AMDGPU_IB_FLAG_PREEMPT (1<<2)F_GETLK64 5_POSIX_SHARED_MEMORY_OBJECTS 200809LAMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2GBM_FORMAT_ARGB2101010 __gbm_fourcc_code('A', 'R', '3', '0')GBM_FORMAT_YUV420 __gbm_fourcc_code('Y', 'U', '1', '2')_SC_2_CHAR_TERM _SC_2_CHAR_TERMRADEON_GEM_GTT_UC (1 << 1)AMDGPU_INFO_ACCEL_WORKING 0x00_T_WCHAR GBM_FORMAT_NV16 __gbm_fourcc_code('N', 'V', '1', '6')_SC_PII_XTI _SC_PII_XTIR200_EMIT_SE_VAP_CNTL_STATUS 57optind_CS_POSIX_V6_WIDTH_RESTRICTED_ENVS _CS_V6_WIDTH_RESTRICTED_ENVSstrlenUINTMAX_MAX (__UINT64_C(18446744073709551615))EXFULL 54__HAVE_FLOAT128X 0O_NOFOLLOW __O_NOFOLLOW_XOPEN_XPG2 1_pad_BITS_BYTESWAP_H 1_IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS)RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)__size_t __UINT16_C(c) cdrm_radeon_infoAMDGPU_GEM_USERPTR_ANONONLY (1 << 1)AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19__WTERMSIG(status) ((status) & 0x7f)DRM_PRIME_CAP_IMPORT 0x1__warndecl(name,msg) extern void name (void) __attribute__((__warning__ (msg)))_LINUX_TYPES_H __u32DRM_MODE_CONNECTOR_DVII 2__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2_CS_LFS_CFLAGS _CS_LFS_CFLAGS__FLT32X_HAS_DENORM__ 1EHWPOISON 133AMDGPU_FAMILY_YC 146_PC_REC_XFER_ALIGN _PC_REC_XFER_ALIGNRWH_WRITE_LIFE_EXTREME 5_STDC_PREDEF_H 1BUFSIZ 8192DRM_MODE_CONNECTOR_TV 13_SC_PHYS_PAGES _SC_PHYS_PAGESDRM_CLIENT_CAP_WRITEBACK_CONNECTORS 5UINT_FAST64_MAX (__UINT64_C(18446744073709551615))_BITS_ERRNO_H 1PATH_MAX 4096DRM_RADEON_GEM_SET_DOMAIN 0x23isprint(c) __isctype((c), _ISprint)__FLT32_MAX_EXP__ 128UINT_FAST8_WIDTH 8drmModeFreeResources_CS_PATH _CS_PATH__intptr_t_defined _STAT_VER_KERNEL 0_LARGEFILE_SOURCE_POSIX_MEMLOCK_RANGE 200809LEL3HLT 46R200_EMIT_PP_TXCBLEND_2 23_DIRENT_H 1R300_CMD_SCRATCH 8_POSIX_REENTRANT_FUNCTIONS 1drm_amdgpu_query_fw__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2_SC_UIO_MAXIOV _SC_UIO_MAXIOVtrue 1AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)cntl_sb_buf_sizeAMDGPU_VA_OP_CLEAR 3GBM_FORMAT_ARGB4444 __gbm_fourcc_code('A', 'R', '1', '2')DRM_RADEON_GETPARAM 0x11_CS_LFS_LIBS _CS_LFS_LIBSAMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43__isxdigit_l(c,l) __isctype_l((c), _ISxdigit, (l))__DEC64_MIN__ 1E-383DD__FD_ELT(d) ((d) / __NFDBITS)DRM_MODE_CONNECTOR_9PinDIN 9_BITS_TYPES_H 1P_tmpdir "/tmp"DT_CHR DT_CHR_POSIX_THREAD_PROCESS_SHARED 200809L__USE_ISOC95 1prim_buf_size__DEC64_MAX__ 9.999999999999999E384DDDRM_AMDGPU_CTX 0x02AT_FDCWD -100DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain)__GLIBC_USE_IEC_60559_BFP_EXT_freeres_buf__FLT128_DIG__ 33AMDGPU_CTX_PRIORITY_VERY_LOW -1023__F_GETOWN_EX 16EHOSTUNREACH 113AMDGPU_CTX_OP_QUERY_STATE 3_BITS_PTHREADTYPES_ARCH_H 1cu_ao_maskF_GET_RW_HINT 1035DRM_PROC_NAME "/proc/dri/"GBM_FORMAT_C8 __gbm_fourcc_code('C', '8', ' ', ' ')__SEG_FS 1RADEON_CS_END_OF_FRAME 0x04_CS_POSIX_V6_LPBIG_OFFBIG_LIBS _CS_POSIX_V6_LPBIG_OFFBIG_LIBSDRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04__alignCLONE_VFORK 0x00004000STA_FREQHOLD 0x0080MESA_LLVMPIPE_MAX_TEXTURE_2D_LEVELS 15DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)__pthread_mutex_sDRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)CLONE_NEWNET 0x40000000AMD_FMT_MOD_RB_SHIFT 30DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8')DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)BO_USE_GPU_DATA_BUFFER (1ull << 18)DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2')AMLOGIC_FBC_LAYOUT_SCATTER (2ULL)STA_CLK 0x8000__sched_priority sched_priority__CPU_CLR_S(cpu,setsize,cpusetp) (__extension__ ({ size_t __cpu = (cpu); __cpu / 8 < (setsize) ? (((__cpu_mask *) ((cpusetp)->__bits))[__CPUELT (__cpu)] &= ~__CPUMASK (__cpu)) : 0; }))PTHREAD_ADAPTIVE_MUTEX_INITIALIZER_NP { { 0, 0, 0, 0, PTHREAD_MUTEX_ADAPTIVE_NP, __PTHREAD_SPINS, { 0, 0 } } }drv_loge(format,...) _drv_log(DRV_LOGE, format, ##__VA_ARGS__)DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4')CPU_ISSET_S(cpu,setsize,cpusetp) __CPU_ISSET_S (cpu, setsize, cpusetp)__CPU_SETSIZE 1024AMD_FMT_MOD_TILE_SHIFT 8CLOCK_REALTIME_COARSE 5DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4')PARAM(x) (struct virtgpu_param) { x, #x, 0 }TIMER_ABSTIME 1CLONE_PARENT 0x00008000__fourcc_mod_amlogic_options_mask 0xffDRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V')AMD_FMT_MOD_TILE_VERSION_MASK 0xFFDRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2')VIRTGPU_PARAM_RESOURCE_BLOB 3AMD_FMT_MOD_TILE_GFX9_64K_D 10BO_USE_NON_GPU_HW (BO_USE_SCANOUT | BO_USE_CAMERA_WRITE | BO_USE_CAMERA_READ | BO_USE_HW_VIDEO_ENCODER | BO_USE_HW_VIDEO_DECODER | BO_USE_SENSOR_DIRECT_DATA)PTHREAD_CANCEL_DISABLE PTHREAD_CANCEL_DISABLEDRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1')__CPU_ZERO_S(setsize,cpusetp) do __builtin_memset (cpusetp, '\0', setsize); while (0)DRM_FORMAT_FLEX_YCbCr_420_888 fourcc_code('9', '9', '9', '9')PTHREAD_CANCELED ((void *) -1)DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)AFBC_FORMAT_MOD_USM (1ULL << 12)DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode)DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2')AFRC_FORMAT_MOD_CU_SIZE_16 (1ULL)DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0')DRM_IOCTL_VIRTGPU_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT, struct drm_virtgpu_3d_wait)_BITS_TYPES_STRUCT_SCHED_PARAM 1SCHED_RR 2rectDRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0')compressionDRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0')DRM_FORMAT_NONE fourcc_code('0', '0', '0', '0')DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4')DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8')DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8')BO_USE_CAMERA_READ (1ull << 7)DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6')DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4')ADJ_OFFSET_SS_READ 0xa001VIRTGPU_BLOB_MEM_GUEST 0x0001AMD_FMT_MOD_SET(field,value) ((uint64_t)(value) << AMD_FMT_MOD_ ##field ##_SHIFT)DRM_FORMAT_MOD_NONE 0virtgpu_virglI915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)__int64_tAMD_FMT_MOD_TILE_MASK 0x1FDRV_LOGEADJ_MAXERROR 0x0004CLONE_NEWUTS 0x04000000DRV_PRIV_H mappingBO_MAP_NONE 0DRV_LOGVMESA_LLVMPIPE_MAX_TEXTURE_2D_SIZE (1 << (MESA_LLVMPIPE_MAX_TEXTURE_2D_LEVELS - 1))DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0')DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5')fourcc_mod_broadcom_code(val,params) fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val))DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)__ownerDRM_FORMAT_MTISP_SXYZW10 fourcc_code('M', 'B', '1', '0')CPU_AND_S(setsize,destset,srcset1,srcset2) __CPU_OP_S (setsize, destset, srcset1, srcset2, &)VIRTGPU_PARAM_HOST_VISIBLE 4CLONE_SIGHAND 0x00000800DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2)CLOCK_TAI 11AMD_FMT_MOD_TILE_GFX9_64K_S 9CLONE_DETACHED 0x00400000__struct_tm_defined 1DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')__tzname__lockAMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24AFBC_FORMAT_MOD_SPARSE (1ULL << 6)drv_logv(format,...) _drv_log(DRV_LOGV, format, ##__VA_ARGS__)__pthread_list_tDRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL)AFBC_FORMAT_MOD_YTR (1ULL << 4)DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4')CPU_CLR(cpu,cpusetp) __CPU_CLR_S (cpu, sizeof (cpu_set_t), cpusetp)CPU_ISSET(cpu,cpusetp) __CPU_ISSET_S (cpu, sizeof (cpu_set_t), cpusetp)DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0')AFRC_FORMAT_MOD_CU_SIZE_32 (3ULL)ADJ_ESTERROR 0x0008DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8')STA_PPSTIME 0x0004DRM_FORMAT_MOD_BROADCOM_SAND64 DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0)CLOCK_BOOTTIME 7AMD_FMT_MOD_DCC_BLOCK_128B 1CPU_SETSIZE __CPU_SETSIZEBO_USE_HW_MASK (BO_USE_GPU_HW | BO_USE_NON_GPU_HW)DRM_VIRTGPU_GETPARAM 0x03AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3VIRTGPU_RESOURCE_INFO_TYPE_DEFAULT 0DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0')fourcc_code(a,b,c,d) ((__u32)(a) | ((__u32)(b) << 8) | ((__u32)(c) << 16) | ((__u32)(d) << 24))CLOCK_MONOTONIC_RAW 4DRM_FORMAT_MOD_VENDOR_QCOM 0x05MOD_TAI ADJ_TAISTA_DEL 0x0020DRM_IOCTL_VIRTGPU_RESOURCE_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, struct drm_virtgpu_resource_info)__dataVIRTGPU_EXECBUF_RING_IDX 0x04CLONE_NEWPID 0x20000000CLONE_SYSVSEM 0x00040000DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) fourcc_mod_broadcom_code(3, v)DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2')AFBC_FORMAT_MOD_BCH (1ULL << 11)DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06fourcc_mod_code(vendor,val) ((((__u64)DRM_FORMAT_MOD_VENDOR_ ## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))PTHREAD_CANCEL_ASYNCHRONOUS PTHREAD_CANCEL_ASYNCHRONOUSAMLOGIC_FBC_LAYOUT_BASIC (1ULL)DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4')DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6')pthread_mutex_tADJ_NANO 0x2000DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5')drm_virtgpu_getparamBO_USE_SCANOUT (1ull << 0)__NCPUBITS (8 * sizeof (__cpu_mask))PTHREAD_CANCEL_ENABLE PTHREAD_CANCEL_ENABLEAMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1AFRC_FORMAT_MOD_CU_SIZE_24 (2ULL)DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0')AMD_FMT_MOD_TILE_VER_GFX10 2AMD_FMT_MOD_DCC_RETILE_SHIFT 14BO_USE_HW_VIDEO_DECODER (1ull << 13)VIRTGPU_CONTEXT_PARAM_NUM_RINGS 0x0002PTHREAD_COND_INITIALIZER { { {0}, {0}, {0, 0}, {0, 0}, 0, 0, {0, 0} } }DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')ADJ_TAI 0x0080PTHREAD_EXPLICIT_SCHED PTHREAD_EXPLICIT_SCHEDDRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8')/source/platform/minigbm/virtgpu.c__kindVIRTGPU_EXECBUF_FLAGS ( VIRTGPU_EXECBUF_FENCE_FD_IN | VIRTGPU_EXECBUF_FENCE_FD_OUT | VIRTGPU_EXECBUF_RING_IDX | 0)I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)CLONE_NEWIPC 0x08000000DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8')MESA_LLVMPIPE_TILE_SIZE (1 << MESA_LLVMPIPE_TILE_ORDER)DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5')MOD_STATUS ADJ_STATUSVIRTGPU_PARAM_SUPPORTED_CAPSET_IDs 7VIRTGPU_PARAM_CONTEXT_INIT 6DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8')DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0')CPU_XOR(destset,srcset1,srcset2) __CPU_OP_S (sizeof (cpu_set_t), destset, srcset1, srcset2, ^)bo_metadataDRV_LOGDDRV_LOGICLOCKS_PER_SEC ((__clock_t) 1000000)ADJ_TICK 0x4000DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2)DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2')_PTHREAD_H 1DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8')rectangleCPU_EQUAL_S(setsize,cpusetp1,cpusetp2) __CPU_EQUAL_S (setsize, cpusetp1, cpusetp2)__CPU_SET_S(cpu,setsize,cpusetp) (__extension__ ({ size_t __cpu = (cpu); __cpu / 8 < (setsize) ? (((__cpu_mask *) ((cpusetp)->__bits))[__CPUELT (__cpu)] |= __CPUMASK (__cpu)) : 0; }))DRM_FORMAT_MOD_BROADCOM_SAND32 DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0)virtgpu_cross_domainDRM_FORMAT_MOD_ARM_CODE(__type,__val) fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL))DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1')BO_USE_CURSOR (1ull << 1)BO_USE_TEXTURE_MASK (BO_USE_LINEAR | BO_USE_RENDERSCRIPT | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN | BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY | BO_USE_TEXTURE | BO_USE_FRONT_RENDERING)VIRTGPU_CONTEXT_PARAM_CAPSET_ID 0x0001__size__isleap(year) ((year) % 4 == 0 && ((year) % 100 != 0 || (year) % 400 == 0))VIRTGPU_PARAM_RESOURCE_SYNC 9MESA_LLVMPIPE_TILE_ORDER 6DRM_FORMAT_MOD_BROADCOM_SAND256 DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0)drv_logd(format,...) _drv_log(DRV_LOGD, format, ##__VA_ARGS__)STA_CLOCKERR 0x1000PTHREAD_MUTEX_INITIALIZER { { 0, 0, 0, 0, 0, __PTHREAD_SPINS, { 0, 0 } } }MOD_MICRO ADJ_MICROCPU_CLR_S(cpu,setsize,cpusetp) __CPU_CLR_S (cpu, setsize, cpusetp)CLONE_NEWNS 0x00020000get_paramDRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')CPU_EQUAL(cpusetp1,cpusetp2) __CPU_EQUAL_S (sizeof (cpu_set_t), cpusetp1, cpusetp2)CLOCK_REALTIME_ALARM 8_BITS_TIMEX_H 1drv_logi(format,...) _drv_log(DRV_LOGI, format, ##__VA_ARGS__)__countDRM_FORMAT_P010 fourcc_code('P', '0', '1', '0')DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v))DRM_FOURCC_H VIRTGPU_BLOB_FLAG_USE_SHAREABLE 0x0002virtgpu_initDRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5')STA_UNSYNC 0x0040backend_virtgpuTIME_UTC 1AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4')DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5')DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0)AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7offsetsBO_USE_GPU_HW (BO_USE_RENDERING | BO_USE_TEXTURE | BO_USE_GPU_DATA_BUFFER)PTHREAD_ONCE_INIT 0VIRTGPU_PARAM_CREATE_GUEST_HANDLE 8AMD_FMT_MOD_TILE_VER_GFX9 1VIRTGPU_PARAM_CAPSET_QUERY_FIX 2DRM_IOCTL_VIRTGPU_EXECBUFFER DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER, struct drm_virtgpu_execbuffer)DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2')DRM_FORMAT_MOD_VENDOR_AMD 0x02CLONE_SETTLS 0x00080000CPU_ALLOC(count) __CPU_ALLOC (count)BO_QUIRK_DUMB32BPP (1ull << 0)__pthread_internal_list__prevDRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0')DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5)AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21BO_USE_LINEAR (1ull << 4)refcountis_test_bufferdrv_log_levelCLOCK_MONOTONIC_COARSE 6AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1SCHED_OTHER 0VIRTGPU_EXECBUF_FENCE_FD_OUT 0x02DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5')sizesPTHREAD_CREATE_JOINABLE PTHREAD_CREATE_JOINABLE__fourcc_mod_amlogic_layout_mask 0xffDRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2')BO_USE_SW_WRITE_OFTEN (1ull << 11)AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0)AMD_FMT_MOD_DCC_SHIFT 13DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0')DRV_MAX_PLANES 4AMD_FMT_MOD fourcc_mod_code(AMD, 0)__timezoneDRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8')BO_USE_SW_READ_OFTEN (1ull << 9)BO_USE_HW_VIDEO_ENCODER (1ull << 14)CPU_SET_S(cpu,setsize,cpusetp) __CPU_SET_S (cpu, setsize, cpusetp)DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1')PTHREAD_CREATE_DETACHED PTHREAD_CREATE_DETACHEDAFRC_FORMAT_MOD_CU_SIZE_P12(__afrc_cu_size) ((__afrc_cu_size) << 4)CLOCK_BOOTTIME_ALARM 9BO_USE_CURSOR_64X64 BO_USE_CURSORDRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0')MOD_CLKB ADJ_TICKDRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) fourcc_mod_broadcom_code(4, v)pthread_cleanup_push(routine,arg) do { __pthread_unwind_buf_t __cancel_buf; void (*__cancel_routine) (void *) = (routine); void *__cancel_arg = (arg); int __not_first_call = __sigsetjmp ((struct __jmp_buf_tag *) (void *) __cancel_buf.__cancel_jmp_buf, 0); if (__glibc_unlikely (__not_first_call)) { __cancel_routine (__cancel_arg); __pthread_unwind_next (&__cancel_buf); } __pthread_register_cancel (&__cancel_buf); do {DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V')drv_import_fd_dataCLONE_PTRACE 0x00002000PTHREAD_PROCESS_PRIVATE PTHREAD_PROCESS_PRIVATEVIRTGPU_WAIT_NOWAIT 1BO_USE_TEXTURE (1ull << 5)VIRTGPU_PARAM_3D_FEATURES 1DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V')CPU_ZERO(cpusetp) __CPU_ZERO_S (sizeof (cpu_set_t), cpusetp)__nextDRM_IOCTL_VIRTGPU_RESOURCE_CREATE_BLOB DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE_BLOB, struct drm_virtgpu_resource_create_blob)AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8)AFBC_FORMAT_MOD_DB (1ULL << 10)DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H')AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17PTHREAD_RECURSIVE_MUTEX_INITIALIZER_NP { { 0, 0, 0, 0, PTHREAD_MUTEX_RECURSIVE_NP, __PTHREAD_SPINS, { 0, 0 } } }AMD_FMT_MOD_PIPE_MASK 0x7ADJ_TIMECONST 0x0020metaDRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2')BO_USE_CAMERA_WRITE (1ull << 6)DRM_VIRTGPU_EXECBUFFER 0x02CLOCK_MONOTONIC 1DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ')_BITS_CPU_SET_H 1DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2')VIRTGPU_RESOURCE_INFO_TYPE_EXTENDED 1AMD_FMT_MOD_GET(field,value) (((value) >> AMD_FMT_MOD_ ##field ##_SHIFT) & AMD_FMT_MOD_ ##field ##_MASK)VIRTGPU_PARAM_CROSS_DEVICE 5DRM_IOCTL_VIRTGPU_RESOURCE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE, struct drm_virtgpu_resource_create)PTHREAD_SCOPE_SYSTEM PTHREAD_SCOPE_SYSTEMDRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')MOD_OFFSET ADJ_OFFSETSTA_PLL 0x0001PTHREAD_CANCEL_DEFERRED PTHREAD_CANCEL_DEFERREDVIRTGPU_BLOB_MEM_HOST3D 0x0002DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6')I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)memory_idx__cleanup_fct_attribute _drv_log(level,format,...) do { drv_log_prefix(level, "minigbm", __FILE__, __LINE__, format, ##__VA_ARGS__); } while (0)DRM_FORMAT_RESERVED ((1ULL << 56) - 1)LINEAR_METADATA (struct format_metadata) { 1, 0, DRM_FORMAT_MOD_LINEAR }AFBC_FORMAT_MOD_TILED (1ULL << 8)DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')pthread_cleanup_pop(execute) do { } while (0); } while (0); __pthread_unregister_cancel (&__cancel_buf); if (execute) __cancel_routine (__cancel_arg); } while (0)IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD)DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2')I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)STA_PPSJITTER 0x0200PTHREAD_PROCESS_SHARED PTHREAD_PROCESS_SHAREDCPU_XOR_S(setsize,destset,srcset1,srcset2) __CPU_OP_S (setsize, destset, srcset1, srcset2, ^)DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H')ADJ_STATUS 0x0010DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4')STA_PPSFREQ 0x0002I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7BO_USE_NONE 0VIRTGPU_DRM_H drv_log_prefixAFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL)DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2')DRM_FORMAT_MOD_ARM_AFRC(__afrc_mode) DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFRC, __afrc_mode)MOD_TIMECONST ADJ_TIMECONSTAMD_FMT_MOD_DCC_MASK 0x1CPU_OR(destset,srcset1,srcset2) __CPU_OP_S (sizeof (cpu_set_t), destset, srcset1, srcset2, |)map_flagsDRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6')I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)AFBC_FORMAT_MOD_SC (1ULL << 9)BO_USE_ARC_SCREEN_CAP_PROBED (1ull << 63)__CPU_OP_S(setsize,destset,srcset1,srcset2,op) (__extension__ ({ cpu_set_t *__dest = (destset); const __cpu_mask *__arr1 = (srcset1)->__bits; const __cpu_mask *__arr2 = (srcset2)->__bits; size_t __imax = (setsize) / sizeof (__cpu_mask); size_t __i; for (__i = 0; __i < __imax; ++__i) ((__cpu_mask *) __dest->__bits)[__i] = __arr1[__i] op __arr2[__i]; __dest; }))BO_USE_SENSOR_DIRECT_DATA (1ull << 19)getdate_errAMD_FMT_MOD_TILE_VERSION_SHIFT 0DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4)__CPU_EQUAL_S(setsize,cpusetp1,cpusetp2) (__builtin_memcmp (cpusetp1, cpusetp2, setsize) == 0)ADJ_OFFSET_SINGLESHOT 0x8001CPU_AND(destset,srcset1,srcset2) __CPU_OP_S (sizeof (cpu_set_t), destset, srcset1, srcset2, &)DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0')BO_USE_SW_READ_RARELY (1ull << 10)BO_MAP_WRITE (1 << 1)CPU_ALLOC_SIZE(count) __CPU_ALLOC_SIZE (count)AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3SCHED_IDLE 5AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1BO_USE_PROTECTED (1ull << 8)__fourcc_mod_broadcom_param_bits 48SCHED_RESET_ON_FORK 0x40000000STA_PPSSIGNAL 0x0100CSIGNAL 0x000000ffDRM_FORMAT_YVU420_ANDROID fourcc_code('9', '9', '9', '7')fourcc_mod_broadcom_param(m) ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0')AFRC_FORMAT_MOD_CU_SIZE_MASK 0xfAMD_FMT_MOD_PACKERS_MASK 0x7DRM_VIRTGPU_TRANSFER_TO_HOST 0x07DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2')virtgpu_paramDRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0')BO_USE_RENDERING (1ull << 2)STA_FLL 0x0008map_infoAFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)__fourcc_mod_amlogic_options_shift 8BO_USE_RENDER_MASK (BO_USE_LINEAR | BO_USE_RENDERING | BO_USE_RENDERSCRIPT | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN | BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY | BO_USE_TEXTURE | BO_USE_FRONT_RENDERING)DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6')DRM_IOCTL_VIRTGPU_RESOURCE_INFO_CROS DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, struct drm_virtgpu_resource_info_cros)MOD_MAXERROR ADJ_MAXERROR__spins__nusersDRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) fourcc_mod_broadcom_code(2, v)CLOCK_THREAD_CPUTIME_ID 3AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15__itimerspec_defined 1STA_INS 0x0010SCHED_BATCH 3drmIoctlDRM_VIRTGPU_CONTEXT_INIT 0x0bBO_USE_FRONT_RENDERING (1ull << 16)DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9')DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)DRM_IOCTL_VIRTGPU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM, struct drm_virtgpu_getparam)CLONE_NEWCGROUP 0x02000000DRM_VIRTGPU_RESOURCE_INFO 0x05DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H')CLONE_IO 0x80000000DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6')DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2')CLOCK_REALTIME 0STA_PPSWANDER 0x0400_BITS_SETJMP_H 1VIRTGPU_BLOB_FLAG_USE_MAPPABLE 0x0001CPU_COUNT_S(setsize,cpusetp) __CPU_COUNT_S (setsize, cpusetp)DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL)I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)CPU_FREE(cpuset) __CPU_FREE (cpuset)CLONE_FILES 0x00000400PTHREAD_INHERIT_SCHED PTHREAD_INHERIT_SCHEDDRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST, struct drm_virtgpu_3d_transfer_from_host)MOD_FREQUENCY ADJ_FREQUENCYDRV_H_ DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5')DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ')VIRTGPU_BLOB_FLAG_CREATE_GUEST_HANDLE 0x0008MOD_CLKA ADJ_OFFSET_SINGLESHOTDRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1')DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST, struct drm_virtgpu_3d_transfer_to_host)VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK 0x0003DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2')DRM_IOCTL_VIRTGPU_MAP DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0')VIRTGPU_EXECBUF_FENCE_FD_IN 0x01DRM_FORMAT_BIG_ENDIAN (1U<<31)DRM_FORMAT_MOD_BROADCOM_SAND128 DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0)__int32_tDRM_VIRTGPU_RESOURCE_CREATE_BLOB 0x0aCLONE_UNTRACED 0x00800000__daylightDRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4')fourcc_mod_broadcom_mod(m) ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << __fourcc_mod_broadcom_param_shift))CPU_COUNT(cpusetp) __CPU_COUNT_S (sizeof (cpu_set_t), cpusetp)SCHED_DEADLINE 6AMD_FMT_MOD_RB_MASK 0x7CPU_OR_S(setsize,destset,srcset1,srcset2) __CPU_OP_S (setsize, destset, srcset1, srcset2, |)_BITS_SCHED_H 1CLOCK_PROCESS_CPUTIME_ID 2DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0')SCHED_ISO 4MOD_ESTERROR ADJ_ESTERRORDRM_VIRTGPU_TRANSFER_FROM_HOST 0x06DRM_FORMAT_MOD_ARM_TYPE_AFRC 0x02ADJ_SETOFFSET 0x0100STA_NANO 0x2000AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL)CLONE_VM 0x00000100__CPUELT(cpu) ((cpu) / __NCPUBITS)DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1)DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c,s,g,k,h) fourcc_mod_code(NVIDIA, (0x10 | ((h) & 0xf) | (((k) & 0xff) << 12) | (((g) & 0x3) << 20) | (((s) & 0x1) << 22) | (((c) & 0x7) << 23)))ADJ_FREQUENCY 0x0002pthread_cleanup_push_defer_np(routine,arg) do { __pthread_unwind_buf_t __cancel_buf; void (*__cancel_routine) (void *) = (routine); void *__cancel_arg = (arg); int __not_first_call = __sigsetjmp ((struct __jmp_buf_tag *) (void *) __cancel_buf.__cancel_jmp_buf, 0); if (__glibc_unlikely (__not_first_call)) { __cancel_routine (__cancel_arg); __pthread_unwind_next (&__cancel_buf); } __pthread_register_cancel_defer (&__cancel_buf); do {lengthDRM_VIRTGPU_MAP 0x01DRM_FORMAT_MOD_VENDOR_INTEL 0x01DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILEAMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16AMD_FMT_MOD_DCC_BLOCK_64B 0__listSTA_RONLY (STA_PPSSIGNAL | STA_PPSJITTER | STA_PPSWANDER | STA_PPSERROR | STA_CLOCKERR | STA_NANO | STA_MODE | STA_CLK)AFBC_FORMAT_MOD_SPLIT (1ULL << 5)PTHREAD_SCOPE_PROCESS PTHREAD_SCOPE_PROCESSCLONE_CHILD_SETTID 0x01000000DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2')AMD_FMT_MOD_TILE_GFX9_64K_R_X 27BO_QUIRK_NONE 0CLONE_THREAD 0x00010000DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4')DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0')VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H')I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)AMD_FMT_MOD_TILE_GFX9_64K_D_X 26AFRC_FORMAT_MOD_CU_SIZE_P0(__afrc_cu_size) (__afrc_cu_size)ADJ_MICRO 0x1000DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1')PTHREAD_ERRORCHECK_MUTEX_INITIALIZER_NP { { 0, 0, 0, 0, PTHREAD_MUTEX_ERRORCHECK_NP, __PTHREAD_SPINS, { 0, 0 } } }CLONE_CHILD_CLEARTID 0x00200000DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4')_BITS_TIME_H 1pthread_cleanup_pop_restore_np(execute) do { } while (0); } while (0); __pthread_unregister_cancel_restore (&__cancel_buf); if (execute) __cancel_routine (__cancel_arg); } while (0)AFBC_FORMAT_MOD_CBR (1ULL << 7)physical_device_idxSTA_MODE 0x4000SCHED_FIFO 1__CPU_ALLOC(count) __sched_cpualloc (count)ADJ_OFFSET 0x0001__CPU_FREE(cpuset) __sched_cpufree (cpuset)virtgpu_backendsAMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0aDRM_VIRTGPU_RESOURCE_CREATE 0x04map_strides__CPU_COUNT_S(setsize,cpusetp) __sched_cpucount (setsize, cpusetp)DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3)DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6')DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2')__CPU_ISSET_S(cpu,setsize,cpusetp) (__extension__ ({ size_t __cpu = (cpu); __cpu / 8 < (setsize) ? ((((const __cpu_mask *) ((cpusetp)->__bits))[__CPUELT (__cpu)] & __CPUMASK (__cpu))) != 0 : 0; }))CLONE_FS 0x00000200AMD_FMT_MOD_PIPE_SHIFT 33DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5')AMD_FMT_MOD_DCC_BLOCK_256B 2STA_PPSERROR 0x0800DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4')DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8')DRM_FORMAT_MOD_AMLOGIC_FBC(__layout,__options) fourcc_mod_code(AMLOGIC, ((__layout) & __fourcc_mod_amlogic_layout_mask) | (((__options) & __fourcc_mod_amlogic_options_mask) << __fourcc_mod_amlogic_options_shift))DRM_VIRTGPU_WAIT 0x08DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED fourcc_code('9', '9', '9', '8')PTHREAD_RWLOCK_INITIALIZER { { 0, 0, 0, 0, 0, 0, 0, 0, __PTHREAD_RWLOCK_ELISION_EXTRA, 0, 0 } }I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9)DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9')AMD_FMT_MOD_TILE_GFX9_64K_S_X 25DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2')VIRTGPU_PARAM_GUEST_VRAM 10AMD_FMT_MOD_CLEAR(field) (~((uint64_t)AMD_FMT_MOD_ ##field ##_MASK << AMD_FMT_MOD_ ##field ##_SHIFT))DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0')DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4')AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xfDRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6')DRM_FORMAT_MOD_VENDOR_ARM 0x08PTHREAD_BARRIER_SERIAL_THREAD -1PTHREAD_RWLOCK_WRITER_NONRECURSIVE_INITIALIZER_NP { { 0, 0, 0, 0, 0, 0, 0, 0, __PTHREAD_RWLOCK_ELISION_EXTRA, 0, PTHREAD_RWLOCK_PREFER_WRITER_NONRECURSIVE_NP } }AMD_FMT_MOD_PACKERS_SHIFT 27DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ')CPU_ZERO_S(setsize,cpusetp) __CPU_ZERO_S (setsize, cpusetp)DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4')BO_USE_TEST_ALLOC (1ull << 15)DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5')DRM_FORMAT_INVALID 0DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')BO_MAP_READ_WRITE (BO_MAP_READ | BO_MAP_WRITE)DRM_VIRTGPU_GET_CAPS 0x09DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y')AMD_FMT_MOD_DCC_RETILE_MASK 0x1DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y')DRM_FORMAT_MOD_VENDOR_NONE 0DRM_IOCTL_VIRTGPU_CONTEXT_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_CONTEXT_INIT, struct drm_virtgpu_context_init)BO_USE_SW_WRITE_RARELY (1ull << 12)DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6')DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2')DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07combosVIRTGPU_BLOB_MEM_HOST3D_GUEST 0x0003__CPU_ALLOC_SIZE(count) ((((count) + __NCPUBITS - 1) / __NCPUBITS) * sizeof (__cpu_mask))DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2')DRM_IOCTL_VIRTGPU_GET_CAPS DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, struct drm_virtgpu_get_caps)VIRTGPU_BLOB_FLAG_CREATE_GUEST_CONTIG 0x0010CPU_SET(cpu,cpusetp) __CPU_SET_S (cpu, sizeof (cpu_set_t), cpusetp)BO_USE_SW_MASK (BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN | BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY | BO_USE_FRONT_RENDERING)BO_MAP_READ (1 << 0)CLONE_NEWUSER 0x10000000DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) fourcc_mod_broadcom_code(5, v)DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')__CPUMASK(cpu) ((__cpu_mask) 1 << ((cpu) % __NCPUBITS))CLONE_PARENT_SETTID 0x00100000DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U')__fourcc_mod_broadcom_param_shift 8drv_arrayMOD_NANO ADJ_NANOBO_USE_RENDERSCRIPT (1ull << 17)plane_widthMCL_CURRENT 1MAP_HUGETLB 0x40000MAP_DENYWRITE 0x00800MREMAP_FIXED 2MAP_TYPE 0x0fMCL_ONFAULT 4drv_num_planes_from_formatPROT_EXEC 0x4MADV_DOFORK 11POSIX_MADV_SEQUENTIAL 2drv_modify_linear_combinationsMADV_DODUMP 17POSIX_MADV_WILLNEED 3MADV_KEEPONFORK 19drv_vertical_subsampling_from_formatout_formatdrv_height_from_formatMS_SYNC 4drv_num_planes_from_modifierdrv_add_combinationdrm_mode_create_dumbMADV_DONTDUMP 16PROT_GROWSUP 0x02000000drm_prime_handledrv_dumb_bo_create_exmmap64out_use_flagsPKEY_DISABLE_ACCESS 0x1MLOCK_ONFAULT 1Ustatic_assertMADV_DONTFORK 10MAP_32BIT 0x40MADV_FREE 8PROT_NONE 0x0MADV_MERGEABLE 12PROT_READ 0x1MCL_FUTURE 2drv_gem_bo_destroybiplanar_yuv_p010_layoutdrv_add_combinationsMAP_HUGE_SHIFT 26packed_3bpp_layoutMAP_PRIVATE 0x02assert_perror(errnum) (!(errnum) ? __ASSERT_VOID_CAST (0) : __assert_perror_fail ((errnum), __FILE__, __LINE__, __ASSERT_FUNCTION))MAP_GROWSDOWN 0x00100MAP_STACK 0x20000PAGE_SIZE 0x1000drv_pick_modifierMAP_FIXED 0x10drv_array_at_idxMAP_NORESERVE 0x04000drv_has_modifierdrv_size_from_formatnum_formatsMAP_SHARED_VALIDATE 0x03quirksMADV_REMOVE 9__s32drv_dumb_bo_createMAP_ANON MAP_ANONYMOUSdrm_gem_closedrv_bo_from_formatdrv_stride_from_formatMADV_HWPOISON 100pitchMAP_FAILED ((void *) -1)MAP_FILE 0DRV_ARRAY_HELPERS_H MAP_FIXED_NOREPLACE 0x100000POSIX_MADV_RANDOM 1MADV_HUGEPAGE 14biplanar_yuv_420_layout__assert_failMAP_HUGE_MASK 0x3fsubsample_strideassert(expr) ((expr) ? __ASSERT_VOID_CAST (0) : __assert_fail (#expr, __FILE__, __LINE__, __ASSERT_FUNCTION))MS_ASYNC 1_ASSERT_H_DECLS PKEY_DISABLE_WRITE 0x2drv_array_appendstatic_assert _Static_assertdrv_prime_bo_importdrm_mode_destroy_dumbcomboMAP_SYNC 0x80000stride_alignMAP_POPULATE 0x08000drv_bo_munmapdrm_mode_map_dumbhorizontal_subsamplingdrv_resolve_format_and_use_flags_helperDRV_HELPERS_H MAP_EXECUTABLE 0x01000aligned_widthMS_INVALIDATE 2MREMAP_MAYMOVE 1/source/platform/minigbm/drv_helpers.cMFD_CLOEXEC 1UMFD_ALLOW_SEALING 2UMADV_UNMERGEABLE 13bytes_per_pixelpacked_4bpp_layoutPOSIX_MADV_DONTNEED 4drv_array_size_ASSERT_H 1MAP_NONBLOCK 0x10000planar_layoutPROT_WRITE 0x2drv_dumb_bo_destroydrv_modify_combinationaligned_heightMADV_NOHUGEPAGE 15triplanar_yuv_420_layoutMADV_WIPEONFORK 18drv_get_protdrv_dumb_bo_mapMFD_HUGETLB 4Upacked_2bpp_layout__ASSERT_VOID_CAST (void)drv_bytes_per_pixel_from_formatlayout_from_formatMAP_ANONYMOUS 0x20vertical_subsampling__ASSERT_FUNCTION __extension__ __PRETTY_FUNCTION__MAP_SHARED 0x01POSIX_MADV_NORMAL 0format_metadatadrv_bo_from_format_and_paddingpacked_1bpp_layoutorder_countMAP_LOCKED 0x02000_SYS_MMAN_H 1PROT_GROWSDOWN 0x01000000packed_8bpp_layout/source/platform/minigbm/dri.cdrv_dataGBM_BO_FORMAT_ARGB8888drv_bo_mapgbm_format_canonicalizegbm_bo_mapdrv_bo_get_widthgbm_bo_newgbm_surface_has_free_buffersdrv_bo_get_plane_stridecallocGBM_BO_TRANSFER_READ_WRITEGBM_BO_USE_SENSOR_DIRECT_DATAdrv_get_combinationgbm_surface_create_with_modifiersdrv_bo_get_plane_handlegbm_bo_get_stride_for_planeGBM_BO_USE_PROTECTEDgbm_format_name_descgbm_bo_unmapgbm_device_destroydrv_bo_importgbm_bo_createGBM_BO_USE_CAMERA_READgbm_surface_destroyGBM_BO_USE_GPU_DATA_BUFFERgbm_surface_release_buffermap_dataGBM_BO_USE_FRONT_RENDERINGgbm_bo_get_plane_sizeGBM_BO_USE_SW_READ_RARELYGBM_BO_USE_LINEARdrv_bo_creategbm_bo_get_offsetGBM_BO_FORMAT_XRGB8888GBM_BO_TRANSFER_WRITEgbm_convert_usageGBM_BO_USE_HW_VIDEO_ENCODERGBM_BO_USE_TEXTURINGgbm_bo_get_devicegbm_bo_set_user_datagbm_bo_transfer_flagsGBM_BO_USE_SW_READ_OFTENGBM_BO_USE_CURSORGBM_PRIV_H gbm_formatgbm_bo_flagsGBM_BO_USE_WRITEdrv_creategbm_bo_get_user_datagbm_bo_get_plane_countgbm_bo_destroyGBM_BO_USE_SW_WRITE_RARELYgbm_bo_get_widthgbm_bo_get_handleGBM_BO_USE_CAMERA_WRITEnum_fdsgbm_bo_map2drv_get_fddrv_bo_get_formatgbm_bo_get_formatgbm_bo_get_fd_for_plane/source/platform/minigbm/gbm.cgbm_device_get_format_modifier_plane_countdrv_bo_get_heightgbm_bo_importgbm_bo_get_heightgbm_device_get_fdGBM_BO_USE_SW_WRITE_OFTENgbm_bo_get_handle_for_planedrv_bo_get_num_planesGBM_BO_USE_CURSOR_64X64GBM_BO_TRANSFER_READGBM_TEST_ALLOCdrv_bo_get_plane_fdGBM_HELPERS_H GBM_BO_USE_SCANOUTdrv_bo_get_format_modifiergbm_bo_handlegbm_surface_createdestroy_user_datamallocgbm_bo_formatgbm_surfacegbm_bo_get_bppdrv_bo_get_plane_sizedrv_bo_flush_or_unmapgbm_bo_get_stridegbm_bodrv_destroygbm_device_get_backend_nameGBM_BO_USE_RENDERINGgbm_bo_get_modifiergbm_import_fd_modifier_datagbm_import_fd_datadrv_bo_destroygbm_format_get_namegbm_surface_lock_front_bufferdrv_bo_get_plane_offsetgbm_bo_create_with_modifiersgbm_bo_get_plane_fdgbm_device_is_format_supportedgbm_bo_get_fddrv_get_namedrv_bo_create_with_modifiersGBM_BO_USE_HW_VIDEO_DECODERrender_target_formatsDRM_VC4_GET_HANG_STATE 0x06VC4_MADV_WILLNEED 0DRM_VC4_PERFMON_DESTROY 0x0dDRM_VC4_PARAM_SUPPORTS_MADVISE 7vc4_bo_create_for_modifierVC4_SUBMIT_CL_RCL_ORDER_INCREASING_X (1 << 2)drm_vc4_mmap_boDRM_VC4_PARAM_SUPPORTS_ETC1 4VC4_MADV_DONTNEED 1VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0)DRM_IOCTL_VC4_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo)DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state)DRM_VC4_CREATE_BO 0x03DRM_VC4_WAIT_SEQNO 0x01__VC4_MADV_PURGED 2VC4_SUBMIT_CL_FIXED_RCL_ORDER (1 << 1)vc4_initDRM_VC4_MAX_PERF_COUNTERS 16DRM_VC4_CREATE_SHADER_BO 0x05DRM_IOCTL_VC4_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GEM_MADVISE, struct drm_vc4_gem_madvise)DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo)DRM_VC4_GEM_MADVISE 0x0bDRM_IOCTL_VC4_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_GET_VALUES, struct drm_vc4_perfmon_get_values)DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)DRM_VC4_SUBMIT_CL 0x00DRM_VC4_SET_TILING 0x08DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling)/source/platform/minigbm/vc4.cDRM_VC4_PARAM_SUPPORTS_BRANCHES 3DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param)DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling)DRM_VC4_WAIT_BO 0x02DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo)backend_vc4DRM_VC4_LABEL_BO 0x0aDRM_VC4_PARAM_V3D_IDENT0 0VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0)DRM_IOCTL_VC4_PERFMON_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_DESTROY, struct drm_vc4_perfmon_destroy)DRM_VC4_PERFMON_GET_VALUES 0x0eDRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo)vc4_bo_create_with_modifiers__VC4_MADV_NOTSUPP 3vc4_bo_createDRM_VC4_PARAM_V3D_IDENT1 1vc4_bo_mapDRM_VC4_MMAP_BO 0x04drm_vc4_create_boDRM_VC4_GET_TILING 0x09DRM_IOCTL_VC4_PERFMON_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_CREATE, struct drm_vc4_perfmon_create)texture_only_formatsDRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER 6DRM_VC4_PERFMON_CREATE 0x0cDRM_VC4_PARAM_SUPPORTS_PERFMON 8DRM_VC4_GET_PARAM 0x07DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo)DRM_VC4_PARAM_V3D_IDENT2 2_VC4_DRM_H_ DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y (1 << 3)I915_BIT_6_SWIZZLE_9_11 3I915_EXEC_BSD_SHIFT (13)I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)DRM_I915_FREE 0x09I915_CONTEXT_PARAM_RECOVERABLE 0x8I915_RESET_UEVENT "RESET"DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)I915_EXEC_BLT (3<<0)I915_OVERLAY_FLAGS_MASK 0xff000000I915_PMU_SAMPLE_INSTANCE_BITS (8)DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)scanout_and_renderDRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)i915_bo_create_from_metadataI915_EXEC_RING_MASK (0x3f)planeB_w pipeB_wI915_LOG_MIN_TEX_REGION_SIZE 14I915_EXEC_FENCE_OUT (1<<17)read_domainsI915_EXEC_FENCE_ARRAY (1<<19)I915_PARAM_HAS_BSD 10EXEC_OBJECT_NEEDS_GTT (1<<1)planeA_h pipeA_hdrm_i915_getparamDRM_I915_GEM_ENTERVT 0x19I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4I915_PARAM_SUBSLICE_TOTAL 33I915_GEM_PPGTT_ALIASING 1I915_PERF_IOCTL_ENABLE _IO('i', 0x0)I915_EXEC_CONSTANTS_REL_SURFACE (2<<6)I915_CACHING_CACHED 1write_domainI915_PMU_SAMPLE_MASK (0xf)gem_handledrm_i915_gem_set_tilingI915_PARAM_HAS_EXEC_ASYNC 43has_hw_protectionI915_GEM_PPGTT_NONE 0mtl_idsDRM_I915_QUERY_PERF_CONFIG_LIST 1I915_PARAM_HAS_SCHEDULER 41I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT)DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)I915_CACHELINE_MASK (I915_CACHELINE_SIZE - 1)__EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1)I915_PMU_ENGINE_SEMA(class,instance) __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)DRM_I915_SETPARAM 0x07I915_TILING_4 9DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE_EXT, struct drm_i915_gem_create_ext)DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0)DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)I915_GEM_DOMAIN_WC 0x00000080DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)I915_PARAM_HAS_GPU_RESET 35EXEC_OBJECT_ASYNC (1<<6)DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)I915_EXEC_VEBOX (4<<0)DRM_I915_GEM_BUSY 0x17i915_bo_mapDRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)gen8_idsI915_GEM_DOMAIN_COMMAND 0x00000008metadata_4_tiledDRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)I915_DEFINE_CONTEXT_ENGINES_BOND(name__,N__) struct { struct i915_user_extension base; struct i915_engine_class_instance master; __u16 virtual_index; __u16 num_bonds; __u64 flags; __u64 mbz64[4]; struct i915_engine_class_instance engines[N__]; } __attribute__((packed)) name__I915_CONTEXT_CLONE_ENGINES (1u << 0)DRM_I915_GEM_PREAD 0x1cDRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)I915_CONTEXT_PARAM_BAN_PERIOD 0x1EXEC_OBJECT_NEEDS_FENCE (1<<0)DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)I915_CONTEXT_CLONE_TIMELINE (1u << 4)i915_execbuffer2_get_context_id(eb2) ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)I915_OVERLAY_YUV410 0x0400I915_EXEC_FENCE_IN (1<<16)__I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x))DRM_I915_GEM_SET_TILING 0x21DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)i915_align_dimensionsDRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT)DRM_I915_GET_SPRITE_COLORKEY 0x2aDRM_I915_QUERY_ENGINE_INFO 2I915_REG_READ_8B_WA (1ul << 0)DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2)DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)DRM_I915_CMDBUFFER 0x0bI915_PARAM_HAS_RESOURCE_STREAMER 36DRM_I915_HWS_ADDR 0x11DRM_I915_GEM_GET_APERTURE 0x23i915_num_planes_from_modifierDRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)I915_CONTEXT_PARAM_SSEU 0x7gen_modifier_orderI915_OVERLAY_TYPE_MASK 0xffDRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3rplp_idsI915_OVERLAY_SWAP_MASK 0xff0000I915_OVERLAY_NO_SWAP 0x000000DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25I915_BIT_6_SWIZZLE_9_10_11 4I915_PARAM_HAS_COHERENT_RINGS 13I915_CONTEXT_CLONE_FLAGS (1u << 1)tiling_modeDRM_I915_BATCHBUFFER 0x03I915_PARAM_SUBSLICE_MASK 47metadata_y_tiledI915_BOX_TEXTURE_LOAD 0x8I915_OVERLAY_RGB15 0x3000EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)I915_CONTEXT_CLONE_UNKNOWN -(I915_CONTEXT_CLONE_VM << 1)EXEC_OBJECT_PINNED (1<<4)DRM_I915_GEM_CONTEXT_DESTROY 0x2eI915_PMU_ENGINE_WAIT(class,instance) __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT)DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)drm_i915_getparam_tDRM_I915_GEM_CONTEXT_CREATE 0x2dI915_PARAM_HAS_SEMAPHORES 20DRM_I915_GEM_CREATE_EXT 0x3cI915_PERF_FLAG_FD_NONBLOCK (1<<1)I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1)I915_PMU_ENGINE_BUSY(class,instance) __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY)I915_SETPARAM_USE_MI_BATCHBUFFER_START 1I915_BIT_6_SWIZZLE_9_17 6I915_MADV_DONTNEED 1I915_PARAM_HAS_COHERENT_PHYS_GTT 29I915_PARAM_REVISION 32i915_bo_compute_metadataDRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)DRM_I915_OVERLAY_PUT_IMAGE 0x27drm_i915_gem_set_domainDRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)I915_EXEC_CONSTANTS_REL_GENERAL (0<<6)DRM_I915_GEM_VM_CREATE 0x3aDRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)I915_EXEC_BATCH_FIRST (1<<18)I915_PARAM_HAS_PAGEFLIPPING 8I915_GEM_DOMAIN_CPU 0x00000001I915_PARAM_HAS_ALIASING_PPGTT 18I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)I915_EXEC_BSD (2<<0)I915_ENGINE_CLASS_INVALID_VIRTUAL -2I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1)I915_PARAM_HAS_GEN7_SOL_RESET 16I915_OVERLAY_RGB24 0x1000ccs_sizeDRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)DRM_I915_SET_SPRITE_COLORKEY 0x2bi915_add_combinationsscanout_render_formatsccs_height_in_tilesI915_PARAM_HAS_SECURE_BATCHES 23metadata_linearI915_EXEC_SECURE (1<<9)DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)addr_ptrDRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)DRM_I915_GEM_THROTTLE 0x18I915_CONTEXT_ENGINES_EXT_BOND 1DRM_I915_GEM_INIT 0x13DRM_I915_GEM_UNPIN 0x16has_llcI915_PARAM_NUM_FENCES_AVAIL 6I915_PARAM_HAS_LLC 17I915_PARAM_ALLOW_BATCHBUFFER 2gen3_idsI915_OVERLAY_ENABLE 0x01000000I915_PMU_CLASS_SHIFT (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS)DRM_I915_INIT 0x00DRM_I915_GEM_MADVISE 0x26I915_CONTEXT_CREATE_EXT_SETPARAM 0DRM_I915_GEM_GET_CACHING 0x30DRM_I915_GEM_SET_CACHING 0x2fI915_TILING_Y 2drm_i915_gem_create_extI915_CONTEXT_PARAM_BANNABLE 0x5i915_get_modifier_orderI915_CONTEXT_CLONE_SCHEDATTR (1u << 2)i915_user_extensionDRM_I915_GEM_USERPTR 0x33gem_mapDRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)I915_PARAM_HAS_VEBOX 22DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)planeA_w pipeA_wI915_BOX_RING_EMPTY 0x1DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)planeB_x pipeB_xDRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)I915_GEM_DOMAIN_RENDER 0x00000002DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)scanout_and_render_not_linearDRM_I915_GEM_CONTEXT_SETPARAM 0x35I915_OVERLAY_DEPTH_MASK 0xff00num_fences_availDRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)I915_OVERLAY_UPDATE_ATTRS (1<<0)I915_OVERLAY_YUV_PLANAR 0x01I915_CONTEXT_PARAM_ENGINES 0xadrm_i915_gem_mmap_gttdrm_i915_gem_create_ext_protected_contentI915_BIT_6_SWIZZLE_9_10 2DRM_I915_GEM_MMAP_GTT 0x24i915_bo_from_formatI915_PARAM_HAS_RELAXED_FENCING 12I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2)I915_CACHING_DISPLAY 2I915_USERPTR_UNSYNCHRONIZED 0x80000000I915_CONTEXT_MAX_USER_PRIORITY 1023I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0)DRM_I915_GEM_LEAVEVT 0x1aI915_NR_TEX_REGIONS 255I915_PARAM_HAS_BLT 11I915_OVERLAY_UV_SWAP 0x010000I915_PARAM_IRQ_ACTIVE 1I915_OVERLAY_YUV420 0x0300drm_i915_gem_mmap_offsetI915_PARAM_HAS_WT 27DRM_I915_PERF_REMOVE_CONFIG 0x38I915_TILING_NONE 0DRM_I915_PERF_OPEN 0x36I915_OVERLAY_YUV411 0x0200DRM_I915_GET_VBLANK_PIPE 0x0e__I915_MADV_PURGED 2DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)i915_bo_invalidateI915_PARAM_HAS_PINNED_BATCHES 24I915_SETPARAM_ALLOW_BATCHBUFFER 3horizontal_alignment__I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SUBMIT << 1))DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)DRM_I915_GEM_WAIT 0x2cDRM_I915_QUERY_TOPOLOGY_INFO 1DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)I915_BIT_6_SWIZZLE_NONE 0I915_USERPTR_READ_ONLY 0x1I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53DRM_I915_GETPARAM 0x06graphics_versionDRM_I915_GEM_SW_FINISH 0x20I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3)gen4_idsI915_BIT_6_SWIZZLE_9_10_17 7I915_CONTEXT_PARAM_RINGSIZE 0xcI915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT)I915_OVERLAY_Y_SWAP 0x020000phys_swizzle_mode__I915_PMU_ENGINE(class,instance,sample) ((class) << I915_PMU_CLASS_SHIFT | (instance) << I915_PMU_SAMPLE_BITS | (sample))DRM_I915_GEM_VM_DESTROY 0x3bI915_BOX_FLIP 0x2I915_PARAM_HAS_EXEC_CONSTANTS 14DRM_I915_QUERY_PERF_CONFIG 3has_mmap_offsetdrm_i915_gem_mmapI915_EXEC_GEN7_SOL_RESET (1<<8)DRM_I915_OVERLAY_ATTRS 0x28backend_i915DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)I915_MMAP_OFFSET_WB 2I915_PARAM_MIN_EU_IN_POOL 39/source/platform/minigbm/i915.cI915_PARAM_HAS_EXEC_CAPTURE 45I915_PARAM_CHIPSET_ID 4I915_EXEC_CONTEXT_ID_MASK (0xffffffff)I915_PARAM_HAS_RELAXED_DELTA 15I915_PERF_IOCTL_CONFIG _IO('i', 0x2)i915_bo_flushplaneA_x pipeA_xvertical_alignmentI915_MMAP_OFFSET_WC 1adlp_idsI915_MMAP_OFFSET_GTT 0DRM_I915_VBLANK_PIPE_A 1DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)i915_deviceI915_PARAM_PERF_REVISION 54gen11_modifier_orderI915_PARAM_HAS_OVERLAY 7I915_PARAM_HAS_CONTEXT_ISOLATION 50i915_clflushmetadata_x_tiledI915_SET_COLORKEY_NONE (1<<0)DRM_I915_PERF_ADD_CONFIG 0x37I915_MMAP_WC 0x1I915_ERROR_UEVENT "ERROR"I915_PERF_IOCTL_DISABLE _IO('i', 0x1)I915_PARAM_HAS_POOLED_EU 38drm_i915_gem_get_tilingI915_CONTEXT_PARAM_NO_ZEROMAP 0x2I915_PMU_LAST I915_PMU_RC6_RESIDENCYgen11_idsI915_TILING_LAST I915_TILING_4I915_PERF_FLAG_DISABLED (1<<2)DRM_I915_GEM_GET_TILING 0x22I915_PARAM_HAS_BSD2 31I915_PARAM_HAS_EXEC_SOFTPIN 37I915_CACHELINE_SIZE 64I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2DRM_I915_GEM_EXECBUFFER 0x14I915_PARAM_CS_TIMESTAMP_FREQUENCY 51I915_CONTEXT_PARAM_PRIORITY 0x6DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0)I915_GEM_DOMAIN_INSTRUCTION 0x00000010DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"DRM_I915_GET_RESET_STATS 0x32next_extensionDRM_I915_GEM_EXECBUFFER2 0x29i915_info_from_device_idEXEC_OBJECT_WRITE (1<<2)DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)gen5_idsI915_CONTEXT_PARAM_GTT_SIZE 0x3I915_EXEC_FENCE_WAIT (1<<0)xe_lpdp_modifier_orderDRM_I915_GEM_CONTEXT_GETPARAM 0x34I915_BIT_6_SWIZZLE_9 1DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)I915_MEM_REGION_AGP 1is_mtlDRM_I915_VBLANK_PIPE_B 2DRM_I915_GEM_MMAP 0x1eI915_PARAM_CMD_PARSER_VERSION 28is_xelpdDRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)I915_CONTEXT_MIN_USER_PRIORITY -1023I915_PARAM_HUC_STATUS 42I915_SET_COLORKEY_SOURCE (1<<2)I915_EXEC_HANDLE_LUT (1<<12)I915_PERF_FLAG_FD_CLOEXEC (1<<0)I915_GEM_DOMAIN_GTT 0x00000040I915_CONTEXT_CREATE_EXT_CLONE 1I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xfDRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)I915_ENGINE_CLASS_INVALID_NONE -1I915_CONTEXT_CLONE_SSEU (1u << 3)hw_protectedDRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)extensionsI915_PARAM_HAS_GEM 5I915_PARAM_HAS_PRIME_VMAP_FLUSH 21I915_DEFINE_CONTEXT_PARAM_ENGINES(name__,N__) struct { __u64 extensions; struct i915_engine_class_instance engines[N__]; } __attribute__((packed)) name__I915_EXEC_NO_RELOC (1<<11)I915_PARAM_LAST_DISPATCH 3DRM_I915_INIT_HEAP 0x0aI915_PARAM_HAS_EXECBUF2 9DRM_I915_FLIP 0x02I915_MMAP_OFFSET_UC 3I915_GEM_DOMAIN_VERTEX 0x00000020I915_PMU_SAMPLE_BITS (4)i915_execbuffer2_set_context_id(eb2,context) (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASKtexture_onlymodifier_support_tI915_EXEC_IS_PINNED (1<<10)I915_CACHING_NONE 0I915_BOX_WAIT 0x4I915_PARAM_EU_TOTAL 34DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)I915_PARAM_SLICE_MASK 46I915_EXEC_FENCE_SIGNAL (1<<1)I915_EXEC_RESOURCE_STREAMER (1<<15)DRM_I915_SET_VBLANK_PIPE 0x0d_UAPI_I915_DRM_H_ I915_SCHEDULER_CAP_PRIORITY (1ul << 1)I915_PARAM_HAS_EXEC_FENCE 44I915_PARAM_MMAP_GTT_VERSION 40I915_SET_COLORKEY_DESTINATION (1<<1)gen12_idscurrent_flagsDRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)DRM_I915_GEM_SET_DOMAIN 0x1fDRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)p010_usageEXEC_OBJECT_PAD_TO_SIZE (1<<5)I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0)DRM_I915_GEM_PWRITE 0x1dDRM_I915_VBLANK_SWAP 0x0fI915_OVERLAY_YUV_PACKED 0x02DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)DRM_I915_QUERY 0x39DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)I915_PARAM_HAS_WAIT_TIMEOUT 19EXEC_OBJECT_CAPTURE (1<<7)ccs_width_in_tilesI915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1)planeB_y pipeB_ygen12_modifier_ordergen6_idsDRM_I915_ALLOC 0x08I915_MADV_WILLNEED 0I915_CONTEXT_CREATE_FLAGS_UNKNOWN (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1))I915_PARAM_HAS_EXEC_BATCH_FIRST 48I915_TILING_X 1rsvdI915_BIT_6_SWIZZLE_UNKNOWN 5I915_SETPARAM_NUM_USED_FENCES 4I915_SCHEDULER_CAP_ENABLED (1ul << 0)I915_OVERLAY_Y_AND_UV_SWAP 0x030000DRM_I915_GEM_PIN 0x15I915_PARAM_HAS_EXEC_NO_RELOC 25i915_inithuge_boI915_GEM_DOMAIN_SAMPLER 0x00000004DRM_I915_GEM_CREATE 0x1bi915_bo_importunset_flagsI915_SCHEDULER_CAP_PREEMPTION (1ul << 2)DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)I915_OVERLAY_YUV422 0x0100__I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1))DRM_IOCTL_I915_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_offset)drm_i915_gem_createI915_BOX_LOST_CONTEXT 0x10I915_OVERLAY_RGB16 0x2000I915_EXEC_RENDER (1<<0)I915_CONTEXT_CLONE_VM (1u << 5)I915_EXEC_DEFAULT (0<<0)gen9_idsI915_OVERLAY_UPDATE_GAMMA (1<<1)I915_EXEC_FENCE_SUBMIT (1 << 20)i915_format_needs_LCU_alignmentplaneB_h pipeB_hI915_PARAM_MMAP_VERSION 30DRM_I915_REG_READ 0x31I915_GEM_PPGTT_FULL 2DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)I915_CONTEXT_DEFAULT_PRIORITY 0I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT)linear_maskDRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2I915_OVERLAY_RGB 0x03I915_EXEC_CONSTANTS_MASK (3<<6)DRM_I915_IRQ_EMIT 0x04getpagesizeDRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)DRM_I915_DESTROY_HEAP 0x0cI915_CONTEXT_PARAM_VM 0x9DRM_I915_IRQ_WAIT 0x05I915_PARAM_HAS_EXEC_HANDLE_LUT 26DRM_I915_FLUSH 0x01I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(name__,N__) struct { struct i915_user_extension base; __u16 engine_index; __u16 num_siblings; __u32 flags; __u64 mbz64; struct i915_engine_class_instance engines[N__]; } __attribute__((packed)) name__planeA_y pipeA_yI915_PARAM_HAS_EXEC_FENCE_ARRAY 49DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)i915_closeI915_PMU_INTERRUPTS __I915_PMU_OTHER(2)nv12_usageI915_PARAM_MMAP_GTT_COHERENT 52gen7_idsDRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)I915_CONTEXT_PARAM_PERSISTENCE 0xbdrv_bo_get_use_flagsdrv_resource_infobackend_rockchipoverflow_arg_areareg_save_areafree_buffer_table_lockbasenamedrv_array_init__builtin_va_listbackend_vkmsdrv_preloaddrv_bo_get_tiling__va_list_tagdrv_bo_newbackend_synapticsminigbm_debugdrv_get_backendbest/source/platform/minigbm/drv.ccurrbackend_mediatek__gnuc_va_listpthread_mutex_destroyis_test_allocpthread_mutex_lockbackend_nouveaudrmHashCreatedrv_array_destroyfree_driverdrv_bo_releasedrv_bo_acquiredrmHashLookupbackend_mesonexact_matchdrv_bo_get_total_sizedrmHashDestroydrm_versionfiledrmPrimeHandleToFDfree_mappingsstrerrordrv_get_max_texture_2d_sizefree_mappings_lockfp_offsetgp_offsetsuccessvfprintflseekbackend_udlbackend_sun4i_drmdrv_resolve_format_and_use_flagsfourcc_internalfree_buffer_tabledrv_bo_flushbackend_komedadrv_bo_unmapdrv_array_removeseek_enddrv_bo_invalidatebackend_marvelllseek64pthread_mutex_initbackend_evdidrv_get_standard_fourccdrv_bo_mapping_destroygetenvdrv_backend_listpthread_mutex_unlockbackend_radeonpriordrmHashInsertdrmHashDeletestrcmpdestroy_bodrv_num_buffers_per_boVIRGL_FORMAT_R16G16B16A16_FLOATVIRGL_SET_BLEND_COLOR(x) ((x) + 1)atomic_is_lock_free(OBJ) __atomic_is_lock_free (sizeof (*(OBJ)), (OBJ))VIRGL_TRANSFER3D_DIRECTION 13VIRGL_PIPE_RES_CREATE_DEPTH 6VIRGL_FORMAT_L16_FLOATVIRGL_OBJ_SHADER_SO_OUTPUT_STREAM(x) (((x) & 0x03) << 0)VIRGL_SET_UNIFORM_BUFFER_RES_HANDLE 5VIRGL_FORMAT_L16A16_SNORMVIRGL_OBJ_SAMPLER_STATE_BORDER_COLOR(x) ((x) + 6)readVIRGL_FORMAT_R8G8B8A8_UNORMVIRGL_SET_SAMPLER_VIEWS_V0_HANDLE 3cur_blob_idvirgl_context_cmdVIRGL_FORMAT_R16_SNORMtexture_buffer_offset_alignmentVIRGL_FORMAT_R32G32B32A32_FLOATVIRGL_FORMAT_R8G8B8X8_SNORMVIRGL_COPY_TRANSFER3D_SRC_RES_HANDLE 12VIRGL_CAP_COMPUTE_SHADER (1 << 7)VIRGL_SET_VERTEX_BUFFER_STRIDE(x) (((x) * 3) + 1)VIRGL_OBJ_RS_S3_LINE_STIPPLE_PATTERN(x) (((x) & 0xffff) << 0)VIRGL_RENDER_CONDITION_HANDLE 1VIRGL_CMD_RCR_DST_LEVEL 2VIRGL_OBJ_RS_S0_FLATSHADE_FIRST(x) (((x) & 0x1) << 4)VIRGL_CMD_RCR_SRC_LEVEL 7VIRGL_CCMD_CREATE_OBJECTVIRGL_RESOURCE_IW_Z 8min_smooth_line_widthVIRGL_OBJ_RS_OFFSET_SCALE 8VIRGL_DRAW_VBO_START 1VIRGL_OBJ_SAMPLER_VIEW_FORMAT 3VIRGL_DRAW_VBO_INDIRECT_STRIDE 17VIRGL_FORMAT_A4B4G4R4_UNORMVIRGL_FORMAT_R16G16_UINTatomic_flag_test_and_set(PTR) __atomic_test_and_set ((PTR), __ATOMIC_SEQ_CST)VIRGL_OBJ_VERTEX_ELEMENTS_V0_VERTEX_BUFFER_INDEX(x) (((x) * 4) + 4)VIRGL_DRAW_VBO_INDIRECT_DRAW_COUNT_HANDLE 20VIRGL_FORMAT_B4G4R4X4_UNORMVIRGL_DRAW_VBO_COUNT 2VIRGL_OBJ_RS_LINE_WIDTH 6transfer_boxsample_locationsVIRGL_OBJ_RS_S0_OFFSET_POINT(x) (((x) & 0x1) << 19)VIRGL_FORMAT_S8_UINT_Z24_UNORMVIRGL_OBJ_RS_S3_LINE_STIPPLE_FACTOR(x) (((x) & 0xff) << 16)VIRGL_OBJ_RS_S0_BOTTOM_EDGE_RULE(x) (((x) & 0x1) << 30)VIRGL_CCMD_SET_STENCIL_REFVIRGL_FORMAT_L16_SINTVIRGL_FORMAT_A32_UINTmax_smooth_point_sizeMIN(a,b) ((a) < (b) ? (a) : (b))xfer_paramsVIRGL_TEXTURE_ARRAY_C 11max_uniform_blocksVIRGL_OBJ_CLEAR_DEPTH_1 7VIRGL_RESOURCE_IW_STRIDE 4virgl_formatsVIRGL_OBJ_RS_S0_FRONT_CCW(x) (((x) & 0x1) << 15)VIRGL_SET_ATOMIC_BUFFER_LENGTH(x) ((x) * VIRGL_SET_ATOMIC_BUFFER_ELEMENT_SIZE + 3)VIRGL_FORMAT_L32_UINThost_feature_check_versionVIRGL_OBJ_SHADER_SO_STRIDE(x) (6 + (x))VIRGL_OBJ_QUERY_OFFSET 3VIRGL_SET_VIEWPORT_STATE_SCALE_2(x) (4 + (x * 6))max_dual_source_render_targetsVIRGL_FORMAT_L16A16_UINTVIRGL_OBJ_VERTEX_ELEMENTS_V0_SRC_FORMAT(x) (((x) * 4) + 5)VIRGL_CAP_COPY_TRANSFER (1 << 26)max_versioncapability_bitsmin_texture_gather_offsetmax_combined_atomic_countersVIRGL_SET_FRAMEBUFFER_STATE_CBUF_HANDLE(x) ((x) + 3)VIRGL_OBJ_SHADER_NUM_TOKENS 4VIRGL_FORMAT_R8_UNORMVIRGL_FORMAT_R8_SRGBVIRGL_CCMD_SET_UNIFORM_BUFFERVIRGL_RENDER_CONDITION_CONDITION 2atomic_signal_fence(MO) __atomic_signal_fence (MO)VIRGL_CAP_BIND_COMMAND_ARGS (1 << 20)VIRGL_CCMD_CLEARVIRGL_FORMAT_R32G32_UINTdumb_texture_source_formatsVIRGL_FORMAT_A8B8G8R8_UNORMVIRGL_OBJ_SAMPLER_VIEW_BUFFER_FIRST_ELEMENT 4VIRGL_OBJ_BLEND_S2(cbuf) (4 + (cbuf))VIRGL_FORMAT_DXT1_SRGBVIRGL_RESOURCE_IW_DATA_START 12min_texel_offsetVIRGL_OBJ_RS_S3_CLIP_PLANE_ENABLE(x) (((x) & 0xff) << 24)VIRGL_TEXTURE_ARRAY_A 9virgl_bo_invalidateVIRGL_FORMAT_A16_SNORMVIRGL_FORMAT_B8G8R8X8_UNORMVIRGL_FORMAT_A8_UINTvirgl_bo_destroyVIRGL_FORMAT_A8_SNORMVIRGL_OBJ_SURFACE_BUFFER_FIRST_ELEMENT 4atomic_thread_fence(MO) __atomic_thread_fence (MO)VIRGL_BIND_CONSTANT_BUFFER (1 << 6)VIRGL_OBJ_DSA_S0_DEPTH_ENABLE(x) (((x) & 0x1) << 0)VIRGL_OBJ_RS_OFFSET_UNITS 7VIRGL_SET_VERTEX_BUFFERS_SIZE(num_buffers) ((num_buffers) * 3)VIRGL_BIND_STAGING (1 << 19)VIRGL_FORMAT_Z32_FLOAT_S8X24_UINTVIRGL_FORMAT_MAXtexture_multisampleVIRGL_OBJ_RS_S0_OFFSET_TRI(x) (((x) & 0x1) << 20)VIRGL_FORMAT_L16A16_SINTVIRGL_FORMAT_Z24X8_UNORMdrm_virtgpu_3d_transfer_from_hostVIRGL_FORMAT_R8G8B8_SINTVIRGL_BIND_CURSOR (1 << 16)VIRGL_SET_VIEWPORT_STATE_SCALE_1(x) (3 + (x * 6))VIRGL_FORMAT_NV21param_supported_capset_idsVIRGL_FORMAT_L8_SNORMtranslate_formatVIRGL_FORMAT_R16G16_SINTVIRGL_OBJ_STREAMOUT_HANDLE 1VIRGL_COPY_TRANSFER3D_SIZE 14bitmask_indexVIRGL_SET_CLIP_STATE_SIZE 32VIRGL_SET_SAMPLER_VIEWS_START_SLOT 2VIRGL_FORMAT_R16G16_SNORMvirgl_capsblob_memvirgl_3d_bo_mapVIRGL_FORMAT_B5G5R5X1_UNORMATOMIC_LLONG_LOCK_FREE __GCC_ATOMIC_LLONG_LOCK_FREEVIRGL_OBJ_SAMPLER_STATE_HANDLE 1ATOMIC_CHAR32_T_LOCK_FREE __GCC_ATOMIC_CHAR32_T_LOCK_FREEshader_buffer_offset_alignmentVIRGL_CCMD_SET_POLYGON_STIPPLEVIRGL_QUERY_RESULT_WAIT 2VIRGL_OBJ_BLEND_S2_RT_ALPHA_DST_FACTOR(x) (((x) & 0x1f) << 22)VIRGL_OBJ_SHADER_SO_OUTPUT_START_COMPONENT(x) (((x) & 0x3) << 8)VIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_LAYERS(x) (x & 0xffff)VIRGL_CCMD_SET_CONSTANT_BUFFERVIRGL_OBJ_SHADER_TYPE 2VIRGL_OBJ_SAMPLER_STATE_SIZE 9VIRGL_TEXTURE_BARRIER_FLAGS 1VIRGL_CCMD_SET_INDEX_BUFFERVIRGL_DRAW_VBO_DRAWID 14VIRGL_CCMD_DESTROY_OBJECTVIRGL_FORMAT_L32A32_SINTVIRGL_FORMAT_L32A32_UINTVIRGL_CAP_3D_ASTC (1 << 24)VIRGL_FORMAT_L8_UINTVIRGL_OBJ_BLEND_S1 3VIRGL_SET_TWEAKS_SIZE 2VIRGL_OBJ_DSA_S1_STENCIL_FUNC(x) (((x) & 0x7) << 1)VIRGL_QUERY_STATE_DONE 1VIRGL_FORMAT_R16G16B16X16_SINTVIRGL_RESOURCE_IW_W 9VIRGL_FORMAT_R32G32B32_UINTVIRGL_QUERY_RESULT_SIZE 2VIRGL_CCMD_SET_SAMPLE_MASKmax_aliased_point_sizeVIRGL_SET_STENCIL_REF 1VIRGL_SET_SCISSOR_MINX_MINY(x) (2 + (x * 2))VIRGL_FORMAT_RGTC2_SNORMVIRGL_OBJ_DSA_S1_STENCIL_ENABLED(x) (((x) & 0x1) << 0)VIRGL_OBJ_DSA_S0_DEPTH_WRITEMASK(x) (((x) & 0x1) << 1)VIRGL_FORMAT_L8A8_UNORMVIRGL_MAX_CLIP_PLANES 8VIRGL_CMD_BLIT_DST_RES_HANDLE 4atomic_fetch_sub_explicit(PTR,VAL,MO) __atomic_fetch_sub ((PTR), (VAL), (MO))VIRGL_DRAW_VBO_INDIRECT_DRAW_COUNT 18atomic_store_explicit(PTR,VAL,MO) __extension__ ({ __auto_type __atomic_store_ptr = (PTR); __typeof__ (*__atomic_store_ptr) __atomic_store_tmp = (VAL); __atomic_store (__atomic_store_ptr, &__atomic_store_tmp, (MO)); })atomic_init(PTR,VAL) atomic_store_explicit (PTR, VAL, __ATOMIC_RELAXED)VIRGL_OBJ_CLEAR_DEPTH_0 6VIRGL_CCMD_DRAW_VBOatomic_fetch_or_explicit(PTR,VAL,MO) __atomic_fetch_or ((PTR), (VAL), (MO))VIRGL_BIND_SAMPLER_STATES_S0_HANDLE 3VIRGL_SET_SHADER_IMAGE_ACCESS(x) ((x) * VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE + 4)VIRGL_OBJ_RS_OFFSET_CLAMP 9VIRGL_OBJ_DSA_S0 2compute_virgl_bind_flagsVIRGL_SET_ATOMIC_BUFFER_RES_HANDLE(x) ((x) * VIRGL_SET_ATOMIC_BUFFER_ELEMENT_SIZE + 4)VIRGL_OBJ_RS_S3 5VIRGL_CMD_BLIT_S0_MASK(x) (((x) & 0xff) << 0)bit_indexVIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_WIDTH(x) (x & 0xffff)VIRGL_LAUNCH_GRID_Y 5VIRGL_SET_SHADER_BUFFER_OFFSET(x) ((x) * VIRGL_SET_SHADER_BUFFER_ELEMENT_SIZE + 3)VIRGL_OBJ_BLEND_S0_ALPHA_TO_COVERAGE(x) (((x) & 0x1) << 3)max_compute_block_sizeVIRGL_OBJ_RS_HANDLE 1ATOMIC_POINTER_LOCK_FREE __GCC_ATOMIC_POINTER_LOCK_FREEVIRGL_FORMAT_R8_SINTatomic_compare_exchange_weak_explicit(PTR,VAL,DES,SUC,FAIL) __extension__ ({ __auto_type __atomic_compare_exchange_ptr = (PTR); __typeof__ (*__atomic_compare_exchange_ptr) __atomic_compare_exchange_tmp = (DES); __atomic_compare_exchange (__atomic_compare_exchange_ptr, (VAL), &__atomic_compare_exchange_tmp, 1, (SUC), (FAIL)); })VIRGL_BIND_MINIGBM_HW_VIDEO_ENCODER (1 << 27)bsetVIRGL_FORMAT_R8G8B8X8_UNORMVIRGL_CCMD_SET_SCISSOR_STATEVIRGL_LAUNCH_INDIRECT_HANDLE 7VIRGL_OBJ_SAMPLER_VIEW_TEXTURE_LEVEL 5VIRGL_CMD_RCR_SRC_X 8VIRGL_CCMD_MEMORY_BARRIERseamless_cube_mapVIRGL_SET_ATOMIC_BUFFER_START_SLOT 1max_shader_image_frag_computeVIRGL_SET_SHADER_IMAGE_LAYER_OFFSET(x) ((x) * VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE + 5)atomic_fetch_or(PTR,VAL) __atomic_fetch_or ((PTR), (VAL), __ATOMIC_SEQ_CST)VIRGL_SET_SAMPLER_VIEWS_SHADER_TYPE 1ATOMIC_INT_LOCK_FREE __GCC_ATOMIC_INT_LOCK_FREEVIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_LAYERS_SAMPLES 2VIRGL_CAP_SRGB_WRITE_CONTROL (1 << 15)max_compute_shared_memory_sizepolygon_offset_clampparam_maxcolor_clampingVIRGL_CCMD_SET_SHADER_IMAGESmax_combined_atomic_counter_buffersVIRGL_CCMD_SET_SHADER_BUFFERSc_plane_heightVIRGL_CMD_BLIT_DST_X 7drm_virtgpu_mapVIRGL_OBJ_DSA_S1_STENCIL_ZFAIL_OP(x) (((x) & 0x7) << 10)max_geom_total_output_componentsATOMIC_WCHAR_T_LOCK_FREE __GCC_ATOMIC_WCHAR_T_LOCK_FREEVIRGL_FORMAT_R16G16B16X16_UNORMdrm_virtgpu_3d_waitVIRGL_PIPE_RES_CREATE_LAST_LEVEL 8max_shader_buffer_frag_computeVIRGL_CCMD_NOPVIRGL_CCMD_SET_SUB_CTXVIRGL_DRAW_VBO_VERTICES_PER_PATCH 13VIRGL_OBJ_DSA_S1_STENCIL_VALUEMASK(x) (((x) & 0xff) << 13)nr_samplesVIRGL_RESOURCE_IW_D 11VIRGL_POLYGON_STIPPLE_P0 1VIRGL_SET_SHADER_IMAGE_FORMAT(x) ((x) * VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE + 3)VIRGL_PIPE_RES_CREATE_TARGET 1VIRGL_OBJ_BLEND_S0_INDEPENDENT_BLEND_ENABLE(x) ((x) & 0x1 << 0)VIRGL_FORMAT_R8G8_SNORMVIRGL_OBJ_CLEAR_COLOR_2 4VIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_HEIGHT(x) ((x >> 16) & 0xffff)VIRGL_SET_TWEAKS_VALUE 2max_texture_3d_sizeVIRGL_BIND_MINIGBM_HW_VIDEO_DECODER (1 << 26)param_guest_vramVIRGL_FORMAT_B10G10R10A2_UINTVIRGL_FORMAT_RGTC1_SNORMVIRGL_RESOURCE_IW_Y 7VIRGL_FORMAT_R32_SINTVIRGL_OBJ_QUERY_SIZE 4VIRGL_QUERY_END_HANDLE 1atomic_fetch_add_explicit(PTR,VAL,MO) __atomic_fetch_add ((PTR), (VAL), (MO))VIRGL_CCMD_BIND_OBJECTVIRGL_OBJ_QUERY_INDEX(x) ((x & 0xffff) << 16)VIRGL_OBJ_DESTROY_HANDLE 1drm_virtgpu_resource_info_crosVIRGL_CCMD_DESTROY_SUB_CTXVIRGL_SET_SAMPLER_VIEWS_SIZE(num_views) ((num_views) + 2)VIRGL_LAUNCH_BLOCK_X 1VIRGL_FORMAT_R16G16B16A16_UINTtimer_queryVIRGL_SET_SHADER_IMAGE_START_SLOT 2VIRGL_OBJ_BLEND_SIZE (VIRGL_MAX_COLOR_BUFS + 3)VIRGL_FORMAT_DXT1_RGBvirgl_3d_get_max_texture_2d_sizeconditional_render_invertedVIRGL_OBJ_DSA_S1_STENCIL_FAIL_OP(x) (((x) & 0x7) << 4)has_tessellation_shadersparam_create_guest_handleparam_resource_blobVIRGL_FORMAT_R8G8_SRGBVIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_SAMPLES(x) ((x >> 16) & 0xff)VIRGL_FORMAT_DXT1_RGBAVIRGL_MEMORY_BARRIER_FLAGS 1max_texture_cube_sizeVIRGL_OBJ_RS_S0_HALF_PIXEL_CENTER(x) (((x) & 0x1) << 29)xfers_neededmin_smooth_point_sizemax_viewportsVIRGL_CAP_TGSI_PRECISE (1 << 4)VIRGL_FORMAT_R16_UNORMVIRGL_QUERY_RESULT_QBO_HANDLE 1VIRGL_CAP_SHADER_CLOCK (1 << 11)max_texture_array_layersVIRGL_DRAW_VBO_INDIRECT_DRAW_COUNT_OFFSET 19VIRGL_FORMAT_BPTC_RGB_UFLOATVIRGL_FORMAT_R9G9B9E5_FLOATVIRGL_BIND_VERTEX_BUFFER (1 << 4)VIRGL_CCMD_RESOURCE_INLINE_WRITEVIRGL_BIND_COMMAND_ARGS (1 << 8)VIRGL_CCMD_SET_ATOMIC_BUFFERSVIRGL_FORMAT_R8G8B8A8_SRGBVIRGL_OBJ_SAMPLER_STATE_MIN_LOD 4VIRGL_FORMAT_R32_FLOATVIRGL_OBJ_RS_S0_LIGHT_TWOSIZE(x) (((x) & 0x1) << 5)VIRGL_TEXTURE_ARRAY_B 10atomic_compare_exchange_strong(PTR,VAL,DES) atomic_compare_exchange_strong_explicit (PTR, VAL, DES, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST)VIRGL_CMD_BLIT_DST_Z 9VIRGL_HW_H VIRGL_OBJ_RS_S0_CLAMP_FRAGMENT_COLOR(x) (((x) & 0x1) << 17)VIRGL_CAP_MEMORY_BARRIER (1 << 6)VIRGL_SET_SAMPLE_MASK_SIZE 1VIRGL_SET_SHADER_BUFFER_START_SLOT 2VIRGL_OBJ_BLEND_S2_RT_ALPHA_SRC_FACTOR(x) (((x) & 0x1f) << 17)VIRGL_PIPE_RES_CREATE_FLAGS 10VIRGL_OBJ_RS_S0_SCISSOR(x) (((x) & 0x1) << 14)VIRGL_TEXTURE_SRC_X 3VIRGL_PROTOCOL_H VIRGL_FORMAT_B10G10R10A2_UNORMVIRGL_DRAW_VBO_SIZE_INDIRECT 20VIRGL_SET_VIEWPORT_START_SLOT 1VIRGL_CMD_BLIT_DST_W 10drm_virtgpu_3d_boxvirgl_supports_combination_through_emulationVIRGL_OBJ_SAMPLER_VIEW_SIZE 6atomic_fetch_xor_explicit(PTR,VAL,MO) __atomic_fetch_xor ((PTR), (VAL), (MO))VIRGL_QUERY_RESULT_QBO_INDEX 6VIRGL_RESOURCE_IW_RES_HANDLE 1VIRGL_CMD_RCR_DST_RES_HANDLE 1VIRGL_FORMAT_R8G8B8X8_SRGBatomic_compare_exchange_strong_explicit(PTR,VAL,DES,SUC,FAIL) __extension__ ({ __auto_type __atomic_compare_exchange_ptr = (PTR); __typeof__ (*__atomic_compare_exchange_ptr) __atomic_compare_exchange_tmp = (DES); __atomic_compare_exchange (__atomic_compare_exchange_ptr, (VAL), &__atomic_compare_exchange_tmp, 0, (SUC), (FAIL)); })VIRGL_FORMAT_R16G16B16X16_FLOATVIRGL_SET_INDEX_BUFFER_OFFSET 3VIRGL_CAP_COPY_IMAGE (1 << 3)VIRGL_OBJ_SAMPLE_STATE_S0_MIN_MIP_FILTER(x) (((x) & 0x3) << 11)atomic_fetch_and_explicit(PTR,VAL,MO) __atomic_fetch_and ((PTR), (VAL), (MO))VIRGL_BIND_DEPTH_STENCIL (1 << 0)virgl_3d_resolve_format_and_use_flagsVIRGL_CAP_TRANSFER (1 << 17)VIRGL_CMD_BLIT_SCISSOR_MAXX_MAXY 3VIRGL_CMD_RCR_SRC_D 13VIRGL_FORMAT_L8A8_SRGBVIRGL_SET_ATOMIC_BUFFER_ELEMENT_SIZE 3VIRGL_CMD_BLIT_SRC_FORMAT 15uniform_buffer_offset_alignmentVIRGL_CMD_BLIT_SRC_Z 18VIRGL_LAUNCH_BLOCK_Z 3VIRGL_QUERY_STATE_NEW 0max_streamout_buffersVIRGL_BIND_PREFER_EMULATED_BGRA (1 << 21)VIRGL_CAP_APP_TWEAK_SUPPORT (1 << 28)VIRGL_DRAW_VBO_PRIMITIVE_RESTART 8atomic_fetch_add(PTR,VAL) __atomic_fetch_add ((PTR), (VAL), __ATOMIC_SEQ_CST)VIRGL_CCMD_GET_QUERY_RESULTVIRGL_OBJ_QUERY_TYPE_INDEX 2VIRGL_CAP_TEXTURE_BARRIER (1 << 12)VIRGL_FORMAT_A16_UNORMVIRGL_CMD_BLIT_SRC_W 19VIRGL_FORMAT_X24S8_UINTVIRGL_OBJ_VERTEX_ELEMENTS_HANDLE 1atomic_intVIRGL_FORMAT_R16G16B16_SINTVIRGL_SET_SHADER_IMAGE_LEVEL_SIZE(x) ((x) * VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE + 6)VIRGL_OBJ_RS_S0_FILL_BACK(x) (((x) & 0x3) << 12)VIRGL_BIND_QUERY_BUFFER (1 << 15)VIRGL_OBJ_RS_S0_RASTERIZER_DISCARD(x) (((x) & 0x1) << 3)VIRGL_FORMAT_BPTC_SRGBAVIRGL_FORMAT_A32_FLOATVIRGL_2D_MAX_TEXTURE_2D_SIZE MIN(ANGLE_ON_SWIFTSHADER_MAX_TEXTURE_2D_SIZE, MESA_LLVMPIPE_MAX_TEXTURE_2D_SIZE)VIRGL_CAP_CLIP_HALFZ (1 << 27)VIRGL_CMD_RESOURCE_COPY_REGION_SIZE 13VIRGL_TESS_STATE_SIZE 6VIRGL_FORMAT_A8_UNORMVIRGL_CCMD_PIPE_RESOURCE_CREATEVIRGL_DRAW_VBO_MIN_INDEX 10VIRGL_SET_CONSTANT_BUFFER_DATA_START 3max_texture_gather_componentskill_dependency(Y) __extension__ ({ __auto_type __kill_dependency_tmp = (Y); __kill_dependency_tmp; })VIRGL_TEXTURE_SRC_D 8VIRGL_SET_FRAMEBUFFER_STATE_NR_ZSURF_HANDLE 2VIRGL_QUERY_STATE_WAIT_HOST 2max_atomic_countersVIRGL_CMD_RCR_SRC_Z 10VIRGL_SET_FRAMEBUFFER_STATE_SIZE(nr_cbufs) (nr_cbufs + 2)VIRGL_FORMAT_MAX_EXTENDEDVIRGL_CMD_RCR_DST_X 3VIRGL_CCMD_BEGIN_QUERYVIRGL_FORMAT_R8G8_SINTATOMIC_BOOL_LOCK_FREE __GCC_ATOMIC_BOOL_LOCK_FREEVIRGL_FORMAT_L8_UNORMVIRGL_SET_SHADER_IMAGE_SIZE(x) (VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE * (x)) + 2VIRGL_SET_ATOMIC_BUFFER_OFFSET(x) ((x) * VIRGL_SET_ATOMIC_BUFFER_ELEMENT_SIZE + 2)VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_R(x) (((x) & 0x7) << 6)VIRGL_TEXTURE_SRC_Y 4VIRGL_FORMAT_R16_FLOATVIRGL_FORMAT_R16G16_UNORMatomic_flag_test_and_set_explicit(PTR,MO) __atomic_test_and_set ((PTR), (MO))VIRGL_PIPE_RES_CREATE_HEIGHT 5max_texture_gather_offsetVIRGL_CCMD_LAUNCH_GRIDVIRGL_CCMD_BIND_SHADERVIRGL_OBJ_RS_S0_SPRITE_COORD_MODE(x) (((x) & 0x1) << 6)VIRGL_SET_VIEWPORT_STATE_TRANSLATE_2(x) (7 + (x * 6))VIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_MODE(x) (((x) & 0x1) << 15)VIRGL_CCMD_COPY_TRANSFER3DVIRGL_OBJ_RS_S0_POLY_SMOOTH(x) (((x) & 0x1) << 21)VIRGL_SET_UNIFORM_BUFFER_OFFSET 3VIRGL_CAP_TGSI_INVARIANT (1 << 0)VIRGL_OBJ_QUERY_RES_HANDLE 4VIRGL_FORMAT_R8G8B8A8_SINTVIRGL_SET_SHADER_BUFFER_SHADER_TYPE 1VIRGL_FORMAT_B2G3R3_UNORMVIRGL_BIND_SCANOUT (1 << 18)next_blob_idvirgl_get_max_texture_2d_sizeVIRGL_FORMAT_A16_UINTis_arc_screen_capture_boVIRGL_SET_INDEX_BUFFER_HANDLE 1VIRGL_OBJ_RS_S0_POINT_QUAD_RASTERIZATION(x) (((x) & 0x1) << 7)max_tbo_sizesupported_readback_formatsVIRGL_FORMAT_L16A16_UNORMVIRGL_OBJ_RS_S0_LINE_LAST_PIXEL(x) (((x) & 0x1) << 28)ATOMIC_VAR_INIT(VALUE) (VALUE)VIRGL_SET_INDEX_BUFFER_INDEX_SIZE 2VIRGL_FORMAT_Z32_UNORM/source/platform/minigbm/virtgpu_virgl.cVIRGL_QUERY_RESULT_HANDLE 1waitcmdmax_texture_lod_biasVIRGL_BIND_DISPLAY_TARGET (1 << 7)VIRGL_OBJ_DSA_ALPHA_REF 5virgl_bitmask_supports_formatVIRGL_OBJ_SAMPLER_STATE_MAX_LOD 5virgl_resource_infoVIRGL_OBJ_SHADER_SO_NUM_OUTPUTS 5VIRGL_SET_SHADER_IMAGE_RES_HANDLE(x) ((x) * VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE + 7)VIRGL_CCMD_SET_BLEND_COLORVIRGL_CMD_BLIT_SRC_H 20VIRGL_OBJ_RS_S0_CULL_FACE(x) (((x) & 0x3) << 8)VIRGL_PIPE_RES_CREATE_ARRAY_SIZE 7VIRGL_FORMAT_L16_UINTVIRGL_FORMAT_R8G8B8X8_SINTtexture_query_lodVIRGL_SET_TWEAKS_ID 1VIRGL_OBJ_SAMPLE_STATE_S0_SEAMLESS_CUBE_MAP(x) (((x) & 0x1) << 19)VIRGL_LAUNCH_GRID_SIZE 8virgl_bo_create_with_modifiersVIRGL_FORMAT_RGTC2_UNORMVIRGL_OBJ_RS_S0_FORCE_PERSAMPLE_INTERP(x) (((x) & 0x1) << 31)VIRGL_SET_SAMPLE_MASK_MASK 1VIRGL_OBJ_RS_S0_LINE_SMOOTH(x) (((x) & 0x1) << 26)VIRGL_OBJ_RS_S0_LINE_STIPPLE_ENABLE(x) (((x) & 0x1) << 27)atomic_fetch_xor(PTR,VAL) __atomic_fetch_xor ((PTR), (VAL), __ATOMIC_SEQ_CST)VIRGL_FORMAT_R32G32B32A32_UINTvertex_element_instance_divisorVIRGL_CCMD_SET_TESS_STATEVIRGL_FORMAT_L8A8_SINTparam_capset_fixVIRGL_OBJ_QUERY_HANDLE 1VIRGL_CMD_RCR_SRC_W 11ATOMIC_LONG_LOCK_FREE __GCC_ATOMIC_LONG_LOCK_FREEVIRGL_BIND_RENDER_TARGET (1 << 1)VIRGL_OBJ_BLEND_S0_LOGICOP_ENABLE(x) (((x) & 0x1) << 1)VIRGL_FORMAT_R32G32B32_FLOATVIRGL_OBJ_RS_S0_CLIP_HALFZ(x) (((x) & 0x1) << 2)VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_G(x) (((x) & 0x7) << 3)VIRGL_OBJ_RS_S0_POLY_STIPPLE_ENABLE(x) (((x) & 0x1) << 22)atomic_exchange_explicit(PTR,VAL,MO) __extension__ ({ __auto_type __atomic_exchange_ptr = (PTR); __typeof__ (*__atomic_exchange_ptr) __atomic_exchange_val = (VAL); __typeof__ (*__atomic_exchange_ptr) __atomic_exchange_tmp; __atomic_exchange (__atomic_exchange_ptr, &__atomic_exchange_val, &__atomic_exchange_tmp, (MO)); __atomic_exchange_tmp; })VIRGL_TRANSFER3D_SIZE 13virgl_initVIRGL_FORMAT_A16_FLOATVIRGL_BIND_MINIGBM_SW_WRITE_OFTEN (1 << 30)VIRGL_OBJ_VERTEX_ELEMENTS_SIZE(num_elements) (((num_elements) * 4) + 1)xfer_boxesVIRGL_OBJ_BLEND_S0 2VIRGL_CMD_RCR_DST_Z 5VIRGL_OBJ_BLEND_S2_RT_RGB_FUNC(x) (((x) & 0x7) << 1)VIRGL_SET_STREAMOUT_TARGETS_H0 2atomic_fetch_sub(PTR,VAL) __atomic_fetch_sub ((PTR), (VAL), __ATOMIC_SEQ_CST)param_context_initVIRGL_FORMAT_A8R8G8B8_UNORMVIRGL_CMD_BLIT_SIZE 21VIRGL_BIND_SHARED (1 << 20)VIRGL_CMD_BLIT_SRC_RES_HANDLE 13VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_A(x) (((x) & 0x7) << 9)VIRGL_CCMD_SET_SAMPLER_VIEWSmax_vertex_attrib_stridevirgl_get_emulated_metadataPIPE_TEXTURE_2D 2VIRGL_FORMAT_A16_SINTstart_instanceVIRGL_OBJ_SHADER_HANDLE 1VIRGL_OBJ_SHADER_SO_OUTPUT_NUM_COMPONENTS(x) (((x) & 0x7) << 10)VIRGL_OBJ_CLEAR_COLOR_1 3VIRGL_OBJ_SHADER_OFFSET_VAL(x) (((x) & 0x7fffffff) << 0)should_use_blobVIRGL_RESOURCE_IW_H 10VIRGL_CCMD_SET_FRAMEBUFFER_STATE_NO_ATTACHlayer_strideVIRGL_CCMD_SET_FRAMEBUFFER_STATEmax_vertex_attribsVIRGL_OBJ_SHADER_SO_OUTPUT_BUFFER(x) (((x) & 0x7) << 13)VIRGL_FORMAT_R32G32B32A32_SINTVIRGL_CCMD_RESOURCE_COPY_REGIONVIRGL_FORMAT_R16_UINTvirtgpu_param_idVIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_FUNC(x) (((x) & 0x7) << 16)VIRGL_COPY_TRANSFER3D_SRC_RES_OFFSET 13shader_stencil_exportVIRGL_OBJ_SURFACE_HANDLE 1VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE 5VIRGL_CCMD_SET_STREAMOUT_TARGETSVIRGL_CCMD_BLITVIRGL_FORMAT_DXT5_RGBAVIRGL_OBJ_RS_S0 2drm_formatsVIRGL_OBJ_BLEND_S2_RT_RGB_DST_FACTOR(x) (((x) & 0x1f) << 9)VIRGL_FORMAT_S8_UINTVIRGL_FORMAT_R8G8_UNORMVIRGL_FORMAT_L16_SNORMVIRGL_DRAW_VBO_INSTANCE_COUNT 5VIRGL_CAP_TGSI_FBFETCH (1 << 10)VIRGL_OBJ_DSA_S0_DEPTH_FUNC(x) (((x) & 0x7) << 2)VIRGL_OBJ_SAMPLE_STATE_S0_MIN_IMG_FILTER(x) (((x) & 0x3) << 9)VIRGL_CMD0_MAX_DWORDS (((1ULL << 16) - 1) / 4) * 4VIRGL_FORMAT_R16G16B16A16_SNORMVIRGL_OBJ_CLEAR_STENCIL 8VIRGL_OBJ_STREAMOUT_RES_HANDLE 2VIRGL_CMD_BLIT_DST_H 11VIRGL_OBJ_BLEND_S2_RT_ALPHA_FUNC(x) (((x) & 0x7) << 14)VIRGL_FORMAT_B8G8R8A8_UNORM_EMULATEDVIRGL_OBJ_SHADER_SO_OUTPUT0_SO(x) (11 + (x * 2))VIRGL_FORMAT_Z16_UNORMVIRGL_FORMAT_R8G8B8_SNORMVIRGL_FORMAT_RGTC1_UNORMVIRGL_OBJ_BIND_HEADER 0VIRGL_TEXTURE_BARRIER_SIZE 1VIRGL_BIND_MINIGBM_SW_READ_OFTEN (1 << 28)VIRGL_SET_VIEWPORT_STATE_SIZE(num_viewports) ((6 * num_viewports) + 1)VIRGL_OBJ_STREAMOUT_BUFFER_SIZE 4atomic_load_explicit(PTR,MO) __extension__ ({ __auto_type __atomic_load_ptr = (PTR); __typeof__ (*__atomic_load_ptr) __atomic_load_tmp; __atomic_load (__atomic_load_ptr, &__atomic_load_tmp, (MO)); __atomic_load_tmp; })occlusion_queryVIRGL_FORMAT_R8G8B8_UINTVIRGL_SET_SCISSOR_START_SLOT 1VIRGL_CLEAR_TEXTURE_SIZE 12VIRGL_SET_SCISSOR_STATE_SIZE(x) (1 + 2 * x)VIRGL_FORMAT_Z32_FLOATVIRGL_PIPE_RES_CREATE_NR_SAMPLES 9VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_R(x) (((x) & 0x7) << 0)virgl_add_combinationsinstanceidVIRGL_FORMAT_P010VIRGL_FORMAT_P012virgl_bo_flushVIRGL_FORMAT_P016VIRGL_BIND_SHADER_SIZE 2VIRGL_BIND_SHARED_SUBFLAGS (0xff << 24)VIRGL_BIND_SAMPLER_VIEW (1 << 3)VIRGL_BIND_SAMPLER_STATES_START_SLOT 2VIRGL_FORMAT_L8_SRGBVIRGL_OBJ_DSA_S1_STENCIL_ZPASS_OP(x) (((x) & 0x7) << 7)VIRGL_OBJ_BLEND_S2_RT_RGB_SRC_FACTOR(x) (((x) & 0x1f) << 4)VIRGL_RESOURCE_IW_LAYER_STRIDE 5VIRGL_CMD_BLIT_SRC_D 21VIRGL_FORMAT_A32_SINTVIRGL_TEXTURE_SRC_Z 5VIRGL_OBJ_STREAMOUT_BUFFER_OFFSET 3VIRGL_OBJ_BLEND_S0_DITHER(x) (((x) & 0x1) << 2)VIRGL_FORMAT_R16G16B16X16_UINTblob_flagstargetbitmaskVIRGL_SET_SHADER_BUFFER_RES_HANDLE(x) ((x) * VIRGL_SET_SHADER_BUFFER_ELEMENT_SIZE + 5)atomic_fetch_and(PTR,VAL) __atomic_fetch_and ((PTR), (VAL), __ATOMIC_SEQ_CST)VIRGL_FORMAT_DXT3_SRGBAVIRGL_MEMORY_BARRIER_SIZE 1has_sample_shadingVIRGL_FORMAT_R16_SINTVIRGL_FORMAT_L32_SINTVIRGL_DRAW_VBO_INDIRECT_OFFSET 16VIRGL_LAUNCH_BLOCK_Y 2VIRGL_OBJ_DSA_S2 4VIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_WIDTH_HEIGHT 1VIRGL_OBJ_RS_S0_FLATSHADE(x) (((x) & 0x1) << 0)seamless_cube_map_per_textureparam_resource_syncVIRGL_BIND_MINIGBM_CAMERA_READ (1 << 25)virgl_3d_bo_createhas_indirect_drawVIRGL_CMD_BLIT_SCISSOR_MINX_MINY 2VIRGL_OBJ_CREATE_HEADER 0VIRGL_FORMAT_R10G10B10A2_UNORMVIRGL_CAP_FAKE_FP64 (1 << 19)fragment_coord_conventionsVIRGL_FORMAT_R8_UINTVIRGL_QUERY_RESULT_QBO_QBO_HANDLE 2VIRGL_SET_SHADER_BUFFER_SIZE(x) (VIRGL_SET_SHADER_BUFFER_ELEMENT_SIZE * (x)) + 2VIRGL_CMD_RCR_SRC_H 12param_host_visibleVIRGL_SET_INDEX_BUFFER_SIZE(ib) (((ib) ? 2 : 0) + 1)VIRGL_FORMAT_BPTC_RGB_FLOATVIRGL_FORMAT_R32G32_SINTsamplerVIRGL_LAUNCH_GRID_X 4VIRGL_OBJ_SAMPLER_STATE_S0 2drm_fourccVIRGL_SET_VIEWPORT_STATE_TRANSLATE_1(x) (6 + (x * 6))VIRGL_CCMD_CREATE_SUB_CTXVIRGL_OBJ_SHADER_SO_OUTPUT0(x) (10 + (x * 2))VIRGL_FORMAT_B10G10R10X2_UNORMVIRGL_FORMAT_B8G8R8A8_SRGBATOMIC_SHORT_LOCK_FREE __GCC_ATOMIC_SHORT_LOCK_FREEVIRGL_SET_MIN_SAMPLES_SIZE 1VIRGL_FORMAT_A8_SINTVIRGL_TRANSFER_FROM_HOST 2VIRGL_CCMD_SET_VERTEX_BUFFERSatomic_compare_exchange_weak(PTR,VAL,DES) atomic_compare_exchange_weak_explicit (PTR, VAL, DES, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST)max_geom_output_verticesres_infovirgl_supported_format_maskVIRGL_CAP_TRANSFORM_FEEDBACK3 (1 << 23)virgl_supports_combination_nativelymax_atomic_counter_buffersVIRGL_CMD_BLIT_S0_FILTER(x) (((x) & 0x3) << 8)VIRGL_PIPE_RES_CREATE_SIZE 11VIRGL_CMD_BLIT_S0_SCISSOR_ENABLE(x) (((x) & 0x1) << 10)last_levelVIRGL_DRAW_VBO_START_INSTANCE 7VIRGL_BIND_SAMPLER_STATES(num_states) ((num_states) + 2)glsl_levelVIRGL_SET_CLIP_STATE_C0 1VIRGL_OBJ_RS_SIZE 9host_write_flagsparam_3datomic_flag_clear_explicit(PTR,MO) __atomic_clear ((PTR), (MO))VIRGL_FORMAT_R16G16_FLOATVIRGL_DRAW_VBO_MAX_INDEX 11VIRGL_OBJ_BLEND_S1_LOGICOP_FUNC(x) (((x) & 0xf) << 0)min_aliased_line_widthVIRGL_CMD_BLIT_SRC_Y 17virgl_2d_resolve_format_and_use_flagsVIRGL_FORMAT_R8G8B8A8_SNORMVIRGL_OBJ_BLEND_S2_RT_COLORMASK(x) (((x) & 0xf) << 27)VIRGL_CAP_FBO_MIXED_COLOR_FORMATS (1 << 18)VIRGL_FORMAT_B8G8R8X8_SRGBVIRGL_QUERY_RESULT_QBO_SIZE 6VIRGL_SET_STENCIL_REF_SIZE 1VIRGL_SET_UNIFORM_BUFFER_SHADER_TYPE 1VIRGL_TRANSFER_TO_HOST 1conditional_renderVIRGL_OBJ_DSA_SIZE 5VIRGL_SET_ATOMIC_BUFFER_SIZE(x) (VIRGL_SET_ATOMIC_BUFFER_ELEMENT_SIZE * (x)) + 1VIRGL_OBJ_BLEND_HANDLE 1VIRGL_FORMAT_R32_UINTVIRGL_CAP_TGSI_COMPONENTS (1 << 13)cap_set_idVIRGL_LAUNCH_INDIRECT_OFFSET 8VIRGL_OBJ_RS_S0_MULTISAMPLE(x) (((x) & 0x1) << 25)VIRGL_OBJ_SHADER_OFFSET_CONT (0x1u << 31)VIRGL_OBJ_SHADER_SO_OUTPUT_REGISTER_INDEX(x) (((x) & 0xff) << 0)virgl_add_combinationmax_compute_grid_sizemax_samplesVIRGL_FORMAT_R10G10B10A2_UINTVIRGL_OBJ_SAMPLER_VIEW_SWIZZLE 6VIRGL_TEXTURE_LEVEL 2VIRGL_OBJ_CLEAR_COLOR_0 2VIRGL_BIND_MINIGBM_SW_WRITE_RARELY (1 << 31)VIRGL_FORMAT_B4G4R4A4_UNORMVIRGL_OBJ_SAMPLER_VIEW_TEXTURE_LAYER 4VIRGL_OBJ_RS_POINT_SIZE 3VIRGL_CAP_QBO (1 << 16)VIRGL_DRAW_VBO_SIZE_TESS 14ATOMIC_CHAR16_T_LOCK_FREE __GCC_ATOMIC_CHAR16_T_LOCK_FREEstreamout_pause_resumeVIRGL_RESOURCE_IW_X 6VIRGL_QUERY_RESULT_QBO_WAIT 3VIRGL_DRAW_VBO_COUNT_FROM_SO 12VIRGL_CCMD_TEXTURE_BARRIERVIRGL_OBJ_DSA_S1_STENCIL_WRITEMASK(x) (((x) & 0xff) << 21)VIRGL_FORMAT_L8_SINTVIRGL_BIND_MINIGBM_SW_READ_RARELY (1 << 29)primitive_restartVIRGL_SET_VIEWPORT_STATE_TRANSLATE_0(x) (5 + (x * 6))VIRGL_CCMD_SET_DEBUG_FLAGSvirgl_bo_mapVIRGL_FORMAT_R32G32B32_SINTvirgl_privvirgl_init_params_and_capsVIRGL_MAX_COLOR_BUFS 8VIRGL_DRAW_VBO_SIZE 12VIRGL_PIPE_RES_CREATE_FORMAT 2VIRGL_CAP_GUEST_MAY_INIT_LOG (1 << 14)VIRGL_TEXTURE_SRC_H 7drm_formatVIRGL_OBJ_RS_S0_POINT_SIZE_PER_VERTEX(x) (((x) & 0x1) << 24)virgl_formatVIRGL_OBJ_DSA_S1 3host_gbm_enabledVIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_B(x) (((x) & 0x7) << 6)VIRGL_LAUNCH_GRID_Z 6VIRGL_OBJ_SURFACE_FORMAT 3caps_is_v2VIRGL_CCMD_SET_TWEAKSVIRGL_OBJ_STREAMOUT_SIZE 4VIRGL_OBJ_QUERY_TYPE(x) (x & 0xffff)VIRGL_QUERY_BEGIN_HANDLE 1VIRGL_RENDER_CONDITION_SIZE 3y_plane_heightVIRGL_CCMD_END_QUERYVIRGL_OBJ_SAMPLE_STATE_S0_WRAP_T(x) (((x) & 0x7) << 3)VIRGL_BIND_SHADER_BUFFER (1 << 14)VIRGL_CCMD_TRANSFER3Dmax_smooth_line_widthVIRGL_FORMAT_IYUVVIRGL_OBJ_SAMPLER_STATE_LOD_BIAS 3VIRGL_OBJ_SURFACE_TEXTURE_LEVEL 4VIRGL_BIND_SHADER_TYPE 2VIRGL_CMD_BLIT_S0_RENDER_CONDITION_ENABLE(x) (((x) & 0x1) << 11)VIRGL_CMD_RCR_SRC_Y 9VIRGL_TEXTURE_ARRAY_D 12VIRGL_OBJ_SHADER_SO_OUTPUT_DST_OFFSET(x) (((x) & 0xffff) << 16)VIRGL_OBJ_RS_S0_POINT_SMOOTH(x) (((x) & 0x1) << 23)VIRGL_OBJ_SURFACE_SIZE 5scanoutVIRGL_FORMAT_R8_SNORMVIRGL_DRAW_VBO_RESTART_INDEX 9check_flagANGLE_ON_SWIFTSHADER_MAX_TEXTURE_2D_SIZE 8192VIRGL_FORMAT_L32A32_FLOATVIRGL_PIPE_RES_CREATE_WIDTH 4VIRGL_BIND_INDEX_BUFFER (1 << 5)VIRGL_PIPE_RES_CREATE_BIND 3VIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_SIZE 2VIRGL_SET_CONSTANT_BUFFER_SHADER_TYPE 1VIRGL_SET_VIEWPORT_STATE_SCALE_0(x) (2 + (x * 6))VIRGL_FORMAT_B8G8R8A8_UNORMVIRGL_OBJ_CREATE_HANDLE 1indep_blend_enablevirgl_bindvirtio_transfers_paramsVIRGL_CAP_TEXTURE_VIEW (1 << 1)VIRGL_FORMAT_DXT1_SRGBAVIRGL_CMD_BLIT_DST_Y 8VIRGL_FORMAT_Z24_UNORM_S8_UINTVIRGL_DRAW_VBO_INDIRECT_HANDLE 15max_shader_patch_varyingsVIRGL_FORMAT_X8R8G8B8_UNORMparam_cross_deviceVIRGL_SET_UNIFORM_BUFFER_LENGTH 4max_combined_shader_buffersVIRGL_CCMD_GET_QUERY_RESULT_QBOVIRGL_DRAW_VBO_MODE 3VIRGL_DRAW_VBO_INDEX_BIAS 6virgl_caps_bool_set1VIRGL_SET_SHADER_IMAGE_SHADER_TYPE 1has_fp64VIRGL_FORMAT_R16G16B16_FLOATVIRGL_CAP_SET_MIN_SAMPLES (1 << 2)VIRGL_OBJ_CLEAR_COLOR_3 5depthstencilVIRGL_OBJ_CLEAR_SIZE 8VIRGL_OBJ_SURFACE_RES_HANDLE 2virgl_get_emulated_transfers_paramsVIRGL_QUERY_RESULT_QBO_OFFSET 5VIRGL_OBJ_DSA_S0_ALPHA_ENABLED(x) (((x) & 0x1) << 8)VIRGL_BIND_SAMPLER_STATES_SHADER_TYPE 1VIRGL_SET_MIN_SAMPLES_MASK 1VIRGL_OBJ_BLEND_S0_ALPHA_TO_ONE(x) (((x) & 0x1) << 4)VIRGL_PIPE_RES_CREATE_BLOB_ID 11VIRGL_OBJ_SAMPLER_VIEW_HANDLE 1VIRGL_SET_SCISSOR_MAXX_MAXY(x) (3 + (x * 2))VIRGL_BIND_SHADER_HANDLE 1VIRGL_FORMAT_B5G5R5A1_UNORMVIRGL_CAP_ROBUST_BUFFER_ACCESS (1 << 9)VIRGL_CAP_TXQS (1 << 5)VIRGL_OBJ_BLEND_S2_RT_BLEND_ENABLE(x) (((x) & 0x1) << 0)VIRGL_CAP_FB_NO_ATTACH (1 << 8)VIRGL_FORMAT_B8G8R8X8_UNORM_EMULATEDVIRGL_SET_SHADER_BUFFER_LENGTH(x) ((x) * VIRGL_SET_SHADER_BUFFER_ELEMENT_SIZE + 4)ATOMIC_CHAR_LOCK_FREE __GCC_ATOMIC_CHAR_LOCK_FREEatomic_exchange(PTR,VAL) atomic_exchange_explicit (PTR, VAL, __ATOMIC_SEQ_CST)cap_argshas_cullVIRGL_CMD_BLIT_S0_ALPHA_BLEND(x) (((x) & 0x1) << 12)VIRGL_SET_FRAMEBUFFER_STATE_NR_CBUFS 1VIRGL_RESOURCE_IW_USAGE 3VIRGL_FORMAT_R16G16B16_UINTVIRGL_CMD_BLIT_SRC_X 16VIRGL_OBJ_SAMPLER_VIEW_RES_HANDLE 2drm_virtgpu_resource_create_blobVIRGL_DRAW_VBO_INDEXED 4VIRGL_OBJ_DSA_HANDLE 1blend_eq_sepVIRGL_SET_CONSTANT_BUFFER_INDEX 2virgl_get_capsVIRGL_FORMAT_R16G16B16A16_SINTVIRGL_SET_VERTEX_BUFFER_HANDLE(x) (((x) * 3) + 3)VIRGL_OBJ_SURFACE_BUFFER_LAST_ELEMENT 5VIRGL_BIND_CUSTOM (1 << 17)VIRGL_CCMD_SET_VIEWPORT_STATEvirgl_caps_v1virgl_caps_v2VIRGL_CCMD_END_TRANSFERSVIRGL_FORMAT_R11G11B10_FLOATvirgl_closeVIRGL_OBJ_SHADER_HDR_SIZE(nso) (5 + ((nso) ? (2 * nso) + 4 : 0))VIRGL_CMD_BLIT_DST_FORMAT 6VIRGL_FORMAT_S8X24_UINTVIRGL_RESOURCE_IW_LEVEL 2poly_stippleVIRGL_CMD_RCR_SRC_RES_HANDLE 6VIRGL_OBJ_RS_S0_CLAMP_VERTEX_COLOR(x) (((x) & 0x1) << 16)VIRGL_CCMD_SET_MIN_SAMPLESVIRGL_SET_SHADER_BUFFER_ELEMENT_SIZE 3VIRGL_SET_UNIFORM_BUFFER_INDEX 2original_widthVIRGL_FORMAT_R8G8_UINTVIRGL_CAP_NONE 0VIRGL_FORMAT_L16_UNORMVIRGL_CCMD_SET_RENDER_CONDITIONVIRGL_FORMAT_R16G16B16A16_UNORMVIRGL_OBJ_SHADER_OFFSET 3VIRGL_CAP_MULTI_DRAW_INDIRECT (1 << 21)VIRGL_CCMD_BIND_SAMPLER_STATESVIRGL_FORMAT_L8A8_SNORMVIRGL_SET_UNIFORM_BUFFER_SIZE 5VIRGL_OBJ_BIND_HANDLE 1VIRGL_COPY_TRANSFER3D_SYNCHRONIZED 14VIRGL_FORMAT_R8G8B8_UNORMres_handleVIRGL_FORMAT_L32_FLOATvertexbuffermax_aliased_line_widthVIRGL_FORMAT_YV12max_shader_image_other_stagesVIRGL_FORMAT_YV16VIRGL_FORMAT_R8G8B8A8_UINTVIRGL_BIND_MINIGBM_PROTECTED (0xf << 28)VIRGL_TRANSFER3D_DATA_OFFSET 12xferprim_maskres_createmax_shader_buffer_other_stagesVIRGL_OBJ_RS_S0_FILL_FRONT(x) (((x) & 0x3) << 10)ATOMIC_FLAG_INIT { 0 }VIRGL_OBJ_DSA_S0_ALPHA_FUNC(x) (((x) & 0x7) << 9)VIRGL_FORMAT_L16A16_FLOATatomic_store(PTR,VAL) atomic_store_explicit (PTR, VAL, __ATOMIC_SEQ_CST)virgl_resolve_format_and_use_flagsVIRGL_FORMAT_R32G32_FLOATVIRGL_OBJ_RS_S0_DEPTH_CLIP(x) (((x) & 0x1) << 1)original_heightVIRGL_BIND_STREAM_OUTPUT (1 << 11)max_render_targetsVIRGL_RESOURCE_Y_0_TOP (1 << 0)max_compute_work_group_invocationsVIRGL_SET_STREAMOUT_TARGETS_APPEND_BITMASK 1VIRGL_BIND_MINIGBM_CAMERA_WRITE (1 << 24)VIRGL_SET_BLEND_COLOR_SIZE 4strstrVIRGL_FORMAT_R8G8B8X8_UINTderivative_controlmax_texel_offsetVIRGL_FORMAT_BPTC_RGBA_UNORMcmd_sizedepth_clip_disableVIRGL_OBJ_VERTEX_ELEMENTS_V0_SRC_OFFSET(x) (((x) * 4) + 2)VIRGL_SET_VERTEX_BUFFER_OFFSET(x) (((x) * 3) + 2)VIRGL_QUERY_RESULT_QBO_RESULT_TYPE 4VIRGL_FORMAT_DXT3_RGBAVIRGL_CMD_BLIT_S0 1VIRGL_FORMAT_L8A8_UINTVIRGL_FORMAT_R16G16B16X16_SNORMVIRGL_CMD_BLIT_SRC_LEVEL 14indep_blend_funcdrm_rc_blobVIRGL_CCMD_CLEAR_TEXTUREVIRGL_OBJ_SAMPLE_STATE_S0_MAG_IMG_FILTER(x) (((x) & 0x3) << 13)VIRGL_OBJ_VERTEX_ELEMENTS_V0_INSTANCE_DIVISOR(x) (((x) * 4) + 3)VIRGL_CAP_INDIRECT_INPUT_ADDR (1 << 25)VIRGL_OBJ_CLEAR_BUFFERS 1max_vertex_outputsmax_image_samplesVIRGL_CMD_BLIT_DST_LEVEL 5VIRGL_CAP_BGRA_SRGB_IS_EMULATED (1 << 29)VIRGL_CMD_BLIT_DST_D 12transform_feedback_overflow_queryhandle_flagVIRGL_FORMAT_R10G10B10X2_UNORMVIRGL_CCMD_SET_CLIP_STATEatomic_load(PTR) atomic_load_explicit (PTR, __ATOMIC_SEQ_CST)_STDATOMIC_H VIRGL_TEXTURE_HANDLE 1VIRGL_FORMAT_DXT5_SRGBAvirgl_bo_createcube_map_arrayVIRGL_OBJ_SAMPLER_VIEW_BUFFER_LAST_ELEMENT 5VIRGL_TEXTURE_SRC_W 6VIRGL_POLYGON_STIPPLE_SIZE 32VIRGL_OBJ_SURFACE_TEXTURE_LAYERS 5virgl_bo_create_blobmirror_clampdrm_virtgpu_resource_createVIRGL_OBJ_SAMPLE_STATE_S0_WRAP_S(x) (((x) & 0x7) << 0)drm_virtgpu_3d_transfer_to_hostvirgl_2d_dumb_bo_createcap_set_verVIRGL_OBJ_RS_SPRITE_COORD_ENABLE 4VIRGL_FORMAT_B5G6R5_UNORMVIRGL_CMD_RCR_DST_Y 4VIRGL_OBJ_RS_S0_OFFSET_LINE(x) (((x) & 0x1) << 18)atomic_flag_clear(PTR) __atomic_clear ((PTR), __ATOMIC_SEQ_CST)VIRGL_STENCIL_REF_VAL(f,s) ((f & 0xff) | (((s & 0xff) << 8)))min_aliased_point_sizeVIRGL_BIND_LINEAR (1 << 22)VIRGL_CMD0(cmd,obj,len) ((cmd) | ((obj) << 8) | ((len) << 16))VIRGL_CAP_INDIRECT_PARAMS (1 << 22)VIRGL_FORMAT_NV12drm_virtgpu_get_capsVIRGL_RENDER_CONDITION_MODE 3new_itemsrealloc__builtin_memcpyallocationsitemitem_size/source/platform/minigbm/drv_array_helpers.c/source/platform/minigbm/msm.c/source/platform/minigbm/mediatek.cdumb_driver_initINIT_DUMB_DRIVER(driver) INIT_DUMB_DRIVER_WITH_NAME(driver, #driver)INIT_DUMB_DRIVER_WITH_NAME(driver,_name) const struct backend backend_ ##driver = { .name = _name, .init = dumb_driver_init, .bo_create = drv_dumb_bo_create, .bo_create_with_modifiers = dumb_bo_create_with_modifiers, .bo_destroy = drv_dumb_bo_destroy, .bo_import = drv_prime_bo_import, .bo_map = drv_dumb_bo_map, .bo_unmap = drv_bo_munmap, .resolve_format_and_use_flags = drv_resolve_format_and_use_flags_helper, };/source/platform/minigbm/dumb_driver.cdumb_bo_create_with_modifiers/source/platform/minigbm/gbm_helpers.c/source/platform/minigbm/rockchip.c/source/platform/minigbm/amdgpu.cout_unlockCROSS_DOMAIN_CHANNEL_RING 1ring_handleCAPSET_CROSS_FAKE 30cross_domain_bo_createfree_privatenum_bo_handlesCROSS_DOMAIN_ID_TYPE_VIRTGPU_SYNC 2cachedCROSS_DOMAIN_CMD_SEND 4/source/platform/minigbm/virtgpu_cross_domain.cexeccross_domain_privateVIRTGPU_CROSS_DOMAIN_PROTOCOL_H ring_addrcross_domain_get_emulated_metadatasupports_external_gpu_memoryCROSS_DOMAIN_CHANNEL_TYPE_WAYLAND 0x0001CROSS_DOMAIN_QUERY_RING 0ring_idCROSS_DOMAIN_ID_TYPE_WRITE_PIPE 4fence_fdcross_domain_submit_cmdCROSS_DOMAIN_CMD_RECEIVE 5channel_typedrm_virtgpu_execbufferCROSS_DOMAIN_CMD_INIT 1CROSS_DOMAIN_CMD_POLL 3CAPSET_CROSS_DOMAIN 5CrossDomainGetImageRequirementsfence_ctx_idxdrm_virtgpu_context_set_paramwait_3dcross_domain_metadata_queryCROSS_DOMAIN_ID_TYPE_VIRTGPU_BLOB 1CROSS_DOMAIN_ID_TYPE_READ_PIPE 3num_paramscurrentremaining_sizecross_domain_capsmetadata_cache_lockcross_domain_initsupported_channelsCROSS_DOMAIN_CHANNEL_TYPE_CAMERA 0x0002CrossDomainCapabilitiessupports_dmabufCROSS_DOMAIN_CMD_READ 6cross_domain_closeCrossDomainHeaderCrossDomainInitCROSS_DOMAIN_RING_NONE 0xffffffffcross_domain_release_privatecmd_get_reqscommandctx_set_paramsCROSS_DOMAIN_CMD_WRITE 7drm_virtgpu_context_initcross_domain_bo_mapcmd_initCROSS_DOMAIN_CMD_GET_IMAGE_REQUIREMENTS 2cached_datametadata_equalmetadata_cacheCROSS_DOMAIN_MAX_IDENTIFIERS 4 .U. ^ U [ ^m P V P P  P  V / P/ 3 V3 8 PV Z PZ [ Ve i Pi \ 8 \ V S  SSnPnA \ \ P8 V \PP V V8 I VI V SNn n S . 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@R.crtstuff.cderegister_tm_clones__do_global_dtors_auxcompleted.7325__do_global_dtors_aux_fini_array_entryframe_dummy__frame_dummy_init_array_entryminigbm_helpers.cdri_node_numfd_node_numradeon_igp_idstry_drm_devicesvirtgpu.cvirtgpu_initdrv_helpers.clayout_from_formatpacked_8bpp_layoutpacked_2bpp_layouttriplanar_yuv_420_layoutpacked_1bpp_layoutpacked_3bpp_layoutbiplanar_yuv_p010_layoutpacked_4bpp_layoutbiplanar_yuv_420_layout__PRETTY_FUNCTION__.6531__PRETTY_FUNCTION__.6537__PRETTY_FUNCTION__.6543__PRETTY_FUNCTION__.6550__PRETTY_FUNCTION__.6569__PRETTY_FUNCTION__.6589dri.cgbm.c__PRETTY_FUNCTION__.5374__PRETTY_FUNCTION__.5396vc4.cvc4_bo_create_for_modifiervc4_bo_create_with_modifiersmodifier_order.5945vc4_bo_createvc4_initrender_target_formatstexture_only_formatsvc4_bo_mapi915.ci915_info_from_device_idi915_bo_invalidatei915_bo_mapi915_bo_create_from_metadatai915_closei915_initgen_modifier_orderscanout_render_formatsxe_lpdp_modifier_ordergen12_modifier_ordergen11_modifier_orderi915_num_planes_from_modifier__PRETTY_FUNCTION__.7086i915_bo_importi915_bo_compute_metadata__PRETTY_FUNCTION__.7076i915_bo_flushdrv.cdrv_bo_acquiredrv_bo_get_plane_offset.part.0__PRETTY_FUNCTION__.6814drv_backend_list__PRETTY_FUNCTION__.6777__PRETTY_FUNCTION__.6748__PRETTY_FUNCTION__.6783__PRETTY_FUNCTION__.6789__PRETTY_FUNCTION__.6819__PRETTY_FUNCTION__.6824__PRETTY_FUNCTION__.6850__PRETTY_FUNCTION__.6809virtgpu_virgl.cvirgl_get_emulated_metadatavirgl_get_emulated_transfers_paramsvirgl_resource_infotranslate_formatvirgl_bo_destroyvirgl_closevirgl_get_max_texture_2d_sizevirgl_supports_combination_natively.isra.3virgl_resolve_format_and_use_flagsvirgl_supports_combination_through_emulation.isra.4virgl_bo_flush__PRETTY_FUNCTION__.7387virgl_bo_invalidate__PRETTY_FUNCTION__.7373virgl_bo_create__PRETTY_FUNCTION__.7247virgl_add_combinationvirgl_initdumb_texture_source_formatsvirgl_bo_mapvirgl_bo_create_with_modifiersdrv_array_helpers.c__PRETTY_FUNCTION__.2813__PRETTY_FUNCTION__.2819__PRETTY_FUNCTION__.2828msm.cmediatek.cdumb_driver.cdumb_driver_initdumb_bo_create_with_modifiersrockchip.camdgpu.cvirtgpu_cross_domain.ccross_domain_submit_cmdcross_domain_bo_mapcross_domain_release_private.isra.1cross_domain_closecross_domain_initcross_domain_bo_create__FRAME_END__backend_radeondrv_preloaddrv_dumb_bo_create_exgbm_convert_usagedrv_gem_bo_destroybackend_rockchipdrv_modify_combinationdrv_bo_create_with_modifiersdrv_add_combinationbackend_vc4drv_resolve_format_and_use_flagsdrv_pick_modifierdrv_bo_get_formatdrv_bo_newdrv_bo_get_format_modifiervirtgpu_cross_domaindrv_get_fddrv_num_buffers_per_bodrv_get_protdrv_get_namedrv_get_max_texture_2d_sizedrv_bo_get_heightdrv_add_combinations_finidrv_bo_from_formatbackend_i915drv_num_planes_from_formatdrv_dumb_bo_createdrv_bo_flush_or_unmapdrv_get_standard_fourccdrv_modify_linear_combinationsdrv_height_from_formatdrv_resource_infodrv_destroydrv_size_from_formatbackend_udlbackend_komedadrv_bo_get_plane_sizedrv_bo_unmapdrv_array_sizedrv_has_modifiervirtgpu_virglbackend_mediatekdrv_bo_createdrv_bo_destroy__dso_handledrv_bo_get_num_planesdrv_bo_get_widthdrv_vertical_subsampling_from_formatdrv_bo_get_plane_offsetbackend_nouveaudrv_bo_from_format_and_paddingdrv_bo_get_total_sizedrv_get_combinationdrv_bo_get_plane_fdbackend_virtgpudrv_bo_get_plane_handledrv_bo_flushdrv_bo_get_use_flagsdrv_dumb_bo_destroydrv_array_appendcross_domain_get_emulated_metadata_DYNAMICdrv_bo_importbackend_mesondrv_bo_munmapdrv_array_destroydrv_prime_bo_importdrv_createdrv_bo_mapbackend_synapticsdrv_array_initdrv_bo_get_tilingbackend_marvelldrv_bo_invalidatedrv_bytes_per_pixel_from_formatdrv_num_planes_from_modifierdrv_array_at_idx__GNU_EH_FRAME_HDRdrv_log_prefix__TMC_END___GLOBAL_OFFSET_TABLE_backend_sun4i_drmbackend_vkmsdrv_dumb_bo_mapdrv_bo_get_plane_stridedrv_stride_from_formatdrv_resolve_format_and_use_flags_helperdrv_array_removebackend_evdigetenv@@GLIBC_2.2.5free@@GLIBC_2.2.5gbm_bo_get_plane_countgbm_bo_get_stride_for_plane__errno_location@@GLIBC_2.2.5strncmp@@GLIBC_2.2.5_ITM_deregisterTMCloneTablestdout@@GLIBC_2.2.5drmPrimeHandleToFDgbm_surface_destroydrmFreeVersiongbm_surface_creategbm_bo_set_user_datareadlink@@GLIBC_2.2.5drmModeGetResourcesdrmModeGetConnectordrmDropMasteropendir@@GLIBC_2.2.5strlen@@GLIBC_2.2.5gbm_bo_get_devicegbm_bo_import__stack_chk_fail@@GLIBC_2.4drmHashDestroygbm_bo_create_with_modifiersgbm_bo_mapgbm_bo_get_plane_fdgbm_bo_get_formatpthread_mutex_destroy@@GLIBC_2.2.5snprintf@@GLIBC_2.2.5__assert_fail@@GLIBC_2.2.5gbm_device_get_fdgbm_device_destroygbm_surface_has_free_buffersgbm_bo_get_offsetgbm_bo_get_fd_for_planegbm_surface_lock_front_buffergbm_bo_unmapclose@@GLIBC_2.2.5gbm_create_devicegbm_bo_destroyclosedir@@GLIBC_2.2.5gbm_bo_get_bppread@@GLIBC_2.2.5calloc@@GLIBC_2.2.5strcmp@@GLIBC_2.2.5gbm_bo_get_handlebasename@@GLIBC_2.2.5gbm_surface_release_buffer__gmon_start__gbm_bo_get_heightstrtol@@GLIBC_2.2.5memcpy@@GLIBC_2.14minigbm_create_default_devicedrmHashLookupmmap64@@GLIBC_2.2.5gbm_bo_get_plane_sizepthread_mutex_unlo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