ELFH@@75$  "%s rate: %lu", __get_str(name), (unsigned long)REC->rateNNfreq enable3Call set rate on the PLL with rounded rates! %s: didn't enable after voting for it! 3Invalid RCG parent rate 4Failed to get the parent's (%s) rounded rate %s state (after %d us timeout): 0x%x, GDS_HW_CTRL: 0x%x. Re-polling. drivers/clk/qcom/clk-pll.cdisablePLL_USER_CTL3Failed to regmap update cfg Couldn't get regmap %s: rcg didn't turn on.ff3%s: Can't find parent with src %d parentcore_root_clkcommon:99:(desc->config)->lock3alpha pll: not in a valid vco range 3alpha_pll: call clk_set_rate with rounded rates! PLL_L_VAL3Invalid MN values derived for requested rate %lu qcom,support-hw-triggerUnable to get vdd_parent regulator, ret=%d Failed to get root clock name 3Error reading mccc period register, ret = %d sleep_clk_srcdomain-addrFailed to get address resource %s final state (after additional %d us timeout): 0x%x, GDS_HW_CTRL: 0x%x PLL_TEST_CTL_U%s: PLL latch failed. Output may be unstable! M_VALvdd_parent%s final state: 0x%x (%d us after timeout) drivers/clk/qcom/clk-debug.cPLL_MODEgdscparent-supplyregulator_register("%s") failed, ret=%d 3Missing the post_div_table for the PLL 3Please check if `measure` clk is registered. 3invalid index %u PLL_FRAC%s: %s: rcg didn't update its configuration.qcom,no-config-gdscrFailed to get bus config data bus scaling failed, ret=%d APSS_PLL_VOTEPLL_USER_CTL_U4%s: PLL configuration lost, reconfiguration of PLL done. 3Failed to lock after L_VAL update qcom,msm-bus,nameclk_debug_lock.wait_lockPLL_CONFIG_CTL_UPLL_TEST_CTLregulator-namenameunsigned longD_VAL3Failed to scale %s to %lu %s: latch ackPLL_USER_CTL_U13Failed to update DFS tables for %s %20s: 0x%.8x qcom,retain-periphgdsc_regulator:765:(&gdsc_regmap_config)->lock3Requested rate (%lu) not matching the PLL's supported frequency (%lu) %s: PLL Update clear failed %s: status stuck at 'o%s'3Failed to map %s (ret=%ld) PLL_TEST_CTL_U1sw-reset%s rate: %lu %lld /clocksPLL_ALPHA_VAL3PLL lock bit detection total wait time: %lld ns 3CFG_RCGR old frequency configuration 0x%x ! 3%s: CXO configuration failed qcom,gds-timeoutreset-namesqcom,clk-dis-wait-valclk_reg_lockdrivers/clk/qcom/trace.hPLL_ALPHA_VAL_U3alpha pll calibration failed PLL_N_VALqcom,skip-disable-before-sw-enable%s enable timed out 4PLLs parent rate hasn't been initialized. update3Failed to update the div value CMD_RCGRnFailed to get reset clock names Failed to get %s, ret=%d 6Dumping %s Registers: drivers/clk/qcom/clk-branch.cPLL_STATUSCBCRqcom,retain-regs4PLL configuration lost, reconfiguration of PLL done. 3%s: RCG configuration is pending 3%s: Can't find parent %d %s disable timed out: 0x%x PLL_CONFIG_CTL_U1N_VALqcom,reset-aon-logicrateclk_debug_lock4------------[ cut here ]------------ drivers/clk/qcom/clk-regmap-mux-div.c3PLL configuration missing. PLL_OPMODE3alpha_pll: Call clk_set_rate with rounded rates! 3Failed to update pre_div in determine rate 3Failed to get GDSC Handle qcom,enable-root-clk%s enable timed out: 0x%x drivers/clk/qcom/clk-alpha-pll.c__data_loc char[]clk_measuresleep_clkPLL_STATUS_CTL6%20s: 0x%.8x 3SET_RATE_PARENT flag needs to be set for %s qcom,force-enable-root-clkvdd_parent-supplyInvalid enable while %s is under HW control (null)3Failed to set the debug mux's parent. drivers/clk/qcom/clk-rcg2.cenable%s: failed to %s! update_ack_clear3DFS register failed for clk %s Failed to get clock names, ret=%d PLL_CONFIG_CTLCFG_RCGRclock-namesqcom,disallow-clearPLL_CAL_L_VAL3alpha pll: no valid parent found 6GDSCR: 0x%.8x CFG: 0x%.8x CFG2: 0x%.8x hw-ctrl-addrqcom,no-status-check-on-disableupdate_ack_set3clock needs to be gated %s 3Failed to configure %s PLL_M_VAL3Failed to read %s registers qcom,retain-memFailed to register bus client 3alpha pll not in a valid vco range qcom,skip-logic-collapseoffline   $ $  $  $,8@  $(,08  $8( ,       ?3 <2xwg4' 9?3 2/dk qcom,gdscclk_qcom @ @@{WO**R****i)]S#9*/2***RR***OBWA{è_{O*qkT**@9?3kT AT OA{¨_ A)?cT_` @I?T Ai__{O*qT***@9_3kT) AT OA{¨_{!BR{_{WOC@ RR r_ JT+5RR r C+R  _)@?TOGWF{E_{{_{og_WO:A;@@RR r@vB ) $@ @ B` X*`4*_@"@hRR r`@ "@*`5!4 @@* @7R~@ Tzha hD `16R~@ T!{ha4* Z6R `5~@_iTu{hu`@!OEWD_CgBoA{ƨ_`nB{WO@@@6R~@Tzha hD `nBOBWA{è_{*G @* _T?T 9@ ya`{_5@)ya {_{_{ O@R*@?BTc@_?T*OB @*{è_{O@R*@?BT@OA{¨_{O`@`OA{¨_{C@@a*@@5@j.@i@9H qi4 @)@?T@{A_{ @9@E)?qC**{_{ @9@E)?q**{_{ OB@4@@@9! @4@@ @9! @4@@!@9! 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tab_clk_debug_measure_add__ksymtab_clk_debug_measure_adddebugfs_attr_readsimple_attr_readregmap_readregmap_bulk_readdevm_kmallocperf_trace_buf_allocrdev_get_drvdataregulator_get_drvdatamsm_bus_cl_get_pdataof_get_regulator_init_dataclk_agera_pll_list_registers.dataclk_fabia_pll_list_registers.dataclk_alpha_pll_list_registers.dataclk_alpha_pll_lucid_list_registers.data$d.499$d.399$x.299$x.199$x.99$d.489$d.389$x.289$x.189$x.89$d.479$d.379$x.279$x.179$x.79$d.569$d.469$x.369$x.269$x.169$d.69$d.559$d.459$d.359$x.259$x.159$d.59$d.549$d.449$x.349$x.249$x.149$d.49.Ltmp39$d.539$d.439$x.339$x.239$x.139$d.39$d.529$d.429$x.329$x.229$x.129$d.29$d.519$d.419$x.319$d.219$x.119$d.19$d.509$d.409$x.309$x.209$x.109$d.9.Ltmp8$d.498$d.398$x.298$x.198$x.98$d.488$d.388$x.288$x.188$x.88$d.478$d.378$d.278$x.178$x.78__UNIQUE_ID_license68$d.568$d.468$d.368$x.268$d.168$d.68$d.558$d.458$x.358$x.258$x.158$d.58$d.548$d.448$x.348$x.248$x.148$d.48$d.538$d.438$x.338$x.238$x.138$d.38$d.528$d.428$x.328$x.228$x.128$d.28$d.518$d.418$x.318$x.218$x.118$d.18$d.508$d.408$x.308$x.208$x.108$d.8$d.497$d.397$x.297$x.197$x.97$d.487$d.387$x.287$x.187$x.87$d.477$d.377$x.277$x.177$d.77$d.567$d.467$x.367$x.267$x.167$d.67$d.557$d.457$d.357$x.257$x.157$d.57$d.547$d.447$x.347$x.247$x.147$d.47$d.537$d.437$x.337$x.237$x.137$d.37$d.527$d.427$x.327$x.227$x.127$d.27$d.517$d.417$x.317$x.217$x.117$d.17$d.507$d.407$x.307$x.207$d.107$d.7_note_6$d.496$d.396$x.296$x.196$x.96$d.486$d.386$x.286$x.186$x.86$d.476$x.376$x.276$x.176$d.76$d.566$d.466$x.366$x.266$x.166$d.66$d.556$d.456$x.356$x.256$x.156$d.56.Ltmp46$d.546$d.446$x.346$x.246$x.146$d.46.Ltmp36$d.536$d.436$x.336$x.236$x.136$d.36$d.526$d.426$x.326$x.226$x.126$d.26$d.516$d.416$x.316$x.216$x.116$d.16$d.506$d.406$x.306$x.206$d.106$d.6.Ltmp5$d.495$d.395$x.295$x.195$x.95$d.485$d.385$x.285$x.185$x.85$d.475$x.375$x.275$x.175gdsc_disable.175$d.75$d.565$d.465$x.365$x.265$x.165$d.65.Ltmp55$d.555$d.455$x.355$x.255$x.155$d.55$d.545$d.445$x.345$x.245$x.145$d.45$d.535$d.435$x.335$x.235$x.135$d.35$d.525$d.425$x.325$x.225$x.125$d.25$d.515$d.415$x.315$x.215$x.115$d.15$d.505$d.405$x.305$x.205$x.105$d.5$d.494$d.394$x.294$x.194$x.94$d.484$d.384$x.284$x.184$x.84$d.474$x.374$x.274gdsc_enable.174$d.174$d.74$d.564$d.464$x.364$x.264$x.164$d.64$d.454$x.354$x.254$x.154$d.54$d.544$d.444$d.344$x.244$x.144$d.44$d.534$d.434$x.334$x.234$x.134$d.34$d.524$d.424$x.324$x.224$x.124$d.24$d.514$d.414$x.314$x.214$x.114$d.14$d.504$d.404$x.304$x.204$x.104$d.4$d.493$d.393$x.293$x.193$x.93$d.483$d.383$x.283$x.183$x.83$d.473$x.373$x.273$x.173$d.73$d.563$d.463$d.363$x.263$x.163$d.63__UNIQUE_ID_intree53$d.453$x.353$x.253$x.153$d.53$d.543$d.443$x.343$x.243$x.143$d.43.Ltmp33$d.533$d.433$x.333$x.233$d.133$d.33$d.523$d.423$x.323$x.223$x.123$d.23$d.513$d.413$x.313$x.213$x.113$d.13$d.503$d.403$x.303$x.203$x.103$d.3.Ltmp2bpf_trace_run2$d.492$d.392$x.292$x.192$x.92$d.482$d.382$x.282$x.182$x.82$d.472$x.372$x.272$d.172$d.72.Ltmp62$d.562$d.462$x.362$x.262$x.162$d.62__UNIQUE_ID_name52$d.452$x.352$x.252$x.152$d.52$d.542$d.442$x.342$x.242$x.142$d.42$d.532$d.432$x.332$x.232$x.132$d.32$d.522$d.422$x.322$x.222$x.122$d.22$d.512$d.412$x.312$x.212$x.112wait_for_pll.12$d.12$d.502$d.402$x.302$x.202$x.102$d.2$d.491$d.391$x.291$x.191$x.91$d.481$d.381$x.281$x.181$x.81$d.571$d.471$x.371$x.271$x.171$d.71$d.561$d.461$d.361$x.261$x.161$d.61__UNIQUE_ID_vermagic51$d.451$x.351$x.251$x.151$d.51$d.541$d.441$x.341$x.241$x.141$d.41$d.531$d.431$d.331$d.231$d.131$d.31$d.521$d.421$x.321$x.221$x.121$d.21.Ltmp11$d.511$d.411$x.311$x.211$x.111$d.11$d.501$d.401$d.301$x.201$x.101$d.1$d.490$d.390$x.290$x.190$x.90$d.480$d.380$x.280$x.180$x.80$d.570$d.470$x.370$x.270$d.170$d.70$d.560$d.460$x.360$x.260$d.160_freq_tbl_determine_rate.60$d.60$d.450$x.350$x.250$x.150$d.50$d.540$d.440$x.340$x.240$x.140$d.40.Ltmp30$d.530$d.430$x.330$x.230$x.130$d.30$d.520$d.420$x.320$x.220$x.120$d.20$d.510$d.410$x.310$x.210$x.110$d.10$d.500$d.400$x.300$x.200$x.100$d.0@@ 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