ELF@@,)FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF %     Q spi-pl022 DMACR: %x spi-pl022 CR0: %x drivers/spi/spi-pl022.cprobe: no platform data defined no dt node defined spi-pl022 SR: %x bad message state in interrupt handlerpl022pl022,autosuspend-delayCommunication mode is configured incorrectly /mnt/disks/build-disk/src/android/common-android14-5.15/out/bazel/output_user_root/c126e7d3c13484ebc27ab7dd47bee034/sandbox/linux-sandbox/33/execroot/__main__/common/include/linux/dmaengine.hrxmessage of %u bytes to transmit but the current chip bus has a data width of %u bytes! read %u surplus bytes (did you request an odd number of bytes on a 16bit bus?) could not enable SSP/SPI bus clock pl022,wait-statecontroller data is incorrect%s: timeout! probe - cannot alloc SPI master mapped registers from %pa to %p TX FIFO Trigger Level is configured incorrectly Requested frequency: %d Hz is less than minimum possible %d Hz RX FIFO Trigger Level is configured incorrectly setup for DMA on RX %s, TX %s RXFIFO is full cpsdvsr is configured incorrectly pl022,ctrl-lenpl022: Matching cpsdvsr and scr not found for %d Hz rate Microwire half duplex mode requested, but this is only available in the ST version of PL022 problem resuming pl022,com-modeMax speed that can be programmed is %d Hz, you requested %d FIFO overrun probe - cannot get IRQ (%d) illegal data size for this controller! spi-pl022 CR1: %x interface is configured incorrectly ssp-pl022pl022,duplexFailed to work in dma mode, work without dma! probe - problem registering spi master unidirectional mode not supported in this hardware version txhierarchy is configured incorrectly CTRL LEN is configured incorrectly pl022,tx-level-trigWait State is configured incorrectly spi-pl022 exp_fifo_level/fifodepth: %u/%d ARM PL022 driver, device ID: 0x%08x This controller can only handle 4 <= n <= %d bit words do_polling_transferpl022,rtMicrowire duplex mode is configured incorrectly skipping this message could not retrieve SSP/SPI bus clock will use autosuspend for runtime pm, delay %dms pl022,interfacepl022,rx-level-trig0X(D`0X  ""#"` 'void (struct dma_chan *)''int (struct dma_chan *, struct dma_slave_config *)''struct dma_async_tx_descriptor *(struct dma_chan *, struct scatterlist *, unsigned int, enum dma_transfer_direction, unsigned long, void *)''int (struct dma_async_tx_descriptor *)''int (struct dma_chan *)' ҈$ȇhVTҨ#,Thܧ~(\ T(ȭt(@ THɈnHxHA Tb҈(alT҈$ȇhVT҈("1@T$h5hdTGҨ#TW(`Th{(AT2(҈(aTHh(T[hT( ȓT  ?T_?#{@9qT{#_ )+ih8J @@*?#{ WOD!H@uzA RR` @9R!2 y#R9!9 R*L@ J )@@y 8 J D)R@y  J 9 R@99hzA @9 x@%@9qRH*5hA aAhAw*OCWB @{Ĩ#_!w!!WbB!?T5!2@@y1 =@y) @)(ya*DB7*1`T5 @92 @964 @9 9vN 5"@_qTR*!*!*!* *! @9h6@{!"@!RH?#{ OL@ )R)h@ @9h6u@`h")R);;OB @{è#_ }_) } 5 }_) } 5@ )@9i42iQR @ 2 R @ y %@92 @I4iQRr 2 R @ yiQR y2 R @ y2* @ R)(y2 @)A*y2 @)Q(y2iR @ y_?#{WOC9h4uK@@vKB@?ֈ@@uKB@?hb@b@#R@M9@CRL_ @@9@9`b@@`^@@`v@OBWA{è#_?#{A{#_?#C{#g_WOA8%CC4AN9AM@xARR@zAH'@9H5H+@95 @uC(R |Iӈ@r|A(}_k`#*Tk*T***HR** kTJk _qAT  kTk ** **qhT K4) 5*!KE5R)R!#RVWcXCB3!#R!#RBS!#R!#RBs!#R!#RH'@95uZH'@94H@x}S9 qITI@? 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