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A value of '1' or '2' forces the corresponding stage. All other values are ignored (i.e. no stage is forced). Note that selecting a specific stage will disable support for nested translation.parmtype=disable_bypass:boolparm=disable_bypass:Disable bypass streams such that incoming transactions from devices that are not attached to an iommu domain will report an abort back to the device and will not be allowed to pass through the SMMU.description=IOMMU API for ARM architected SMMU implementationsauthor=Will Deacon alias=platform:arm-smmulicense=GPL v2vermagic=6.8.0-mainline-g830a3b57edc6-ab11649714 SMP preempt mod_unload modversions aarch64name=arm_smmuintree=Yscmversion=g830a3b57edc6depends=qcom-scmalias=of:N*T*Carm,smmu-v1alias=of:N*T*Carm,smmu-v1C*alias=of:N*T*Carm,smmu-v2alias=of:N*T*Carm,smmu-v2C*alias=of:N*T*Carm,mmu-400alias=of:N*T*Carm,mmu-400C*alias=of:N*T*Carm,mmu-401alias=of:N*T*Carm,mmu-401C*alias=of:N*T*Carm,mmu-500alias=of:N*T*Carm,mmu-500C*alias=of:N*T*Ccavium,smmu-v2alias=of:N*T*Ccavium,smmu-v2C*alias=of:N*T*Cnvidia,smmu-500alias=of:N*T*Cnvidia,smmu-500C*alias=of:N*T*Cqcom,smmu-v2alias=of:N*T*Cqcom,smmu-v2C*N N N failed to allocate arm_smmu_device probing hardware configuration... rs.lockstream ID 0x%x out of range for SMMU (0x%x) PAR = 0x%llx arm-smmu global faultfailed to request global IRQ %d (%u) smmu.%pafound %d interrupts but expected at least %d __arm_smmu_tlb_syncmmu-masters Stage-1: %lu-bit VA -> %lu-bit IPA failed to get clocks %d Failed to register iommu Stage-2: %lu-bit IPA -> %lu-bit PA qcom,msm8996-smmu-v2found only %d context irq(s) but %d required simpossible number of S2 context banks! stage 2 translation &smmu->stream_map_mutexnvidia,tegra234-smmu address translation ops _rs.lock preserved %d boot mapping%s enabling workaround for Cavium erratum 27704 not probing due to mismatched DT properties stream-match-mask (IDR0.CTTW overridden by FW configuration) SMR mask 0x%x out of range for SMMU (0x%x) failed to allocate %d irqs #global-interruptsnvidia,tegra186-smmu&smmu_domain->cb_lock GFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x 5arm-smmu: deprecated "mmu-masters" DT property in use; %s support unavailable SMMU stage 1 translation %u context banks (%u stage-2 only) failed to set DMA mask for table walker Unexpected global fault, this could be serious Limiting the stream matching groups to 128 nested translation disabling translation arm-smmu-context-faultUnhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d Failed to disable prefetcher [errata #841119 and #826419], check ACR.CACHE_LOCK calxeda,smmu-secure-config-accessarm_smmu_global_faultarm_smmu_context_faultSMMUv%d with: %scoherent table walk SMMU address space size (0x%x) differs from mapped region size (0x%x)! &smmu->global_sync_lockmarvell,ap806-smmu-500Missing qcom_smmu_impl_of_match entry for: %sstream-matching supported, but no SMRs present! &smmu_domain->init_mutexfailed to request context IRQ %d (%u) Failed to turn off SAFE logic arm-smmumissing #global-interrupts property translation fault! Failed to register iommu in sysfs no translation support! Supported page sizes: 0x%08lx Blocked unknown Stream ID 0x%hx; boot with "arm-smmu.disable_bypass=0" to allow, but this may have security implications stream matching with %u register groupsnvidia,tegra194-smmunon-TLB sync timed out -- SMMU may be deadlocked iova to phys timed out on %pad. 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