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g@?#{{#_drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.cdrivers/gpu/drm/msm/adreno/a5xx_gpu.cdrivers/gpu/drm/msm/disp/dpu1/dpu_plane.cdrivers/gpu/drm/msm/adreno/a6xx_gpu_state.cdrivers/gpu/drm/msm/adreno/adreno_device.cdrivers/gpu/drm/msm/msm_fence.cdrivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.cdrivers/gpu/drm/msm/disp/mdp5/mdp5_kms.hdrivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.cdrivers/gpu/drm/msm/msm_gem.hdrivers/gpu/drm/msm/disp/mdp5/mdp5.xml.hdrivers/gpu/drm/msm/disp/dpu1/dpu_crtc.cinclude/linux/mmap_lock.hdrivers/gpu/drm/msm/adreno/a3xx_gpu.cdrivers/gpu/drm/msm/msm_gpu_trace.hdrivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.cinclude/linux/thread_info.hdrivers/gpu/drm/msm/msm_gem_submit.cdrivers/gpu/drm/msm/disp/mdp_format.cdrivers/gpu/drm/msm/disp/mdp4/mdp4_plane.cdrivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.cdrivers/gpu/drm/msm/disp/dpu1/dpu_kms.cdrivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.cdrivers/gpu/drm/msm/msm_drv.cdrivers/gpu/drm/msm/msm_gem_vma.cdrivers/gpu/drm/msm/disp/mdp5/mdp5_kms.cdrivers/gpu/drm/msm/msm_iommu.cdrivers/gpu/drm/msm/adreno/a4xx_gpu.cdrivers/gpu/drm/msm/adreno/a6xx_gpu.cdrivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.cdrivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.cdrivers/gpu/drm/msm/msm_atomic_trace.hdrivers/gpu/drm/msm/adreno/a6xx_hfi.cinclude/drm/drm_modeset_lock.hdrivers/gpu/drm/msm/disp/mdp4/mdp4_kms.hdrivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.cdrivers/gpu/drm/msm/msm_gpu.cdrivers/gpu/drm/msm/adreno/a6xx_gmu.cdrivers/gpu/drm/msm/disp/mdp4/mdp4.xml.hdrivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.cdrivers/gpu/drm/msm/disp/mdp_kms.cdrivers/gpu/drm/msm/msm_atomic.cdrivers/gpu/drm/msm/hdmi/hdmi_i2c.cdrivers/gpu/drm/msm/disp/msm_disp_snapshot.cdrivers/gpu/drm/msm/dp/dp_drm.cinclude/linux/local_lock_internal.hdrivers/gpu/drm/msm/msm_kms.cdrivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.cdrivers/gpu/drm/msm/disp/dpu1/dpu_trace.hdrivers/gpu/drm/msm/disp/mdp5/mdp5_plane.cdrivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.cdrivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.cdrivers/gpu/drm/msm/disp/dpu1/dpu_encoder.cdrivers/gpu/drm/msm/msm_gem.cdrivers/gpu/drm/msm/adreno/adreno_gpu.cdrivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.cdrivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.cdrivers/gpu/drm/msm/msm_gem_prime.cdrivers/gpu/drm/msm/msm_gem_shrinker.cdrivers/gpu/drm/msm/hdmi/hdmi_hdcp.cdrivers/gpu/drm/msm/adreno/adreno_gpu.hparm=hang_debug:Dump registers when hang is detected (can be slow!)parmtype=hang_debug:boolparm=snapshot_debugbus:Include debugbus sections in GPU devcoredump (if not fused off)parmtype=snapshot_debugbus:boolparm=allow_vram_carveout:Allow using VRAM Carveout, in place of IOMMUparmtype=allow_vram_carveout:boolfirmware=qcom/a300_pm4.fwfirmware=qcom/a300_pfp.fwfirmware=qcom/a330_pm4.fwfirmware=qcom/a330_pfp.fwfirmware=qcom/a420_pm4.fwfirmware=qcom/a420_pfp.fwfirmware=qcom/a530_pm4.fwfirmware=qcom/a530_pfp.fwfirmware=qcom/a530v3_gpmu.fw2firmware=qcom/a530_zap.mdtfirmware=qcom/a530_zap.b00firmware=qcom/a530_zap.b01firmware=qcom/a530_zap.b02firmware=qcom/a540_gpmu.fw2firmware=qcom/a619_gmu.binfirmware=qcom/a630_sqe.fwfirmware=qcom/a630_gmu.binfirmware=qcom/a630_zap.mbnfirmware=qcom/a640_gmu.binfirmware=qcom/a650_gmu.binfirmware=qcom/a650_sqe.fwfirmware=qcom/a660_gmu.binfirmware=qcom/a660_sqe.fwfirmware=qcom/leia_pfp_470.fwfirmware=qcom/leia_pm4_470.fwfirmware=qcom/yamato_pfp.fwfirmware=qcom/yamato_pm4.fwparm=address_space_size:Override for size of processes private GPU address spaceparmtype=address_space_size:ullongparm=vram:Configure VRAM size (for devices without IOMMU/GPUMMU)parmtype=vram:charpparm=dumpstate:Dump KMS state on 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vbif_rt@@@wb_2Pdspp_0@dspp_1`dspp_2dspp_3%&5 #ix   top_0ctl_0P~*ctl_1`~+ctl_2p|,ctl_3|-ctl_4|.ctl_5|8sspp_0@D[sspp_1`D[sspp_2D[sspp_3D[ sspp_8 @D{sspp_9 `D{sspp_10 D{ sspp_11 D{ sspp_12 D{sspp_13D{lm_0@4lm_1P4lm_2`4lm_3p4lm_44lm_54pingpong_0 pingpong_1 pingpong_2 pingpong_3 pingpong_4?pingpong_5@pingpong_6`pingpong_7dpingpong_8 pingpong_9 merge_3d_0merge_3d_1merge_3d_2merge_3d_3gmerge_3d_4dce_0_0 dce_0_1 dce_1_0 dce_1_1 dce_2_0 dce_2_1 intf_0@ intf_1Pintf_2`intf_3p  vbif_rtt@@wb_2Pdspp_0@dspp_1`dspp_2dspp_3@f%&5 #ix  scaler csc)AR24AB24RA24BX24BA24AR30XR30XR24XB24RX24RG24BG24RG16BG16AR15AB15RA15BA15XR15XB15RX15BX15AR12AB12RA12BA12XR12XB12RX12BX12P010NV12NV21NV16NV61VYUYUYVYYUYVYVYUYU12YV12AR24AB24RA24BA24XR24RX24BX24XB24AR30XR30RG24BG24RG16BG16AR15AB15RA15BA15XR15XB15RX15BX15AR12AB12RA12BA12XR12XB12RX12BX12  P0`te2 dither0 dither0 8pjpcc[[[[ [U [U [U [U[UU   Uscaler csc) 8PhpccWW3W3W3"W3" W3"" W3"" W3""" W3""" W3""""W3""""W3"""" wfUD wfUD3 wfUD3 wfUD3"wfUD3"wfUD3#top_0\scaler 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7qcom,mdssqcom,msm8998-mdssqcom,qcm2290-mdssqcom,sdm670-mdssqcom,sdm845-mdssqcom,sc7180-mdssqcom,sc7280-mdssqcom,sc8180x-mdssqcom,sc8280xp-mdssqcom,sm6115-mdssqcom,sm6125-mdssqcom,sm6350-mdssqcom,sm6375-mdssqcom,sm8150-mdssqcom,sm8250-mdssqcom,sm8350-mdssqcom,sm8450-mdssqcom,sm8550-mdssqcom,sm8650-mdss,, , , ,0@!00,@@, ,0 ,00,@@,@@!@@AR24AB24RA24BA24XR24XB24RX24BX24RG24BG24RG16BG16NV12NV21NV16NV61VYUYUYVYYUYVYVYUYU12YV12drm_msm_atomic\, vramdumpstatemodeset ; @d Ad@ Bd Cd Dd@ Ed@ FdH Gd @ Hd Jd Kd@ Ld@ qcom,adrenoqcom,adreno-3xxamd,imageonqcom,kgsl-3d0enable_evictionrd_fullnum_hw_submissionsdrm_msm_gpup$LLLLMMM MPPPP P PPP$P*P-P0P@PSPPPPPPPPPPPPPPPQQ@Q@QBQDQLQMQOQQQTQTQWQXQ]Q]QbQbQdQeQQQQQQQQQQQQQRR@R -<=?@BIXZ@^ '@BDGL/<?D #&&(+..03668;>>@CFF+@@ T= = @ <<%%< <@<B<E<G<I<J<<<< <@<G<<<::00 000-000104060<0=0@0@0B0B0I0I0X0X0Z0a0d0h0l0m00000000000000000000011111111 1 1$1%1)1)11111T1T1V1V1X1X1Z1Z1\1\1^1^1`1`1b1b1 4 4448828<BBDDGGVV = 33@U !#$&'03@EOo    ( > B M      +0289 (+07$7 #0144prxy 00 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RBBM | ATB bus overflow cx.lvl*ERROR* %u SH0core_physicaln=%u, cts=%u, multiplier=%u *ERROR* failed to disable pwr regulator: %d *ERROR* pinctrl state chg failed: %d DDC timeout: %d hdmi_pllxo_boardcom_lock_cmp2_mode0 = 0x%x invalid pipers.lockRGB1*ERROR* Height up scaling exceeds limits! *ERROR* failed to allocate CTL manager rotator-memSTAGE_BASEscale config = %x min_llcc_ibperf_mode6[drm] normal performance mode &dpu_crtc->spin_lock&dpu_crtc->event_lock3[drm:%s:%d] [dpu error]failed to allocate state crtc%d no crtc found for encoder %d dpu_encoder_setup_displayfalsewait disable failed: id:%u intf:%d ret:%d DSC_BPG_OFFSETsblk->enc.base + DSC_RC_SCALEsblk->enc.base + DSC_RC_OFFSETS_4INTF_ACTIVE_HCTLINTF_TEAR_RD_PTR_IRQ3[dpu error]enc%d intf%d disable autorefresh failed SSPP_SRC3_ADDRbase + PCC_RED_B_OFFbase + PCC_GREEN_B_OFFMERGE_3D_MUXlut_addrtrace_namesw_event3[drm:%s:%d] [dpu error]rm init failed: %d 3[drm:%s:%d] [dpu error]plane%d failed to allocate state multirect_index[0]=%s 3[drm:%s] [dpu error]failed sspp object creation: err %d VBIF_RThangcheck_period_msis_unevictable(msm_obj)%08x: %c %2d (%2d) %08llx %p*ERROR* %s: hangcheck recover! &df->lock*ERROR* kms hw init failed: %d %sticks lclk = %lld CP_DRAW_STATECP_BV_DRAW_STATE_ADDRA6XX_SP_TMO_UMO_TAGCLUSTER_SP_VScx_dbgc - regs-name: dp_linkBefore, type=%d hpd_state=%d Requested preEmphasisLevel=%d, change to %d panel edid read failed version: %d.%d 3%s: auth prepare failed %d msm_hdmi_hdcp_recv_bksv3%s: BSTATUS read failed msm_dsi_host_initmsm_dsi_host_cmd_rx4%s:Invalid response cmd 3%s: unable to calc clk rate, %d 3%s: failed to set pinctrl default state, %d disp-teVideo test pattern setup done 3%s: dsi%d already registered dsi%d_pll_bit_clk*ERROR* qcom,phy-rescode-offset-top value %d is not in range [-32..31] &pll_7nm->postdiv_lockUsing legacy qcom,chipid binding! wptr: %u bos: fast_rate=%u, slow_rate=27000000 *ERROR* no a3xx device %s: timeout waiting for SP GDSC enable CP ucode error interrupt hfi*ERROR* Unable to power on the GPU RSC HDMI_HPDfailed to set clk %s (%d) fdata: %llu tx_l2_lane_mode = 0x%x *ERROR* modeset_init failed: %d %s: release from plane %s %s: check (%d -> %d) comp-%d (T/B): rpt=%d/%d, ovf=%d/%d, req=%d pitches[%d]:%8u (work_completion)(&(&dpu_enc->delayed_off_work)->work)id: %u, sw_event:%d, rc:%d !ON state 3[drm:%s:%d] [dpu error]enc%d failed to add phys encs dpu_encoder_virt_add_phys_encsintf CDM_CSC_10_OPMODECTL_INTF_FLUSHCTL_TOPCTL_LAYER_EXT(mixer_id)DSC_SCALE_INC_INTERVALsblk->enc.base + DSC_RC_BUF_THRESH_0sblk->enc.base + DSC_RC_MIN_QP_03invalid IRQ=[%d, %d] intr->intr_set[i].clr_offPP_VSYNC_INIT_VALout_size_offSSPP_SRC_CONSTANT_COLOR_REC1base + PCC_RED_R_OFFQSEED3_SRC_SIZE_Y_RGB_A + scaler_offsetcsc_reg_off + 0x34crtc:%d trace_beginfuncs64 %08x3[drm:%s:%d] [dpu error]device config not known! 3[drm:%s:%d] [dpu error]modeset_init failed for dsi[%d], rc = %d _dpu_kms_initialize_writeback3[drm:%s:%d] [dpu error]invalid arg(s) dpu_plane_initplane%d pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x] 3[drm:%s] [dpu error]Allocated resource %d unavailable to assign to enc %d _dpu_rm_reserve_cdmshrinkmsm_obj->pin_count < 0msm_ioctl_gem_submitmsm_gem_vma_closedrm-engine-gpu: %llu ns vddcxoffending task: %s (%s)cmdline: %s new_freq=%u purgedme size: %zu debugbus: size: %d aux status: %#x wide_bus_en=%d reg=%#x max. pre-emphasis level reached %d sink: pattern=%x failed to request IRQ%u: %d DP panel not enabled, handle TPG on next on pixel clock (KHz)=(%d) 3%s:BKSV Process failed dsi_get_phy3%s: mode not set dsi_calc_clk_rate_6g3%s: Invalid version 3%s: read data does not match with rx_buf len %zu Unable to create bridge connector dsi_mgr_bridge_power_onDSI%d PLL parent rate=%lu parent rate %lu *ERROR* %s: D-PHY timing calculation failed DSI PLL%d qcom,phy-rescode-offset-bota530_pm4.fw*ERROR* timeout waiting for space in ringbuffer %d kgsl_3d0_reg_memory*ERROR* Unable to load %s %s: zap-shader resume failed: %d The GMU is not set up yet debug*ERROR* The GMU did not go into slumber a6xx_gmu_irqfailed to get hpd regulators failed to get hpd gpio disabling audio: unsupported pixclock: %lu *ERROR* %s: failed to map phy base refsetting lcdc_clk=%lu lut_clk*ERROR* failed to construct plane for RGB%d VG1msm8x74msm8x53CTL %d FLUSH pending mask %x *ERROR* too many planes! cnt=%d, start stage=%d Release BW crtc=%d crtc=%d disable mode %d %s: send event: %pK cpp[%d]:%u autocrtc %d stage:%d - plane %d sspp %d fb %d multirect_idx %d frame done wait timed out, ret:%d dpu_encoder_helper_wait_for_irqenc%d enable %d id:%u, sw_event:%d, rc in %d state _dpu_encoder_resource_control_helpermode: %s id:%u pp:%d state:%d pp_done_irqenc%d intf%d tc cfgheight %u thresh_start %u thresh_cont %u drm_mode_to_intf_timing_paramsenc%d intf%d less vfp than fetch req, using entire vfp failed: id:%u intf:%d ret:%d enable:%d refcnt:%d 3[drm:%s:%d] [dpu error][enc:%d] unsupported chroma sampling type CDM_CDWN2_COEFF_COSITE_VCTL_FLUSHCTL_LAYER_EXT2(lm)DSC_SCALE_DEC_INTERVALINTF_DISPLAY_V_END_F0INTF_TEAR_SYNC_CONFIG_HEIGHTINTF_TEAR_SYNC_WRCOUNTPP_SYNC_WRCOUNTintf_mode_stridxexpected_timesspp [%x]plane%d Check plane state failed (%d) plane%d invalid framebuffer %dx%d%+d%+d 3[drm:%s] [dpu error]blk type %d not managed by rm _dpu_vbif_wait_for_xin_haltfailed to create disp state task gem%s Status: user MSM_GET_PARAMfb: %dx%d@%4.4s (%2d, ID:%d) could not allocate stolen bo &fctx->spinlockstrscpy!is_vunmapable(msm_obj) msm_gem_fault*ERROR* failed to allocate sgt *ERROR* failed to create crtc_event kthread front_porch = %dx%d active_low = %dx%d A6XX_TP1_MIPMAP_BASE_DATAA6XX_HLSQ_CVS_MISC_RAMA6XX_DBGBUS_CCU_06[drm-dp] %s: %08x: %08x %08x %08x %08xusing phy test link parameters Failed to start link clocks. ret=%d sink_count=%d link_ready = %s Requested: rate = 0x%x, lane count = 0x%x Requested: v_level = 0x%x, p_level = 0x%x failed to update edid property %d still active or activating or no askv. returning 3%s: receive r0 failed %d 3: BKSV chk fail. BKSV=%02x%02x%02x%02x%02x msm_hdmi_hdcp_recv_check_bstatusmsm_hdmi_hdcp_recv_ksv_fifo3%s: can't find src clock. ret=%d 3%s: Read cmd Tx failed, %d Unable to get clocks, ret = %d 3DSI: invalid input: pic_width: %d pic_height: %d *ERROR* %s: phy enable failed, %d dsi%dpllDSI%d PLL a660_gmu.bina660_zap.mbn - { offset: 0x%04x, value: 0x%08x } Unable to find the OPP table. Falling back to 450 MHz. MH_INT: %08X CP VSD decoder parity error CP illegal instruction error *ERROR* failed to power off SPTPRAC: 0x%x hubhdmi_msm*ERROR* cannot find phy device %u Hz, %d bit, %d channels TX_BAND: %d *ERROR* failed to enable regulators: %d RGB3*ERROR* vsync_clk clk_prepare_enable failed, %d CURSOR0LM5STAGE1dpu_core_perf_crtc_release_bw6[drm] fix performance mode dpu_encoder_initrd_ptr_irqenc%d intf%d pp:%d pending_cnt %d 3[drm:%s:%d] [dpu error]vblank timeout [enc:%d] cdm_enable:%d,%d,%X,%d,%d,%d,%d] sblk->enc.base + DSC_HRD_DELAYSsblk->enc.base + DSC_RC_BUF_THRESH_1sblk->enc.base + DSC_RC_MIN_QP_2PP_SYNC_CONFIG_HEIGHTxin_idsrc_xy_offSSPP_SRC_YSTRIDE0csc_reg_off + 0x2cvbif_idxpending_kickoff_cnttimedst_rectid:%u enable:%s state{enabled:%s} indexVBIF NRT is not defined3[drm:%s:%d] [dpu error]failed to init perf %d _dpu_danger_signal_status3[drm:%s:%d] [dpu error]clock enable failed rc:%d unmappedinvalid type: %08x invalid offset %u at reloc %u gpu_reg: %p No per-process page tables*ERROR* failed to install IRQ handler A6XX_HLSQ_INDIRECT_METAA6XX_SP_LB_7_DATAA6XX_DBGBUS_TESSA6XX_DBGBUS_TPL1_1 - { offset: 0x%06x, value: 0x%08x } Mem allocation failure failed to initialize parser, rc = %d type=%d isr=0x%x DRM DP AUX register failed Disconnected, no DP_LINK_STATUS_UPDATED lane count = 0x%x failed to read link bit depth. rlen=%zd %dx%d@%dfps 6%s:AUTH_SUCCESS_INT received HDCP_DDC_STATUS=0x%x, FAIL=%d, NACK0=%d After: HDMI_DDC_SW_STATUS=0x%08x End DDC read %d 3%s:BKSV read failed msm_hdmi_hdcp_transfer_v_hrefgen3%s: can't find dsi_byte clock. ret=%d Mode %dx%d dsi%d_reg*ERROR* failed to register PLL: %d *ERROR* DSI PLL lock failed div_frac_start = %x DSI%d PLL parent rate=%lu yamato_pm4.fwleia_pm4_470.fwrevision: %u (%u.%u.%u.%u) iova: 0x%016llx core_clk*ERROR* cx gdsc didn't collapse *ERROR* Unable to start the HFI queues Failed to attach an audio codec %d core-vddaslave_iface*ERROR* failed to enable clock: %s (%d) PLL_RCTRL: %u tx_l0_lane_mode = 0x%x msm8x94*ERROR* No more CTL available!Stage %d fg_alpha %x bg_alpha %x alpha=%u threshold_lowfix_core_ab_voteMISR read failed max_per_pipe_ib: %llu dpu_crtc_frame_event_workdpu_crtc_disable&(&dpu_enc->delayed_off_work)->timer_dpu_encoder_calculate_linetime3[drm:%s:%d] [dpu error]enc%d mode unsupported, phys idx %d 3[drm:%s:%d] [dpu error]enc%d failed to init wb enc: %ld dpu_encoder_phys_cmd_enableCreated dpu_encoder_phys for wb %d dpu_encoder_helper_phys_setup_cdmCTL_LAYER(mixer_id)CTL_LAYER_EXT2(mixer_id)sblk->enc.base + DSC_PICTURE_SIZEsblk->enc.base + DSC_MISC_SIZEmisr_ctrl_offsetVBIF_WRITE_GATHER_ENid=%u, intf_idx=%d multirect_idxid:%d enc_id:%u pp_id:%u 3[drm:%s:%d] [dpu error]failed to get MDSS data: %d 3[drm:%s:%d] [dpu error]initialize HDMI failed, rc = %d %s_%sInactive plane:%d dpu_plane_flush3[drm:%s:%d] [dpu error]plane%d failed to get format layout, %d plane%d invalid source %dx%d%+d%+d 3[drm:%s] [dpu error]failed intf object creation: err %d lm %d dspp %d already reserved mdss_physfailed to add irq_domain msm_gem_vunmapmsm_gem_free_object!vma->iovaOnly creating %zu ringbuffers perfCP_ROQA6XX_DBGBUS_TSEA6XX_DBGBUS_VFD_04[drm] Some DP AUX interrupts unhandled: %#010x No valid test pattern requested: %#x Failed to disable link clocks. ret=%d failedinit sub module failed &dp->event_mutexfailed to initialize panel, rc = %d HDCP: Off 3%s: recv ksv fifo failed %d msm_reset_hdcp_ddc_failuresV' H03%s: can't find byte_intf clock. ret=%d 3%s: alloc rx temp buf failed *ERROR* %s: can't enable ahb clk, %d PERMISSIONREAD%s: timeout waiting to drain ringbuffer %d rptr/wptr = %X/%X core%s %xiommusCDP Prefetchgx*ERROR* HFI queue %d is not empty HFI_H2F_MSG_INITdis*ERROR* failed to enable pwr regulator: %d PLL_CMP: %u failed to get irq *ERROR* failed to init kms &kms->commit_lock[i]%s: assign to plane %s for caps %x STAGE0STAGE2TOTAL: %d (of %d) 3[drm:%s:%d] [dpu error]failed to set core clock rate %llu core_clk_ratefix_core_ib_votecrtc_frame_eventencoder_underrun_callbackidle_dpu_encoder_trigger_startctl_start_irq_dpu_encoder_phys_cmd_pingpong_config[wb:%d] no ctl assigned 3[drm:%s:%d] [dpu error]unsupported format modifier %llX CTL_INTF_ACTIVEDSC_PICTUREsblk->enc.base + DSC_MAIN_CONFINTF_UNDERFLOW_COLORINTF_CONFIG2LM_BLEND0_OP + stage_offwd_ctlcsc_reg_offQSEED3_DE_SHARPEN + offsetWB_DST2_ADDRcrtc_iddpu_kms_hw_inithw_log_maskMDP : 0x%x 3[drm:%s:%d] [dpu error]invalid rotation cfg %s client %d is halted UBWC_DEC_HW_VERSION: 0x%x fbcon get_vma_lockeddrm-maxfreq-gpu: %u Hz [drm] no IOMMU, fallback to phys contig buffers for scanout ROQ state: msm_dpgpu-initialized: %d A6XX_DBGBUS_HLSQA6XX_DBGBUS_DBGCA6XX_DBGBUS_RB_0dump_regsfailed to initialize debug, rc = %d failed to pm_runtime_resume failed to add bridge, rc=%d Start DDC read Set clk rates: pclk=%d, byteclk=%lu dsi_link_clk_enable_v2&msm_host->intr_lockcannot get disp-enable-gpios %ld *ERROR* wait for video done timed out vco_clk_rate=%lld ref_clk_rate=%lld *ERROR* gpu hw init failed: %d leia_pfp_470.fwa630_sqe.fwa690_zap.mdt last-fence: %u firmware-nameCP | Protected mode error| %s | addr=%x registers-hlsq: crashdumpdummy*ERROR* GMU firmware initialization timed out GMU fence error: 0x%x *ERROR* Unexpected message id %d on the response queue *ERROR* failed to enable HPD: %d Disabling PHY com_div_frac_start2_mode0 = 0x%x vccaunref cursorDMA_Pno iommu, fallback to phys contig buffers for scanout *ERROR* could not pin blank-cursor bo: %d *ERROR* failed to construct plane for VG%d *ERROR* failed to %sable cursor: %d assigning Right Layer Mixer %d to crtc %s zpos=%u fix_core_clk_rate_dpu_core_perf_calc_crtc6[drm] minimum performance mode %s: successfully initialized crtc mixer:%d ctl:%d width:%d height:%d format:%p4cc, alpha_en:%u blend_op:0x%x INTF_MODE_WB_LINEenc%d sw_event:%d, work cancelled 3[drm:%s:%d] [dpu error]enc%d intf%d already disabled enc%d intf%d tc vsync_clk_speed_hz %lu vtotal %u vrefresh %u [wb:%d] dpu_encoder_phys_wb_disable3[drm:%s:%d] [dpu error]connector not connected %d CDM_CDWN2_COEFF_OFFSITE_VCTL_MERGE_3D_ACTIVEsblk->enc.base + DSC_RC_MAX_QP_03[dpu error]Failed/ to enable IRQ=[%d, %d] core_irqLM_OP_MODELM_BLEND0_BG_ALPHA + stage_offPP_DSC_MODEout_xy_offQSEED3_PHASE_INIT_UV_H + scaler_offsetQSEED3_SRC_SIZE_UV + scaler_offsetoffset + QOS_CREQ_LUT_0reg_lvl + reg_highpnumboolrc_stateenum dpu_wbis_virtual_dpu_kms_drm_obj_init multirect_index[1]=%s plane%d plane doesn't have scaler/csc for yuv plane%d plane exceeds max mdp core clk limits dpu_rm_get_assigned_resources_dpu_rm_reserve_lmsdynamic_ot_wr_%d_pps3[drm:%s:%d] [dpu error]%s client %d not halting. TIMEDOUT. ====================%s================ 20130625MSM_SUBMITQUEUE_CLOSE__fortify_strleninit *ERROR* failed to allocate fb non-aligned cmdstream buffer: %u &rd->read_lockstart_ticksfreq=%u, perf_index=%u gmu-debug: CP_BV_MEMPOOLA6XX_SP_LB_4_DATAA6XX_HLSQ_CHUNK_CVS_RAMA6XX_HLSQ_CPS_MISC_RAMA6XX_DBGBUS_CP - type: %s: failed to register drm aux: %d set state_bit for link_train=%d failed Failed to reinitialize mainlink. rc=%d max tries reached &dp->event_lockinvalid data hpd_state=%d sink_request=%d link 0x%x not supported test_audio_period_ch_1 = 0x%x hdcp inactive or no aksv. returning msm_hdmi_hdcp_init3%s: Wait Auth IRQ timeout ibb_reg3%s: Failed to set rate esc clk, %d 3%s: unable to initialize dsi clks qcom,dsi-phy-regulator-ldo-modeFailed to map phy lane base dec_start = %x DSI%d PLL save state %x %x *ERROR* qcom,phy-drive-ldo-level %d is not supported a330_pm4.fwa650_gmu.bina660_zap.mdta740_zap.mdta5xx_uche_err_irq*ERROR* %s: preemption timed out unknownTP|VFD&x->waitHFI_H2F_MSG_STARTEnableaudio: enabled=%d, channels=%d, channel_allocation=0x%x, level_shift_value=%d, downmix_inhibit=%d, rate=%d &hdmi_i2c->ddc_eventHDMI PLL is %slocked lvds-vddamdp4_irq_error_handlerfetch config: dmap=%02x, vg=%02x VG3%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u msm8x76*ERROR* vsync_clk is not initialized smpclk:%llu threshold_high3[drm:%s:%d] [dpu error]enc%d failed to init vid enc: %ld dpu_encoder_phys_cmd_prepare_for_kickoffid:%d pp:%d kickoff timeout %d cnt %d koff_cnt %d enc%d intf%d prog fetch is not needed, large vbp+vsw 3[drm:%s:%d] [dpu error]invalid fb w=%d, mode w=%d CTL_DSPP_n_FLUSH(dspp - DSPP_0)CTL_DSC_ACTIVECTL_LAYER_EXT3(lm)sblk->enc.base + DSC_RC_MODEL_SIZEsblk->enc.base + DSC_RC_MIN_QP_1PP_TEAR_CHECK_ENQSEED3LITE_DIR_FILTER_WEIGHT + offsetpnum=%d fmt=%x rt=%d fl=%d lut=0x%llx lut_usage=%d crtc=%d bw_ctl=%llu clk_rate=%u stop_req=%d u_bus=%d u_clk=%d 3[drm:%s:%d] [dpu error]failed to get hw_mdp: %d 3[drm:%s:%d] [dpu error]modeset_init failed for DP, rc = %d danger Safe signal status: %d dpu_plane_resetplane%d invalid src %dx%d%+d%+d line:%u, tiled format plane%d invalid src %dx%d%+d%+d line:%u 3[drm:%s] [dpu error]failed wb object creation: err %d %pVvma->iova != iova %08zu %9s %-32s non-aligned reloc offset: %u *ERROR* failed to ioremap: %s %.*s/%d: fence=%uevicted %02x: %08x %08x %08x %08x h_skew = %d indexed-registers: A6XX_SP_LB_5_DATAA6XX_DBGBUS_RBBMmax. voltage swing level reached %d link rate=%d dp_hpd_handlerHPD already %s failed to read phy link pattern. rlen=%zd invalid test_audio_period_ch_1 = 0x%x Current: v_level = 0x%x, p_level = 0x%x h_porches(back|front|width) = (%d|%d|%d) msm_hdmi_hdcp_auth_part2_wait_ksv_fifo_readyV' H2COMP_DONE 6%s: abort reauthentication! 4%s: hw_ddc_clean failed byte%s: Version %x:%x 3%s: host %d power off failed,%d *ERROR* %s: failed to restore phy state, %d dsi_phya650_zap.mdta740_sqe.fw size: %u RBBM_INT: %08X Zap shader not enabled - using SECVID_TRUST_CNTL instead *ERROR* failed to match fw block (addr=%.8x size=%d data[0]=%.8x) HFI_H2F_MSG_TESTfailed to get pwr regulators mdp_corepinctrl state chg failed: %d status=%04x, ctrl=%04x hdmi_phy*ERROR* failed to map pll base PLL_CPCTRL: %u com_hsclk_sel = 0x%x com_div_frac_start3_mode0 = 0x%x com_integloop_gain1_mode0 = 0x%x %s: event: %p failed to allocate kms *ERROR* failed to initialize intf: %d, %d *ERROR* Width down scaling exceeds limits! MDP5: %s hw config selected pingpong_tearcheck_setup*ERROR* vsync_clk clk_set_rate failed, %d fall back to the other CTL category for INTF %d! update clk rate = %lld HZ stateencoder is disabled id=%u, callback=%ps, IRQ=[%d, %d] &dpu_enc->enc_spinlock&phys_enc->pending_kickoff_wqINTF_MODE_UNKNOWN3[drm:%s:%d] [dpu error]invalid mdptop dpu_encoder_prep_dsc3[drm:%s:%d] [dpu error]enc%d invalid phys both intf and wb block at idx: %d 3[drm:%s:%d] [dpu error]failed to allocate 3[drm:%s:%d] [dpu error]enc%d intf%d tearcheck not supported enc%d intf%d 3[drm:%s:%d] [dpu error]invalid params - hstart:%d,hend:%d,htot:%d,hdisplay:%d DSC_ENCDSC_SCALE_INITIALskip mixer %d without pingpong SSPP_SW_PIX_EXT_C1C2_LRSSPP_SW_PIX_EXT_C3_LRbase + PCC_RED_G_OFFMERGE_3D_MODEQSEED3_PHASE_INIT_Y_H + scaler_offsetoffset + QOS_DANGER_LUTWB_DST_OP_MODEu32fllut_usageupdate_clk%s: id:%u, sw_event:%d, idle_pc_supported:%s, rc_state:%d id=%u, event=%u id:%u mixer:%d bounds:%dx%d%+d%+d plane%d invalid src %dx%d%+d%+d line:%u, can't use split source lm %d already reserved disp_snapshotinvalid drm printer devfreqMSM_GEM_CPU_FINIMSM_GEM_MADVISETotal: %4d objects, %9zu bytes Resident: %4d objects, %9zu bytes Purged: %4d objects, %9zu bytes invalid flags: %x failed to map: %d crtc=%u%3d.%d%%active_purged bpp = %d Copied %d bytes from user memcpyA6XX_TP1_TMO_DATAA6XX_DBGBUS_RBPA6XX_DBGBUS_GMU_GX%s: invalid msg: size(%zu), request(%x) no test pattern selected by sink DP link status read failed, err: %d type=%d Done Disconnected sink_request: %d channel_eq_done = %d, clock_recovery_done = %d SET NEW RESOLUTION: clock-names3%s: key exchange failed %d 3%s: verify r0 failed %d 3%s: check v match failed %d msm_hdmi_hdcp_recv_bcapsBCAPS=%02x HDCP_SHA_STATUS=%08x 3%s: failed to parse dt 3%s: rx ACK_ERR_PACLAGE *ERROR* %s: invalid lane configuration %d dsi_cmd_dma_txdsi_short_read1_respDSI%d PHY disabled *ERROR* failed to parse qcom,phy-rescode-offset-bot, %d a540_zap.mdta615_zap.mdtTRANSLATIONNo memory protection without MMU *ERROR* no a4xx device %s: Int status %08x crashdump readrscccxextpWaiting for PHY ready com_pll_cctrl_mode0 = 0x%x msm8x26mdp0-memcalculated bandwidth=%uk multirect[1]: mode: %d index: %d dpu_encoder_helper_split_configkickoffenc%d enable:%d id:%u ctl %d reset intf:%d wb:%d vsync:%8d underrun:%8d frame_done_cnt:%d3[drm:%s:%d] [dpu error]enc%d timeout pending enc%d intf%d tc enable %u start_pos %u rd_ptr_irq %u mismatch in subsample vs dimensions CTL_WB_FLUSHUnbinding dsc:%d from any pp INTF_TEAR_TEAR_CHECK_ENLM_BLEND0_CONST_ALPHA + stage_offbase + PP_DITHER_BITDEPTHMDP_VSYNC_SELreg_offid=%u, mode=%dx%d crtc_id:%u plane_id:%u fb_id:%u src:%d.%06ux%d.%06u%+d.%06u%+d.%06u dst:%dx%d%+d%+d stage_idx:%u stage:%d, sspp:%d multirect_index:%d multirect_mode:%u pix_format:%u modifier:%llu boundslayoutenum dpu_vbif3[drm:%s:%d] [dpu error]hw_intr init failed: %d 3[drm:%s:%d] [dpu error]wait for commit done returned %d plane%d using 0x%X 0x%X 0x%X... plane%d pnum:%d ds:%d is_rt:%d 3[drm:%s:%d] [dpu error]invalid plane state 3[drm:%s] [dpu error]failed pingpong object creation: err %d lm %d pp %d already reserved idle_clampMSM_SUBMITQUEUE_QUERY*ERROR* unable to parse port endpoint msm_gem_unpin_activeupdate_lru_active!aspace(&gpu->hangcheck_timer)MEQ state: dp_panel_info: active = %dx%d A6XX_DBGBUS_COMA6XX_DBGBUS_UCHE_WRAPPERA6XX_DBGBUS_RB_2A6XX_DBGBUS_TPL1_4dpu_dp_aux6[drm-dp] %s: AUXCLK regs %s: enabled tpg mainlink_level = 0x%x, safe_to_exit_level = 0x%x 4[drm-dp] %s: PUSH_IDLE pattern timedout PSR_ENTRY timedout voltage level: %d emphasis level: %d Audio registration Dp failed aux read failed. rlen=%zd link rate = 0x%x test_audio_period_ch_7 = 0x%x test_audio_period_ch_8 = 0x%x calling catalog tpg_enable unable to remap link region: %pe &hdcp_ctrl->auth_event_queue6%s: Authentication Part I successful An not ready after enabling HDCP :BKSV=%02x%08x 3%s: no. of devs connected exceeds max allowed3%s: transfer V failed vdda3%s: failed to enable link clocks. ret=%d *ERROR* DSI does not support fractional bits_per_pixel lane number=%d dsi%d_pll&pll_14nm->postdiv_lockssc freq=%d spread=%d period=%d DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x a650_sqe.fw*ERROR* Unable to set the OPP table Legacy firmware detected, disabling protection support *ERROR* No A5XX device is defined RBBM | AHB bus error | %s | addr=0x%X | ports=0x%X:0x%X RBBM | ETS master split | status=0x%X (&a5xx_gpu->preempt_timer)cx_memVFD*ERROR* The HFI response queue is unexpectedly empty audio %sabled requested=%ld, actual=%ld PLL calculation failed VCO freq: %llu tmds clk: %llu com_svs_mode_clk_sel = 0x%x com_lock_cmp1_mode0 = 0x%x DMA_E*ERROR* Invalid or unsupported interface *ERROR* CTLs already paired *ERROR* CTL_%d: base is null! Pool of %d CTLs created. mdp5_crtc_wait_for_pp_donemsm_mdpRGB0*ERROR* Cannot allocate %d SMP blocks: %d *ERROR* out of blks (req=%d > avail=%d) core_clk_rate: %llu IRQ=[%d, %d] not triggered id=%u, callback=%ps, pp=%d, atomic_cnt=%d 3[drm:%s:%d] [dpu error]crtc/crtc state object is NULL id:%d, sw_event:%d,rc:%d-unexpected 3[drm:%s:%d] [dpu error]missing trigger cb id:%u invalid timeout frame_busy_mask=%lu 3[drm:%s:%d] [dpu error]already enabled id:%u pp:%d enable=%s/%d enc%d intf%d tearcheck not supported enc%d intf%d update pending flush ctl %d intf %d 3[drm:%s:%d] [dpu error]invalid hw_intf %d hw_ctl %d [atomic_check:%d, "%s",%d,%d] 3[drm:%s:%d] [dpu error]invalid arguments Pending flush mask for CTL_%d is 0x%x, WB %d dpu_encoder_phys_wb_prepare_wb_job3hw recovery is not complete for ctl:%d sblk->enc.base + ENC_DF_CTRLLM_BLEND0_FG_ALPHA + stage_offclk_ctrlSSPP_UBWC_STATIC_CTRLsblk->scaler_blk.base + SSPP_VIG_OP_MODEoffset + QOS_SAFE_LUTnew_countid:%u frame_pending:%d pp_idintf:%d cfg:%u pending_mask_dpu_kms_setup_displays3[drm:%s:%d] [dpu error]encoder init failed for dsi display sspp[1]=%s rect_1default_wr_ot_limit%s xin:%d w:%d h:%d fps:%d pps:%llu ot:%u time: %lld.%09ld crtc_mask*ERROR* could not install rd debugfs 0x%08llx MSM_SET_PARAMfini create framebuffer: mode_cmd=%p (%dx%d@%4.4s) purgedmapped!msm_obj->pagesgpu-ring-%dGot %d for test active A6XX_DBGBUS_RB_1A6XX_DBGBUS_TPL1_26[drm-dp] %s: P0CLK regs hw: bit=%d train=%d mainlink not ready dp_video_ready *ERROR* failed to create dp connector: %d &dp->event_qcomponent add failed, rc=%d failed to get DP sink modes, rc=%d invalid audio pattern type = 0x%x Illegal link rate=%d lane=%d msm_hdmi_hdcp_irq3%s: write ksv fifo failed %d 6%s: hdcp authentication canceled HDCP_DEBUG_CTRL=0x%08x 3%s: Wait key state timedoutmsm_hdmi_hdcp_wait_key_an_readyV' H3*ERROR* failed to create dsi connector: %d dsi_link_clk_set_rate_6g3%s: get config failed dsi_host_parse_dt*ERROR* %s: failed to get sfpb regmap 3%s: failed to add cmd type = 0x%x DSI%d PHY enabled qcom,adreno-%08xa640_zap.mdtloaded %s from new location Unable to find the OPP table. Falling back to 200 MHz. *ERROR* could not allocate PFP: %d CP | opcode error | possible opcode=0x%8.8X *ERROR* gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x *ERROR* Unable to power on SPTPRAC: 0x%x a6xx_hfi_irqhpdcom_core_clk_en = 0x%x %s: disabled! *ERROR* Increase static pool size to at least %d lut*ERROR* failed to construct pipe for %s (%d) *ERROR* failed to construct INTF%d %s: assign to right of plane %s for caps %x STAGE_UNUSED%s:%d %d %s crtc=%d p=%d new_bw=%llu,old_bw=%llu crtc_commitstatusInvalid source %s for CRTC%d dpu_encoder_vsync_time3[drm:%s:%d] [dpu error]pclk period is 0 enc%d encoder disabled dpu_encoder_frame_done_timeoutfailed wait_for_idle: id:%u ret:%d intf:%d vblank_irqimage dimensions outside max range 3[dpu error]%s invalid horz down sampling type CDM_CDWN2_OP_MODECTL_WB_ACTIVECTL_LAYER_EXT(lm)INTF_TEAR_AUTOREFRESH_CONFIGbaseSPLIT_DISPLAY_UPPER_PIPE_CTRLQSEED3_DST_SIZE + scaler_offsetcsc_reg_off + 0x38update_busvdisplayid=%u, pp=%d, new_count=%d, event=%u enum dpu_stagenew=%x existing=%x pending_mask=%x CTL_FLUSH=%x failed to parse clocks 6[drm:%s:%d] dpu hardware revision:0x%x 3[drm:%s:%d] [dpu error]dpu_writeback_init, rc = %d _dpu_rm_check_lm_and_get_connected_blksinvalid arguments vbif %d *ERROR* could not install perf debugfs *ERROR* waiting on invalid fence: %u (of %u) Purgeable: %4d objects, %9zu bytes use_vram && !priv->vram.sizerelocs not allowed l->owner != currentmsm_gem_vma_map%s: no IOMMU, fallback to VRAM carveout! memptrsUsing legacy clk name binding. Use "%s" instead of "%s" %%BUSYhangrdelapsedend_ticksPFP state: msm_dp_test_data sync_width = %dx%d CP_LPAC_FIFO_DBG_ADDRA6XX_SP_STATE_DATAA6XX_HLSQ_INST_RAMA6XX_DBGBUS_CCUFCHEA6XX_DBGBUS_SP_1A6XX_DBGBUS_VBIFmainlink %s n_sym = %d, num_of_tus = %d dp_display_isrphy_test_pattern_sel = 0x%x failed to parse (DP_TEST_VSYNC_HI) px: 0=%d, 1=%d, 2=%d, 3=%d %s clocks for %s (work_completion)(&hdcp_ctrl->hdcp_reauth_work)3%s: wait ksv fifo ready failed %d msm_hdmi_hdcp_read_validate_aksv3%s: error: scm_call ret=%d resp=%u &msm_host->dev_mutex- pclk=%lu, bclk=%lu %s: no endpoint 3%s: can't find dsi_pixel clock. ret=%d 3%s: status=%x cannot get disp-te-gpios %ld 3%s: invalid id %d 3%s: enable host %d failed, %d %d, %d, %d, %d, %d, %d, %d, %d, %d, %d *ERROR* DSI PLL(%d) lock failed, status=0x%08x *ERROR* %s: PHY timing calculation failed a508_zap.mdtgmu_gen70000.bingpuCP_SCRATCH_REG%d: %u pfp readVPCGMU set GPU frequency error: %d *ERROR* Unable to find the %s registers *ERROR* Unable to get interrupt %s %d sw_status=%08x, hw_status=%08x, int_ctrl=%08x msm_hdmi_phy_probecom_lock_cmp3_mode0 = 0x%x %s: flush=%08x *ERROR* failed to get tv_clk mpd4_lvds_pllfailed to get lut_clk *ERROR* Width up scaling exceeds limits! tbu_rtSkipping eDP interface %d src_x:%4d src_y:%4d src_w:%4d src_h:%4d encoderdpu_encoder_helper_hw_reset3[drm:%s:%d] [dpu error]enc%d dpu resource control failed: %d failed wait_for_idle: id:%u ret:%d pp:%d 3[drm:%s:%d] [dpu error]failed to create encoder due to memory allocation error dpu_encoder_phys_vid_setup_timing_enginefailed to retrieve base addr intr->intr_set[i].en_offINTF_DISPLAY_V_START_F0PP_START_POSQSEED3_PRELOAD + scaler_offsetcsc_reg_off + 0x10csc_reg_off + 0x14csc_reg_off + 0x24csc_reg_off + 0x28csc_reg_off + 0x3crd_limcrtcenum dpu_pingponghdisplayid=%u, intf_mode=%s, intf_idx=%d, wb_idx=%d, pending_kickoff_cnt=%d ctl_idx=%d extra_flush_bits=0x%x pending_flush_ret=0x%x struct drm_rectmultirect_mode3[drm:%s:%d] [dpu error]vbif register memory map failed: %d time_mxplane%d FB[%u] 3[drm:%s:%d] [dpu error]failed to prepare framebuffer 3[drm:%s] [dpu error]failed to global state 3[drm:%s] [dpu error]unable to find appropriate mixers &priv->lru.lockqcom,mdp4dumbmsm_gem_purgemsm_gem_vma_initmdp_kmsid=%d pid=%d ring=%d:%d elapsed=%lld ns mhz=%lld start=%lld end=%lld registers-gmu: clusters: A6XX_TP0_MIPMAP_BASE_DATAA6XX_SP_UAV_DATAA6XX_HLSQ_CHUNK_CVS_RAM_TAGA6XX_HLSQ_CPS_MISC_RAM_TAG process phy_test_req failed LM failed: TEST_LINK_TRAINING After, phy=%p init_count=%d power_on=%d Test:(0x%x) requested streamKeys not ready(%d). s=%d, l0=%0x08x An not ready(%d). l0_status=0x%08x Link0-AKSV=%02x%08x msm_hdmi_hdcp_auth_part1_verify_r0hdcp auth failed, queue reauth work msm_dsi_host_modeset_initdsi host already off data-lanesdsi_cmds2buf_tx*ERROR* could not find DSC RC parameters PHY timings: %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d dsi%d_phyphy-typedsi%dvco_clkdsi%d_pclk_muxa420_pfp.fwgmu_gen70200.bin_rs.lockloaded %s from legacy location - source=%s rptr: %u *ERROR* memory region is too small to load the MDT %sshadowreservedcrashdump writeqcom,adreno-gmu-wrappera6xx_irqHLSQ*ERROR* Invalid non-legacy GMU request %s *ERROR* GMU firmware error %d hpd gpio tells us: %d hdmi_tx_l%dxocom_pll_rctrl_mode0 = 0x%x com_cp_ctrl_mode0 = 0x%x tx_l%d_tx_emp_post1_lvl = 0x%x tx_l%d_vmode_ctrl2 = 0x%x iface_clkbus_clkoff&mdp5_crtc->cursor.lockVIG1%s: release from crtc %s stage=%s dpu_crtc_duplicate_statelm ctl[%d]=%d crtc%d -> enable %d, skip atomic_begin 3[drm:%s:%d] [dpu error]invalid crtc index[%d] id:%u intf:%d state:%d 3[drm:%s:%d] [dpu error]enc%d intf%d ctl start interrupt wait failed enc%d intf%d fmt_fourcc 0x%X dpu_encoder_phys_vid_wait_for_commit_done3[drm:%s:%d] [dpu error]invalid writeback hardware DSC_COMMON_MODEdsc_ctl_offsetDSC_CMN_MAIN_CNFsblk->enc.base + DSC_RC_OFFSETS_3sblk->enc.base + DSC_RC_BUF_THRESH_2enc%d intf%d disabled autorefresh PP_SYNC_CONFIG_VSYNCSSPP_SW_PIX_EXT_C0_LRSSPP_SW_PIX_EXT_C0_TBcsc_reg_off + 0x40clk_ctrl_reg->reg_offuint32_tid=%u, callback=%ps, IRQ=[%d, %d], pp=%d, atomic_cnt=%d pp:%d cfg:%u 3[drm:%s:%d] [dpu error]initialize_DP failed, rc = %d src[0]=%dx%d%+d%+d src[1]=%dx%d%+d%+d rect_0dpu_plane_check_inline_rotation3[drm:%s] [dpu error]failed ctl object creation: err %d qcom,mdssfailed to parse clocks, ret=%d stolenfb purgeable*ERROR* IOMMU support or CAP_SYS_RAWIO required! invalid cmdstream size: %u *ERROR* Couldn't initialize GPU devfreq &queue->idr_locknr_cmds %02x: %08x msm_dp_test_active back_porch = %dx%d gmu-log: CP_UCODE_DBG_DATAA6XX_HLSQ_INST_RAM_1CLUSTER_PC_VSA6XX_DBGBUS_RASA6XX_DBGBUS_VFD_4 count: %d dp_aux_registerInvalid pixel mux divider PSR exit done failed to add DP OPP table successlink training #1 failed. ret=%d TU: upper_boundary_count: %d Power client create failed Event thread create failed no phy test height=%d vporch= %d %d %d psr version: 0x%x, psr_cap: 0x%x unable to remap p0 region: %pe no ctrl clocks are defined hdcp irq %x 6%s: hdcp is not supported 3%s: read bcaps error, abort 3%s: Wait KSV fifo ready timedout*ERROR* failed to read lane data *ERROR* DSI does not support bits_per_component != 8 yet msm_dsi_manager_cmd_xfer3%s: host1 power off failed, %d dsi_7nm_phy_enable*ERROR* Couldn't power up the GPU: %d a506_zap.mdta630_gmu.bin - iova=%.16lx rptr: %d speed_binRBBM | PFP master split | status=0x%X UCHE{class: gpu, res: acd, val: %d}failed to send GPU ACD state ACVCN0pxo%s: intf_sel=%08x &mdp4_crtc->cursor.lock%s: begin mdp4vdd*ERROR* failed to enable regulator vdd: %d msm8x36 right hwmixer=%s LM2comp-%d (L/R): rpt=%d/%d, ovf=%d/%d, req=%d 3[drm:%s:%d] [dpu error]Failed to initialize %s with self-refresh helpers %d intf_mode: %d 3[drm:%s:%d] [dpu error]crtc%d failed performance check %d begintruefound fmt: %4.4s DRM_FORMAT_MOD_QCOM_COMPRESSED CTL_PREPARECTL_LAYER(lm)sblk->enc.base + DSC_RC_MAX_QP_1INTF_PANEL_FORMATbase + PCC_BLUE_G_OFFSPLIT_DISPLAY_ENoffset + QOS_CREQ_LUT_1atomic_cntctl_idxpppixel_formatvbif%s xin:%d lvl:%d/%d mdssHW_REV: 0x%x kmsfbMSM_SUBMITQUEUE_NEWmsm_gem_newmsm_obj->madv != 0ebi1_clk: %p *ERROR* could not allocate memptrs: %d simple_ondemand4*** fault: iova=%16lx, flags=%d id=%d pid=%d ring=%d bos=%d cmds=%d perf_index capabilities = %lu A6XX_SP_LB_3_DATAA6XX_HLSQ_INST_RAM_TAGA6XX_HLSQ_DATAPATH_METAA6XX_DBGBUS_DPMA6XX_DBGBUS_VPCfailed to enable DP link controller link training #2 successful TU: valid_boundary_link: %d adjusted: v_level=%d, p_level=%d &link->psm_mutexfailed to read lane count. rlen=%zd failed to parse test_v_start(DP_TEST_V_START_HI) failed to parse test_rr_n failed to initialize power data %d (work_completion)(&hdcp_ctrl->hdcp_auth_work)*ERROR* %s: phy driver is not ready src3%s: Failed to set rate src clk, %d dsi_short_read2_resp3%s: failed to prepare non-trigger host, %d msm_dsi_manager_registerdsi_mgr_bridge_pre_enable4PLL turned on before configuring PHY *ERROR* failed to parse qcom,phy-rescode-offset-top, %d 3DSI PLL(%d) lock failed, status=0x%08x qcom,chipida420_pm4.fw*ERROR* failed to load %s: %d name: %-32s memory-regiona5xx_cp_err_irqCP | protected mode error | %s | addr=0x%8.8X | status=0x%8.8X gpmufwpreempt_countersarm,mmu-500a6xx_cp_hw_err_irqicacheGMU watchdog expired mx.lvlHFI_H2F_MSG_FW_VERSION*ERROR* failed to attach next HDMI bridge: %d hdmi_isrdisabling audio: no video power down pixclock: %lu HDMI_HPD_INT_STATUS tells us: %d pix_clk: %lu tv_clk*ERROR* could not allocate blank-cursor bo: %d *ERROR* failed to construct DTV encoder *ERROR* failed to initialize DSI: %d %s: cleanup: FB[%u] %s: alloc SMP blocks LM33[drm:%s:%d] [dpu error]crtc%d wait for frame done failed;frame_pending%d dpu_encoder_trigger_kickoff_pendinginvalid FB not kicking off dpu_encoder_wait_for_event3[drm:%s:%d] [dpu error]enc%d ctl %d reset failure h_tile_instance %d = %d, split_role %d _dpu_encoder_phys_cmd_wait_for_ctl_start4[drm:%s:%d] low vbp+vfp may lead to perf issues in some cases 3[drm:%s:%d] [dpu error]enc%d intf%d ctl %d reset failure: %d dpu_encoder_phys_vid_prepare_for_kickoff[fb_id:%u][fb:%u,%u] 3[drm:%s:%d] [dpu error]invalid fb h=%d, mode h=%d dpu_encoder_phys_wb_setup_ctlCDM_CDWN2_COEFF_COSITE_H_0CDM_CDWN2_COEFF_OFFSITE_H_0DSC_FLATNESSDSC_RCsblk->enc.base + DSC_FLATNESS_QPoffset + QOS_QOS_CTRLWB_DST0_ADDRWB_ALPHA_X_VALUErtpnum=%d fmt=%x mode=%d luts[0x%x, 0x%x] Enew_bitsdpu_kms_initdpu_kms_destroy3[drm:%s:%d] [dpu error]invalid plane plane%d plane%d invalid height for inline rot:%d max:%d dpu_rm_init3[drm:%s] [dpu error]failed to get dspp on lm %d qos tbl not defined dpu devcoredump %d: offset=%d pitch=%d, obj: invalid handle %u at index %u gpu_cx: %p *ERROR* %s: offending task: unknown *ERROR* failed to get memory resource: %s (work_completion)(&vbl_work->work)&rd->fifo_eventrcu_read_lock() used illegally while idlereset refresh rate = %d A6XX_SP_LB_2_DATAA6XX_DBGBUS_A2DA6XX_DBGBUS_SP_2stream_pixelFailed to disable pclk. ret=%d wait4video timedout *ERROR* max v_level reached new rate=0x%x drm_dpinvalid link rate = 0x%x failed to read link audio mode. rlen=%zd lane_count=%d 3%s: KSV FIFO read failed HDCP REAUTH WORK 6%s: reauth work aborted 3%s: Failed to set rate pixel clk, %d 3%s: Failed to enable dsi esc clk 3%s: cannot duplicate mode failed to find data lane mapping, using default 3%s: power on host %d failed, %d msm_dsi_phy_enableDSI%d DSI PLL%d rate=%lu, parent's=%lu 3a540_gpmu.fw2a640_gmu.binadreno_fault_handlerocmem*ERROR* could not allocate PM4: %d RBBM | AHB transfer timeout HFI_H2F_MSG_GX_BW_PERF_VOTE*ERROR* failed to set pixel clk: %s (%d) *ERROR* failed to enable hpd regulators: %d *ERROR* timeout waiting for DDC DIV_FRAC_START: %llu *ERROR* failed to get hdmi_clk *ERROR* failed to set mdp_clk to %lu: %d VG4DMA1 normalized_zpos=%u Invalid source size %d.%06ux%d.%06u%+d.%06u%+d.%06u max_core_clk_ratemin_dram_ib sspp[1]:%s 3[drm:%s:%d] [dpu error]pclk is 0, cannot calculate line time 3[drm:%s:%d] [dpu error]enc%d invalid params for DSC _dpu_encoder_trigger_flushdsi_info->num_of_h_tiles %d enc%d intf%d created enc%d intf%d enabling mode: enc%d intf%d split_role %d, halve horizontal %d %d %d %d 3[drm:%s:%d] [dpu error]failed to get format %x plane %u expected pitch %u, fb %u 3[dpu error]invalid IRQ=[%d, %d] 3[dpu error]Failed to disable IRQ=[%d, %d]: %d 3[dpu error]IRQ=[%d, %d] still enabled/registered SSPP_SW_PIX_EXT_C0_REQ_PIXELSwd_load_valueQSEED3_PHASE_STEP_Y_H + scaler_offsetcsc_reg_off + 0xcQSEED3_DE_ADJUST_DATA_2 + offsetWB_DST_YSTRIDE0pnum:%d xin_id:%d ot:%d vbif:%d intpidrcid:%u encoder:%u enable:%s state{enabled:%s} idindex:%d xin_id:%u dev:%s stop_req:%s clk_rate:%llu [%x]_dpu_kms_initialize_hdmi[crtc:%d] not enable src[%d,%d,%d,%d] dst[%d,%d,%d,%d] solo3[drm:%s] [dpu error]unable to find CDM blk ctl %d match _dpu_vbif_get_ot_limitasyncMSM_GEM_NEWmsm_gem_evict:invalid cache flag: %x %s_clk*ERROR* failed to load kms seqnoroq %dA6XX_TP0_TMO_DATAA6XX_DBGBUS_CXdp_aux_transferUnable to start pixel clocks. ret=%d Failed to enable mainlink clks. ret=%d TU: tu_size_minus1: %d failed to attach bridge, rc=%d invalid lane count = 0x%x link video pattern = 0x%x link dynamic range = 0x%x link bit depth = 0x%x TEST_H_TOTAL = %d, TEST_V_TOTAL = %d TEST_H_START = %d, TEST_V_START = %d TEST_HSYNC_POL = %d TEST_HSYNC_WIDTH = %d TEST_VSYNC_POL = %d TEST_VSYNC_WIDTH = %d TEST_H_WIDTH = %d TEST_V_HEIGHT = %d TEST_REFRESH_DENOMINATOR = %d TEST_REFRESH_NUMERATOR = %d DP_CTRL_PMHeader Byte 3: value = 0x%x, parity_byte = 0x%x Start DDC write End DDC write %d 3%s: no. of cascade conn exceeds max allowed%s =%x 3%s: Failed to enable dsi pixel clk esc=%lu, src=%lu tx_gem3DSI: pic_width %d has to be multiple of slice %d isr=0x%x, id=%d 3%s: get vaddr failed, %d *ERROR* %s: set pll usecase failed, %d dsi%d_phy_pll_out_dsiclkUnknown GPU revision: %u.%u.%u.%u amd,imageon-%u.%ua300_pm4.fw - iova: 0x%016llx Tried to idle a non-current ringbuffer RBBM | ME master split | status=0x%X GMU AHB bus error gfx.lvlphy driver is not ready PLL_CCTRL: %u phy_mode = 0x%x *ERROR* unexpected MDP version: v%d.%d sdm630*ERROR* Only pair booked CTLs %s: assign pipe %s on stage=%d mdp5_irq_error_handlerassigning Layer Mixer %d to crtc %s dpu_core_perf_crtc_updatecrtc:%d width:%d height:%d crtc%d -> enable %d, active %d, skip atomic_check id: %u, sw_event:%d, rc in state %d 3[drm:%s:%d] [dpu error]invalid arg(s), drm_enc %d, crtc/conn state %d/%d 3[drm:%s:%d] [dpu error]enc%d frame done timeout dpu_encoder_phys_cmd_enable_helperenc%d intf%d tc hw_vsync_mode %u vsync_count %u vsync_init_val %u dpu_encoder_phys_vid_init3[drm:%s:%d] [dpu error]invalid wb_conn or wb_job [mode_set:%d, "%s",%d,%d] 3[drm:%s:%d] [dpu error]prep fb failed, %d sblk->enc.base + DSC_RC_SCALE_INC_DECsblk->enc.base + DSC_RC_CONFIGsblk->enc.base + DSC_RC_RANGE_BPG_OFFSETS_1INTF_DISPLAY_HCTLINTF_HSYNC_SKEWSSPP_UBWC_ERROR_STATUSSSPP_MULTIRECT_OPMODEwd_ctl2HDMI_DP_CORE_SELECTQSEED3_COEF_LUT_CTRL + offsetWB_DST_WRITE_CONFIGpp_idxid=%u, enable=%s refcntsrc_rectstage_idxindex:%d layout:{%ux%u @ [%u/%u, %u/%u, %u/%u, %u/%u]} multirect_index:%d mdp3[drm:%s:%d] [dpu error]NULL MDSS data top_2plane:%d img:%dx%d 3[drm:%s] [dpu error]failed merge_3d object creation: err %d 3[drm:%s] [dpu error]failed dspp object creation: err %d _dpu_rm_reserve_dscdynamic_ot_rd_%d_ppsdynamic_ot_wr_%d_ot_limitkernel: 6.8.0-mainline-g830a3b57edc6-ab11649714 msm_gem_put_vaddr_lockedinvalid buffer index: %u (out of %u) *ERROR* Couldn't register GPU cooling device ringid%llx 1vdisplay: %d queue-history[%u]:A6XX_SP_INST_TAGA6XX_HLSQ_ICB_CPS_CB_BASE_TAGCLUSTER_PSA6XX_DBGBUS_GPCbuf size greater than allowed size of 128 bytes dp_ahbdp_audio_cfg = 0x%x invalid DP OPP table in device tree unknown displayport instance failed to initialize aux, rc = %d device service irq vector = 0x%x invalid link bit depth = 0x%x v_porches(back|front|width) = (%d|%d|%d) failed to read psr info, rlen=%zd DP_CORE_PM3%s: ASKV validation failed msm_hdmi_hdcp_auth_prepare3%s:An write failed 3%s: bstatus error &msm_host->cmd_mutexdsi_drm_work3DSI: pic_height %d has to be multiple of slice %d dsi%d_ctrldsi_plldsi%d_pll_out_div_clkdsi%d_pll_by_2_bit_clk3Ref gen not ready. Aborting qcom,phy-drive-ldo-levela610_zap.mdtmsmloaded %s with helper preempt&a6xx_gpu->gmu.lock*ERROR* unknown GPU, add it to a6xx_ucode_check_version()!! *ERROR* Unable to slumber GMU: status = 0%x/0%x *ERROR* Level %u not found in the RPMh list *ERROR* Message %s id %d returned error %d failed to get hpd clk: %s *ERROR* failed to get i2c: %d en*ERROR* failed to enable pwr clk: %s (%d) *ERROR* failed to enabled mdp_clk: %d pixclk=%lu (%lu) apq8084msm8998Border Color is enabled *ERROR* failed to construct LM%d (%d) %d MMBs allocated (%d reserved) crtc=%d bw=%llu paths:%d dspp[%d]=%d 3[drm:%s:%d] [dpu error]%s: failed to get plane%d state, %d (&dpu_enc->frame_done_timer)wait_for_completion_eventdpu_encoder_get_intf_mode_dpu_encoder_virt_enable_helper3[drm:%s:%d] [dpu error]invalid num phys enc %d/%d dpu_encoder_virt_atomic_disable3[drm:%s:%d] [dpu error]enc%d no intf or wb block assigned at idx: %d enc%d intf%d created intf idx:%d 3[drm:%s:%d] [dpu error]already disabled dpu_get_dpu_format_extUBWC format not supported for fmt: %4.4s CTL_FETCH_PIPE_ACTIVEDSC_DSC_OFFSETsblk->ctl.base + DSC_CFGsblk->enc.base + DSC_RC_MAX_QP_2INTF_TEAR_SYNC_THRESHunpack_pat_offSPLIT_DISPLAY_LOWER_PIPE_CTRLirq_regpending_flush_retmultirect_indexmax core clk rate not determined, using default %s created for pipe:%u id:%u 3[drm:%s] [dpu error]CDM_0 is already allocated dynamic_ot_rd_%d_ot_limitdrm-cycles-gpu: %llu &ring->submit_lockfreq p_level = %d A6XX_DBGBUS_SPTP_4Panel not ready for aux transactions dp_ctrl_link_train_1Dp display driver register failedfailed to initialize catalog, rc = %d sink count: %d no test requested invalid link video pattern = 0x%x failed to parse test_h_width(DP_TEST_H_WIDTH_HI) failed to parse test_rr_d (DP_TEST_MISC1) link-frequencieserror reading clock-names %d no stream (pixel) clocks are defined unsupported power module: %s ???Before: HDMI_DDC_SW_STATUS=0x%08x msm_hdmi_hdcp_msleep3%s:AKSV write failed msm_hdmi_hdcp_reauth_worklab_regmsm_dsi_host_get_phy_clk_reqdsi_get_config3%s: can't find dsi_esc clock. ret=%d intr=%x enable=%d 3%s: packet size is too big msm_dsi_phyFailed to map pll base *ERROR* qcom,phy-rescode-offset-bot value %d is not in range [-32..31] amd,imageona660_sqe.fw retired-fence: %u rb %d: fence: %d/%d loading PM4 ucode version: %x a5xx_rbbm_err_irq%s: GPMU firmware initialization timed out qcom,gmuPCTP*ERROR* GPU RSC sequence stuck while waking up the GPU failed to init hdcp: disabled video: power_on=%d, pixclock=%lu msm_hdmi_phyvblank time out, crtc=%d DMA_S%s: check *ERROR* failed to get lvds_clk *ERROR* Height down scaling exceeds limits! intf_%d: %s dpu_core_perf_crtc_checkfinal threshold bw limit = %d dpu_crtc_initerror3[drm:%s:%d] [dpu error]invalid argument(s) 3[drm:%s:%d] [dpu error]timing engine setup is not supported 3[drm:%s:%d] [dpu error]invalid parameter(s) dpu_encoder_phys_wb_setup_fb3[drm:%s:%d] [dpu error][enc:%d] failed to enable CDM; ret:%d CDM_CDWN2_COEFF_OFFSITE_H_1Binding dsc:%d to pp:%d sblk->enc.base + DSC_RC_OFFSETS_2sblk->enc.base + DSC_RC_RANGE_BPG_OFFSETS_0sblk->enc.base + DSC_RC_RANGE_BPG_OFFSETS_2reg->en_offINTF_VSYNC_PERIOD_F0base + PP_DITHER_MATRIX + iSSPP_SW_PIX_EXT_C1C2_TBinvalid ctx %pK QSEED3_OP_MODE + scaler_offsetWB_DST_YSTRIDE1WB_OUT_IMAGE_SIZE__data_loc char[]valuewb_idxid:%u is_virtual:%s multirect_mode:%u cfg_dpu_kms_initialize_dsiparalleldpu_plane_atomic_check3[drm:%s] [dpu error]failed to reserve hw resources: %d VBIF_NRTUnsupported UBWC decoder version %x &priv->vram.lock flags id ref offset kaddr size madv name *ERROR* cannot import without IOMMU msm_obj->vaddrPurging %u vmaps dp_debugA6XX_SP_CB_BINDLESS_DATAA6XX_DBGBUS_GMU_CX dwords: %d 6[drm-dp] %s: AHB regs mvid=0x%x, nvid=0x%x select: %#x, acr_ctrl: %#x ctrl_linkTU: delay_start_link: %d eDP auxbus population failed, rc=%d max_lanes=%d max_link_rate=%d type=%d hpd=%d PSR RFB STORAGE ERROR no core clocks are defined Enable core clks before link clks invalid dp_audio data 3%s: BSTATUS write failed V' H1dsi probed=%p 3%s: Failed to enable byte intf clk 3%s: unable to map Dsi ctrl base 3%s: Read cmd Tx failed, too short: %d PLL%d vddsdsi%d_phy_pll_out_byteclk4*** gpu fault: iova=%.16lx flags=%d (%u,%u,%u,%u) WRITE ringbuffer: CP | HW fault | status=0x%8.8X CPSP*ERROR* Unable to map the %s registers msm_hdmi*ERROR* failed to get phy regulators: %d hdmipllWaiting for PLL lock com_div_frac_start1_mode0 = 0x%x tx_l%d_tx_band = 0x%x pxo_boardhdmi_clk*ERROR* errors: %08x *ERROR* unexpected MDP minor revision: v%d.%d Cursor off *ERROR* failed to construct encoder STAGE6name inuse plane offsets[%d]:%8u crtc%d event:%u ts:%lld 3[drm:%s:%d] [dpu error]crtc%d ts:%lld received panel dead event id;%u, sw_event:%d, rc in ON state 3[drm:%s:%d] [dpu error]invalid pingpong hw 3[drm:%s:%d] [dpu error]Failed to get global statedpu_encoder_phys_cmd_disableenc%d intf%d vfp_fetch_lines %u vfp_fetch_start_vsync_counter %u enc%d intf%d v_front_porch %u v_back_porch %u vsync_pulse_width %u invalid handle for plane %d DSC_RC_MODEL_SIZESSPP_SRC_CONSTANT_COLORcsc_reg_off + 0x4QSEED3_DE_SHARPEN_CTL + offsetWB_DST1_ADDRBvaltimeout_countid=%u, intf_idx=%d enable=%s refcnt=%d enc_idclk_ratedpu_dev_probe3[drm:%s:%d] [dpu error]invalid kms disable_danger multirect_mode[0]=%s 3[drm:%s] [dpu error]invalid kms 3[drm:%s] [dpu error]DSC %d does not exist dpu_vbif_set_qos_remapcpu-cfgasync=%d crtc_mask=%x invalid flags: %08x msm_gem_unpin_iova???/%d: fence=%umeqME state: name = %s drm_dp_link rate = %u v_level = %d A6XX_HLSQ_CHUNK_CPS_RAM_TAGA6XX_HLSQ_PWR_REST_TAGA6XX_DBGBUS_SPTP_0 - debugbus-block: dp_catalog_dump_regsPSR frame capture done idle_patterns_sent enterfailed to read link video pattern. rlen=%zd sampling rate (0x%x) greater than max (0x%x) bpp = %d dp3[drm-dp] %s: invalid input core_mmssdsi_err_worker3%s: failed to get iova: %d data = 0x%x and ntohl(data) = 0x%x Couldn't identify PHY index Unable to get ahb clk DSI PLL lock success DSI PLL is %slocked, %sready dsi_14nm_phy_enable4Turning OFF PHY while PLL is on 3PLL(%d) lock failed qcom,sm4350a619_gmu.bina730_sqe.fw6 data: !!ascii85 | ALUACTIVEloading PFP ucode version: %u CP | DMA error The GMU frequency table is being truncated *ERROR* Available levels: *ERROR* Message %s id %d timed out waiting for response *ERROR* failed to create HDMI connector: %d can't find qfprom resource power up msm hdmi i2cPHY is %sready failed to get core_clk *ERROR* failed to initialize LVDS connector pp done time out, lm=%d vsyncVIG3%s: failed to assign hwpipe(s)! nonelm %d, op_mode 0x%X, ctl %d crtc%d -> enable %d, skip atomic_flush dpu_crtc_frame_event_cbenc%d cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld INTF_MODE_WB_BLOCKid: %u, sw_event:%d, rc in OFF state 3[drm:%s:%d] [dpu error]invalid encoder/device dpu_encoder_phys_wb_atomic_checkCDM_CDWN2_COEFF_COSITE_H_1CDM_CDWN2_OUT_SIZECTL_LAYER_EXT3(mixer_id)DSC_CHUNK_SIZEINTF_MUX%dformat_offSSPP_SRC1_ADDRSSPP_QOS_CTRLinvalid ctx %pK pcc base 0x%x csc_reg_off + 0x30WB_DST_FORMATid=%u, val=%d intf_idxIRQ=[%d, %d] callback:%ps msm_dpuCreate plane type %d with features %lx (cur %lx) dpu_plane_sspp_atomic_updateplane%d pipe:%d vbif:%d xin:%d rt:%d 3[drm:%s] [dpu error]failed lm object creation: err %d reserving hw for enc %d crtc %d num_lm: %d num_dsc: %d num_intf: %d cdm: %d 3[drm:%s] [dpu error]failed to get pp on lm %d default_rd_ot_limitclock enable failed, ret:%d *ERROR* failed to allocate VRAM strnlenmsm_obj->madv != 1*ERROR* %s: hangcheck detected gpu lockup rb %d! msm_fault_handlercrtc_event:%d%u CP_SQE_AC_STAT_ADDRA6XX_DBGBUS_VFDPA6XX_DBGBUS_VSCA6XX_DBGBUS_CCU_2&aux->mutex6[drm-dp] %s: LCLK regs enable=%d mainlink off TU: boundary_moderation_en: %d type=%d wrong hpd_state=%d pdev not found failed to initialize ctrl, rc = %d 3failed to initialize audio, rc = %d Link already setup, return failed to attach panel bridge: %d sampling_rate = 0x%x, channel_count = 0x%x Invalid: link rate = 0x%x,lane count = 0x%x Header Byte 1: value = 0x%x, parity_byte = 0x%x setting the default safe_to_exit_level = %u 3%s: QFPROM AKSV chk failed (AKSV=%02x%08x) 3%s: Authentication Part I failed 3%s: Read %s failed dsi_link_clk_enable_6g3%s: alloc tx gem obj failed, %d 3%s:Failed to enable vregs.ret=%d disp-enable3%s: host %d disable failed, %d dsi_mgr_bridge_post_disabledsi%d_lanedsi_phy_laneEXTERNAL%u.%u.%u.%ugfx-memtimestamp hifailed to read speed-bin. Some OPPs may not be supported by hardware *ERROR* Could not allocate SQE ucode: %d CP AHB error interrupt CCUGPU_SETGPU_DCVSHFI_H2F_MSG_PERF_TABLEHFI_H2F_MSG_CORE_FW_START*ERROR* failed to request IRQ%u: %d alt_ifacecom_coreclk_div = 0x%x rate=%lu pixclock=%lu *ERROR* failed to enable hdmi_clk: %d *ERROR* failed to enable lcdc_clk: %d *ERROR* %s: vtotal(%d) or vrefresh(%d) is 0 lm%d: blend config = 0x%08x. ext_cfg = 0x%08x hwmixer=%s %s: x=%d, y=%d roi_w=%d roi_h=%d src_x=%d src_y=%d hwpipe=%s STAGE4core_perfmin_core_ibclient type: %d Invalid CRC source %s for CRTC%d frame done completion waitenc%d intf%d pp %d, enabling mode: dpu_encoder_phys_wb_set_qosCDM_CDWN2_COEFF_OFFSITE_H_2sblk->enc.base + DSC_SLICE_SIZE&intr->irq_lockINTF_BORDER_COLORSSPP_SW_PIX_EXT_C3_TBSSPP_SW_PIX_EXT_C3_REQ_PIXELSSSPP_SPAREQSEED3_DE_ADJUST_DATA_1 + offset%d|%s|%d unsigned intIRQ=[%d, %d] uint64_tstruct dpu_hw_fmt_layoutdpu_plane_prepare_fb3[drm:%s] [dpu error]failed dsc object creation: err %d failed to acquire mdss reset MSM_WAIT_FENCE [%s%s%s: aspace=%p, %08llx,%s]&gpu->active_lock*ERROR* failed to initialize vblank id=%d pid=%d ring=%d:%d ticks=%lld nr_to_scan=%u pg, purged=%u pg, evicted=%u pg, active_purged=%u pg, active_evicted=%u pg CP_BV_SQE_STAT_ADDRA6XX_TP1_SMO_DATAA6XX_DBGBUS_VFD_3A6XX_DBGBUS_SPTP_1A6XX_DBGBUS_SPTP_2misc settings = 0x%x phy=%p init=%d power_on=%d READYPSR frame update done link training #2 failed. ret=%d Failed to disable clocks. ret=%d channel_count (0x%x) greater than max (0x%x) audio pattern type = 0x%x test_audio_period_ch_6 = 0x%x PSR LINK CRC ERROR DP_PHY_PMHeader Byte 2: value = 0x%x, parity_byte = 0x%x AKSV=%02x%08x msm_hdmi_hdcp_send_aksv_anV' H43%s: HDCP V Match timedoutbyte_intfdsi_link_clk_set_rate_v23%s: Failed to enable dsi src clk 3%s: failed to register mipi dsi host for DSI %d: %d qcom,dual-dsi-modePLL init failed; need separate clk driver returning vco rate = %lu dsi%d_pll_post_out_div_clkqcom,adreno-%u.%u*ERROR* could not parse qcom,chipid: %d size: %zd loading PM4 ucode version: %u HDMI Core: %s, HDMI_CTRL=0x%08x &hdmi->reg_lockmaster_iface*ERROR* failed to register pll clock *ERROR* bad cursor size: %dx%d lvds-vccs-3p3v*ERROR* unexpected MDP major version: v%d.%d msm8x16msm8917on*ERROR* unsupported configurationCURSOR1*ERROR* failed to construct plane %d (%d) LM4%s[%d]: request %d SMP blocks 3[drm:%s:%d] [dpu error]exceeds bandwidth: %ukb > %ukb 3[drm:%s:%d] [dpu error]invalid parameters crtc%d commit dpu_crtc_atomic_checkirq timeout id=%u, intf_mode=%s intf=%d wb=%d, pp=%d, intr=%d 3[drm:%s:%d] [dpu error]failed to setup encoder id;%u, sw_event:%d, rc in state %d id:%d skip schedule work 3[drm:%s:%d] [dpu error]get_line_count function not defined enc%d clk_rate=%lldkHz, clk_period=%d, linetime=%dns &cmd_enc->pending_vblank_wq3[drm:%s:%d] [dpu error]invalid phys encoder 3[drm:%s:%d] [dpu error]failed to create encoder due to invalid parameter 3[drm:%s:%d] [dpu error]vstart:%d,vend:%d,vtot:%d,vdisplay:%d id:%u enable=%d/%d dpu_encoder_phys_wb_prepare_for_kickoffplane format modifier 0x%llX CTL_LAYER_EXT4(lm)3[dpu error]invalid IRQ=[%d, %d] irq_cb:%ps no registered cb, IRQ=[%d, %d] INTF_ACTIVE_V_END_F0PP_SYNC_THRESHcsc_blkSSPP_SRC0_ADDR + i * 0x4SSPP_SRC2_ADDRQSEED3_PHASE_INIT + scaler_offsetQSEED3_PHASE_STEP_UV_H + scaler_offsetcsc_reg_off + 0x8WB_DST3_ADDRWB_DST_PACK_PATTERNWB_DST_ADDR_SW_STATUSu64irq_bitvoid *idle_pc_supportedid=%u, IRQ=[%d, %d], rc=%d, time=%lld, expected=%lld cnt=%d modifierinvalid OPP table in device tree top3[drm:%s:%d] [dpu error][%u]SSPP is invalid %s: pnd 0x%X, src 0x%X xin_halt_timeout3[drm:%s:%d] [dpu error]invalid arguments vbif %d %s xin:%d ot_lim:%d upthreshold&ctx->queuelockFB[%u]: iova[%d]: %08llx (%d)*ERROR* could not allocate mmap offset msm_obj->pin_countput_task_map-wait-type-overridedrm-msm_gemvma->iova*ERROR* msm_disp_snapshot_init failed ret = %d include/linux/rcupdate.h&xa->xa_lockpid_tnr_bosnr_to_scanmsm_dp_test_type0CP_BV_SQE_UCODE_DBG_ADDRA6XX_SP_CB_LEGACY_DATAA6XX_DBGBUS_VFD_1 - { offset: 0x%06x, value: 0x%08x } pattern: %#x NOT READYFailed to disable pixel clocks. ret=%d request: 0x%x audio comp timeout sink request=%#x failed to read 0x%x updated bpp = %d 3%s: hdcp authentication failed Link0-An=%08x%08x 3%s: BCAPS read failed msm_hdmi_hdcp_auth_part2_recv_ksv_fifomsm_hdmi_hdcp_hw_ddc_cleanpixelret=%d 3%s: enable host1 failed, %d *ERROR* %s: resource enable failed, %d *ERROR* failed to parse qcom,phy-drive-ldo-level, %d a300_pfp.fwa530_zap.mdtUNKNOWN%s: invalid param: %u - ttbr0=%.16llx *ERROR* Unable to find the OPP table UCHE | Out of bounds access | addr=0x%llX %s: Unable to load GPMU firmware. GPMU will not be active *ERROR* a630 SQE ucode is too old. Have version %x need at least %x *ERROR* Unable to power off the GPU RSC GMU firmware fault *ERROR* Unable to set the OPP table for the GMU MC0qfprom_physical*ERROR* failed to enable regulators: (%d) com_dec_start_mode0 = 0x%x msm8x96&ctl_mgr->pool_lock&mdp5_kms->resource_lockno SMP pool multirect[0]: mode: %d index: %d 3[drm:%s:%d] [dpu error]invalid encoder id:%u, sw_event:%d, rc:%d frame pending 3[drm:%s:%d] [dpu error]enc%d intf%d no INTF provided dpu_encoder_phys_wb_set_qos_remap[fb_stride:%8.8x,%8.8x,%8.8x,%8.8x] CTL_CDM_ACTIVEINTF_TEAR_VSYNC_INIT_VALsrc_size_offSSPP_SRC_YSTRIDE1csc_reg_off + 0x20danger_lutsafe_lut%s|%d|%s eventenum dpu_intfid=%u, event=%u, intf_mode=%s intf=%d wb=%d 3[drm:%s:%d] [dpu error]failed to init vbif %d: %d SSPP%d : 0x%x Disabling danger: dpu_plane_duplicate_state3[drm:%s:%d] [dpu error]> %d plane stages assigned 3[drm:%s] [dpu error]invalid number of lm: %d wait_event.lockinvalid params --- 0x%lx : %08x %08x %08x %08x init_lock.wait_lockinclude/linux/uaccess.h vmas:update_lru_locked(vma->iova + obj->size) > range_end&gpu->perf_lock*ERROR* %s: offending task: %s (%s) rcu_read_unlock() used illegally while idleentity_lock.wait_lockclock num_lanes = %u sdp_cfg2 = 0x%x setting rate=%lu on clk=%s After, type=%d hpd_state=%d bpp=%d not supported, use bpc=8 PSR VSC SDP UNCORRECTABLE ERROR ctrl6%s: AUTH_FAIL_INT rcvd, LINK0_STATUS=0x%08x msm_hdmi_hdcp_scm_wrmsm_hdmi_hdcp_auth_part1_recv_r0Queue AUTH WORK dsi_ctrlbuf=%p dlen=%d diff=%d 3%s: unable to enable ahb_clk dsi_cmd_dma_addFailed to map phy regulator base dsi_phy_enable_resourceDSI%d PLL restore state %x %x compatiblea330_pfp.fwqcom/%sfault-info: registers: no a2xx device MMU_PAGE_FAULT: %08X %s: timeout waiting for RBCCU GDSC enable: %X a5xx_gpmu_err_irq%s: GPMU firmware initialization failed: %d GMU firmware is not loaded failed to get pwr clk: %s phys*ERROR* failed to configure avi infoframe tx_l%d_tx_drv_lvl = 0x%x vddioVG2No interconnect support may cause display underflows! *ERROR* failed to construct crtc %d (%d) AVAIL: %d 3[drm:%s:%d] [dpu error]no bandwidth limits specified crtc=%d clk_rate=%llu core_ib=%llu core_ab=%llu modifier:%8llu dst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d 3[drm:%s:%d] [dpu error]invalid dpu encoder/master frame doneid:%u, unexpected sw_event: %d dpu_encoder_virt_atomic_mode_set3[drm:%s:%d] [dpu error]enc%d no pp block assigned at idx: %d 3[drm:%s:%d] [dpu error]enc%d failed to init cmd enc: %ld vblank irq err id:%u pp:%d ret:%d, enable %s/%d buffers total size too small %u expected %u CTL_STARTDSC_FIRST_LINE_BPG_OFFSETsblk->enc.base + DSC_RC_BUF_THRESH_3reg->clr_offINTF_ACTIVE_V_START_F0LM_BORDER_COLOR_0featuresVBIF_XIN_CLR_ERRid=%u flagsid=%u, pp=%d, enable=%s, refcnt=%d enum dpu_sspp3[drm:%s:%d] [dpu error]failed to init kms, ret=%d 3[drm:%s:%d] [dpu error]initialize_dsi failed, rc = %d 3[drm:%s:%d] [dpu error]initialize_WB failed, rc = %d dpu_kms_wait_for_commit_done multirect_mode[1]=%s plane%d invalid yuv source %dx%d%+d%+d plane%d pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx 3[drm:%s] [dpu error]DSC %d is already allocated ===================dpu drm state================ downdifferential6[drm] using VRAM carveout: %lx@%pa vma->mapped*ERROR* could not create ringbuffer %d: %d *ERROR* %s: completed fence: %u &perf->read_lockCP_SQE_AC_UCODE_DBG_ADDRA6XX_HLSQ_GFX_CVS_CONST_RAM_TAGA6XX_DBGBUS_LARCA6XX_DBGBUS_VFD_2A6XX_DBGBUS_TPL1_0A6XX_DBGBUS_SPTP_5Unexpected DP AUX IRQ %#010x when not busy intr_mask=%#x config=%#x Failed to set v/p levels failed to initialize power, rc = %d lane=%d req_vol_swing=%d req_pre_emphasis=%d failed to parse test_htotal(DP_TEST_H_TOTAL_HI) failed to parse test_v_total(DP_TEST_V_TOTAL_HI) test_audio_period_ch_3 = 0x%x PSR Capability Change no clocks are defined 6%s: Unable to clear HDCP DDC Failure 3%s: Wait An timedoutmsm_hdmi_hdcp_auth_part2_check_v_match3%s: unable to identify DSI host index Dsi Host %d initialized msm_dsi_host_power_on*ERROR* bad number of data lanes 3%s: failed to prepare host, %d qcom,master-dsi%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d dsi%dn1_postdiv_clkSSC not enabled qcom,phy-rescode-offset-topa530v3_gpmu.fw24*** gpu fault: ttbr0=%.16llx iova=%.16lx dir=%s type=%s source=%s (%u,%u,%u,%u) *ERROR* failed to load %s IO:region %s 00000000 00020000 IO:R %08x %08x %s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d pfp writeme writeCP | AHB error | addr=%X access=%s error=%d | status=0x%8.8X GPMU | voltage droop dcache*ERROR* GMU firmware is bigger than the available region &queue->lockDisableddc_status=%08x *ERROR* %s: failed to register clk provider: %d com_lock_cmp_en = 0x%x msm_hdmi_pll_8960_initqcom,lcdc-align-lsbcursor_set is deprecated with cursor planes no encoder found for crtc %d LM1 right-hwpipe=%s assign %s:%u, %u blks crtc%d first commit 3[drm:%s:%d] [dpu error]time to vsync should not be zero, vtotal=%d &dpu_enc->enc_lockenc%d pre stopstopenddpu_encoder_virt_atomic_enabledpu_encoder_virt_atomic_check3[drm:%s:%d] [dpu error]invalid arg(s), enc %d 3[drm:%s:%d] [dpu error]invalid encoder %d 3[drm:%s:%d] [dpu error]invalid fb w=%d, maxlinewidth=%u invalid arguments CDM_CDWN2_COEFF_COSITE_H_2DSC_SLICEintr->intr_set[reg_idx].clr_offINTF_VSYNC_PULSE_WIDTH_F0base + PP_DITHER_ENsblk->csc_blk.base + SSPP_VIG_CSC_10_OP_MODE[%s:0x%X] <= 0x%X QSEED3_PHASE_INIT_Y_V + scaler_offsetQSEED3_PHASE_STEP_Y_V + scaler_offsetQSEED3_DE_THRESHOLD + offsetQSEED3_DE_ADJUST_DATA_0 + offsetextra_flush_bitsid:%d enc_id:%u callbackctl_flush Danger signal status: Enabling danger: 3[drm:%s:%d] [dpu error]failed to install zpos property, rc = %d unable to find appropriate mixers qos remap not supported crtc_mask=%x invalid op: %08x *ERROR* unsupported pixel format: %4.4s Invalid madv state: %u vs %u *ERROR* failed to enable 'gpu_reg': %d comm: %s %5d.%02drd&rd->write_lock pixel clock khz = %d num_lanes = %d A6XX_SP_CB_BINDLESS_TAGA6XX_HLSQ_CVS_MISC_RAM_TAGA6XX_HLSQ_GFX_CPS_CONST_RAM_TAGA6XX_SP_LB_6_DATAA6XX_DBGBUS_CCU_1A6XX_DBGBUS_SP_0A6XX_DBGBUS_TPL1_54[drm] Unexpected interrupt: %#010x dp_p0DP_CONFIGURATION_CTRL=0x%x rate=%d, num_lanes=%d, pixel_rate=%lu %s: test->0x%x failed to resume power failed to complete DP link training 3event_q is full: pndx=%d gndx=%d No sink connected DP link status read failed test_audio_period_ch_4 = 0x%x strem_clks:%s link_clks:%s core_clks:%s msm_hdmi_hdcp_auth_work6%s: msleep is canceled by event %d 3%s: No downstream devices 3%s: Failed to set rate byte clk, %d 3%s: forcing mdss_dsi lanes to 1 rlen=%d pkt_size=%d rx_byte=%d dsi host already on msm_dsi_host_set_display_modedsi_clk_init3%s: host1 disable failed, %d dsi_phy_regulatorvco=%lld ref=%d &pll_10nm->postdiv_lock - dir=%s rb wptr: %d CP_INT: %08X ALUFULL*ERROR* missing support for speed-bin: %u. Some OPPs may not be supported by hardware UCHE | Out of bounds access gmu_pdcHFI_H2F_MSG_PREPARE_SLUMBERmsm_hdmi_pll_8996_initDEC_START: %llu *ERROR* unknown bpp: %d MDP4 version v%d.%d&mdp5_crtc->lm_lock cmd_mode=%d *ERROR* couldn't assign mixers %d &mdp5_encoder->intf_lockbusmdp1-memVIG2DMA0*ERROR* unknown intf: %d %s: update ---- ----- ----- crtc:%d enabled:%d core_clk:%llu enable_bw_release plane:%u stage:%d dpu_crtc_atomic_flush3[drm:%s:%d] [dpu error]invalid params enc_prepare_for_kickoffenc%d created 3[drm:%s:%d] [dpu error]enc%d unknown wait event %d INTF_MODE_CMDid:%u invalid timeout enc%d intf%d pp %d dpu_encoder_phys_wb_init3[drm:%s:%d] [dpu error]encoder is already disabled 3[drm:%s:%d] [dpu error]unsupported fmt: %4.4s modifier 0x%llX CDM_HDMI_PACK_OP_MODECDM_MUXCTL_DSC_FLUSHCTL_SW_RESETINTF_ACTIVE_DATA_HCTLINTF_TIMING_ENGINE_EN3[dpu error]enc%d pp%d disable autorefresh failed PP_DCE_DATA_OUT_SWAPsrc_blkcsc_reg_off + 0x18offsetVBIF_XINL_QOS_RP_REMAP_000 + reg_highWB_OUT_XYWB_MUXdrm_idstage_strid=%u, idx=%u, frame_busy_mask=%lx id=%u, pp=%d, timeout_count=%d, kickoff_count=%d, event=%u plane_iddev_name3[drm:%s:%d] [dpu error]modeset init failed: %d 3[drm:%s:%d] [dpu error]encoder init failed for HDMI display kms_complete_commit3[drm:%s] [dpu error]failed cdm object creation: err %d _dpu_rm_make_reservationctl %d caps 0x%lX MSM Snapdragon DRMwait_fencerbbmtimeractive_evictedhdisplay: %d gmu-hfi: A6XX_SP_SMO_TAGA6XX_HLSQ_CHUNK_CPS_RAMA6XX_HLSQ_ICB_CVS_CB_BASE_TAGA6XX_HLSQ_GFX_CVS_CONST_RAMCLUSTER_FEA6XX_DBGBUS_UCHEA6XX_DBGBUS_TPFCHEA6XX_DBGBUS_HLSQ_SPTPA6XX_DBGBUS_VFD_5 - bank: %d - debugbus-block: A6XX_DBGBUS_VBIF failed to disable DP controller type=%d core_init=%d phy_init=%d failed to read test_audio_period (0x%x) Current: rate = 0x%x, lane count = 0x%x legacy memory region not large enough links clks already enabled pixel clks already enabled failed to get audio data dp_audio_hook_plugged_cbAfter enabling HDCP Link0_Status=0x%08x Link ASKV=%08x%08x R0'=%02x%02x dsi_byte_clk_get_rate(work_completion)(&msm_host->err_work)3%s: cannot get interface clock 3%s: cmd dma tx failed, type=0x%x, data0=0x%x, ret=%d len=%d qcom,sync-dual-dsi*ERROR* PLL(%d) lock failed dsi_10nm_phy_enableFound GPU: %u.%u.%u.%u a630_zap.mdtTimeout waiting for GPU to suspend - id: %d zap-shader*ERROR* No memory protection without IOMMU VSCgmuBOOT_SLUMBER(work_completion)(&hdmi_bridge->hpd_work)frame_ctrl=%08x *not* HSCLK_SEL: %d set mode: "%s": %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x *ERROR* failed to construct crtc for %s RGB2msm8x74v1mdp5_crtc_flip_cleanup ctl=%d mdp_physVIG0 blend_mode=%u *ERROR* Y scaling (%d->%d) failed: %d crtc:%d bw:%llu ctrl:%d invalid FB not kicking off crtc encoder_kickoff&dpu_enc->rc_lock_dpu_encoder_update_vsync_source3[drm:%s:%d] [dpu error]enc%d no ctl block assigned at idx: %d &phys_enc->vblank_ctl_lockid:%u pp:%d pending_cnt:%d programmable_fetch_get_num_linesenc%d intf%d wc_lines %u needed_vfp_lines %u actual_vfp_lines %u 3[drm:%s:%d] [dpu error]failed to allocate wb phys_enc enc failed to populate layout %d [fb_offset:%8.8x,%8.8x,%8.8x,%8.8x] dpu_hw_cdm_setup_cdwnSkip intf %d with type NONE INTF_TEAR_MDP_VSYNC_SELPP_AUTOREFRESH_CONFIGdisable pcc feature csc_reg_off + 0x1cQSEED3_DE_SHAPE_CTL + offsetVBIF_XIN_HALT_CTRL0WB_OUT_SIZEfmtcounter_nameunsigned longenabledframe_pending3[drm:%s:%d] [dpu error]dpu_plane_init failed danger_statusdpu_runtime_resume sspp[0]=%s dst[0]=%dx%d%+d%+d _dpu_plane_calc_fill_level3[drm:%s:%d] [dpu error]invalid vbif %d *ERROR* failed to populate children devices 6[drm] using %s VRAM carveout VRAM: %08x->%08x MSM_GEM_CPU_PREPMSM_GEM_SUBMIT*ERROR* failed to allocate buffer object create: FB ID: %d (%p)msm_gem_set_iova&gpu->lock&gpu->retire_event dp_link: test_requested = %d CP_MEMPOOLA6XX_SP_INST_DATAA6XX_HLSQ_PWR_REST_RAMA6XX_HLSQ_FRONTEND_METACLUSTER_GRASCLUSTER_SP_PSA6XX_DBGBUS_DCSA6XX_DBGBUS_TPL1_3 - cluster-name: dp_catalog_panel_tpg_enabledp_ctrl_push_idlePHY_TEST_PATTERN request Unable to start link clocks. ret=%d link training #1 successful %s clock doesn't exit to set rate %lu failed to initialize link, rc = %d sink count is zero, nothing to do DP parse sink count failed failed to parse test_h_start(DP_TEST_H_START_HI) failed to parse (DP_TEST_HSYNC_HI) failed to parse test_v_height test_audio_period_ch_2 = 0x%x link_rate=%d 3%s: HDCP is not supported without qfprom DDC failure detected 3%s: wait key and an ready failed msm_hdmi_hdcp_auth_part1_key_exchange3%s:An/Aksv write failed 3%s: Recv ksv fifo timedoutmsm_hdmi_hdcp_auth_part2_write_ksv_fifoBLOCK_DONE *ERROR* failed to create dsi bridge: %d msm_dsiavdddsi_clk_init_6g_v23%s: Set max pkt size failed, %d 3%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d, ret=%d *ERROR* %s: regulator enable failed, %d Failed to register clk provider no GPU device was found adrenofailed to load adreno gpu qcom,sm6375*ERROR* SCM is not available zloading PFP ucode version: %x status: %08x pm4fwpfpfwtimestamp lo*ERROR* %s: Preemption failed to complete PERFCOUNTER*ERROR* failed to create HDMI bridge: %d failed to get HPD gpio *ERROR* rate[%d] not supported! iface*ERROR* couldn't init PLL *ERROR* failed to get phy clock: %s (%d) com_integloop_gain0_mode0 = 0x%x %s: error: %08x setting mdp_clk=%lu failed to get axi_clk *ERROR* CTL %d cannot find LM*ERROR* failed to get %s (%ld) fb:%d image format:%4.4s wxh:%ux%u *ERROR* crtc%d event %d overflow no frames pending IRQ=[%d, %d] timeout id=%u, callback=%ps, pp=%d, atomic_cnt=%d dpu_encoder_resource_controlenc%d intf%d intf %d pp %d enc%d intf%d room in vfp for needed prefetch 3[drm:%s:%d] [dpu error]invalid connector state [enc:%d] cdm_disable fmt:%x CTL_MERGE_3D_FLUSH3unknown interface type %d sblk->enc.base + DSC_RC_OFFSETS_1INTF_POLARITY_CTLINTF_CONFIGINTF_TEAR_SYNC_CONFIG_VSYNCINTF_TEAR_START_POSLM_OUT_SIZESSPP_SRC0_ADDRmodestop_reqframe_busy_maskfb_idstage dst[1]=%dx%d%+d%+d dpu_rm_reserve3[drm:%s] [dpu error]More than %d resources assigned to enc %d ??msm-mdss&kms->dump_mutexmodule: msm allocating %d bytes for fb %d *ERROR* framebuffer init failed: %d !vma!is_purgeable(msm_obj)vma->iova < range_start*ERROR* %s: submitted fence: %u aspace create, error %pe bpc: %u %02xshader-blocks: CP_SQE_STATsdp_cfg = 0x%x Failed to start pixel clocks. ret=%d Failed to %s low power mode Requested vSwingLevel=%d, change to %d failed to read link rate. rlen=%zd vx: 0=%d, 1=%d, 2=%d, 3=%d width=%d hporch= %d %d %d core_clk_on=%d link_clk_on=%d stream_clk_on=%d DP_STREAM_PM3: BKSV doesn't have 20 1's and 20 0's 3%s:R0' read failed *ERROR* failed to modeset init host: %d 3%s: Failed to set rate byte intf clk, %d Set clk rates: pclk=%d, byteclk=%lu, esc_clk=%lu, dsi_src_clk=%lu dsi_isr*ERROR* bad physical lane entry %u Cmd test pattern setup done Failed to map phy base dsi%dpllbytedsi%dn1_postdivby2_clkstep_size=%lld DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x a530_pfp.fwa512_zap.mdta730_zap.mdtrbbm-status: 0x%08x *ERROR* Unable to authorize the image %s: %08x me read*ERROR* a650 SQE ucode is too old. Have version %x need at least %x CP | AHB bus error LRZ*ERROR* Timeout waiting for GMU OOB set %s: 0x%x gmu_pdc_seq*ERROR* Unable to send message %s id %d *ERROR* failed to get phy core-vcc*ERROR* failed to enable hpd clk: %s (%d) INTEGLOOP_GAIN: %u tx_l%d_vmode_ctrl1 = 0x%x %s:%dmdp4_crtc_flip_cleanup%s: send event: %p *ERROR* failed to configure lcdc_clk: %d *ERROR* failed to get lut_clk *ERROR* failed to construct LCDC encoder *ERROR* failed to initialize HDMI: %d *ERROR* failed to construct DSI encoder: %d *ERROR* vsync_clk round rate failed %ld Single FLUSH mask %x,ID %d cursor_move is deprecated with cursor planes tbuskipping %s %s: free SMP blocks LM0*ERROR* X scaling (%d->%d) failed: %d 3[drm:%s:%d] [dpu error]invalid crtc crtc%u sspp[0]:%s bw_ctl: %llu id=%u, callback=%ps, IRQ=[%d, %d], pp=%d, pending_cnt=%d 3[drm:%s:%d] [dpu error]invalid arg(s), encoder %d dpu_encoder_register_frame_event_callbackINTF_MODE_VIDEOdpu_encoder_phys_cmd_control_vblank_irqenc%d intf%d invalid - no vsync clock dpu_encoder_phys_vid_disableCDM_CDWN2_CLAMP_OUTsblk->ctl.base + DSC_CTLIRQ=[%d, %d] count:%d cb:%ps INTF_HSYNC_CTLINTF_DISPLAY_DATA_HCTLINTF_PROG_FETCH_STARTLM_BORDER_COLOR_1scaler_blkSSPP_FETCH_CONFIGop_mode_offSSPP_SW_PIX_EXT_C1C2_REQ_PIXELSbase + PCC_BLUE_R_OFFQSEED3_PHASE_STEP_UV_V + scaler_offsetoffset + QOS_CREQ_LUTenableenum dpu_sspp_multirect_indexintfmapped dpu address space @%pK [crtc:%d] not active plane%d invalid dest rect %dx%d%+d%+d plane%d FB[%u] %d.%06ux%d.%06u%+d.%06u%+d.%06u->crtc%u %dx%d%+d%+d, %4.4s ubwc %d 3[drm:%s] [dpu error]CDM block does not exist handle irq fail: irq=%lu rc=%d mm*ERROR* failed to allocate drm_device &priv->obj_lockMSM_GEM_INFOmsm_gem_unpin_lockedActive: %4d objects, %9zu bytes DEBUG_LOCKS_WARN_ON(%s)&aspace->lock*ERROR* failed to enable 'gpu_cx': %d &ring->preempt_lockA6XX_SP_LB_0_DATAA6XX_SP_LB_1_DATAA6XX_HLSQ_GFX_CPS_CONST_RAMA6XX_DBGBUS_LRZA6XX_DBGBUS_SPTP_3Before, phy=%p init_count=%d power_on=%d TU: valid_lower_boundary_link: %d msm-dp-displaydevice tree parsing failed PSR IRQ_HPD received PSR Capability changed core clks already enabled 3%s: AKSV QFPROM doesn't have 20 1's, 20 0's 3%s:BCAPS read failed 3%s: fail to reset sha engine 3%s: Write KSV fifo timedoutsyscon-sfpbid=%d Power on failed: %d yamato_pfp.fwRBBM | ATB ASYNC overflow sqefwlogHFI_H2F_MSG_BW_TABLEhdmi-audio-codechtotal=%d, vtotal=%d, hstart=%d, hend=%d, vstart=%d, vend=%d failed to disable hpd regulator: %d %s: set mode: "%s": %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x sdm660CTL %d allocated &ctl->hw_lock(null)MDP5 version v%d.%d*ERROR* failed to find dsi from intf %d STAGE3release %s vblank fps:%lld count:%u total:%llums total_framecount:%llu lm[%d]=%d encoder_vblank_callback3[drm:%s:%d] [dpu error]encoder master not set 3[drm:%s:%d] [dpu error]line time calculation is 0 3[drm:%s:%d] [dpu error]enc%d too many physical encoders %d dpu_encoder_phys_cmd_init[qos_remap] wb:%d vbif:%d xin:%d is_rt:%d fmt %4.4s mod 0x%llX ubwc %d yuv %d invalid pointer CTL_CDM_FLUSHDSC_DELAYINTF_FRAME_LINE_COUNT_ENPP_RD_PTR_IRQenc%d pp%d disabled autorefresh base + PCC_GREEN_R_OFFbase + PCC_GREEN_G_OFFbase + PCC_BLUE_B_OFFQSEED3_PHASE_INIT_UV_V + scaler_offsetbw_ctlid=%u, flags=%u kickoff_countmixer3[drm:%s:%d] [dpu error]mdp register memory map failed: %d vbif_nrt3[drm:%s:%d] [dpu error]dpu_kms_mmu_init failed: %d _dpu_kms_initialize_displayportsafe_status stage=%d plane%d pnum:%d fmt: %4.4s w:%u fl:%u 3[drm:%s] [dpu error]unable to find appropriate CTL msm_mdsslist_lockatomic-worker-%ddisable_err_irq16minit_lockmsm_obj->vmap_count < 1*ERROR* could not get pages: %ld non-aligned cmdstream buffer size: %u gpu-workergpu-irqring%dentity_lockpfpinvalid input bw_code = %d CP_LPAC_DRAW_STATE_ADDRA6XX_TP0_SMO_DATAA6XX_DBGBUS_PC - context: %d dp_auxsink: p|v=0x%x TU: lower_boundary_count: %d *ERROR* failed to create dp bridge: %d exittest_audio_period_ch_5 = 0x%x Test:0x%x link rate = 0x%x, lane count = 0x%x read dpcd failed %d unable to remap aux region: %pe disableUnknown link rate dsi_clk_init_v23%s: dev_pm_opp_set_rate failed %d 3%s: Failed to enable dsi byte clk 3%s: cmd cannot fit into BLLP period, len=%d 3%s: create packet failed, %d 3%s: power on host1 failed, %d %d, %d, %d, %d, %d    \  xu  CN N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N $NN N NN N N pingpong_00 pingpong_10 "pnum=%d fmt=%x rt=%d fl=%d lut=0x%llx lut_usage=%d", REC->pnum, REC->fmt, REC->rt, REC->fl, REC->lut, REC->lut_usage"pnum=%d fmt=%x mode=%d luts[0x%x, 0x%x]", REC->pnum, REC->fmt, REC->mode, REC->danger_lut, REC->safe_lut"pnum:%d xin_id:%d ot:%d vbif:%d", REC->pnum, REC->xin_id, REC->rd_lim, REC->vbif_idx"crtc:%d", REC->crtc_id"%s|%d|%s", REC->trace_begin ? "B" : "E", REC->pid, __get_str(trace_name)"%d|%s|%d", REC->pid, __get_str(counter_name), REC->value"crtc=%d bw_ctl=%llu clk_rate=%u stop_req=%d u_bus=%d u_clk=%d", REC->crtc, REC->bw_ctl, REC->core_clk_rate, REC->stop_req, REC->update_bus, REC->update_clk"IRQ=[%d, %d]", REC->irq_reg, REC->irq_bit"id=%u, callback=%ps, IRQ=[%d, %d], pp=%d, atomic_cnt=%d", REC->drm_id, REC->func, REC->irq_reg, REC->irq_bit, REC->pp_idx, REC->atomic_cnt"id=%u", REC->drm_id"id=%u, mode=%dx%d", REC->drm_id, REC->hdisplay, REC->vdisplay"id=%u, val=%d", REC->drm_id, REC->val"id=%u, flags=%u", REC->drm_id, REC->flags"id=%u, enable=%s", REC->drm_id, REC->enable ? "true" : "false""%s: id:%u, sw_event:%d, idle_pc_supported:%s, rc_state:%d", __get_str(stage_str), REC->drm_id, REC->sw_event, REC->idle_pc_supported ? "true" : "false", REC->rc_state"id=%u, event=%u, intf_mode=%s intf=%d wb=%d", REC->drm_id, REC->event, __get_str(intf_mode_str), REC->intf_idx, REC->wb_idx"id=%u, idx=%u, frame_busy_mask=%lx", REC->drm_id, REC->idx, REC->frame_busy_mask"id=%u, intf_mode=%s, intf_idx=%d, wb_idx=%d, pending_kickoff_cnt=%d ctl_idx=%d extra_flush_bits=0x%x pending_flush_ret=0x%x", REC->drm_id, __get_str(intf_mode_str), REC->intf_idx, REC->wb_idx, REC->pending_kickoff_cnt, REC->ctl_idx, REC->extra_flush_bits, REC->pending_flush_ret"id=%u, event=%u", REC->drm_id, REC->event"id=%u, IRQ=[%d, %d], rc=%d, time=%lld, expected=%lld cnt=%d", REC->drm_id, REC->irq_reg, REC->irq_bit, REC->rc, REC->time, REC->expected_time, REC->atomic_cnt"id=%u, pp=%d, enable=%s, refcnt=%d", REC->drm_id, REC->pp, REC->enable ? "true" : "false", REC->refcnt"id=%u, pp=%d, new_count=%d, event=%u", REC->drm_id, REC->pp, REC->new_count, REC->event"id=%u, pp=%d, timeout_count=%d, kickoff_count=%d, event=%u", REC->drm_id, REC->pp, REC->timeout_count, REC->kickoff_count, REC->event"id=%u, intf_idx=%d", REC->drm_id, REC->intf_idx"id=%u, intf_idx=%d enable=%s refcnt=%d", REC->drm_id, REC->intf_idx, REC->enable ? "true" : "false", REC->drm_id"crtc_id:%u plane_id:%u fb_id:%u src:%d.%06ux%d.%06u%+d.%06u%+d.%06u dst:%dx%d%+d%+d stage_idx:%u stage:%d, sspp:%d multirect_index:%d multirect_mode:%u pix_format:%u modifier:%llu", REC->crtc_id, REC->plane_id, REC->fb_id, drm_rect_width(&REC->src_rect) >> 16, ((drm_rect_width(&REC->src_rect) & 0xffff) * 15625) >> 10, drm_rect_height(&REC->src_rect) >> 16, ((drm_rect_height(&REC->src_rect) & 0xffff) * 15625) >> 10, (&REC->src_rect)->x1 >> 16, (((&REC->src_rect)->x1 & 0xffff) * 15625) >> 10, (&REC->src_rect)->y1 >> 16, (((&REC->src_rect)->y1 & 0xffff) * 15625) >> 10, drm_rect_width(&REC->dst_rect), drm_rect_height(&REC->dst_rect), (&REC->dst_rect)->x1, (&REC->dst_rect)->y1, REC->stage_idx, REC->stage, REC->sspp, REC->multirect_idx, REC->multirect_mode, REC->pixel_format, REC->modifier"id:%u mixer:%d bounds:%dx%d%+d%+d", REC->drm_id, REC->mixer, drm_rect_width(&REC->bounds), drm_rect_height(&REC->bounds), (&REC->bounds)->x1, (&REC->bounds)->y1"id:%u encoder:%u enable:%s state{enabled:%s}", REC->drm_id, REC->enc_id, REC->enable ? "true" : "false", REC->enabled ? "true" : "false""id:%u enable:%s state{enabled:%s}", REC->drm_id, REC->enable ? "true" : "false", REC->enabled ? "true" : "false""id:%u frame_pending:%d", REC->drm_id, REC->frame_pendingH"index:%d layout:{%ux%u @ [%u/%u, %u/%u, %u/%u, %u/%u]} multirect_index:%d", REC->index, REC->layout.width, REC->layout.height, REC->layout.plane_addr[0], REC->layout.plane_size[0], REC->layout.plane_addr[1], REC->layout.plane_size[1], REC->layout.plane_addr[2], REC->layout.plane_size[2], REC->layout.plane_addr[3], REC->layout.plane_size[3], REC->multirect_index"id:%u is_virtual:%s multirect_mode:%u", REC->drm_id, REC->is_virtual ? "true" : "false", REC->multirect_mode"id:%d enc_id:%u", REC->id, REC->enc_id"id:%d enc_id:%u pp_id:%u", REC->id, REC->enc_id, REC->pp_id"index:%d xin_id:%u", REC->index, REC->xin_id"pp:%d cfg:%u", REC->pp, REC->cfg"intf:%d cfg:%u", REC->intf, REC->cfg"IRQ=[%d, %d] callback:%ps", REC->irq_reg, REC->irq_bit, REC->callback"IRQ=[%d, %d]", REC->irq_reg, REC->irq_bit"dev:%s stop_req:%s clk_rate:%llu", __get_str(dev_name), REC->stop_req ? "true" : "false", REC->clk_rate"new=%x existing=%x", REC->new_bits, REC->pending_mask"pending_mask=%x CTL_FLUSH=%x", REC->pending_mask, REC->ctl_flushT1T7`T 2lENN"async=%d crtc_mask=%x", REC->async, REC->crtc_mask"async=%d crtc_mask=%x", REC->async, REC->crtc_mask"crtc_mask=%x", REC->crtc_mask"crtc_mask=%x", REC->crtc_mask"crtc_mask=%x", REC->crtc_mask"crtc_mask=%x", REC->crtc_mask"crtc_mask=%x", REC->crtc_maskNN N N N N N N N N N N N N N N N N N N N N N 2N N"id=%d pid=%d ring=%d bos=%d cmds=%d", REC->id, REC->pid, REC->ringid, REC->nr_bos, REC->nr_cmds"id=%d pid=%d ring=%d:%d ticks=%lld", REC->id, REC->pid, REC->ringid, REC->seqno, REC->ticks"id=%d pid=%d ring=%d:%d elapsed=%lld ns mhz=%lld start=%lld end=%lld", REC->id, REC->pid, REC->ringid, REC->seqno, REC->elapsed, REC->clock, REC->start_ticks, REC->end_ticks"new_freq=%u", REC->freq"freq=%u, perf_index=%u", REC->freq, REC->perf_index"nr_to_scan=%u pg, purged=%u pg, evicted=%u pg, active_purged=%u pg, active_evicted=%u pg", REC->nr_to_scan, REC->purged, REC->evicted, REC->active_purged, REC->active_evicted"Purging %u vmaps", REC->unmapped"%u", REC->dummy"%u", REC->dummy 3   3  ) * 3 ' ( @ 6 @   ! ! 3     ` @DD044x||N N   @ @ @0 D4$ @H8( @ $D`dpu_perf_set_qos_lutsdpu_perf_set_danger_lutsdpu_perf_set_otdpu_cmd_release_bwtracing_mark_writedpu_trace_counterdpu_perf_crtc_updatedpu_irq_register_successdpu_irq_unregister_successdpu_enc_irq_wait_successdpu_enc_atomic_checkdpu_enc_mode_setdpu_enc_disabledpu_enc_kickoffdpu_enc_prepare_kickoffdpu_enc_prepare_kickoff_resetdpu_crtc_complete_flipdpu_crtc_vblank_cbdpu_crtc_complete_commitdpu_kms_commitdpu_kms_wait_for_commit_donedpu_crtc_runtime_resumedpu_enc_enabledpu_enc_underrun_cbdpu_enc_trigger_startdpu_enc_atomic_check_flagsdpu_enc_rc_helperdpu_enc_vblank_cbdpu_enc_frame_event_cbdpu_enc_phys_cmd_connect_tedpu_enc_rcdpu_enc_frame_done_cb_not_busydpu_enc_frame_done_cbdpu_enc_trigger_flushdpu_enc_frame_done_timeoutdpu_crtc_frame_event_cbdpu_crtc_frame_event_donedpu_crtc_frame_event_more_pendingdpu_enc_wait_event_timeoutdpu_enc_phys_cmd_irq_ctrldpu_enc_phys_cmd_pp_tx_donedpu_enc_phys_cmd_pdone_timeoutdpu_enc_phys_vid_post_kickoffdpu_enc_phys_vid_irq_ctrldpu_crtc_setup_mixerdpu_crtc_setup_lm_boundsdpu_crtc_vblank_enabledpu_crtc_enabledpu_crtc_disabledpu_crtc_vblankdpu_crtc_disable_frame_pendingdpu_plane_set_scanoutdpu_plane_disabledpu_rm_reserve_intfdpu_rm_reserve_ctlsdpu_rm_reserve_lmsdpu_vbif_wait_xin_halt_faildpu_pp_connect_ext_tedpu_intf_connect_ext_tedpu_core_irq_register_callbackdpu_core_irq_unregister_callbackdpu_core_perf_update_clkdpu_hw_ctl_update_pending_flushdpu_hw_ctl_clear_pending_flushdpu_hw_ctl_trigger_pending_flushdpu_hw_ctl_trigger_preparedpu_hw_ctl_trigger_startmsm_atomic_commit_tail_startmsm_atomic_commit_tail_finishmsm_atomic_async_commit_startmsm_atomic_async_commit_finishmsm_atomic_wait_flush_startmsm_atomic_wait_flush_finishmsm_atomic_flush_commitmsm_gpu_submitmsm_gpu_submit_flushmsm_gpu_submit_retiredmsm_gpu_freq_changemsm_gmu_freq_changemsm_gem_shrinkmsm_gem_purge_vmapsmsm_gpu_suspendmsm_gpu_resumeLinuxLinuxmsmk%w_dev_err pm_runtime_enableeE__pm_runtime_resume&{Hmutex_lock_nestedO*5drm_crtc_vblank_get.7drm_crtc_vblank_putU*v__drmm_crtc_alloc_with_planes$udrm_flip_work_initzk__drmm_add_action_or_resetdrm_crtc_send_vblank_event(;drm_flip_work_queuewdrm_flip_work_commitsdrm_flip_work_cleanup~drm_gem_object_lookup 4drm_mode_vrefreshyadrm_crtc_vblank_on;drm_crtc_vblank_off}drm_atomic_helper_crtc_reset3Ldrm_atomic_helper_set_configI0drm_atomic_helper_page_flipPlt{drm_atomic_helper_crtc_duplicate_statedrm_atomic_helper_crtc_destroy_state__drmm_encoder_alloc_of_drm_find_panel=tdrm_panel_disableֲdrm_panel_unprepare헫Yof_find_property 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xcomponent_master_del\regulator_enabler!rof_graph_get_remote_node꜇5drm_universal_plane_initqdrm_plane_cleanup\$9!drm_plane_enable_fb_damage_clipszdrm_gem_plane_helper_prepare_fbx/drm_atomic_helper_update_planedrm_atomic_helper_disable_planeKdrm_atomic_helper_plane_reset1XBdrm_atomic_helper_plane_duplicate_stateMdrm_atomic_helper_plane_destroy_state'͂__drm_atomic_helper_crtc_destroy_state|__drm_atomic_helper_crtc_resetA̴fkmemdup*__drm_atomic_helper_crtc_duplicate_state8Udrm_format_infoCsort]4Pdrm_crtc_set_max_vblank_countZ)drm_crtc_vblank_helper_get_vblank_timestampŔdrm_modeset_lock5zdrm_atomic_get_private_obj_stateJ]drm_modeset_lock_initRdrm_atomic_private_obj_initdrm_atomic_private_obj_finijЛ__drm_atomic_helper_private_obj_duplicate_state Ӂ%drm_debugfs_create_filesS__drm_printfn_seq_filer0Q__drm_puts_seq_fileF__sw_hweight64;drm_plane_create_rotation_propertyo'gdrm_plane_create_alpha_property7Jdrm_plane_create_blend_mode_propertydrm_plane_create_zpos_propertyaf__drm_atomic_helper_plane_destroy_state'Q__drm_atomic_helper_plane_reset__drm_atomic_helper_plane_duplicate_state8drm_atomic_helper_check_plane_stateifdrm_rotation_simplifyJu_find_first_bitQR!__bitmap_weight7{_find_first_zero_bit__bitmap_andnotS_find_next_bittdrm_modeset_unlock9#dev_pm_opp_set_rate`debugfs_create_dir'debugfs_create_u64TAdebugfs_create_u32 debugfs_create_file΁simple_read_from_buffer``kstrtouint_from_user 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|bpf_trace_run5&1bpf_trace_run4q>bpf_trace_run1fq`bpf_trace_run35(MVbpf_trace_run29bpf_trace_run8[Fbpf_trace_run74trace_raw_output_prepR+trace_event_printf хtrace_handle_returng$kdebugfs_create_x32*1ftrace_event_regytrace_event_raw_initC__drmm_universal_plane_allocdrm_writeback_connector_init_with_encoderܭ(drm_add_modes_noedid]__reset_control_getfKlreset_control_assertd !reset_control_deassert>h@reset_control_putxj#devm_platform_ioremap_resource_byname;of_icc_get7|:devm_clk_bulk_get_optionalq'__irq_domain_addٗeiirq_set_chained_handler_and_dataKof_platform_populate؜sirq_domain_remove9of_platform_depopulategeneric_handle_domain_irqn+__irq_set_lockdep_class#handle_level_irq)|Wirq_set_chip_and_handler_name irq_set_chip_data-zirq_domain_xlate_onecellkthread_create_workerddev_coredumpmzzkthread_destroy_workermutex_destroy^;__drm_puts_coredump__drm_printfn_coredumpdrm_atomic_print_new_statecNdrm_modeset_acquire_init` Sdrm_modeset_lock_all_ctxʲ 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