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CTRL LEN is configured incorrectly LinuxLinuxspi_pl022*amba_driver_registerūamba_driver_unregister=@_dev_info%]devm_kmalloc`HPof_property_read_variable_u32_array헫Yof_find_property __spi_alloc_controller\Ъamba_request_regions. devm_ioremapÞ7amba_release_regionsput_devicek%w_dev_errdevm_clk_get_enabled"devm_request_threaded_irq~bdevm_spi_register_controllerLPdev_err_probeϣ`__pm_runtime_idlem@pm_runtime_set_autosuspend_delaydh__pm_runtime_use_autosuspendm\alt_cb_patch_nopss^dma_release_channel zkfree/lspi_controller_suspendhnpm_runtime_force_suspend+spi_controller_resumeSpinctrl_pm_select_sleep_stateսpm_runtime_force_resumeclk_disable wclk_unpreparepinctrl_pm_select_idle_statepinctrl_pm_select_default_stateqs|clk_prepareUclk_enable9kmalloc_cachesڏnkmalloc_traceCnUclk_get_rateGV__warn_printkeGT_dev_warn__stack_chk_failIloops_per_jiffyPjiffiessg_alloc_tabledma_map_sg_attrsL-dma_unmap_sg_attrsPsg_free_table+@log_write_mmio$=Y\_bcUVWXf5%& ( . 5@ o a((pd p$LLDn\g|AX/Q@YHjcH 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fifodepthmax_bpwunidirextended_crpl023internal_cs_ctrlpl022_config_chiphierarchyslave_tx_disableclk_freqcom_moderx_lev_trigtx_lev_trigctrl_lenwait_stateclkdelayssp_interfaceSSP_INTERFACE_MOTOROLA_SPISSP_INTERFACE_TI_SYNC_SERIALSSP_INTERFACE_NATIONAL_MICROWIRESSP_INTERFACE_UNIDIRECTIONALssp_hierarchySSP_MASTERSSP_SLAVEssp_clock_paramscpsdvsrssp_modeINTERRUPT_TRANSFERPOLLING_TRANSFERDMA_TRANSFERssp_rx_level_trigSSP_RX_1_OR_MORE_ELEMSSP_RX_4_OR_MORE_ELEMSSP_RX_8_OR_MORE_ELEMSSP_RX_16_OR_MORE_ELEMSSP_RX_32_OR_MORE_ELEMssp_tx_level_trigSSP_TX_1_OR_MORE_EMPTY_LOCSSP_TX_4_OR_MORE_EMPTY_LOCSSP_TX_8_OR_MORE_EMPTY_LOCSSP_TX_16_OR_MORE_EMPTY_LOCSSP_TX_32_OR_MORE_EMPTY_LOCssp_microwire_ctrl_lenSSP_BITS_4SSP_BITS_5SSP_BITS_6SSP_BITS_7SSP_BITS_8SSP_BITS_9SSP_BITS_10SSP_BITS_11SSP_BITS_12SSP_BITS_13SSP_BITS_14SSP_BITS_15SSP_BITS_16SSP_BITS_17SSP_BITS_18SSP_BITS_19SSP_BITS_20SSP_BITS_21SSP_BITS_22SSP_BITS_23SSP_BITS_24SSP_BITS_25SSP_BITS_26SSP_BITS_27SSP_BITS_28SSP_BITS_29SSP_BITS_30SSP_BITS_31SSP_BITS_32ssp_microwire_wait_stateSSP_MWIRE_WAIT_ZEROSSP_MWIRE_WAIT_ONEssp_duplexSSP_MICROWIRE_CHANNEL_FULL_DUPLEXSSP_MICROWIRE_CHANNEL_HALF_DUPLEXssp_clkdelaySSP_FEEDBACK_CLK_DELAY_NONESSP_FEEDBACK_CLK_DELAY_1TSSP_FEEDBACK_CLK_DELAY_2TSSP_FEEDBACK_CLK_DELAY_3TSSP_FEEDBACK_CLK_DELAY_4TSSP_FEEDBACK_CLK_DELAY_5TSSP_FEEDBACK_CLK_DELAY_6TSSP_FEEDBACK_CLK_DELAY_7Tssp_readingREADING_NULLREADING_U8READING_U16READING_U32ssp_writingWRITING_NULLWRITING_U8WRITING_U16WRITING_U32ssp_rx_endianSSP_RX_MSBSSP_RX_LSBssp_tx_endianSSP_TX_MSBSSP_TX_LSBssp_spi_clk_polSSP_CLK_POL_IDLE_LOWSSP_CLK_POL_IDLE_HIGHssp_spi_clk_phaseSSP_CLK_FIRST_EDGESSP_CLK_SECOND_EDGEssp_loopbackLOOPBACK_DISABLEDLOOPBACK_ENABLEDssp_data_sizeSSP_DATA_BITS_4SSP_DATA_BITS_5SSP_DATA_BITS_6SSP_DATA_BITS_7SSP_DATA_BITS_8SSP_DATA_BITS_9SSP_DATA_BITS_10SSP_DATA_BITS_11SSP_DATA_BITS_12SSP_DATA_BITS_13SSP_DATA_BITS_14SSP_DATA_BITS_15SSP_DATA_BITS_16SSP_DATA_BITS_17SSP_DATA_BITS_18SSP_DATA_BITS_19SSP_DATA_BITS_20SSP_DATA_BITS_21SSP_DATA_BITS_22SSP_DATA_BITS_23SSP_DATA_BITS_24SSP_DATA_BITS_25SSP_DATA_BITS_26SSP_DATA_BITS_27SSP_DATA_BITS_28SSP_DATA_BITS_29SSP_DATA_BITS_30SSP_DATA_BITS_31SSP_DATA_BITS_32pl022_ssp_controllerpl022phybasevirtbasecur_transfercur_chiptx_endrx_endexp_fifo_leveldma_rx_channeldma_tx_channelsgt_rxsgt_txdummypagedma_runningcur_cscr0cr1n_bytesxfer_typedma_callbackload_ssp_default_configpl022_cleanuppl022_cs_controlpl022_dma_autoprobepl022_dma_probepl022_dma_removepl022_handle_errpl022_interrupt_handlerpl022_probepl022_removepl022_resumepl022_runtime_resumepl022_runtime_suspendpl022_setuppl022_suspendpl022_transfer_onepl022_unprepare_transfer_hardwarereadwritersgtabsetup_dma_scatterterminate_dmac@0 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