8( +hisilicon,hi3660-hikey960hisilicon,hi3660 + 7HiKey960psci arm,psci-0.2=smccpus+cpu-mapcluster0core0Dcore1Dcore2Dcore3Dcluster1core0Dcore1Dcore2Dcore3D cpu@0arm,cortex-a53HcpuTXpscif w P ncpu@1arm,cortex-a53HcpuTXpscif w P cpu@2arm,cortex-a53HcpuTXpscif w P cpu@3arm,cortex-a53HcpuTXpscif w P cpu@100arm,cortex-a73HcpuTXpscifw &cpu@101arm,cortex-a73HcpuTXpscifw cpu@102arm,cortex-a73HcpuTXpscifw cpu@103arm,cortex-a73HcpuTXpscifw  idle-statespscicpu-sleep-0arm,idle-state,< cluster-sleep-0arm,idle-state,@<  cpu-sleep-1arm,idle-state,&<cluster-sleep-1arm,idle-state , T< l2-cache0cache l2-cache1cacheopp_table0operating-points-v2Mopp00X@_ `mopp01X;_ 5mopp02XSҀ_ mopp03XeE@_B@mopp04Xm5_mopp_table1operating-points-v2Mopp10X5ү_ `mopp11XT@_ 5mopp12Xk@_ mopp13X}_B@mopp14XB_minterrupt-controller@e82b0000 arm,gic-400@T++ +@ +` ~  a53-pmuarm,cortex-a53-pmu0a73-pmuarm,cortex-a73-pmu0 timerarm,armv8-timer 0   soc simple-bus+crg_ctrl@fff35000 hisilicon,hi3660-crgctrlsysconTPcrg_rst_controllerhisilicon,hi3660-reset$pctrl@e8a09000hisilicon,hi3660-pctrlsysconT蠐 Rcrg_ctrl@fff34000 hisilicon,hi3660-pmuctrlsysconT@sctrl@fff0a000hisilicon,hi3660-sctrlsysconT>iomcu@ffd7e000hisilicon,hi3660-iomcusysconTresethisilicon,hi3660-resetmailbox@e896b000hisilicon,hi3660-mboxT薰stub_clock@e896b500hisilicon,hi3660-stub-clkT薵  timer@fff14000arm,sp804arm,primecellT@01   timer1timer2apb_pclki2c@ffd71000snps,designware-i2cT v+ " )default7AokayHLS-I2C0i2c@ffd72000snps,designware-i2cT  w+ " )default7Aokayrt1711h@4erichtek,rt1711hTNAokay )default7connectorusb-c-connectorHUSB-CNdualXdualcsinkr2~2Adports+port@1TendpointUport+endpoint@0Tadv7533@39Aokay adi,adv7533T9  ! "ports+port@0Tendpoint#{port@1Ti2c@fdf0c000snps,designware-i2cT Q+7 "$x)default7%& Adisabledi2c@fdf0b000snps,designware-i2cT :+6 "$`)default7'(AokayHLS-I2C1serial@fdf02000arm,pl011arm,primecellT  Jhuartclkapb_pclk)default7)* Adisabledserial@fdf00000arm,pl011arm,primecellT Krxtx++99uartclkapb_pclk)default7,- Adisabledserial@fdf03000arm,pl011arm,primecellT0 Lrxtx++:uartclkapb_pclk)default7./ Adisabledserial@ffd74000arm,pl011arm,primecellT@ ruartclkapb_pclk)default701Aokay HLS-UART0serial@fdf01000arm,pl011arm,primecellT Mrxtx++;;uartclkapb_pclk)default723Aokaybluetooth ti,wl1837-st 4*-serial@fdf05000arm,pl011arm,primecellTP Nrxtx++ <<uartclkapb_pclk)default756 Adisabledserial@fff32000arm,pl011arm,primecellT  O uartclkapb_pclk)default778Aokay HLS-UART1dma@fdf30000hisilicon,k3-dma-1.0T4?L Y >j uhi3660_dma+dma-controller@e804b000hisilicon,hisi-pcm-asp-dma-1.0T4?L   ~asp_dma_irqrtc@fff04000arm,pl031arm,primecellT@ . apb_pclkgpio@e8a0b000arm,pl061arm,primecellT蠰 T9~ apb_pclkLTP901[PMU0_SSI][PMU1_SSI][PMU2_SSI][PMU0_CLKOUT][JTAG_TCK][JTAG_TMS]gpio@e8a0c000arm,pl061arm,primecellT U9~  apb_pclkC[JTAG_TRST_N][JTAG_TDI][JTAG_TDO]NCNC[I2C3_SCL][I2C3_SDA]NC gpio@e8a0d000arm,pl061arm,primecellT V9~! apb_pclkGNCNCNCGPIO-JGPIO_020_HDMI_SELGPIO-LGPIO_022_UFSBUCK_INT_NGPIO-G"gpio@e8a0e000arm,pl061arm,primecellT W9~" apb_pclkJ[CSI0_MCLK][CSI1_MCLK]NC[I2C2_SCL][I2C2_SDA][I2C3_SCL][I2C3_SDA]NCgpio@e8a0f000arm,pl061arm,primecellT X9~# apb_pclkANCNCPWR_BTN_NGPIO_035_PMU2_ENGPIO_036_USB_HUB_RESETNCNCNC~gpio@e8a10000arm,pl061arm,primecellT Y9&~$ apb_pclkQGPIO-HGPIO_041_HDMI_PDTP904TP905NCNCGPIO_046_HUB_VDD33_ENGPIO_047_PMU1_EN!gpio@e8a11000arm,pl061arm,primecellT Z9.~% apb_pclkANCNCNCGPIO_051_WIFI_ENGPIO-I[SD_DAT1][SD_DAT2][UART1_RXD]gpio@e8a12000arm,pl061arm,primecellT  [96~& apb_pclky[UART1_TXD][UART0_CTS][UART0_RTS][UART0_RXD][UART0_TXD][SOC_BT_UART4_CTS_N][SOC_BT_UART4_RTS_N][SOC_BT_UART4_RXD]gpio@e8a13000arm,pl061arm,primecellT0 \9>~' apb_pclk?[SOC_BT_UART4_TXD]NC[PMU_HKADC_SSI]NCGPIO_068_SELNCNCNCgpio@e8a14000arm,pl061arm,primecellT@ ]9F~( apb_pclkNCNCNCGPIO-KNCNCNCNCgpio@e8a15000arm,pl061arm,primecellTP ^9N~) apb_pclkNCNCNCNCNCNCNCNCgpio@e8a16000arm,pl061arm,primecellT` _9V~* apb_pclk$NC[PCIE_PERST_N]NCNCNCNCNCNCDgpio@e8a17000arm,pl061arm,primecellTp ` 9^9e~+ apb_pclkNCNCNCNCgpio@e8a18000arm,pl061arm,primecellT血 a9f~, apb_pclkNCNCNCNCNCNCNCNCgpio@e8a19000arm,pl061arm,primecellT衐 b9n~- apb_pclkNCNCNCNCNCNCNCNCgpio@e8a1a000arm,pl061arm,primecellT衠 c9v~. apb_pclk'NCNCNCNCNCNCGPIO_126_BT_ENTP9024gpio@e8a1b000arm,pl061arm,primecellT衰 d~/ apb_pclkgpio@e8a1c000arm,pl061arm,primecellT e~0 apb_pclkgpio@ff3b4000arm,pl061arm,primecellT;@ f:~1 apb_pclkm[UFS_REF_CLK][UFS_RST_N][SPI1_SCLK][SPI1_DIN][SPI1_DOUT][SPI1_CS]GPIO_150_USER_LED1GPIO_151_USER_LED2Cgpio@ff3b5000arm,pl061arm,primecellT;P g:~2 apb_pclkNCNCNCNCgpio@e8a1f000arm,pl061arm,primecellT h;~3 apb_pclk@[SD_CLK][SD_CMD][SD_DATA0][SD_DATA1][SD_DATA2][SD_DATA3]gpio@e8a20000arm,pl061arm,primecellT i~<4 apb_pclk^[WL_SDIO_CLK][WL_SDIO_CMD][WL_SDIO_DATA0][WL_SDIO_DATA1][WL_SDIO_DATA2][WL_SDIO_DATA3]gpio@fff0b000arm,pl061arm,primecellT j=~> apb_pclkd[GPIO_176_PMU_PWR_HOLD]NA[SYSCLK_EN]GPIO_179_WL_WAKEUP_APGPIO_180_HDMI_INTNAGPIO-F[I2C0_SCL]Ogpio@fff0c000arm,pl061arm,primecellT k=~> apb_pclk^[I2C0_SDA][I2C1_SCL][I2C1_SDA][I2C1_SCL][I2C1_SDA]GPIO_189_USER_LED3GPIO_190_USER_LED4gpio@fff0d000arm,pl061arm,primecellT l= ~> apb_pclkt[PCM_DI][PCM_DO][PCM_CLK][PCM_FS][GPIO_196_I2S2_DI][GPIO_197_I2S2_DO][GPIO_198_I2S2_XCLK][GPIO_199_I2S2_XFS]gpio@fff0e000arm,pl061arm,primecellT m ==~> apb_pclkzNCNCGPIO_202_VBUS_TYPECGPIO_203_SD_DETGPIO_204_PMU12_IRQ_NGPIO_205_WIFI_ACTIVEGPIO_206_USBSW_SELGPIO_207_BT_ACTIVEEgpio@fff0f000arm,pl061arm,primecellT n=~> apb_pclkLGPIO-AGPIO-BGPIO-CGPIO-DGPIO-E[PCIE_CLKREQ_N][PCIE_WAKE_N][SPI0_CLK]gpio@fff10000arm,pl061arm,primecellT o=$~> apb_pclkB[SPI0_DIN][SPI0_DOUT][SPI0_CS]GPIO_219_CC_INTNCNC[PMU_INT]gpio@fff1d000arm,pl061arm,primecellT ~> apb_pclkspi@ffd68000arm,pl022arm,primecellTր+ t apb_pclk)default7?@ AokayHLS-SPI0spi@ff3b3000arm,pl022arm,primecellT;0+ 85 apb_pclk)default7AB CAokayHHS-SPI1pcie@f4000000hisilicon,kirin960-pcie@T? dbiapbphyconfig+Hpci~ ~msi(RSQP:pcie_phy_refpcie_auxpcie_apb_phypcie_apb_syspcie_aclk Dufs@ff3b0000#hisilicon,hi3660-ufsjedec,ufs-1.1 T;;  feref_clkphy_clk! "$ /rstdwmmc1@ff37f000hisilicon,hi3660-dw-mshcT7+ Kciubiu0 "$/reset;>WAokayis E)default 7FGHIJdwmmc2@ff3ff000hisilicon,hi3660-dw-mshcT?+ Lciubiu "$/resetWAokayi)default 7KLMNwlcore@2 ti,wl1837T Owatchdog@e8a06000arm,sp805arm,primecellT` ,  wdog_clkapb_pclkwatchdog@e8a07000arm,sp805arm,primecellTp -  wdog_clkapb_pclktsensor@fff30000hisilicon,hi3660-tsensorT Pthermal-zonescls0'5dK]Ptripstrip-point@0myOpassivetrip-point@1m$yOpassiveQcooling-mapsmap0Q0map1Q0 usb3_otg_bc@ff200000sysconsimple-mfdT usb-phyhisilicon,hi3660-usb-phyR$fSdwc3@ff100000 snps,dwc3TIrefbus_earlyI C@0"$$$$!S &usb3-phy0otg 8super-speedFutmiOp%hostport+endpoint@0TTendpoint@1TUetm@ecc40000"arm,coresight-etm4xarm,primecellT apb_pclkDout-portsportendpointV[etm@ecd40000"arm,coresight-etm4xarm,primecellT apb_pclkDout-portsportendpointW\etm@ece40000"arm,coresight-etm4xarm,primecellT apb_pclkDout-portsportendpointX]etm@ecf40000"arm,coresight-etm4xarm,primecellT apb_pclkDout-portsportendpointY^funnel@ec801000+arm,coresight-dynamic-funnelarm,primecellT apb_pclkout-portsportendpointZ_in-ports+port@0Tendpoint[Vport@1Tendpoint\Wport@2Tendpoint]Xport@3Tendpoint^Yetf@ec802000 arm,coresight-tmcarm,primecellT  apb_pclkin-portsportendpoint_Zout-portsportendpoint`metm@ed440000"arm,coresight-etm4xarm,primecellTD apb_pclkDout-portsportendpointafetm@ed540000"arm,coresight-etm4xarm,primecellTT apb_pclkDout-portsportendpointbgetm@ed640000"arm,coresight-etm4xarm,primecellTd apb_pclkDout-portsportendpointchetm@ed740000"arm,coresight-etm4xarm,primecellTt apb_pclkD out-portsportendpointdifunnel@ed001000+arm,coresight-dynamic-funnelarm,primecellT apb_pclkout-portsportendpointejin-ports+port@0Tendpointfaport@1Tendpointgbport@2Tendpointhcport@3Tendpointidetf@ed002000 arm,coresight-tmcarm,primecellT  apb_pclkin-portsportendpointjeout-portsportendpointknfunnelarm,coresight-static-funnel apb_pclkout-portsportendpointlpin-ports+port@0Tendpointm`port@1Tendpointnkfunnel@ec031000+arm,coresight-dynamic-funnelarm,primecellT apb_pclkout-portsportendpointoqin-ports+port@0Tendpointpletf@ec036000 arm,coresight-tmcarm,primecellT` apb_pclkin-portsportendpointqoout-portsportendpointrsreplicator arm,coresight-static-replicator apb_pclkin-portsportendpointsrout-ports+port@0Tendpointtvport@1Tendpointuwetr@ec033000 arm,coresight-tmcarm,primecellT0 apb_pclkin-portsportendpointvttpiu@ec032000!arm,coresight-tpiuarm,primecellT  apb_pclkin-portsportendpointwugpio-range>xpinmux@e896c000pinctrl-singleT_n  xxt9pmu_pmx_func  csi0_pwd_n_pmx_funcDcsi1_pwd_n_pmx_funcLisp0_pmx_funcXdhisp1_pmx_func\lppwr_key_pmx_func|i2c3_pmx_func,0%i2c4_pmx_funcpcie_perstn_pmx_func\usbhub5734_pmx_func uart0_pmx_func)uart1_pmx_func ,uart2_pmx_func .uart3_pmx_func 0uart4_pmx_func 2uart5_pmx_func 5uart6_pmx_func 7cam0_rst_pmx_funccam1_rst_pmx_func$pinmux@ff37e000pinctrl-singleT7n_ x;sd_pmx_func0 Fpinmux@ff3b6000pinctrl-singleT;`0_n x :ufs_pmx_funcspi3_pmx_func  Apinmux@ff3fd000pinctrl-singleT?_n x<sdio_pmx_func0 Kpinmux@fff11000pinctrl-singleT_n x*=i2s2_pmx_func DHLPslimbus_pmx_func,0i2c0_pmx_funci2c1_pmx_func i2c7_pmx_func$('pcie_pmx_funcspi2_pmx_func ?i2s0_pmx_func 48<@pinmux@e896c800pinconf-singleT_ pmu_cfg_func  ! i2c3_cfg_func8<!&csi0_pwd_n_cfg_funcP!csi1_pwd_n_cfg_funcX!isp0_cfg_funcdpt!isp1_cfg_funchx|!pwr_key_cfg_func!}uart1_cfg_func !-uart2_cfg_func !/uart5_cfg_func !6cam0_rst_cfg_func!uart0_cfg_func!*uart6_cfg_func !8uart3_cfg_func !1uart4_cfg_func !3cam1_rst_cfg_func0!pinmux@ff3b6800pinconf-singleT;h_ ufs_cfg_func!0spi3_cfg_func  ! Bpinmux@ff3fd800pinconf-singleT?_ sdio_clk_cfg_func!Lsdio_cfg_func( !Mpinmux@ff37e800pinconf-singleT7_ sd_clk_cfg_func!Gsd_cfg_func( !Hpinmux@fff11800pinconf-singleT_ i2c0_cfg_func !i2c1_cfg_func$(!i2c7_cfg_func,0!(slimbus_cfg_func48!i2s0_cfg_func @DHL!i2s2_cfg_func PTX\!pcie_cfg_func!spi2_cfg_func ! @usb_cfg_func!dpe@E8600000hisilicon,hi3660-dpeAokPT`Pl 8@?DBA>>Gaclk_dsspclk_dssclk_edc0clk_ldi0clk_ldi1clk_dss_axi_mmpclk_mmbuf?portendpointyziommu_infoLWdsi@E8601000hisilicon,hi3660-dsiAok T`P0FHEGNOTclk_txdphy0_refclk_txdphy1_refclk_txdphy0_cfgclk_txdphy1_cfgpclk_dsi0pclk_dsi1+ \"ports+port@0Tendpointzyport@1+Tendpoint@0T{#mali@E82C0000arm,malit6xxarm,mali-midgardeT,@$ ~JOBMMUGPU0uP  `" 5 PX B@aliases/soc/dwmmc1@ff37f000/soc/dwmmc2@ff3ff000/soc/serial@fdf02000/soc/serial@fdf00000/soc/serial@fdf03000/soc/serial@ffd74000/soc/serial@fdf01000/soc/serial@fdf05000/soc/serial@fff32000chosenserial6:115200n8memory@0HmemoryTreserved-memory+ramoops@32000000ramoopsT2linux,cmashared-dma-poolT  reboot-mode-syscon@32100000sysconsimple-mfdT2reboot-modesyscon-reboot-mode  wfU )wfU 9wfUkeys gpio-keys)default7|}power G $~ HGPIO Power Utleds gpio-ledsuser_led1 Hgreen:user1 $C `heartbeatuser_led2 Hgreen:user2 $C `noneuser_led3 Hgreen:user3 $ `mmc0user_led4 Hgreen:user4 $ v `nonewlan_active_led Hyellow:wlan $E `phy0tx offbt_active_ledHblue:bt $E `hci0-power offpmic@fff34000hisilicon,hi6421v530-pmicT@~regulatorsLDO3 VOUT3_1V85 w@ ! xLDO9 VOUT9_1V8_2V95  2Z JLDO11 VOUT11_1V8_2V95  2Z LDO15 VOUT15_3V0  -   xLDO16 VOUT16_2V95  - hIwlan-en-1-8vregulator-fixed wlan-en-regulator w@ w@  p &Nfirmwareopteelinaro,optee-tz=smchisi_hikey_usbhisilicon,gpio_hubv1 9E JE [!port+endpoint@0TTendpoint@1Thi3660_i2shisilicon,hi3660-i2s-1.0 T)default7rxtxsoundsimple-audio-card nhikey-hdmi i2s  simple-audio-card,cpu simple-audio-card,codec  compatibleinterrupt-parent#address-cells#size-cellsmodelmethodcpudevice_typeregenable-methodnext-level-cachecpu-idle-statescapacity-dmips-mhzclocksoperating-points-v2#cooling-cellsdynamic-power-coefficientphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-ns#interrupt-cellsinterrupt-controllerinterruptsinterrupt-affinityranges#clock-cells#reset-cellshisi,rst-syscon#mbox-cellsmboxesclock-namesclock-frequencyresetspinctrl-namespinctrl-0statuslabeldata-rolepower-roletry-power-rolesource-pdossink-pdosop-sink-microwattremote-endpointv1p2-supplyvdd-supplypd-gpiosel-gpioadi,dsi-lanesadi,disable-timing-generator#sound-dai-cellsdma-namesdmasenable-gpiosmax-speed#dma-cellsdma-channelsdma-requestsdma-channel-maskdma-no-ccidma-typeinterrupt-namesgpio-controller#gpio-cellsgpio-rangesgpio-line-namesnum-cscs-gpiosreg-namesbus-rangenum-lanesinterrupt-map-maskinterrupt-mapreset-gpiosfreq-table-hzreset-nameshisilicon,peripheral-sysconcard-detect-delaybus-widthcap-sd-highspeedsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104disable-wpcd-gpiosvmmc-supplyvqmmc-supplynon-removablebroken-cdcap-power-off-card#thermal-sensor-cellspolling-delaypolling-delay-passivesustainable-powerthermal-sensorstemperaturehysteresistripcontributioncooling-device#phy-cellshisilicon,pericrg-sysconhisilicon,pctrl-sysconhisilicon,eye-diagram-paramassigned-clocksassigned-clock-ratesphysphy-namesdr_modemaximum-speedphy_typesnps,dis-del-phy-power-chg-quirksnps,lfps_filter_quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirksnps,tx_de_emphasis_quirksnps,tx_de_emphasissnps,dis_enblslpm_quirksnps,gctl-reset-quirkusb-role-switchrole-switch-default-mode#pinctrl-single,gpio-range-cells#pinctrl-cells#gpio-range-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,gpio-rangepinctrl-single,pinspinctrl-single,bias-pulldownpinctrl-single,bias-pulluppinctrl-single,drive-strengthdma-coherentstart-addrsizemux-gpiogpu_outstandingoperating-pointsmshc1mshc2serial0serial1serial2serial3serial4serial5serial6stdout-pathrecord-sizeconsole-sizeftrace-sizereusablelinux,cma-defaultoffsetmode-normalmode-bootloadermode-recoverywakeup-sourcelinux,codelinux,default-triggerpanic-indicatordefault-stateregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-boot-onregulator-always-onstartup-delay-usenable-active-hightypec-vbus-gpiosotg-switch-gpioshub-vdd33-en-gpiossimple-audio-card,namesimple-audio-card,formatsimple-audio-card,bitclock-mastersimple-audio-card,frame-mastersound-dai