Searched defs:Asr (Results 1 – 4 of 4) sorted by relevance
| /art/compiler/optimizing/ |
| D | code_generator_vector_arm64_sve.cc | 810 __ Asr(dst.VnB(), p_reg, lhs.VnB(), value); in VisitVecShr() local
814 __ Asr(dst.VnH(), p_reg, lhs.VnH(), value); in VisitVecShr() local
817 __ Asr(dst.VnS(), p_reg, lhs.VnS(), value); in VisitVecShr() local
820 __ Asr(dst.VnD(), p_reg, lhs.VnD(), value); in VisitVecShr() local
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| D | code_generator_arm_vixl.cc | 4179 __ Asr(HighRegisterFrom(out), LowRegisterFrom(out), 31); in VisitTypeConversion() local
4518 __ Asr(out, in, ctz_imm); in DivRemByPowerOfTwo() local
4569 __ Asr(out, dividend, 31); in DivRemByPowerOfTwo() local
4654 __ Asr(temp1, temp1, shift); in GenerateDivRemWithAnyConstant() local
5205 __ Asr(mask, in_reg, 31); in VisitAbs() local
5219 __ Asr(mask, in_reg_hi, 31); in VisitAbs() local
5483 __ Asr(out_reg, first_reg, out_reg); in HandleShift() local
5495 __ Asr(out_reg, first_reg, shift_value); in HandleShift() local
5551 __ Asr(o_h, high, o_h); in HandleShift() local
5580 __ Asr(o_l, high, shift_value - 32); in HandleShift() local
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| D | code_generator_arm64.cc | 2465 __ Asr(dst, lhs, shift_value); in HandleShift() local
2475 __ Asr(dst, lhs, rhs_reg); in HandleShift() local
3396 __ Asr(out, final_dividend, ctz_imm); in FOR_EACH_CONDITION_INSTRUCTION() local
3538 __ Asr(temp, temp, shift); in GenerateInt64DivRemWithAnyConstant() local
3602 __ Asr(temp.X(), temp.X(), 32 + shift); in GenerateInt32DivRemWithAnyConstant() local
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| D | intrinsics_arm_vixl.cc | 749 __ Asr(temp3, temp3, 7u); // uncompressed ? 0xffff0000u : 0xff0000u. in GenerateStringCompareToLoop() local
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