| /art/runtime/interpreter/ |
| D | safe_math_test.cc | 96 TEST(SafeMath, Mul) { in TEST() argument
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| /art/compiler/utils/arm/ |
| D | assembler_arm_vixl.h | 144 void Mul(vixl32::Register rd, vixl32::Register rn, vixl32::Register rm) { in Mul() function
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| /art/test/660-clinit/src/ |
| D | Main.java | 222 class Mul { class
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| /art/compiler/optimizing/ |
| D | code_generator_vector_arm64_sve.cc | 553 __ Mul(dst.VnB(), p_reg, lhs.VnB(), rhs.VnB()); in VisitVecMul() local
557 __ Mul(dst.VnH(), p_reg, lhs.VnH(), rhs.VnH()); in VisitVecMul() local
560 __ Mul(dst.VnS(), p_reg, lhs.VnS(), rhs.VnS()); in VisitVecMul() local
563 __ Mul(dst.VnD(), p_reg, lhs.VnD(), rhs.VnD()); in VisitVecMul() local
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| D | code_generator_vector_arm64_neon.cc | 635 __ Mul(dst.V16B(), lhs.V16B(), rhs.V16B()); in VisitVecMul() local
640 __ Mul(dst.V8H(), lhs.V8H(), rhs.V8H()); in VisitVecMul() local
644 __ Mul(dst.V4S(), lhs.V4S(), rhs.V4S()); in VisitVecMul() local
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| D | code_generator_arm_vixl.cc | 4434 __ Mul(OutputRegister(mul), InputRegisterAt(mul, 0), InputRegisterAt(mul, 1)); in VisitMul() local
4460 __ Mul(temp, in1_lo, in2_hi); in VisitMul() local
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| D | code_generator_arm64.cc | 5923 __ Mul(OutputRegister(mul), InputRegisterAt(mul, 0), InputRegisterAt(mul, 1)); in VisitMul() local
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| D | code_generator_riscv64.cc | 4674 __ Mul(locations->Out().AsRegister<XRegister>(), in VisitMul() local
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| /art/compiler/utils/riscv64/ |
| D | assembler_riscv64_test.cc | 2741 TEST_F(AssemblerRISCV64Test, Mul) { in TEST_F() argument
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| D | assembler_riscv64.cc | 648 void Riscv64Assembler::Mul(XRegister rd, XRegister rs1, XRegister rs2) { in Mul() function in art::riscv64::Riscv64Assembler
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