| /art/compiler/utils/arm64/ |
| D | assembler_arm64.cc | 167 ___ Neg(reg, Operand(reg)); in PoisonHeapReference() local
173 ___ Neg(reg, Operand(reg)); in UnpoisonHeapReference() local
|
| /art/compiler/optimizing/ |
| D | code_generator_vector_arm64_sve.cc | 311 __ Neg(dst.VnB(), p_reg, src.VnB()); in VisitVecNeg() local
315 __ Neg(dst.VnH(), p_reg, src.VnH()); in VisitVecNeg() local
318 __ Neg(dst.VnS(), p_reg, src.VnS()); in VisitVecNeg() local
321 __ Neg(dst.VnD(), p_reg, src.VnD()); in VisitVecNeg() local
|
| D | code_generator_vector_arm64_neon.cc | 315 __ Neg(dst.V16B(), src.V16B()); in VisitVecNeg() local
320 __ Neg(dst.V8H(), src.V8H()); in VisitVecNeg() local
324 __ Neg(dst.V4S(), src.V4S()); in VisitVecNeg() local
328 __ Neg(dst.V2D(), src.V2D()); in VisitVecNeg() local
|
| D | code_generator_riscv64.cc | 1491 __ Neg(out, out); in DivRemByPowerOfTwo() local
1669 __ Neg(rd, rd); // 0 -> 0, 1 -> -1 in GenerateIntLongCondition() local
1860 __ Neg(rd, rd); // 0 -> 0, 1 -> -1 in GenerateFpCondition() local
4721 __ Neg(locations->Out().AsRegister<XRegister>(), locations->InAt(0).AsRegister<XRegister>()); in VisitNeg() local
5161 __ Neg(tmp, tmp); in VisitSelect() local
5374 __ Neg(tmp, tmp); // 0 for NaN, -1 otherwise. in VisitTypeConversion() local
|
| D | code_generator_arm64.cc | 2589 __ Neg(out, right_operand); in VisitDataProcWithShifterOp() local
3398 __ Neg(out, Operand(final_dividend, ASR, ctz_imm)); in FOR_EACH_CONDITION_INSTRUCTION() local
5961 __ Neg(OutputRegister(neg), InputOperandAt(neg, 0)); in VisitNeg() local
|
| D | intrinsics_riscv64.cc | 557 __ Neg(tmp, rs1); in VisitLongLowestOneBit() local
|
| D | intrinsics_arm64.cc | 475 __ Neg(temp, src); in GenLowestOneBit() local
|
| /art/compiler/utils/riscv64/ |
| D | assembler_riscv64_test.cc | 8148 TEST_F(AssemblerRISCV64Test, Neg) { in TEST_F() argument
|
| D | assembler_riscv64.cc | 6123 void Riscv64Assembler::Neg(XRegister rd, XRegister rs) { Sub(rd, Zero, rs); } in Neg() function in art::riscv64::Riscv64Assembler
|