1 { 2 "License": [ 3 "Copyright (C) 2023 The Android Open Source Project", 4 "", 5 "Licensed under the Apache License, Version 2.0 (the “License”);", 6 "you may not use this file except in compliance with the License.", 7 "You may obtain a copy of the License at", 8 "", 9 " http://www.apache.org/licenses/LICENSE-2.0", 10 "", 11 "Unless required by applicable law or agreed to in writing, software", 12 "distributed under the License is distributed on an “AS IS” BASIS,", 13 "WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.", 14 "See the License for the specific language governing permissions and", 15 "limitations under the License." 16 ], 17 "arch": "common_x86", 18 "insns": [ 19 { 20 "encodings": { 21 "Adcb": { "opcodes": [ "80", "2" ] }, 22 "Rclb": { "opcodes": [ "C0", "2" ] }, 23 "Rcrb": { "opcodes": [ "C0", "3" ] }, 24 "Sbbb": { "opcodes": [ "80", "3" ] } 25 }, 26 "args": [ 27 { "class": "GeneralReg8/Mem8", "usage": "use_def" }, 28 { "class": "Imm8" }, 29 { "class": "FLAGS", "usage": "use_def" } 30 ] 31 }, 32 { 33 "encodings": { 34 "Adcb": { "opcodes": [ "12" ] }, 35 "Sbbb": { "opcodes": [ "1A" ] } 36 }, 37 "args": [ 38 { "class": "GeneralReg8", "usage": "use_def" }, 39 { "class": "Mem8", "usage": "use" }, 40 { "class": "FLAGS", "usage": "use_def" } 41 ] 42 }, 43 { 44 "encodings": { 45 "Adcb": { "opcodes": [ "10" ], "reg_to_rm": true }, 46 "Sbbb": { "opcodes": [ "18" ], "reg_to_rm": true } 47 }, 48 "args": [ 49 { "class": "GeneralReg8/Mem8", "usage": "use_def" }, 50 { "class": "GeneralReg8", "usage": "use" }, 51 { "class": "FLAGS", "usage": "use_def" } 52 ] 53 }, 54 { 55 "encodings": { 56 "AdcbAccumulator": { "opcodes": [ "14" ] }, 57 "SbbbAccumulator": { "opcodes": [ "1C" ] } 58 }, 59 "args": [ 60 { "class": "AL", "usage": "use_def" }, 61 { "class": "Imm8" }, 62 { "class": "FLAGS", "usage": "use_def" } 63 ] 64 }, 65 { 66 "encodings": { 67 "Adcl": { "opcodes": [ "13" ] }, 68 "Sbbl": { "opcodes": [ "1B" ] } 69 }, 70 "args": [ 71 { "class": "GeneralReg32", "usage": "use_def" }, 72 { "class": "Mem32", "usage": "use" }, 73 { "class": "FLAGS", "usage": "use_def" } 74 ] 75 }, 76 { 77 "encodings": { 78 "Adcl": { "opcodes": [ "81", "2" ] }, 79 "Sbbl": { "opcodes": [ "81", "3" ] } 80 }, 81 "args": [ 82 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 83 { "class": "Imm32" }, 84 { "class": "FLAGS", "usage": "use_def" } 85 ] 86 }, 87 { 88 "encodings": { 89 "Adcl": { "opcodes": [ "11" ], "reg_to_rm": true }, 90 "Sbbl": { "opcodes": [ "19" ], "reg_to_rm": true } 91 }, 92 "args": [ 93 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 94 { "class": "GeneralReg32", "usage": "use" }, 95 { "class": "FLAGS", "usage": "use_def" } 96 ] 97 }, 98 { 99 "encodings": { 100 "AdclAccumulator": { "opcodes": [ "15" ] }, 101 "SbblAccumulator": { "opcodes": [ "1D" ] } 102 }, 103 "args": [ 104 { "class": "EAX", "usage": "use_def" }, 105 { "class": "Imm32" }, 106 { "class": "FLAGS", "usage": "use_def" } 107 ] 108 }, 109 { 110 "encodings": { 111 "AdclImm8": { "opcodes": [ "83", "2" ] }, 112 "Rcll": { "opcodes": [ "C1", "2" ] }, 113 "Rcrl": { "opcodes": [ "C1", "3" ] }, 114 "SbblImm8": { "opcodes": [ "83", "3" ] } 115 }, 116 "args": [ 117 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 118 { "class": "Imm8" }, 119 { "class": "FLAGS", "usage": "use_def" } 120 ] 121 }, 122 { 123 "encodings": { 124 "Adcw": { "opcodes": [ "66", "13" ] }, 125 "Sbbw": { "opcodes": [ "66", "1B" ] } 126 }, 127 "args": [ 128 { "class": "GeneralReg16", "usage": "use_def" }, 129 { "class": "Mem16", "usage": "use" }, 130 { "class": "FLAGS", "usage": "use_def" } 131 ] 132 }, 133 { 134 "encodings": { 135 "Adcw": { "opcodes": [ "66", "81", "2" ] }, 136 "Sbbw": { "opcodes": [ "66", "81", "3" ] } 137 }, 138 "args": [ 139 { "class": "GeneralReg16/Mem16", "usage": "use_def" }, 140 { "class": "Imm16" }, 141 { "class": "FLAGS", "usage": "use_def" } 142 ] 143 }, 144 { 145 "encodings": { 146 "Adcw": { "opcodes": [ "66", "11" ], "reg_to_rm": true }, 147 "Sbbw": { "opcodes": [ "66", "19" ], "reg_to_rm": true } 148 }, 149 "args": [ 150 { "class": "GeneralReg16/Mem16", "usage": "use_def" }, 151 { "class": "GeneralReg16", "usage": "use" }, 152 { "class": "FLAGS", "usage": "use_def" } 153 ] 154 }, 155 { 156 "encodings": { 157 "AdcwAccumulator": { "opcodes": [ "66", "15" ] }, 158 "SbbwAccumulator": { "opcodes": [ "66", "1D" ] } 159 }, 160 "args": [ 161 { "class": "AX", "usage": "use_def" }, 162 { "class": "Imm16" }, 163 { "class": "FLAGS", "usage": "use_def" } 164 ] 165 }, 166 { 167 "encodings": { 168 "AdcwImm8": { "opcodes": [ "66", "83", "2" ] }, 169 "Rclw": { "opcodes": [ "66", "C1", "2" ] }, 170 "Rcrw": { "opcodes": [ "66", "C1", "3" ] }, 171 "SbbwImm8": { "opcodes": [ "66", "83", "3" ] } 172 }, 173 "args": [ 174 { "class": "GeneralReg16/Mem16", "usage": "use_def" }, 175 { "class": "Imm8" }, 176 { "class": "FLAGS", "usage": "use_def" } 177 ] 178 }, 179 { 180 "encodings": { 181 "Addb": { "opcodes": [ "80", "0" ] }, 182 "Andb": { "opcodes": [ "80", "4" ] }, 183 "Orb": { "opcodes": [ "80", "1" ] }, 184 "Rolb": { "opcodes": [ "C0", "0" ] }, 185 "Rorb": { "opcodes": [ "C0", "1" ] }, 186 "Sarb": { "opcodes": [ "C0", "7" ] }, 187 "Shlb": { "opcodes": [ "C0", "4" ] }, 188 "Shrb": { "opcodes": [ "C0", "5" ] }, 189 "Subb": { "opcodes": [ "80", "5" ] }, 190 "Xorb": { "opcodes": [ "80", "6" ] } 191 }, 192 "args": [ 193 { "class": "GeneralReg8/Mem8", "usage": "use_def" }, 194 { "class": "Imm8" }, 195 { "class": "FLAGS", "usage": "def" } 196 ] 197 }, 198 { 199 "encodings": { 200 "Addb": { "opcodes": [ "02" ] }, 201 "Andb": { "opcodes": [ "22" ] }, 202 "Orb": { "opcodes": [ "0A" ] }, 203 "Subb": { "opcodes": [ "2A" ] }, 204 "Xorb": { "opcodes": [ "32" ] } 205 }, 206 "args": [ 207 { "class": "GeneralReg8", "usage": "use_def" }, 208 { "class": "Mem8", "usage": "use" }, 209 { "class": "FLAGS", "usage": "def" } 210 ] 211 }, 212 { 213 "encodings": { 214 "Addb": { "opcodes": [ "00" ], "reg_to_rm": true }, 215 "Andb": { "opcodes": [ "20" ], "reg_to_rm": true }, 216 "Orb": { "opcodes": [ "08" ], "reg_to_rm": true }, 217 "Subb": { "opcodes": [ "28" ], "reg_to_rm": true }, 218 "Xorb": { "opcodes": [ "30" ], "reg_to_rm": true } 219 }, 220 "args": [ 221 { "class": "GeneralReg8/Mem8", "usage": "use_def" }, 222 { "class": "GeneralReg8", "usage": "use" }, 223 { "class": "FLAGS", "usage": "def" } 224 ] 225 }, 226 { 227 "encodings": { 228 "AddbAccumulator": { "opcodes": [ "04" ] }, 229 "AndbAccumulator": { "opcodes": [ "24" ] }, 230 "OrbAccumulator": { "opcodes": [ "0C" ] }, 231 "SubbAccumulator": { "opcodes": [ "2C" ] }, 232 "XorbAccumulator": { "opcodes": [ "34" ] } 233 }, 234 "args": [ 235 { "class": "AL", "usage": "use_def" }, 236 { "class": "Imm8" }, 237 { "class": "FLAGS", "usage": "def" } 238 ] 239 }, 240 { 241 "encodings": { 242 "Addl": { "opcodes": [ "01" ], "reg_to_rm": true }, 243 "Andl": { "opcodes": [ "21" ], "reg_to_rm": true }, 244 "Btcl": { "opcodes": [ "0F", "BB" ], "reg_to_rm": true }, 245 "Btrl": { "opcodes": [ "0F", "B3" ], "reg_to_rm": true }, 246 "Btsl": { "opcodes": [ "0F", "AB" ], "reg_to_rm": true }, 247 "Orl": { "opcodes": [ "09" ], "reg_to_rm": true }, 248 "Subl": { "opcodes": [ "29" ], "reg_to_rm": true }, 249 "Xorl": { "opcodes": [ "31" ], "reg_to_rm": true } 250 }, 251 "args": [ 252 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 253 { "class": "GeneralReg32", "usage": "use" }, 254 { "class": "FLAGS", "usage": "def" } 255 ] 256 }, 257 { 258 "encodings": { 259 "Addl": { "opcodes": [ "03" ] }, 260 "Andl": { "opcodes": [ "23" ] }, 261 "Orl": { "opcodes": [ "0B" ] }, 262 "Subl": { "opcodes": [ "2B" ] }, 263 "Xorl": { "opcodes": [ "33" ] } 264 }, 265 "args": [ 266 { "class": "GeneralReg32", "usage": "use_def" }, 267 { "class": "Mem32", "usage": "use" }, 268 { "class": "FLAGS", "usage": "def" } 269 ] 270 }, 271 { 272 "encodings": { 273 "Addl": { "opcodes": [ "81", "0" ] }, 274 "Andl": { "opcodes": [ "81", "4" ] }, 275 "Orl": { "opcodes": [ "81", "1" ] }, 276 "Subl": { "opcodes": [ "81", "5" ] }, 277 "Xorl": { "opcodes": [ "81", "6" ] } 278 }, 279 "args": [ 280 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 281 { "class": "Imm32" }, 282 { "class": "FLAGS", "usage": "def" } 283 ] 284 }, 285 { 286 "encodings": { 287 "AddlAccumulator": { "opcodes": [ "05" ] }, 288 "AndlAccumulator": { "opcodes": [ "25" ] }, 289 "OrlAccumulator": { "opcodes": [ "0D" ] }, 290 "SublAccumulator": { "opcodes": [ "2D" ] }, 291 "XorlAccumulator": { "opcodes": [ "35" ] } 292 }, 293 "args": [ 294 { "class": "EAX", "usage": "use_def" }, 295 { "class": "Imm32" }, 296 { "class": "FLAGS", "usage": "def" } 297 ] 298 }, 299 { 300 "encodings": { 301 "AddlImm8": { "opcodes": [ "83", "0" ] }, 302 "AndlImm8": { "opcodes": [ "83", "4" ] }, 303 "Btcl": { "opcodes": [ "0F", "BA", "7" ] }, 304 "Btl": { "opcodes": [ "0F", "BA", "4" ] }, 305 "Btrl": { "opcodes": [ "0F", "BA", "6" ] }, 306 "Btsl": { "opcodes": [ "0F", "BA", "5" ] }, 307 "OrlImm8": { "opcodes": [ "83", "1" ] }, 308 "Roll": { "opcodes": [ "C1", "0" ] }, 309 "Rorl": { "opcodes": [ "C1", "1" ] }, 310 "Sarl": { "opcodes": [ "C1", "7" ] }, 311 "Shll": { "opcodes": [ "C1", "4" ] }, 312 "Shrl": { "opcodes": [ "C1", "5" ] }, 313 "SublImm8": { "opcodes": [ "83", "5" ] }, 314 "XorlImm8": { "opcodes": [ "83", "6" ] } 315 }, 316 "args": [ 317 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 318 { "class": "Imm8" }, 319 { "class": "FLAGS", "usage": "def" } 320 ] 321 }, 322 { 323 "encodings": { 324 "Addpd": { "opcodes": [ "66", "0F", "58" ] }, 325 "Addps": { "opcodes": [ "0F", "58" ] }, 326 "Andpd": { "opcodes": [ "66", "0F", "54" ] }, 327 "Andps": { "opcodes": [ "0F", "54" ] }, 328 "Cmpeqpd": { "opcodes": [ "66", "0F", "C2", "00" ] }, 329 "Cmpeqps": { "opcodes": [ "0F", "C2", "00" ] }, 330 "Cmplepd": { "opcodes": [ "66", "0F", "C2", "02" ] }, 331 "Cmpleps": { "opcodes": [ "0F", "C2", "02" ] }, 332 "Cmpltpd": { "opcodes": [ "66", "0F", "C2", "01" ] }, 333 "Cmpltps": { "opcodes": [ "0F", "C2", "01" ] }, 334 "Cmpneqpd": { "opcodes": [ "66", "0F", "C2", "04" ] }, 335 "Cmpneqps": { "opcodes": [ "0F", "C2", "04" ] }, 336 "Cmpnlepd": { "opcodes": [ "66", "0F", "C2", "06" ] }, 337 "Cmpnleps": { "opcodes": [ "0F", "C2", "06" ] }, 338 "Cmpnltpd": { "opcodes": [ "66", "0F", "C2", "05" ] }, 339 "Cmpnltps": { "opcodes": [ "0F", "C2", "05" ] }, 340 "Cmpordpd": { "opcodes": [ "66", "0F", "C2", "07" ] }, 341 "Cmpordps": { "opcodes": [ "0F", "C2", "07" ] }, 342 "Cmpunordpd": { "opcodes": [ "66", "0F", "C2", "03" ] }, 343 "Cmpunordps": { "opcodes": [ "0F", "C2", "03" ] }, 344 "Divpd": { "opcodes": [ "66", "0F", "5E" ] }, 345 "Divps": { "opcodes": [ "0F", "5E" ] }, 346 "Haddpd": { "feature": "SSE3", "opcodes": [ "66", "0F", "7C" ] }, 347 "Haddps": { "feature": "SSE3", "opcodes": [ "F2", "0F", "7C" ] }, 348 "Maxpd": { "opcodes": [ "66", "0F", "5F" ] }, 349 "Maxps": { "opcodes": [ "0F", "5F" ] }, 350 "Minpd": { "opcodes": [ "66", "0F", "5D" ] }, 351 "Minps": { "opcodes": [ "0F", "5D" ] }, 352 "Mulpd": { "opcodes": [ "66", "0F", "59" ] }, 353 "Mulps": { "opcodes": [ "0F", "59" ] }, 354 "Orpd": { "opcodes": [ "66", "0F", "56" ] }, 355 "Orps": { "opcodes": [ "0F", "56" ] }, 356 "Packssdw": { "opcodes": [ "66", "0F", "6B" ] }, 357 "Packsswb": { "opcodes": [ "66", "0F", "63" ] }, 358 "Packusdw": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "2B" ] }, 359 "Packuswb": { "opcodes": [ "66", "0F", "67" ] }, 360 "Paddb": { "opcodes": [ "66", "0F", "FC" ] }, 361 "Paddd": { "opcodes": [ "66", "0F", "FE" ] }, 362 "Paddq": { "opcodes": [ "66", "0F", "D4" ] }, 363 "Paddsb": { "opcodes": [ "66", "0F", "EC" ] }, 364 "Paddsw": { "opcodes": [ "66", "0F", "ED" ] }, 365 "Paddusb": { "opcodes": [ "66", "0F", "DC" ] }, 366 "Paddusw": { "opcodes": [ "66", "0F", "DD" ] }, 367 "Paddw": { "opcodes": [ "66", "0F", "FD" ] }, 368 "Pand": { "opcodes": [ "66", "0F", "DB" ] }, 369 "Pandn": { "opcodes": [ "66", "0F", "DF" ] }, 370 "Pavgb": { "opcodes": [ "66", "0F", "E0" ] }, 371 "Pavgw": { "opcodes": [ "66", "0F", "E3" ] }, 372 "Pcmpeqb": { "opcodes": [ "66", "0F", "74" ] }, 373 "Pcmpeqd": { "opcodes": [ "66", "0F", "76" ] }, 374 "Pcmpeqq": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "29" ] }, 375 "Pcmpeqw": { "opcodes": [ "66", "0F", "75" ] }, 376 "Pcmpgtb": { "opcodes": [ "66", "0F", "64" ] }, 377 "Pcmpgtd": { "opcodes": [ "66", "0F", "66" ] }, 378 "Pcmpgtq": { "feature": "SSE4_2", "opcodes": [ "66", "0F", "38", "37" ] }, 379 "Pcmpgtw": { "opcodes": [ "66", "0F", "65" ] }, 380 "Phaddd": { "feature": "SSSE3", "opcodes": [ "66", "0F", "38", "02" ] }, 381 "Phaddw": { "feature": "SSSE3", "opcodes": [ "66", "0F", "38", "01" ] }, 382 "Pmaxsb": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "3C" ] }, 383 "Pmaxsd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "3D" ] }, 384 "Pmaxsw": { "opcodes": [ "66", "0F", "EE" ] }, 385 "Pmaxub": { "opcodes": [ "66", "0F", "DE" ] }, 386 "Pmaxud": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "3F" ] }, 387 "Pmaxuw": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "3E" ] }, 388 "Pminsb": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "38" ] }, 389 "Pminsd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "39" ] }, 390 "Pminsw": { "opcodes": [ "66", "0F", "EA" ] }, 391 "Pminub": { "opcodes": [ "66", "0F", "DA" ] }, 392 "Pminud": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "3B" ] }, 393 "Pminuw": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "3A" ] }, 394 "Pmulhrsw": { "feature": "SSSE3", "opcodes": [ "66", "0F", "38", "0B" ] }, 395 "Pmulhw": { "opcodes": [ "66", "0F", "E5" ] }, 396 "Pmulld": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "40" ] }, 397 "Pmullw": { "opcodes": [ "66", "0F", "D5" ] }, 398 "Pmuludq": { "opcodes": [ "66", "0F", "F4" ] }, 399 "Por": { "opcodes": [ "66", "0F", "EB" ] }, 400 "Psadbw": { "opcodes": [ "66", "0F", "F6" ] }, 401 "Pshufb": { "feature": "SSSE3", "opcodes": [ "66", "0F", "38", "00" ] }, 402 "Pslld": { "opcodes": [ "66", "0F", "F2" ] }, 403 "Psllq": { "opcodes": [ "66", "0F", "F3" ] }, 404 "Psllw": { "opcodes": [ "66", "0F", "F1" ] }, 405 "Psrad": { "opcodes": [ "66", "0F", "E2" ] }, 406 "Psraw": { "opcodes": [ "66", "0F", "E1" ] }, 407 "Psrld": { "opcodes": [ "66", "0F", "D2" ] }, 408 "Psrlq": { "opcodes": [ "66", "0F", "D3" ] }, 409 "Psrlw": { "opcodes": [ "66", "0F", "D1" ] }, 410 "Psubb": { "opcodes": [ "66", "0F", "F8" ] }, 411 "Psubd": { "opcodes": [ "66", "0F", "FA" ] }, 412 "Psubq": { "opcodes": [ "66", "0F", "FB" ] }, 413 "Psubsb": { "opcodes": [ "66", "0F", "E8" ] }, 414 "Psubsw": { "opcodes": [ "66", "0F", "E9" ] }, 415 "Psubusb": { "opcodes": [ "66", "0F", "D8" ] }, 416 "Psubusw": { "opcodes": [ "66", "0F", "D9" ] }, 417 "Psubw": { "opcodes": [ "66", "0F", "F9" ] }, 418 "Punpckhbw": { "opcodes": [ "66", "0F", "68" ] }, 419 "Punpckhdq": { "opcodes": [ "66", "0F", "6A" ] }, 420 "Punpckhqdq": { "opcodes": [ "66", "0F", "6D" ] }, 421 "Punpckhwd": { "opcodes": [ "66", "0F", "69" ] }, 422 "Punpcklbw": { "opcodes": [ "66", "0F", "60" ] }, 423 "Punpckldq": { "opcodes": [ "66", "0F", "62" ] }, 424 "Punpcklqdq": { "opcodes": [ "66", "0F", "6C" ] }, 425 "Punpcklwd": { "opcodes": [ "66", "0F", "61" ] }, 426 "Pxor": { "opcodes": [ "66", "0F", "EF" ] }, 427 "Rsqrtps": { "opcodes": [ "0F", "52" ] }, 428 "Subpd": { "opcodes": [ "66", "0F", "5C" ] }, 429 "Subps": { "opcodes": [ "0F", "5C" ] }, 430 "Vrsqrtps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "52" ] }, 431 "Xorpd": { "opcodes": [ "66", "0F", "57" ] }, 432 "Xorps": { "opcodes": [ "0F", "57" ] } 433 }, 434 "args": [ 435 { "class": "VecReg128", "usage": "use_def" }, 436 { "class": "VecReg128/VecMem128", "usage": "use" } 437 ] 438 }, 439 { 440 "encodings": { 441 "Addsd": { "opcodes": [ "F2", "0F", "58" ] }, 442 "Cmpeqsd": { "opcodes": [ "F2", "0F", "C2", "00" ] }, 443 "Cmplesd": { "opcodes": [ "F2", "0F", "C2", "02" ] }, 444 "Cmpltsd": { "opcodes": [ "F2", "0F", "C2", "01" ] }, 445 "Cmpneqsd": { "opcodes": [ "F2", "0F", "C2", "04" ] }, 446 "Cmpnlesd": { "opcodes": [ "F2", "0F", "C2", "06" ] }, 447 "Cmpnltsd": { "opcodes": [ "F2", "0F", "C2", "05" ] }, 448 "Cmpordsd": { "opcodes": [ "F2", "0F", "C2", "07" ] }, 449 "Cmpunordsd": { "opcodes": [ "F2", "0F", "C2", "03" ] }, 450 "Divsd": { "opcodes": [ "F2", "0F", "5E" ] }, 451 "Mulsd": { "opcodes": [ "F2", "0F", "59" ] }, 452 "Subsd": { "opcodes": [ "F2", "0F", "5C" ] } 453 }, 454 "args": [ 455 { "class": "FpReg64", "usage": "use_def" }, 456 { "class": "FpReg64/VecMem64", "usage": "use" } 457 ] 458 }, 459 { 460 "encodings": { 461 "Addss": { "opcodes": [ "F3", "0F", "58" ] }, 462 "Cmpeqss": { "opcodes": [ "F3", "0F", "C2", "00" ] }, 463 "Cmpless": { "opcodes": [ "F3", "0F", "C2", "02" ] }, 464 "Cmpltss": { "opcodes": [ "F3", "0F", "C2", "01" ] }, 465 "Cmpneqss": { "opcodes": [ "F3", "0F", "C2", "04" ] }, 466 "Cmpnless": { "opcodes": [ "F3", "0F", "C2", "06" ] }, 467 "Cmpnltss": { "opcodes": [ "F3", "0F", "C2", "05" ] }, 468 "Cmpordss": { "opcodes": [ "F3", "0F", "C2", "07" ] }, 469 "Cmpunordss": { "opcodes": [ "F3", "0F", "C2", "03" ] }, 470 "Divss": { "opcodes": [ "F3", "0F", "5E" ] }, 471 "Mulss": { "opcodes": [ "F3", "0F", "59" ] }, 472 "Subss": { "opcodes": [ "F3", "0F", "5C" ] } 473 }, 474 "args": [ 475 { "class": "FpReg32", "usage": "use_def" }, 476 { "class": "FpReg32/VecMem32", "usage": "use" } 477 ] 478 }, 479 { 480 "encodings": { 481 "Addw": { "opcodes": [ "66", "01" ], "reg_to_rm": true }, 482 "Andw": { "opcodes": [ "66", "21" ], "reg_to_rm": true }, 483 "Btcw": { "opcodes": [ "66", "0F", "BB" ], "reg_to_rm": true }, 484 "Btrw": { "opcodes": [ "66", "0F", "B3" ], "reg_to_rm": true }, 485 "Btsw": { "opcodes": [ "66", "0F", "AB" ], "reg_to_rm": true }, 486 "Orw": { "opcodes": [ "66", "09" ], "reg_to_rm": true }, 487 "Subw": { "opcodes": [ "66", "29" ], "reg_to_rm": true }, 488 "Xorw": { "opcodes": [ "66", "31" ], "reg_to_rm": true } 489 }, 490 "args": [ 491 { "class": "GeneralReg16/Mem16", "usage": "use_def" }, 492 { "class": "GeneralReg16", "usage": "use" }, 493 { "class": "FLAGS", "usage": "def" } 494 ] 495 }, 496 { 497 "encodings": { 498 "Addw": { "opcodes": [ "66", "03" ] }, 499 "Andw": { "opcodes": [ "66", "23" ] }, 500 "Orw": { "opcodes": [ "66", "0B" ] }, 501 "Subw": { "opcodes": [ "66", "2B" ] }, 502 "Xorw": { "opcodes": [ "66", "33" ] } 503 }, 504 "args": [ 505 { "class": "GeneralReg16", "usage": "use_def" }, 506 { "class": "Mem16", "usage": "use" }, 507 { "class": "FLAGS", "usage": "def" } 508 ] 509 }, 510 { 511 "encodings": { 512 "Addw": { "opcodes": [ "66", "81", "0" ] }, 513 "Andw": { "opcodes": [ "66", "81", "4" ] }, 514 "Orw": { "opcodes": [ "66", "81", "1" ] }, 515 "Subw": { "opcodes": [ "66", "81", "5" ] }, 516 "Xorw": { "opcodes": [ "66", "81", "6" ] } 517 }, 518 "args": [ 519 { "class": "GeneralReg16/Mem16", "usage": "use_def" }, 520 { "class": "Imm16" }, 521 { "class": "FLAGS", "usage": "def" } 522 ] 523 }, 524 { 525 "encodings": { 526 "AddwAccumulator": { "opcodes": [ "66", "05" ] }, 527 "AndwAccumulator": { "opcodes": [ "66", "25" ] }, 528 "OrwAccumulator": { "opcodes": [ "66", "0D" ] }, 529 "SubwAccumulator": { "opcodes": [ "66", "2D" ] }, 530 "XorwAccumulator": { "opcodes": [ "66", "35" ] } 531 }, 532 "args": [ 533 { "class": "AX", "usage": "use_def" }, 534 { "class": "Imm16" }, 535 { "class": "FLAGS", "usage": "def" } 536 ] 537 }, 538 { 539 "encodings": { 540 "AddwImm8": { "opcodes": [ "66", "83", "0" ] }, 541 "AndwImm8": { "opcodes": [ "66", "83", "4" ] }, 542 "OrwImm8": { "opcodes": [ "66", "83", "1" ] }, 543 "Rolw": { "opcodes": [ "66", "C1", "0" ] }, 544 "Rorw": { "opcodes": [ "66", "C1", "1" ] }, 545 "Sarw": { "opcodes": [ "66", "C1", "7" ] }, 546 "Shlw": { "opcodes": [ "66", "C1", "4" ] }, 547 "Shrw": { "opcodes": [ "66", "C1", "5" ] }, 548 "SubwImm8": { "opcodes": [ "66", "83", "5" ] }, 549 "XorwImm8": { "opcodes": [ "66", "83", "6" ] } 550 }, 551 "args": [ 552 { "class": "GeneralReg16/Mem16", "usage": "use_def" }, 553 { "class": "Imm8" }, 554 { "class": "FLAGS", "usage": "def" } 555 ] 556 }, 557 { 558 "encodings": { 559 "Andnl": { "feature": "BMI", "opcodes": [ "C4", "02", "00", "F2" ], "vex_rm_to_reg": true } 560 }, 561 "args": [ 562 { "class": "GeneralReg32", "usage": "def" }, 563 { "class": "GeneralReg32", "usage": "use" }, 564 { "class": "GeneralReg32/Mem32", "usage": "use" }, 565 { "class": "FLAGS", "usage": "def" } 566 ] 567 }, 568 { 569 "encodings": { 570 "Bextrl": { "feature": "BMI", "opcodes": [ "C4", "02", "00", "F7" ] }, 571 "Bzhil": { "feature": "BMI2", "opcodes": [ "C4", "02", "00", "F5" ] } 572 }, 573 "args": [ 574 { "class": "GeneralReg32", "usage": "use_def" }, 575 { "class": "GeneralReg32/Mem32", "usage": "use" }, 576 { "class": "GeneralReg32", "usage": "use" }, 577 { "class": "FLAGS", "usage": "def" } 578 ] 579 }, 580 { 581 "encodings": { 582 "Blsil": { "feature": "BMI", "opcodes": [ "C4", "02", "00", "F3", "3" ], "rm_to_vex": true }, 583 "Blsmskl": { "feature": "BMI", "opcodes": [ "C4", "02", "00", "F3", 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"GeneralReg16", "usage": "def" }, 607 { "class": "GeneralReg16/Mem16", "usage": "use" }, 608 { "class": "FLAGS", "usage": "def" } 609 ] 610 }, 611 { 612 "encodings": { 613 "Bswapl": { "opcodes": [ "0F", "C8" ] } 614 }, 615 "args": [ 616 { "class": "GeneralReg32", "usage": "use_def" } 617 ] 618 }, 619 { 620 "encodings": { 621 "Btl": { "opcodes": [ "0F", "A3" ], "reg_to_rm": true }, 622 "Cmpl": { "opcodes": [ "39" ], "reg_to_rm": true }, 623 "Testl": { "opcodes": [ "85" ], "reg_to_rm": true } 624 }, 625 "args": [ 626 { "class": "GeneralReg32/Mem32", "usage": "use" }, 627 { "class": "GeneralReg32", "usage": "use" }, 628 { "class": "FLAGS", "usage": "def" } 629 ] 630 }, 631 { 632 "encodings": { 633 "Btw": { "opcodes": [ "66", "0F", "A3" ], "reg_to_rm": true }, 634 "Cmpw": { "opcodes": [ "66", "39" ], "reg_to_rm": true }, 635 "Testw": { "opcodes": [ "66", "85" ], "reg_to_rm": true } 636 }, 637 "args": [ 638 { "class": "GeneralReg16/Mem16", "usage": "use" }, 639 { "class": "GeneralReg16", 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"args": [ 687 { "class": "FLAGS", "usage": "use_def" } 688 ] 689 }, 690 { 691 "encodings": { 692 "Cmovl": { "opcodes": [ "0F", "40" ] } 693 }, 694 "args": [ 695 { "class": "Cond" }, 696 { "class": "GeneralReg32", "usage": "use_def" }, 697 { "class": "GeneralReg32/Mem32", "usage": "use" }, 698 { "class": "FLAGS", "usage": "use" } 699 ] 700 }, 701 { 702 "encodings": { 703 "Cmovw": { "opcodes": [ "66", "0F", "40" ] } 704 }, 705 "args": [ 706 { "class": "Cond" }, 707 { "class": "GeneralReg16", "usage": "use_def" }, 708 { "class": "GeneralReg16/Mem16", "usage": "use" }, 709 { "class": "FLAGS", "usage": "use" } 710 ] 711 }, 712 { 713 "encodings": { 714 "CmpXchg8b": { "opcodes": [ "0F", "C7", "1" ] }, 715 "LockCmpXchg8b": { "opcodes": [ "F0", "0F", "C7", "1" ] } 716 }, 717 "args": [ 718 { "class": "EAX", "usage": "use_def" }, 719 { "class": "EDX", "usage": "use_def" }, 720 { "class": "EBX", "usage": "use" }, 721 { "class": "ECX", "usage": "use" }, 722 { "class": "VecMem64", "usage": "use_def" }, 723 { "class": "FLAGS", "usage": "def" } 724 ] 725 }, 726 { 727 "encodings": { 728 "CmpXchgl": { "opcodes": [ "0F", "B1" ], "reg_to_rm": true } 729 }, 730 "args": [ 731 { "class": "EAX", "usage": "use_def" }, 732 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 733 { "class": "GeneralReg32", "usage": "use" }, 734 { "class": "FLAGS", "usage": "def" } 735 ] 736 }, 737 { 738 "encodings": { 739 "Cmpb": { "opcodes": [ "80", "7" ] }, 740 "Testb": { "opcodes": [ "F6", "0" ] } 741 }, 742 "args": [ 743 { "class": "GeneralReg8/Mem8", "usage": "use" }, 744 { "class": "Imm8" }, 745 { "class": "FLAGS", "usage": "def" } 746 ] 747 }, 748 { 749 "encodings": { 750 "Cmpb": { "opcodes": [ "38" ], "reg_to_rm": true }, 751 "Testb": { "opcodes": [ "84" ], "reg_to_rm": true } 752 }, 753 "args": [ 754 { "class": "GeneralReg8/Mem8", "usage": "use" }, 755 { "class": "GeneralReg8", "usage": "use" }, 756 { "class": "FLAGS", "usage": "def" } 757 ] 758 }, 759 { 760 "encodings": { 761 "Cmpb": { "opcodes": [ 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804 "TestlAccumulator": { "opcodes": [ "A9" ] } 805 }, 806 "args": [ 807 { "class": "EAX", "usage": "use" }, 808 { "class": "Imm32" }, 809 { "class": "FLAGS", "usage": "def" } 810 ] 811 }, 812 { 813 "encodings": { 814 "CmplImm8": { "opcodes": [ "83", "7" ] } 815 }, 816 "args": [ 817 { "class": "GeneralReg32/Mem32", "usage": "use" }, 818 { "class": "Imm8" }, 819 { "class": "FLAGS", "usage": "def" } 820 ] 821 }, 822 { 823 "encodings": { 824 "Cmpw": { "opcodes": [ "66", "81", "7" ] }, 825 "Testw": { "opcodes": [ "66", "F7", "0" ] } 826 }, 827 "args": [ 828 { "class": "GeneralReg16/Mem16", "usage": "use" }, 829 { "class": "Imm16" }, 830 { "class": "FLAGS", "usage": "def" } 831 ] 832 }, 833 { 834 "encodings": { 835 "Cmpw": { "opcodes": [ "66", "3B" ] } 836 }, 837 "args": [ 838 { "class": "GeneralReg16", "usage": "use" }, 839 { "class": "Mem16", "usage": "use" }, 840 { "class": "FLAGS", "usage": "def" } 841 ] 842 }, 843 { 844 "encodings": { 845 "CmpwAccumulator": { "opcodes": [ "66", "3D" ] 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"class": "FpReg64/VecMem64", "usage": "use" } 898 ] 899 }, 900 { 901 "encodings": { 902 "Cvtsd2ss": { "opcodes": [ "F2", "0F", "5A" ] } 903 }, 904 "args": [ 905 { "class": "FpReg32", "usage": "def" }, 906 { "class": "FpReg64/VecMem64", "usage": "use" } 907 ] 908 }, 909 { 910 "encodings": { 911 "Cvtsi2sdl": { "opcodes": [ "F2", "0F", "2A" ] } 912 }, 913 "args": [ 914 { "class": "FpReg64", "usage": "def" }, 915 { "class": "GeneralReg32/Mem32", "usage": "use" } 916 ] 917 }, 918 { 919 "encodings": { 920 "Cvtsi2ssl": { "opcodes": [ "F3", "0F", "2A" ] } 921 }, 922 "args": [ 923 { "class": "FpReg32", "usage": "def" }, 924 { "class": "GeneralReg32/Mem32", "usage": "use" } 925 ] 926 }, 927 { 928 "encodings": { 929 "Cvtss2sd": { "opcodes": [ "F3", "0F", "5A" ] } 930 }, 931 "args": [ 932 { "class": "FpReg64", "usage": "def" }, 933 { "class": "FpReg32/VecMem32", "usage": "use" } 934 ] 935 }, 936 { 937 "encodings": { 938 "Cvtss2sil": { "opcodes": [ "F3", "0F", "2D" ] }, 939 "Cvttss2sil": { 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}, 975 "SarbByOne": { "opcodes": [ "D0", "7" ] }, 976 "ShlbByOne": { "opcodes": [ "D0", "4" ] }, 977 "ShrbByOne": { "opcodes": [ "D0", "5" ] } 978 }, 979 "args": [ 980 { "class": "GeneralReg8/Mem8", "usage": "use_def" }, 981 { "class": "FLAGS", "usage": "def" } 982 ] 983 }, 984 { 985 "encodings": { 986 "Decl": { "opcodes": [ "FF", "1" ] }, 987 "Incl": { "opcodes": [ "FF", "0" ] } 988 }, 989 "args": [ 990 { "class": "Mem32", "usage": "use_def" }, 991 { "class": "FLAGS", "usage": "def" } 992 ] 993 }, 994 { 995 "encodings": { 996 "Decw": { "opcodes": [ "66", "FF", "1" ] }, 997 "Incw": { "opcodes": [ "66", "FF", "0" ] } 998 }, 999 "args": [ 1000 { "class": "Mem16", "usage": "use_def" }, 1001 { "class": "FLAGS", "usage": "def" } 1002 ] 1003 }, 1004 { 1005 "encodings": { 1006 "Divb": { "opcodes": [ "F6", "6" ] }, 1007 "Idivb": { "opcodes": [ "F6", "7" ] } 1008 }, 1009 "args": [ 1010 { "class": "AX", "usage": "use_def" }, 1011 { "class": "GeneralReg8/Mem8", "usage": "use" }, 1012 { "class": "FLAGS", "usage": "def" } 1013 ] 1014 }, 1015 { 1016 "encodings": { 1017 "Divl": { "opcodes": [ "F7", "6" ] }, 1018 "Idivl": { "opcodes": [ "F7", "7" ] } 1019 }, 1020 "args": [ 1021 { "class": "EAX", "usage": "use_def" }, 1022 { "class": "EDX", "usage": "use_def" }, 1023 { "class": "GeneralReg32/Mem32", "usage": "use" }, 1024 { "class": "FLAGS", "usage": "def" } 1025 ] 1026 }, 1027 { 1028 "encodings": { 1029 "Divw": { "opcodes": [ "66", "F7", "6" ] }, 1030 "Idivw": { "opcodes": [ "66", "F7", "7" ] } 1031 }, 1032 "args": [ 1033 { "class": "AX", "usage": "use_def" }, 1034 { "class": "DX", "usage": "use_def" }, 1035 { "class": "GeneralReg16/Mem16", "usage": "use" }, 1036 { "class": "FLAGS", "usage": "def" } 1037 ] 1038 }, 1039 { 1040 "encodings": { 1041 "F2xm1": { "opcodes": [ "D9", "F0" ] }, 1042 "Fabs": { "opcodes": [ "D9", "E1" ] }, 1043 "Fchs": { "opcodes": [ "D9", "E0" ] }, 1044 "Fcos": { "opcodes": [ "D9", "FF" ] }, 1045 "Frndint": { "opcodes": [ "D9", "FC" ] }, 1046 "Fscale": { "opcodes": [ "D9", "FD" ] }, 1047 "Fsin": { "opcodes": [ "D9", "FE" ] }, 1048 "Fsqrt": { "opcodes": [ "D9", "FA" ] }, 1049 "Ftst": { "opcodes": [ "D9", "E4" ] } 1050 }, 1051 "args": [ 1052 { "class": "ST", "usage": "use_def" } 1053 ] 1054 }, 1055 { 1056 "encodings": { 1057 "FaddFromSt": { "opcodes": [ "DC", "0" ] }, 1058 "FaddpFromSt": { "opcodes": [ "DE", "0" ] }, 1059 "FdivFromSt": { "opcodes": [ "DC", "6" ] }, 1060 "FdivpFromSt": { "opcodes": [ "DE", "6" ] }, 1061 "FdivrFromSt": { "opcodes": [ "DC", "7" ] }, 1062 "FdivrpFromSt": { "opcodes": [ "DE", "7" ] }, 1063 "FmulFromSt": { "opcodes": [ "DC", "1" ] }, 1064 "FmulpFromSt": { "opcodes": [ "DE", "1" ] }, 1065 "FsubFromSt": { "opcodes": [ "DC", "4" ] }, 1066 "FsubpFromSt": { "opcodes": [ "DE", "4" ] }, 1067 "FsubrFromSt": { "opcodes": [ "DC", "5" ] }, 1068 "FsubrpFromSt": { "opcodes": [ "DE", "5" ] } 1069 }, 1070 "args": [ 1071 { "class": "RegX87", "usage": "use_def" }, 1072 { "class": "ST", "usage": "use" } 1073 ] 1074 }, 1075 { 1076 "encodings": { 1077 "FaddToSt": { "opcodes": [ "D8", "0" ] }, 1078 "FdivToSt": { "opcodes": [ "D8", "6" ] }, 1079 "FdivrToSt": { "opcodes": [ "D8", "7" ] }, 1080 "FmulToSt": { "opcodes": [ "D8", "1" ] }, 1081 "FsubToSt": { "opcodes": [ "D8", "4" ] }, 1082 "FsubrToSt": { "opcodes": [ "D8", "5" ] } 1083 }, 1084 "args": [ 1085 { "class": "ST", "usage": "use_def" }, 1086 { "class": "RegX87", "usage": "use" } 1087 ] 1088 }, 1089 { 1090 "encodings": { 1091 "Faddl": { "opcodes": [ "DC", "0" ] }, 1092 "Fdivl": { "opcodes": [ "DC", "6" ] }, 1093 "Fdivrl": { "opcodes": [ "DC", "7" ] }, 1094 "Fmull": { "opcodes": [ "DC", "1" ] }, 1095 "Fsubl": { "opcodes": [ "DC", "4" ] }, 1096 "Fsubrl": { "opcodes": [ "DC", "5" ] } 1097 }, 1098 "args": [ 1099 { "class": "ST", "usage": "use_def" }, 1100 { "class": "MemX8764", "usage": "use" } 1101 ] 1102 }, 1103 { 1104 "encodings": { 1105 "Fadds": { "opcodes": [ "D8", "0" ] }, 1106 "Fdivrs": { "opcodes": [ "D8", "7" ] }, 1107 "Fdivs": { "opcodes": [ "D8", "6" ] }, 1108 "Fiaddl": { "opcodes": [ "DA", "0" ] }, 1109 "Fidivl": { "opcodes": [ "DA", "6" ] }, 1110 "Fidivrl": { "opcodes": [ "DA", "7" ] }, 1111 "Fimull": { "opcodes": [ "DA", "1" ] }, 1112 "Fisubl": { "opcodes": [ "DA", "4" ] }, 1113 "Fisubrl": { "opcodes": [ "DA", "5" ] }, 1114 "Fmuls": { "opcodes": [ "D8", "1" ] }, 1115 "Fsubrs": { "opcodes": [ "D8", "5" ] }, 1116 "Fsubs": { "opcodes": [ "D8", "4" ] } 1117 }, 1118 "args": [ 1119 { "class": "ST", "usage": "use_def" }, 1120 { "class": "MemX8732", "usage": "use" } 1121 ] 1122 }, 1123 { 1124 "encodings": { 1125 "Fbld": { "opcodes": [ "DF", "4" ] }, 1126 "Fldt": { "opcodes": [ "DB", "5" ] } 1127 }, 1128 "args": [ 1129 { "class": "ST", "usage": "def" }, 1130 { "class": "MemX8780", "usage": "use" } 1131 ] 1132 }, 1133 { 1134 "encodings": { 1135 "Fbstp": { "opcodes": [ "DF", "6" ] }, 1136 "Fstpt": { "opcodes": [ "DB", "7" ] } 1137 }, 1138 "args": [ 1139 { "class": "MemX8780", "usage": "def" }, 1140 { "class": "ST", "usage": "use" } 1141 ] 1142 }, 1143 { 1144 "encodings": { 1145 "FcmovbToSt": { "opcodes": [ "DA", "0" ] }, 1146 "FcmovbeToSt": { "opcodes": [ "DA", "2" ] }, 1147 "FcmoveToSt": { "opcodes": [ "DA", "1" ] }, 1148 "FcmovnbToSt": { "opcodes": [ "DB", "0" ] }, 1149 "FcmovnbeToSt": { "opcodes": [ "DB", "2" ] }, 1150 "FcmovneToSt": { "opcodes": [ "DB", "1" ] }, 1151 "FcmovnuToSt": { "opcodes": [ "DB", "3" ] }, 1152 "FcmovuToSt": { "opcodes": [ "DA", "3" ] } 1153 }, 1154 "args": [ 1155 { "class": "ST", "usage": "use_def" }, 1156 { "class": "RegX87", "usage": "use" }, 1157 { "class": "FLAGS", "usage": "use" } 1158 ] 1159 }, 1160 { 1161 "encodings": { 1162 "Fcom": { "opcodes": [ "D8", "2" ] }, 1163 "Fcomp": { "opcodes": [ "D8", "3" ] }, 1164 "Fucom": { "opcodes": [ "DD", "4" ] }, 1165 "Fucomp": { "opcodes": [ "DD", "5" ] } 1166 }, 1167 "args": [ 1168 { "class": "ST", "usage": "use" }, 1169 { "class": "RegX87", "usage": "use" }, 1170 { "class": "CC", "usage": "def" } 1171 ] 1172 }, 1173 { 1174 "encodings": { 1175 "Fcomi": { "opcodes": [ "DB", "6" ] }, 1176 "Fcomip": { "opcodes": [ "DF", "6" ] }, 1177 "Fucomi": { "opcodes": [ "DB", "5" ] }, 1178 "Fucomip": { "opcodes": [ "DF", "5" ] } 1179 }, 1180 "args": [ 1181 { "class": "ST", "usage": "use" }, 1182 { "class": "RegX87", "usage": "use" }, 1183 { "class": "FLAGS", "usage": "def" } 1184 ] 1185 }, 1186 { 1187 "encodings": { 1188 "Fcoml": { "opcodes": [ "DC", "2" ] }, 1189 "Fcompl": { "opcodes": [ "DC", "3" ] } 1190 }, 1191 "args": [ 1192 { "class": "ST", "usage": "use" }, 1193 { "class": "MemX8764", "usage": "use" }, 1194 { "class": "CC", "usage": "def" } 1195 ] 1196 }, 1197 { 1198 "encodings": { 1199 "Fcompp": { "opcodes": [ "DE", "D9" ] }, 1200 "Fucompp": { "opcodes": [ "DA", "E9" ] } 1201 }, 1202 "args": [ 1203 { "class": "ST", "usage": "use" }, 1204 { "class": "ST1", "usage": "use" }, 1205 { "class": "CC", "usage": "def" } 1206 ] 1207 }, 1208 { 1209 "encodings": { 1210 "Fcomps": { "opcodes": [ "D8", "3" ] }, 1211 "Fcoms": { "opcodes": [ "D8", "2" ] }, 1212 "Ficoml": { "opcodes": [ "DA", "2" ] }, 1213 "Ficompl": { "opcodes": [ "DA", "3" ] } 1214 }, 1215 "args": [ 1216 { "class": "ST", "usage": "use" }, 1217 { "class": "MemX8732", "usage": "use" }, 1218 { "class": "CC", "usage": "def" } 1219 ] 1220 }, 1221 { 1222 "encodings": { 1223 "Fdecstp": { "opcodes": [ "D9", "F6" ] }, 1224 "Fincstp": { "opcodes": [ "D9", "F7" ] }, 1225 "Fnop": { "opcodes": [ "D9", "D0" ] }, 1226 "Fwait": { "opcodes": [ "9B" ] }, 1227 "Int3": { "opcodes": [ "CC" ] }, 1228 "Lfence": { "opcodes": [ "0F", "AE", "E8" ] }, 1229 "Mfence": { "opcodes": [ "0F", "AE", "F0" ] }, 1230 "Sfence": { "opcodes": [ "0F", "AE", "F8" ] }, 1231 "Nop": { "opcodes": [ "90" ] }, 1232 "UD2": { "opcodes": [ "0F", "0B" ] }, 1233 "Wait": { "opcodes": [ "9B" ] } 1234 }, 1235 "args": [] 1236 }, 1237 { 1238 "encodings": { 1239 "Ffree": { "opcodes": [ "DD", "0" ] } 1240 }, 1241 "args": [ 1242 { "class": "RegX87", "usage": "use" } 1243 ] 1244 }, 1245 { 1246 "encodings": { 1247 "Fiadds": { "opcodes": [ "DE", "0" ] }, 1248 "Fidivrs": { "opcodes": [ "DE", "7" ] }, 1249 "Fidivs": { "opcodes": [ "DE", "6" ] }, 1250 "Fimuls": { "opcodes": [ "DE", "1" ] }, 1251 "Fisubrs": { "opcodes": [ "DE", "5" ] }, 1252 "Fisubs": { "opcodes": [ "DE", "4" ] } 1253 }, 1254 "args": [ 1255 { "class": "ST", "usage": "use_def" }, 1256 { "class": "MemX8716", "usage": "use" } 1257 ] 1258 }, 1259 { 1260 "encodings": { 1261 "Ficomps": { "opcodes": [ "DE", "3" ] }, 1262 "Ficoms": { "opcodes": [ "DE", "2" ] } 1263 }, 1264 "args": [ 1265 { "class": "ST", "usage": "use" }, 1266 { "class": "MemX8716", "usage": "use" }, 1267 { "class": "CC", "usage": "def" } 1268 ] 1269 }, 1270 { 1271 "encodings": { 1272 "Fildl": { "opcodes": [ "DB", "0" ] }, 1273 "Flds": { "opcodes": [ "D9", "0" ] } 1274 }, 1275 "args": [ 1276 { "class": "ST", "usage": "def" }, 1277 { "class": "MemX8732", "usage": "use" } 1278 ] 1279 }, 1280 { 1281 "encodings": { 1282 "Fildll": { "opcodes": [ "DF", "5" ] }, 1283 "Fldl": { "opcodes": [ "DD", "0" ] } 1284 }, 1285 "args": [ 1286 { "class": "ST", "usage": "def" }, 1287 { "class": "MemX8764", "usage": "use" } 1288 ] 1289 }, 1290 { 1291 "encodings": { 1292 "Filds": { "opcodes": [ "DF", "0" ] } 1293 }, 1294 "args": [ 1295 { "class": "ST", "usage": "def" }, 1296 { "class": "MemX8716", "usage": "use" } 1297 ] 1298 }, 1299 { 1300 "encodings": { 1301 "Fistl": { "opcodes": [ "DB", "2" ] }, 1302 "Fistpl": { "opcodes": [ "DB", "3" ] }, 1303 "Fisttpl": { "feature": "SSE3", "opcodes": [ "DB", "1" ] }, 1304 "Fstps": { "opcodes": [ "D9", "3" ] }, 1305 "Fsts": { "opcodes": [ "D9", "2" ] } 1306 }, 1307 "args": [ 1308 { "class": "MemX8732", "usage": "def" }, 1309 { "class": "ST", "usage": "use" } 1310 ] 1311 }, 1312 { 1313 "encodings": { 1314 "Fistpll": { "opcodes": [ "DF", "7" ] }, 1315 "Fisttpll": { "feature": "SSE3", "opcodes": [ "DD", "1" ] }, 1316 "Fstl": { "opcodes": [ "DD", "2" ] }, 1317 "Fstpl": { "opcodes": [ "DD", "3" ] } 1318 }, 1319 "args": [ 1320 { "class": "MemX8764", "usage": "def" }, 1321 { "class": "ST", "usage": "use" } 1322 ] 1323 }, 1324 { 1325 "encodings": { 1326 "Fistps": { "opcodes": [ "DF", "3" ] }, 1327 "Fists": { "opcodes": [ "DF", "2" ] }, 1328 "Fisttps": { "feature": "SSE3", "opcodes": [ "DF", "1" ] } 1329 }, 1330 "args": [ 1331 { "class": "MemX8716", "usage": "def" }, 1332 { "class": "ST", "usage": "use" } 1333 ] 1334 }, 1335 { 1336 "encodings": { 1337 "Fld1": { "opcodes": [ "D9", "E8" ] }, 1338 "Fldl2e": { "opcodes": [ "D9", "EA" ] }, 1339 "Fldl2t": { "opcodes": [ "D9", "E9" ] }, 1340 "Fldlg2": { "opcodes": [ "D9", "EC" ] }, 1341 "Fldln2": { "opcodes": [ "D9", "ED" ] }, 1342 "Fldpi": { "opcodes": [ "D9", "EB" ] }, 1343 "Fldz": { "opcodes": [ "D9", "EE" ] } 1344 }, 1345 "args": [ 1346 { "class": "ST", "usage": "use_def" } 1347 ] 1348 }, 1349 { 1350 "encodings": { 1351 "Fld": { "opcodes": [ "D9", "0" ] } 1352 }, 1353 "args": [ 1354 { "class": "ST", "usage": "def" }, 1355 { "class": "RegX87", "usage": "use" } 1356 ] 1357 }, 1358 { 1359 "encodings": { 1360 "Fldcw": { "opcodes": [ "D9", "5" ] } 1361 }, 1362 "args": [ 1363 { "class": "CC", "usage": "def" }, 1364 { "class": "MemX8732", "usage": "use" } 1365 ] 1366 }, 1367 { 1368 "encodings": { 1369 "Fldenv": { "opcodes": [ "D9", "4" ] }, 1370 "Frstor": { "opcodes": [ "DD", "4" ] }, 1371 "Fxrstor": { "opcodes": [ "0F", "AE", "1" ] } 1372 }, 1373 "args": [ 1374 { "class": "MemX87", "usage": "use" }, 1375 { "class": "CC", "usage": "def" } 1376 ] 1377 }, 1378 { 1379 "encodings": { 1380 "Fnclex": { "opcodes": [ "DB", "E2" ] }, 1381 "Fndisi": { "opcodes": [ "DB", "E1" ] }, 1382 "Fneni": { "opcodes": [ "DB", "E0" ] }, 1383 "Fninit": { "opcodes": [ "DB", "E3" ] }, 1384 "Fnsetpm": { "opcodes": [ "DB", "E4" ] } 1385 }, 1386 "args": [ 1387 { "class": "CC", "usage": "def" } 1388 ] 1389 }, 1390 { 1391 "encodings": { 1392 "Fnsave": { "opcodes": [ "DD", "6" ] }, 1393 "Fnstenv": { "opcodes": [ "D9", "6" ] }, 1394 "Fxsave": { "opcodes": [ "0F", "AE", "0" ] } 1395 }, 1396 "args": [ 1397 { "class": "CC", "usage": "def" }, 1398 { "class": "MemX87", "usage": "use" } 1399 ] 1400 }, 1401 { 1402 "encodings": { 1403 "Fnstcw": { "opcodes": [ "D9", "7" ] } 1404 }, 1405 "args": [ 1406 { "class": "MemX8732", "usage": "def" }, 1407 { "class": "CC", "usage": "use" } 1408 ] 1409 }, 1410 { 1411 "encodings": { 1412 "Fnstsw": { "opcodes": [ "DF", "E0" ] } 1413 }, 1414 "args": [ 1415 { "class": "AX", "usage": "def" }, 1416 { "class": "SW", "usage": "use" } 1417 ] 1418 }, 1419 { 1420 "encodings": { 1421 "Fnstsw": { "opcodes": [ "DD", "7" ] } 1422 }, 1423 "args": [ 1424 { "class": "MemX8732", "usage": "def" }, 1425 { "class": "SW", "usage": "use" } 1426 ] 1427 }, 1428 { 1429 "encodings": { 1430 "Fpatan": { "opcodes": [ "D9", "F3" ] }, 1431 "Fprem": { "opcodes": [ "D9", "F8" ] }, 1432 "Fprem1": { "opcodes": [ "D9", "F5" ] }, 1433 "Fyl2x": { "opcodes": [ "D9", "F1" ] }, 1434 "Fyl2xp1": { "opcodes": [ "D9", "F9" ] } 1435 }, 1436 "args": [ 1437 { "class": "ST", "usage": "use_def" }, 1438 { "class": "ST1", "usage": "use" } 1439 ] 1440 }, 1441 { 1442 "encodings": { 1443 "Fptan": { "opcodes": [ "D9", "F2" ] }, 1444 "Fsincos": { "opcodes": [ "D9", "FB" ] }, 1445 "Fxtract": { "opcodes": [ "D9", "F4" ] } 1446 }, 1447 "args": [ 1448 { "class": "ST", "usage": "use_def" }, 1449 { "class": "ST1", "usage": "def" } 1450 ] 1451 }, 1452 { 1453 "encodings": { 1454 "Fst": { "opcodes": [ "DD", "2" ] }, 1455 "Fstp": { "opcodes": [ "DD", "3" ] } 1456 }, 1457 "args": [ 1458 { "class": "RegX87", "usage": "def" }, 1459 { "class": "ST", "usage": "use" } 1460 ] 1461 }, 1462 { 1463 "encodings": { 1464 "Fxam": { "opcodes": [ "D9", "E5" ] } 1465 }, 1466 "args": [ 1467 { "class": "ST", "usage": "use" }, 1468 { "class": "CC", "usage": "def" } 1469 ] 1470 }, 1471 { 1472 "encodings": { 1473 "Fxch": { "opcodes": [ "D9", "1" ] } 1474 }, 1475 "args": [ 1476 { "class": "RegX87", "usage": "use_def" }, 1477 { "class": "ST", "usage": "use_def" } 1478 ] 1479 }, 1480 { 1481 "encodings": { 1482 "Imulb": { "opcodes": [ "F6", "5" ] }, 1483 "Mulb": { "opcodes": [ "F6", "4" ] } 1484 }, 1485 "args": [ 1486 { "class": "AL", "usage": "use" }, 1487 { "class": "AX", "usage": "def" }, 1488 { "class": "GeneralReg8/Mem8", "usage": "use" }, 1489 { "class": "FLAGS", "usage": "def" } 1490 ] 1491 }, 1492 { 1493 "encodings": { 1494 "Imull": { "opcodes": [ "F7", "5" ] }, 1495 "Mull": { "opcodes": [ "F7", "4" ] } 1496 }, 1497 "args": [ 1498 { "class": "EAX", "usage": "use_def" }, 1499 { "class": "EDX", "usage": "def" }, 1500 { "class": "GeneralReg32/Mem32", "usage": "use" }, 1501 { "class": "FLAGS", "usage": "def" } 1502 ] 1503 }, 1504 { 1505 "encodings": { 1506 "Imull": { "opcodes": [ "69" ] } 1507 }, 1508 "args": [ 1509 { "class": "GeneralReg32", "usage": "def" }, 1510 { "class": "GeneralReg32/Mem32", "usage": "use" }, 1511 { "class": "Imm32" }, 1512 { "class": "FLAGS", "usage": "def" } 1513 ] 1514 }, 1515 { 1516 "encodings": { 1517 "Imull": { "opcodes": [ "0F", "AF" ] } 1518 }, 1519 "args": [ 1520 { "class": "GeneralReg32", "usage": "use_def" }, 1521 { "class": "GeneralReg32/Mem32", "usage": "use" }, 1522 { "class": "FLAGS", "usage": "def" } 1523 ] 1524 }, 1525 { 1526 "encodings": { 1527 "ImullImm8": { "opcodes": [ "6B" ] } 1528 }, 1529 "args": [ 1530 { "class": "GeneralReg32", "usage": "def" }, 1531 { "class": "GeneralReg32/Mem32", "usage": "use" }, 1532 { "class": "Imm8" }, 1533 { "class": "FLAGS", "usage": "def" } 1534 ] 1535 }, 1536 { 1537 "encodings": { 1538 "Imulw": { "opcodes": [ "66", "F7", "5" ] }, 1539 "Mulw": { "opcodes": [ "66", "F7", "4" ] } 1540 }, 1541 "args": [ 1542 { "class": "AX", "usage": "use_def" }, 1543 { "class": "DX", "usage": "def" }, 1544 { "class": "GeneralReg16/Mem16", "usage": "use" }, 1545 { "class": "FLAGS", "usage": "def" } 1546 ] 1547 }, 1548 { 1549 "encodings": { 1550 "Imulw": { "opcodes": [ "66", "69" ] } 1551 }, 1552 "args": [ 1553 { "class": "GeneralReg16", "usage": "def" }, 1554 { "class": "GeneralReg16/Mem16", "usage": "use" }, 1555 { "class": "Imm16" }, 1556 { "class": "FLAGS", "usage": "def" } 1557 ] 1558 }, 1559 { 1560 "encodings": { 1561 "Imulw": { "opcodes": [ "66", "0F", "AF" ] } 1562 }, 1563 "args": [ 1564 { "class": "GeneralReg16", "usage": "use_def" }, 1565 { "class": "GeneralReg16/Mem16", "usage": "use" }, 1566 { "class": "FLAGS", "usage": "def" } 1567 ] 1568 }, 1569 { 1570 "encodings": { 1571 "ImulwImm8": { "opcodes": [ "66", "6B" ] } 1572 }, 1573 "args": [ 1574 { "class": "GeneralReg16", "usage": "def" }, 1575 { "class": "GeneralReg16/Mem16", "usage": "use" }, 1576 { "class": "Imm8" }, 1577 { "class": "FLAGS", "usage": "def" } 1578 ] 1579 }, 1580 { 1581 "stems": [ "Jcc" ], 1582 "args": [ 1583 { "class": "Cond" }, 1584 { "class": "Label" }, 1585 { "class": "FLAGS", "usage": "use" } 1586 ] 1587 }, 1588 { 1589 "stems": [ "Jmp" ], 1590 "args": [ 1591 { "class": "Label" } 1592 ] 1593 }, 1594 { 1595 "encodings": { 1596 "Jmp": { "opcodes": [ "FF", "4" ] } 1597 }, 1598 "args": [ 1599 { "class": "GeneralReg", "usage": "use" } 1600 ] 1601 }, 1602 { 1603 "encodings": { 1604 "Lahf": { "opcodes": [ "9F" ] } 1605 }, 1606 "args": [ 1607 { "class": "EAX", "usage": "use_def" }, 1608 { "class": "FLAGS", "usage": "use" } 1609 ], 1610 "comment": "Use use_def below because LAHF writes to AH while preserving the rest of RAX" 1611 }, 1612 { 1613 "encodings": { 1614 "Ldmxcsr": { "opcodes": [ "0F", "AE", "2" ] }, 1615 "Vldmxcsr": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "AE", "2" ] } 1616 }, 1617 "args": [ 1618 { "class": "Mem32", "usage": "use" } 1619 ] 1620 }, 1621 { 1622 "encodings": { 1623 "Leal": { "opcodes": [ "8D" ] }, 1624 "Movl": { "opcodes": [ "8B" ] } 1625 }, 1626 "args": [ 1627 { "class": "GeneralReg32", "usage": "def" }, 1628 { "class": "Mem32", "usage": "use" } 1629 ] 1630 }, 1631 { 1632 "encodings": { 1633 "LockCmpXchgb": { "opcodes": [ "F0", "0F", "B0" ], "reg_to_rm": true } 1634 }, 1635 "args": [ 1636 { "class": "AL", "usage": "use_def" }, 1637 { "class": "Mem8", "usage": "use_def" }, 1638 { "class": "GeneralReg8", "usage": "use" }, 1639 { "class": "FLAGS", "usage": "def" } 1640 ] 1641 }, 1642 { 1643 "encodings": { 1644 "LockCmpXchgl": { "opcodes": [ "F0", "0F", "B1" ], "reg_to_rm": true } 1645 }, 1646 "args": [ 1647 { "class": "EAX", "usage": "use_def" }, 1648 { "class": "Mem32", "usage": "use_def" }, 1649 { "class": "GeneralReg32", "usage": "use" }, 1650 { "class": "FLAGS", "usage": "def" } 1651 ] 1652 }, 1653 { 1654 "encodings": { 1655 "LockCmpXchgw": { "opcodes": [ "F0", "66", "0F", "B1" ], "reg_to_rm": true } 1656 }, 1657 "args": [ 1658 { "class": "AX", "usage": "use_def" }, 1659 { "class": "Mem16", "usage": "use_def" }, 1660 { "class": "GeneralReg16", "usage": "use" }, 1661 { "class": "FLAGS", "usage": "def" } 1662 ] 1663 }, 1664 { 1665 "encodings": { 1666 "Movapd": { "opcodes": [ "66", "0F", "29" ] }, 1667 "Movaps": { "opcodes": [ "0F", "29" ] }, 1668 "Vmovapd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "29" ] }, 1669 "Vmovaps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "29" ] } 1670 }, 1671 "args": [ 1672 { "class": "VecMem128", "usage": "def" }, 1673 { "class": "XmmReg", "usage": "use" } 1674 ] 1675 }, 1676 { 1677 "encodings": { 1678 "Movapd": { "opcodes": [ "66", "0F", "28" ] }, 1679 "Movaps": { "opcodes": [ "0F", "28" ] } 1680 }, 1681 "args": [ 1682 { "class": "XmmReg", "usage": "def" }, 1683 { "class": "XmmReg/VecMem128", "usage": "use" } 1684 ] 1685 }, 1686 { 1687 "encodings": { 1688 "Movb": { "opcodes": [ "B0" ] } 1689 }, 1690 "args": [ 1691 { "class": "GeneralReg8", "usage": "def" }, 1692 { "class": "Imm8" } 1693 ] 1694 }, 1695 { 1696 "encodings": { 1697 "Movb": { "opcodes": [ "8A" ] } 1698 }, 1699 "args": [ 1700 { "class": "GeneralReg8", "usage": "def" }, 1701 { "class": "Mem8", "usage": "use" } 1702 ] 1703 }, 1704 { 1705 "encodings": { 1706 "Movb": { "opcodes": [ "88" ], "reg_to_rm": true } 1707 }, 1708 "args": [ 1709 { "class": "GeneralReg8/Mem8", "usage": "def" }, 1710 { "class": "GeneralReg8", "usage": "use" } 1711 ] 1712 }, 1713 { 1714 "encodings": { 1715 "Movb": { "opcodes": [ "C6", "0" ] } 1716 }, 1717 "args": [ 1718 { "class": "Mem8", "usage": "def" }, 1719 { "class": "Imm8" } 1720 ] 1721 }, 1722 { 1723 "encodings": { 1724 "Movd": { "opcodes": [ "66", "0F", "7E" ], "reg_to_rm": true }, 1725 "Vmovd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "7E" ], "reg_to_rm": true } 1726 }, 1727 "args": [ 1728 { "class": "GeneralReg32/Mem32", "usage": "def" }, 1729 { "class": "XmmReg", "usage": "use" } 1730 ] 1731 }, 1732 { 1733 "encodings": { 1734 "Movd": { "opcodes": [ "66", "0F", "6E" ] }, 1735 "Vmovd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "6E" ] } 1736 }, 1737 "args": [ 1738 { "class": "XmmReg", "usage": "def" }, 1739 { "class": "GeneralReg32/Mem32", "usage": "use" } 1740 ] 1741 }, 1742 { 1743 "name": "MovdqRegReg", 1744 "args": [ 1745 { "class": "XmmReg", "usage": "def" }, 1746 { "class": "XmmReg", "usage": "use" } 1747 ], 1748 "asm": "Pmov", 1749 "mnemo": "MOVDQ" 1750 }, 1751 { 1752 "encodings": { 1753 "Movdqa": { "opcodes": [ "66", "0F", "7F" ] }, 1754 "Movdqu": { "opcodes": [ "F3", "0F", "7F" ] }, 1755 "Vmovdqa": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "7F" ] }, 1756 "Vmovdqu": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "7F" ] } 1757 }, 1758 "args": [ 1759 { "class": "VecMem128", "usage": "def" }, 1760 { "class": "XmmReg", "usage": "use" } 1761 ] 1762 }, 1763 { 1764 "encodings": { 1765 "Movdqa": { "opcodes": [ "66", "0F", "6F" ] }, 1766 "Movdqu": { "opcodes": [ "F3", "0F", "6F" ] } 1767 }, 1768 "args": [ 1769 { "class": "XmmReg", "usage": "def" }, 1770 { "class": "XmmReg/VecMem128", "usage": "use" } 1771 ] 1772 }, 1773 { 1774 "encodings": { 1775 "Movhlps": { "opcodes": [ "0F", "12" ] }, 1776 "Movlhps": { "opcodes": [ "0F", "16" ] }, 1777 "Movsd": { "opcodes": [ "F2", "0F", "10" ] }, 1778 "Movss": { "opcodes": [ "F3", "0F", "10" ] } 1779 }, 1780 "args": [ 1781 { "class": "XmmReg", "usage": "use_def" }, 1782 { "class": "XmmReg", "usage": "use" } 1783 ], 1784 "comment": "Upper bits (lower bits for Movlhps) are unchanged" 1785 }, 1786 { 1787 "encodings": { 1788 "Movhpd": { "opcodes": [ "66", "0F", "17" ] }, 1789 "Movhps": { "opcodes": [ "0F", "17" ] }, 1790 "Movlpd": { "opcodes": [ "66", "0F", "13" ] }, 1791 "Movlps": { "opcodes": [ "0F", "13" ] }, 1792 "Vmovhpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "17" ] }, 1793 "Vmovhps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "17" ] }, 1794 "Vmovlpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "13" ] }, 1795 "Vmovlps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "13" ] } 1796 }, 1797 "args": [ 1798 { "class": "VecMem64", "usage": "use_def" }, 1799 { "class": "XmmReg", "usage": "use" } 1800 ] 1801 }, 1802 { 1803 "encodings": { 1804 "Movhpd": { "opcodes": [ "66", "0F", "16" ] }, 1805 "Movhps": { "opcodes": [ "0F", "16" ] }, 1806 "Movlpd": { "opcodes": [ "66", "0F", "12" ] }, 1807 "Movlps": { "opcodes": [ "0F", "12" ] } 1808 }, 1809 "args": [ 1810 { "class": "XmmReg", "usage": "use_def" }, 1811 { "class": "VecMem64", "usage": "use" } 1812 ] 1813 }, 1814 { 1815 "encodings": { 1816 "Movl": { "opcodes": [ "B8" ] } 1817 }, 1818 "args": [ 1819 { "class": "GeneralReg32", "usage": "def" }, 1820 { "class": "Imm32" } 1821 ] 1822 }, 1823 { 1824 "encodings": { 1825 "Movl": { "opcodes": [ "89" ], "reg_to_rm": true } 1826 }, 1827 "args": [ 1828 { "class": "GeneralReg32/Mem32", "usage": "def" }, 1829 { "class": "GeneralReg32", "usage": "use" } 1830 ] 1831 }, 1832 { 1833 "encodings": { 1834 "Movl": { "opcodes": [ "C7", "0" ] } 1835 }, 1836 "args": [ 1837 { "class": "Mem32", "usage": "def" }, 1838 { "class": "Imm32" } 1839 ] 1840 }, 1841 { 1842 "encodings": { 1843 "Movmskpd": { "opcodes": [ "66", "0F", "50" ] }, 1844 "Movmskps": { "opcodes": [ "0F", "50" ] }, 1845 "Vmovmskpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "50" ] }, 1846 "Vmovmskps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "50" ] } 1847 }, 1848 "args": [ 1849 { "class": "GeneralReg32", "usage": "def" }, 1850 { "class": "XmmReg", "usage": "use" } 1851 ] 1852 }, 1853 { 1854 "encodings": { 1855 "Movq": { "opcodes": [ "66", "0F", "D6" ] }, 1856 "Movsd": { "opcodes": [ "F2", "0F", "11" ] }, 1857 "Vmovq": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "D6" ] }, 1858 "Vmovsd": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "11" ] } 1859 }, 1860 "args": [ 1861 { "class": "VecMem64", "usage": "def" }, 1862 { "class": "XmmReg", "usage": "use" } 1863 ] 1864 }, 1865 { 1866 "encodings": { 1867 "Movq": { "opcodes": [ "F3", "0F", "7E" ] }, 1868 "Pmovsxbw": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "20" ] }, 1869 "Pmovsxdq": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "25" ] }, 1870 "Pmovsxwd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "23" ] }, 1871 "Pmovzxbw": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "30" ] }, 1872 "Pmovzxdq": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "35" ] }, 1873 "Pmovzxwd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "33" ] }, 1874 "Vmovq": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "7E" ] } 1875 }, 1876 "args": [ 1877 { "class": "XmmReg", "usage": "def" }, 1878 { "class": "XmmReg/VecMem64", "usage": "use" } 1879 ], 1880 "comment": "Upper bits are zero-filled for Movq/Vmovq" 1881 }, 1882 { 1883 "encodings": { 1884 "Movsd": { "opcodes": [ "F2", "0F", "10" ] }, 1885 "Vmovsd": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "10" ] } 1886 }, 1887 "args": [ 1888 { "class": "XmmReg", "usage": "def" }, 1889 { "class": "VecMem64", "usage": "use" } 1890 ], 1891 "comment": "Upper bits are zero-filled" 1892 }, 1893 { 1894 "encodings": { 1895 "Movss": { "opcodes": [ "F3", "0F", "10" ] }, 1896 "Vmovss": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "10" ] } 1897 }, 1898 "args": [ 1899 { "class": "XmmReg", "usage": "def" }, 1900 { "class": "VecMem32", "usage": "use" } 1901 ], 1902 "comment": "Upper bits are zero-filled" 1903 }, 1904 { 1905 "encodings": { 1906 "Movss": { "opcodes": [ "F3", "0F", "11" ] } 1907 }, 1908 "args": [ 1909 { "class": "Mem32", "usage": "def" }, 1910 { "class": "XmmReg", "usage": "use" } 1911 ] 1912 }, 1913 { 1914 "encodings": { 1915 "Movsxbl": { "opcodes": [ "0F", "BE" ] }, 1916 "Movzxbl": { "opcodes": [ "0F", "B6" ] } 1917 }, 1918 "args": [ 1919 { "class": "GeneralReg32", "usage": "def" }, 1920 { "class": "GeneralReg8/Mem8", "usage": "use" } 1921 ] 1922 }, 1923 { 1924 "encodings": { 1925 "Movsxwl": { "opcodes": [ "0F", "BF" ] }, 1926 "Movzxwl": { "opcodes": [ "0F", "B7" ] } 1927 }, 1928 "args": [ 1929 { "class": "GeneralReg32", "usage": "def" }, 1930 { "class": "GeneralReg16/Mem16", "usage": "use" } 1931 ] 1932 }, 1933 { 1934 "encodings": { 1935 "Movw": { "opcodes": [ "66", "B8" ] } 1936 }, 1937 "args": [ 1938 { "class": "GeneralReg16", "usage": "def" }, 1939 { "class": "Imm16" } 1940 ] 1941 }, 1942 { 1943 "encodings": { 1944 "Movw": { "opcodes": [ "66", "8B" ] } 1945 }, 1946 "args": [ 1947 { "class": "GeneralReg16", "usage": "def" }, 1948 { "class": "Mem16", "usage": "use" } 1949 ] 1950 }, 1951 { 1952 "encodings": { 1953 "Movw": { "opcodes": [ "66", "89" ], "reg_to_rm": true } 1954 }, 1955 "args": [ 1956 { "class": "GeneralReg16/Mem16", "usage": "def" }, 1957 { "class": "GeneralReg16", "usage": "use" } 1958 ] 1959 }, 1960 { 1961 "encodings": { 1962 "Movw": { "opcodes": [ "66", "C7", "0" ] } 1963 }, 1964 "args": [ 1965 { "class": "Mem16", "usage": "def" }, 1966 { "class": "Imm16" } 1967 ] 1968 }, 1969 { 1970 "encodings": { 1971 "Mulxl": { "feature": "BMI2", "opcodes": [ "C4", "02", "03", "F6" ], "vex_rm_to_reg": true }, 1972 "Pdepl": { "feature": "BMI2", "opcodes": [ "C4", "02", "03", "F5" ], "vex_rm_to_reg": true }, 1973 "Pextl": { "feature": "BMI2", "opcodes": [ "C4", "02", "02", "F5" ], "vex_rm_to_reg": true } 1974 }, 1975 "args": [ 1976 { "class": "GeneralReg32", "usage": "use_def" }, 1977 { "class": "GeneralReg32", "usage": "use" }, 1978 { "class": "GeneralReg32/Mem32", "usage": "use" } 1979 ] 1980 }, 1981 { 1982 "encodings": { 1983 "Negl": { "opcodes": [ "F7", "3" ] }, 1984 "RollByOne": { "opcodes": [ "D1", "0" ] }, 1985 "RorlByOne": { "opcodes": [ "D1", "1" ] }, 1986 "SarlByOne": { "opcodes": [ "D1", "7" ] }, 1987 "ShllByOne": { "opcodes": [ "D1", "4" ] }, 1988 "ShrlByOne": { "opcodes": [ "D1", "5" ] } 1989 }, 1990 "args": [ 1991 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 1992 { "class": "FLAGS", "usage": "def" } 1993 ] 1994 }, 1995 { 1996 "encodings": { 1997 "Negw": { "opcodes": [ "66", "F7", "3" ] }, 1998 "RolwByOne": { "opcodes": [ "66", "D1", "0" ] }, 1999 "RorwByOne": { "opcodes": [ "66", "D1", "1" ] }, 2000 "SarwByOne": { "opcodes": [ "66", "D1", "7" ] }, 2001 "ShlwByOne": { "opcodes": [ "66", "D1", "4" ] }, 2002 "ShrwByOne": { "opcodes": [ "66", "D1", "5" ] } 2003 }, 2004 "args": [ 2005 { "class": "GeneralReg16/Mem16", "usage": "use_def" }, 2006 { "class": "FLAGS", "usage": "def" } 2007 ] 2008 }, 2009 { 2010 "encodings": { 2011 "Notb": { "opcodes": [ "F6", "2" ] } 2012 }, 2013 "args": [ 2014 { "class": "GeneralReg8/Mem8", "usage": "use_def" } 2015 ] 2016 }, 2017 { 2018 "encodings": { 2019 "Notl": { "opcodes": [ "F7", "2" ] } 2020 }, 2021 "args": [ 2022 { "class": "GeneralReg32/Mem32", "usage": "use_def" } 2023 ] 2024 }, 2025 { 2026 "encodings": { 2027 "Notw": { "opcodes": [ "66", "F7", "2" ] } 2028 }, 2029 "args": [ 2030 { "class": "GeneralReg16/Mem16", "usage": "use_def" } 2031 ] 2032 }, 2033 { 2034 "encodings": { 2035 "Pextrb": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "14" ], "reg_to_rm": true }, 2036 "Pextrd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "16" ], "reg_to_rm": true }, 2037 "Pextrw": { "opcodes": [ "66", "0F", "C5" ] }, 2038 "Vpextrb": { "feature": "AVX", "opcodes": [ "C4", "03", "01", "14" ], "reg_to_rm": true }, 2039 "Vpextrd": { "feature": "AVX", "opcodes": [ "C4", "03", "01", "16" ], "reg_to_rm": true }, 2040 "Vpextrw": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "C5" ] } 2041 }, 2042 "args": [ 2043 { "class": "GeneralReg32", "usage": "def" }, 2044 { "class": "VecReg128", "usage": "use" }, 2045 { "class": "Imm8" } 2046 ] 2047 }, 2048 { 2049 "encodings": { 2050 "Pinsrb": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "20" ] }, 2051 "Pinsrd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "22" ] }, 2052 "Pinsrw": { "opcodes": [ "66", "0F", "C4" ] } 2053 }, 2054 "args": [ 2055 { "class": "VecReg128", "usage": "use_def" }, 2056 { "class": "GeneralReg32", "usage": "use" }, 2057 { "class": "Imm8" } 2058 ] 2059 }, 2060 { 2061 "encodings": { 2062 "Pmovmskb": { "opcodes": [ "66", "0F", "D7" ] }, 2063 "Vpmovmskb": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "D7" ] } 2064 }, 2065 "args": [ 2066 { "class": "GeneralReg32", "usage": "def" }, 2067 { "class": "VecReg128", "usage": "use" } 2068 ] 2069 }, 2070 { 2071 "encodings": { 2072 "Pmovsxbd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "21" ] }, 2073 "Pmovsxwq": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "24" ] }, 2074 "Pmovzxbd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "31" ] }, 2075 "Pmovzxwq": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "34" ] } 2076 }, 2077 "args": [ 2078 { "class": "XmmReg", "usage": "def" }, 2079 { "class": "XmmReg/VecMem32", "usage": "use" } 2080 ] 2081 }, 2082 { 2083 "encodings": { 2084 "Pop": { "opcodes": [ "58" ] } 2085 }, 2086 "args": [ 2087 { "class": "RSP", "usage": "use_def" }, 2088 { "class": "GeneralReg", "usage": "def" } 2089 ] 2090 }, 2091 { 2092 "encodings": { 2093 "Pshufd": { "opcodes": [ "66", "0F", "70" ] }, 2094 "Pshufhw": { "opcodes": [ "F3", "0F", "70" ] }, 2095 "Pshuflw": { "opcodes": [ "F2", "0F", "70" ] }, 2096 "Roundpd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "09" ] }, 2097 "Roundps": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "08" ] }, 2098 "Vpshufd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "70" ] }, 2099 "Vpshufhw": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "70" ] }, 2100 "Vpshuflw": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "70" ] }, 2101 "Vroundpd": { "feature": "AVX", "opcodes": [ "C4", "03", "01", "09" ] }, 2102 "Vroundps": { "feature": "AVX", "opcodes": [ "C4", "03", "01", "08" ] } 2103 }, 2104 "args": [ 2105 { "class": "VecReg128", "usage": "def" }, 2106 { "class": "VecReg128/VecMem128", "usage": "use" }, 2107 { "class": "Imm8" } 2108 ] 2109 }, 2110 { 2111 "encodings": { 2112 "Pslld": { "opcodes": [ "66", "0F", "72", "6" ] }, 2113 "Pslldq": { "opcodes": [ "66", "0F", "73", "7" ] }, 2114 "Psllq": { "opcodes": [ "66", "0F", "73", "6" ] }, 2115 "Psllw": { "opcodes": [ "66", "0F", "71", "6" ] }, 2116 "Psrad": { "opcodes": [ "66", "0F", "72", "4" ] }, 2117 "Psraw": { "opcodes": [ "66", "0F", "71", "4" ] }, 2118 "Psrld": { "opcodes": [ "66", "0F", "72", "2" ] }, 2119 "Psrldq": { "opcodes": [ "66", "0F", "73", "3" ] }, 2120 "Psrlq": { "opcodes": [ "66", "0F", "73", "2" ] }, 2121 "Psrlw": { "opcodes": [ "66", "0F", "71", "2" ] } 2122 }, 2123 "args": [ 2124 { "class": "VecReg128", "usage": "use_def" }, 2125 { "class": "Imm8" } 2126 ] 2127 }, 2128 { 2129 "encodings": { 2130 "Push": { "opcodes": [ "68" ] } 2131 }, 2132 "args": [ 2133 { "class": "RSP", "usage": "use_def" }, 2134 { "class": "Imm32" } 2135 ] 2136 }, 2137 { 2138 "encodings": { 2139 "PushImm8": { "opcodes": [ "6A" ] } 2140 }, 2141 "args": [ 2142 { "class": "RSP", "usage": "use_def" }, 2143 { "class": "Imm8" } 2144 ] 2145 }, 2146 { 2147 "encodings": { 2148 "RclbByCl": { "opcodes": [ "D2", "2" ] }, 2149 "RcrbByCl": { "opcodes": [ "D2", "3" ] } 2150 }, 2151 "args": [ 2152 { "class": "GeneralReg8/Mem8", "usage": "use_def" }, 2153 { "class": "CL", "usage": "use" }, 2154 { "class": "FLAGS", "usage": "use_def" } 2155 ] 2156 }, 2157 { 2158 "encodings": { 2159 "RclbByOne": { "opcodes": [ "D0", "2" ] }, 2160 "RcrbByOne": { "opcodes": [ "D0", "3" ] } 2161 }, 2162 "args": [ 2163 { "class": "GeneralReg8/Mem8", "usage": "use_def" }, 2164 { "class": "FLAGS", "usage": "use_def" } 2165 ] 2166 }, 2167 { 2168 "encodings": { 2169 "RcllByCl": { "opcodes": [ "D3", "2" ] }, 2170 "RcrlByCl": { "opcodes": [ "D3", "3" ] } 2171 }, 2172 "args": [ 2173 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 2174 { "class": "CL", "usage": "use" }, 2175 { "class": "FLAGS", "usage": "use_def" } 2176 ] 2177 }, 2178 { 2179 "encodings": { 2180 "RcllByOne": { "opcodes": [ "D1", "2" ] }, 2181 "RcrlByOne": { "opcodes": [ "D1", "3" ] } 2182 }, 2183 "args": [ 2184 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 2185 { "class": "FLAGS", "usage": "use_def" } 2186 ] 2187 }, 2188 { 2189 "encodings": { 2190 "RclwByCl": { "opcodes": [ "66", "D3", "2" ] }, 2191 "RcrwByCl": { "opcodes": [ "66", "D3", "3" ] } 2192 }, 2193 "args": [ 2194 { "class": "GeneralReg16/Mem16", "usage": "use_def" }, 2195 { "class": "CL", "usage": "use" }, 2196 { "class": "FLAGS", "usage": "use_def" } 2197 ] 2198 }, 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"C4", "03", "81", "5C" ], "vex_imm_rm_to_reg": true }, 2713 "Vfmsubaddpd": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "5F" ], "vex_imm_rm_to_reg": true }, 2714 "Vfmsubaddps": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "5E" ], "vex_imm_rm_to_reg": true }, 2715 "Vfmsubpd": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "6D" ], "vex_imm_rm_to_reg": true }, 2716 "Vfmsubps": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "6C" ], "vex_imm_rm_to_reg": true }, 2717 "Vfnmaddpd": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "79" ], "vex_imm_rm_to_reg": true }, 2718 "Vfnmaddps": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "78" ], "vex_imm_rm_to_reg": true }, 2719 "Vfnmsubpd": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "7D" ], "vex_imm_rm_to_reg": true }, 2720 "Vfnmsubps": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "7C" ], "vex_imm_rm_to_reg": true } 2721 }, 2722 "args": [ 2723 { "class": "VecReg128", "usage": "def" }, 2724 { "class": "VecReg128", "usage": "use" }, 2725 { "class": "VecReg128", "usage": "use" }, 2726 { "class": "VecReg128/VecMem128", "usage": "use" } 2727 ] 2728 }, 2729 { 2730 "encodings": { 2731 "Vfmaddsd": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "6B" ], "vex_rm_imm_to_reg": true }, 2732 "Vfmsubsd": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "6F" ], "vex_rm_imm_to_reg": true }, 2733 "Vfnmaddsd": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "7B" ], "vex_rm_imm_to_reg": true }, 2734 "Vfnmsubsd": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "7F" ], "vex_rm_imm_to_reg": true } 2735 }, 2736 "args": [ 2737 { "class": "XmmReg", "usage": "def" }, 2738 { "class": "XmmReg", "usage": "use" }, 2739 { "class": "VecMem64", "usage": "use" }, 2740 { "class": "XmmReg", "usage": "use" } 2741 ] 2742 }, 2743 { 2744 "encodings": { 2745 "Vfmaddsd": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "6B" ], "vex_imm_rm_to_reg": true }, 2746 "Vfmsubsd": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "6F" ], "vex_imm_rm_to_reg": true }, 2747 "Vfnmaddsd": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "7B" ], "vex_imm_rm_to_reg": true }, 2748 "Vfnmsubsd": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "7F" ], "vex_imm_rm_to_reg": true } 2749 }, 2750 "args": [ 2751 { "class": "XmmReg", "usage": "def" }, 2752 { "class": "XmmReg", "usage": "use" }, 2753 { "class": "XmmReg", "usage": "use" }, 2754 { "class": "XmmReg/VecMem64", "usage": "use" } 2755 ] 2756 }, 2757 { 2758 "encodings": { 2759 "Vfmaddss": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "6A" ], "vex_rm_imm_to_reg": true }, 2760 "Vfmsubss": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "6E" ], "vex_rm_imm_to_reg": true }, 2761 "Vfnmaddss": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "7A" ], "vex_rm_imm_to_reg": true }, 2762 "Vfnmsubss": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "7E" ], "vex_rm_imm_to_reg": true } 2763 }, 2764 "args": [ 2765 { "class": "XmmReg", "usage": "def" }, 2766 { "class": "XmmReg", "usage": "use" }, 2767 { "class": "VecMem32", "usage": "use" }, 2768 { "class": "XmmReg", "usage": "use" } 2769 ] 2770 }, 2771 { 2772 "encodings": { 2773 "Vfmaddss": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "6A" ], "vex_imm_rm_to_reg": true }, 2774 "Vfmsubss": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "6E" ], "vex_imm_rm_to_reg": true }, 2775 "Vfnmaddss": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "7A" ], "vex_imm_rm_to_reg": true }, 2776 "Vfnmsubss": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "7E" ], "vex_imm_rm_to_reg": true } 2777 }, 2778 "args": [ 2779 { "class": "XmmReg", "usage": "def" }, 2780 { "class": "XmmReg", "usage": "use" }, 2781 { "class": "XmmReg", "usage": "use" }, 2782 { "class": "XmmReg/VecMem32", "usage": "use" } 2783 ] 2784 }, 2785 { 2786 "encodings": { 2787 "Vmovapd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "28" ] }, 2788 "Vmovaps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "28" ] } 2789 }, 2790 "args": [ 2791 { "class": "XmmReg", "usage": "def" }, 2792 { "class": "VecMem128", "usage": "use" } 2793 ] 2794 }, 2795 { 2796 "encodings": { 2797 "Vmovdqa": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "6F" ] }, 2798 "Vmovdqu": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "6F" ] } 2799 }, 2800 "args": [ 2801 { "class": "XmmReg", "usage": "def" }, 2802 { "class": "VecMem128", "usage": "use" } 2803 ] 2804 }, 2805 { 2806 "encodings": { 2807 "Vmovhlps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "12" ], "vex_rm_to_reg": true }, 2808 "Vmovlhps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "16" ], "vex_rm_to_reg": true } 2809 }, 2810 "args": [ 2811 { "class": "XmmReg", "usage": "def" }, 2812 { "class": "XmmReg", "usage": "use" }, 2813 { "class": "XmmReg", "usage": "use" } 2814 ] 2815 }, 2816 { 2817 "encodings": { 2818 "Vmovhpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "16" ] }, 2819 "Vmovhps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "16" ] }, 2820 "Vmovlpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "12" ] }, 2821 "Vmovlps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "12" ] } 2822 }, 2823 "args": [ 2824 { "class": "XmmReg", "usage": "def" }, 2825 { "class": "XmmReg", "usage": "use" }, 2826 { "class": "VecMem64", "usage": "use" } 2827 ] 2828 }, 2829 { 2830 "encodings": { 2831 "Vpermil2pd": { "feature": "AVX", "opcodes": [ "C4", "03", "81", "49" ], "vex_imm_rm_to_reg": true }, 2832 "Vpermil2ps": { "feature": "AVX", "opcodes": [ "C4", "03", "81", "48" ], "vex_imm_rm_to_reg": true } 2833 }, 2834 "args": [ 2835 { "class": "VecReg128", "usage": "def" }, 2836 { "class": "VecReg128", "usage": "use" }, 2837 { "class": "VecReg128", "usage": "use" }, 2838 { "class": "VecMem128", "usage": "use" }, 2839 { "class": "Imm2" } 2840 ] 2841 }, 2842 { 2843 "encodings": { 2844 "Vpermil2pd": { "feature": "AVX", "opcodes": [ "C4", "03", "01", "49" ], "vex_rm_imm_to_reg": true }, 2845 "Vpermil2ps": { "feature": "AVX", "opcodes": [ "C4", "03", "01", "48" ], "vex_rm_imm_to_reg": true } 2846 }, 2847 "args": [ 2848 { "class": "VecReg128", "usage": "def" }, 2849 { "class": "VecReg128", "usage": "use" }, 2850 { "class": "VecReg128/VecMem128", "usage": "use" }, 2851 { "class": "VecReg128", "usage": "use" }, 2852 { "class": "Imm2" } 2853 ] 2854 }, 2855 { 2856 "encodings": { 2857 "Vpinsrb": { "feature": "AVX", "opcodes": [ "C4", "03", "01", "20" ], "vex_rm_to_reg": true }, 2858 "Vpinsrd": { "feature": "AVX", "opcodes": [ "C4", "03", "01", "22" ], "vex_rm_to_reg": true }, 2859 "Vpinsrw": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "C4" ], "vex_rm_to_reg": true } 2860 }, 2861 "args": [ 2862 { "class": "VecReg128", "usage": "use_def" }, 2863 { "class": "VecReg128", "usage": "use" }, 2864 { "class": "GeneralReg32", "usage": "use" }, 2865 { "class": "Imm8" } 2866 ] 2867 }, 2868 { 2869 "encodings": { 2870 "Vpslld": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "72", "6" ], "rm_to_vex": true }, 2871 "Vpslldq": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "73", "7" ], "rm_to_vex": true }, 2872 "Vpsllq": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "73", "6" ], "rm_to_vex": true }, 2873 "Vpsllw": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "71", "6" ], "rm_to_vex": true }, 2874 "Vpsrad": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "72", "4" ], "rm_to_vex": true }, 2875 "Vpsraw": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "71", "4" ], "rm_to_vex": true }, 2876 "Vpsrld": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "72", "2" ], "rm_to_vex": true }, 2877 "Vpsrldq": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "73", "3" ], "rm_to_vex": true }, 2878 "Vpsrlq": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "73", "2" ], "rm_to_vex": true }, 2879 "Vpsrlw": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "71", "2" ], "rm_to_vex": true } 2880 }, 2881 "args": [ 2882 { "class": "VecReg128", "usage": "def" }, 2883 { "class": "VecReg128", "usage": "use" }, 2884 { "class": "Imm8" } 2885 ] 2886 }, 2887 { 2888 "encodings": { 2889 "Vroundsd": { "feature": "AVX", "opcodes": [ "C4", "03", "01", "0B" ], "vex_rm_to_reg": true } 2890 }, 2891 "args": [ 2892 { "class": "FpReg64", "usage": "def" }, 2893 { "class": "XmmReg", "usage": "use" }, 2894 { "class": "FpReg64/VecMem64", "usage": "use" }, 2895 { "class": "Imm8" } 2896 ] 2897 }, 2898 { 2899 "encodings": { 2900 "Vroundss": { "feature": "AVX", "opcodes": [ "C4", "03", "01", "0A" ], "vex_rm_to_reg": true } 2901 }, 2902 "args": [ 2903 { "class": "FpReg32", "usage": "def" }, 2904 { "class": "XmmReg", "usage": "use" }, 2905 { "class": "FpReg32/VecMem32", "usage": "use" }, 2906 { "class": "Imm8" } 2907 ] 2908 }, 2909 { 2910 "encodings": { 2911 "Vshufpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "C6" ], "vex_rm_to_reg": true }, 2912 "Vshufps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "C6" ], "vex_rm_to_reg": true } 2913 }, 2914 "args": [ 2915 { "class": "VecReg128", "usage": "def" }, 2916 { "class": "VecReg128", "usage": "use" }, 2917 { "class": "VecReg128/VecMem128", "usage": "use" }, 2918 { "class": "Imm8" } 2919 ] 2920 }, 2921 { 2922 "stems": [ "Xchgl" ], 2923 "args": [ 2924 { "class": "GeneralReg32", "usage": "use_def" }, 2925 { "class": "GeneralReg32", "usage": "use_def" } 2926 ] 2927 }, 2928 { 2929 "encodings": { 2930 "Xchgl": { "opcodes": [ "87" ] } 2931 }, 2932 "args": [ 2933 { "class": "GeneralReg32", "usage": "use_def" }, 2934 { "class": "Mem32", "usage": "use_def" } 2935 ] 2936 } 2937 ] 2938 } 2939