1 /*
2  * Copyright (C) 2015 The Android Open Source Project
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  *      http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
17 #include "linker/arm64/relative_patcher_arm64.h"
18 
19 #include "arch/arm64/asm_support_arm64.h"
20 #include "arch/arm64/instruction_set_features_arm64.h"
21 #include "art_method.h"
22 #include "base/bit_utils.h"
23 #include "base/malloc_arena_pool.h"
24 #include "driver/compiled_method-inl.h"
25 #include "driver/compiler_driver.h"
26 #include "entrypoints/quick/quick_entrypoints_enum.h"
27 #include "heap_poisoning.h"
28 #include "linker/linker_patch.h"
29 #include "lock_word.h"
30 #include "mirror/array-inl.h"
31 #include "mirror/object.h"
32 #include "oat/oat.h"
33 #include "oat/oat_quick_method_header.h"
34 #include "read_barrier.h"
35 #include "stream/output_stream.h"
36 
37 namespace art {
38 namespace linker {
39 
40 namespace {
41 
42 // Maximum positive and negative displacement for method call measured from the patch location.
43 // (Signed 28 bit displacement with the last two bits 0 has range [-2^27, 2^27-4] measured from
44 // the ARM64 PC pointing to the BL.)
45 constexpr uint32_t kMaxMethodCallPositiveDisplacement = (1u << 27) - 4u;
46 constexpr uint32_t kMaxMethodCallNegativeDisplacement = (1u << 27);
47 
48 // Maximum positive and negative displacement for a conditional branch measured from the patch
49 // location. (Signed 21 bit displacement with the last two bits 0 has range [-2^20, 2^20-4]
50 // measured from the ARM64 PC pointing to the B.cond.)
51 constexpr uint32_t kMaxBcondPositiveDisplacement = (1u << 20) - 4u;
52 constexpr uint32_t kMaxBcondNegativeDisplacement = (1u << 20);
53 
54 // The ADRP thunk for erratum 843419 is 2 instructions, i.e. 8 bytes.
55 constexpr uint32_t kAdrpThunkSize = 8u;
56 
IsAdrpPatch(const LinkerPatch & patch)57 inline bool IsAdrpPatch(const LinkerPatch& patch) {
58   switch (patch.GetType()) {
59     case LinkerPatch::Type::kCallRelative:
60     case LinkerPatch::Type::kCallEntrypoint:
61     case LinkerPatch::Type::kBakerReadBarrierBranch:
62       return false;
63     case LinkerPatch::Type::kIntrinsicReference:
64     case LinkerPatch::Type::kBootImageRelRo:
65     case LinkerPatch::Type::kMethodRelative:
66     case LinkerPatch::Type::kMethodBssEntry:
67     case LinkerPatch::Type::kJniEntrypointRelative:
68     case LinkerPatch::Type::kTypeRelative:
69     case LinkerPatch::Type::kTypeAppImageRelRo:
70     case LinkerPatch::Type::kTypeBssEntry:
71     case LinkerPatch::Type::kPublicTypeBssEntry:
72     case LinkerPatch::Type::kPackageTypeBssEntry:
73     case LinkerPatch::Type::kStringRelative:
74     case LinkerPatch::Type::kStringBssEntry:
75     case LinkerPatch::Type::kMethodTypeBssEntry:
76       return patch.LiteralOffset() == patch.PcInsnOffset();
77   }
78 }
79 
MaxExtraSpace(size_t num_adrp,size_t code_size)80 inline uint32_t MaxExtraSpace(size_t num_adrp, size_t code_size) {
81   if (num_adrp == 0u) {
82     return 0u;
83   }
84   uint32_t alignment_bytes =
85       CompiledMethod::AlignCode(code_size, InstructionSet::kArm64) - code_size;
86   return kAdrpThunkSize * num_adrp + alignment_bytes;
87 }
88 
89 }  // anonymous namespace
90 
Arm64RelativePatcher(RelativePatcherThunkProvider * thunk_provider,RelativePatcherTargetProvider * target_provider,const Arm64InstructionSetFeatures * features)91 Arm64RelativePatcher::Arm64RelativePatcher(RelativePatcherThunkProvider* thunk_provider,
92                                            RelativePatcherTargetProvider* target_provider,
93                                            const Arm64InstructionSetFeatures* features)
94     : ArmBaseRelativePatcher(thunk_provider, target_provider, InstructionSet::kArm64),
95       fix_cortex_a53_843419_(features->NeedFixCortexA53_843419()),
96       reserved_adrp_thunks_(0u),
97       processed_adrp_thunks_(0u) {
98   if (fix_cortex_a53_843419_) {
99     adrp_thunk_locations_.reserve(16u);
100     current_method_thunks_.reserve(16u * kAdrpThunkSize);
101   }
102 }
103 
ReserveSpace(uint32_t offset,const CompiledMethod * compiled_method,MethodReference method_ref)104 uint32_t Arm64RelativePatcher::ReserveSpace(uint32_t offset,
105                                             const CompiledMethod* compiled_method,
106                                             MethodReference method_ref) {
107   if (!fix_cortex_a53_843419_) {
108     DCHECK(adrp_thunk_locations_.empty());
109     return ReserveSpaceInternal(offset, compiled_method, method_ref, 0u);
110   }
111 
112   // Add thunks for previous method if any.
113   if (reserved_adrp_thunks_ != adrp_thunk_locations_.size()) {
114     size_t num_adrp_thunks = adrp_thunk_locations_.size() - reserved_adrp_thunks_;
115     offset = CompiledMethod::AlignCode(offset, InstructionSet::kArm64) +
116              kAdrpThunkSize * num_adrp_thunks;
117     reserved_adrp_thunks_ = adrp_thunk_locations_.size();
118   }
119 
120   // Count the number of ADRP insns as the upper bound on the number of thunks needed
121   // and use it to reserve space for other linker patches.
122   size_t num_adrp = 0u;
123   DCHECK(compiled_method != nullptr);
124   for (const LinkerPatch& patch : compiled_method->GetPatches()) {
125     if (IsAdrpPatch(patch)) {
126       ++num_adrp;
127     }
128   }
129   ArrayRef<const uint8_t> code = compiled_method->GetQuickCode();
130   uint32_t max_extra_space = MaxExtraSpace(num_adrp, code.size());
131   offset = ReserveSpaceInternal(offset, compiled_method, method_ref, max_extra_space);
132   if (num_adrp == 0u) {
133     return offset;
134   }
135 
136   // Now that we have the actual offset where the code will be placed, locate the ADRP insns
137   // that actually require the thunk.
138   uint32_t quick_code_offset = compiled_method->AlignCode(offset + sizeof(OatQuickMethodHeader));
139   uint32_t thunk_offset = compiled_method->AlignCode(quick_code_offset + code.size());
140   DCHECK(compiled_method != nullptr);
141   for (const LinkerPatch& patch : compiled_method->GetPatches()) {
142     if (IsAdrpPatch(patch)) {
143       uint32_t patch_offset = quick_code_offset + patch.LiteralOffset();
144       if (NeedsErratum843419Thunk(code, patch.LiteralOffset(), patch_offset)) {
145         adrp_thunk_locations_.emplace_back(patch_offset, thunk_offset);
146         thunk_offset += kAdrpThunkSize;
147       }
148     }
149   }
150   return offset;
151 }
152 
ReserveSpaceEnd(uint32_t offset)153 uint32_t Arm64RelativePatcher::ReserveSpaceEnd(uint32_t offset) {
154   if (!fix_cortex_a53_843419_) {
155     DCHECK(adrp_thunk_locations_.empty());
156   } else {
157     // Add thunks for the last method if any.
158     if (reserved_adrp_thunks_ != adrp_thunk_locations_.size()) {
159       size_t num_adrp_thunks = adrp_thunk_locations_.size() - reserved_adrp_thunks_;
160       offset = CompiledMethod::AlignCode(offset, InstructionSet::kArm64) +
161                kAdrpThunkSize * num_adrp_thunks;
162       reserved_adrp_thunks_ = adrp_thunk_locations_.size();
163     }
164   }
165   return ArmBaseRelativePatcher::ReserveSpaceEnd(offset);
166 }
167 
WriteThunks(OutputStream * out,uint32_t offset)168 uint32_t Arm64RelativePatcher::WriteThunks(OutputStream* out, uint32_t offset) {
169   if (fix_cortex_a53_843419_) {
170     if (!current_method_thunks_.empty()) {
171       uint32_t aligned_offset = CompiledMethod::AlignCode(offset, InstructionSet::kArm64);
172       if (kIsDebugBuild) {
173         CHECK_ALIGNED(current_method_thunks_.size(), kAdrpThunkSize);
174         size_t num_thunks = current_method_thunks_.size() / kAdrpThunkSize;
175         CHECK_LE(num_thunks, processed_adrp_thunks_);
176         for (size_t i = 0u; i != num_thunks; ++i) {
177           const auto& entry = adrp_thunk_locations_[processed_adrp_thunks_ - num_thunks + i];
178           CHECK_EQ(entry.second, aligned_offset + i * kAdrpThunkSize);
179         }
180       }
181       uint32_t aligned_code_delta = aligned_offset - offset;
182       if (aligned_code_delta != 0u && !WriteCodeAlignment(out, aligned_code_delta)) {
183         return 0u;
184       }
185       if (!WriteMiscThunk(out, ArrayRef<const uint8_t>(current_method_thunks_))) {
186         return 0u;
187       }
188       offset = aligned_offset + current_method_thunks_.size();
189       current_method_thunks_.clear();
190     }
191   }
192   return ArmBaseRelativePatcher::WriteThunks(out, offset);
193 }
194 
PatchCall(std::vector<uint8_t> * code,uint32_t literal_offset,uint32_t patch_offset,uint32_t target_offset)195 void Arm64RelativePatcher::PatchCall(std::vector<uint8_t>* code,
196                                      uint32_t literal_offset,
197                                      uint32_t patch_offset,
198                                      uint32_t target_offset) {
199   DCHECK_ALIGNED(literal_offset, 4u);
200   DCHECK_ALIGNED(patch_offset, 4u);
201   DCHECK_ALIGNED(target_offset, 4u);
202   uint32_t displacement = CalculateMethodCallDisplacement(patch_offset, target_offset & ~1u);
203   PatchBl(code, literal_offset, displacement);
204 }
205 
PatchPcRelativeReference(std::vector<uint8_t> * code,const LinkerPatch & patch,uint32_t patch_offset,uint32_t target_offset)206 void Arm64RelativePatcher::PatchPcRelativeReference(std::vector<uint8_t>* code,
207                                                     const LinkerPatch& patch,
208                                                     uint32_t patch_offset,
209                                                     uint32_t target_offset) {
210   DCHECK_ALIGNED(patch_offset, 4u);
211   DCHECK_ALIGNED(target_offset, 4u);
212   uint32_t literal_offset = patch.LiteralOffset();
213   uint32_t insn = GetInsn(code, literal_offset);
214   uint32_t pc_insn_offset = patch.PcInsnOffset();
215   uint32_t disp = target_offset - ((patch_offset - literal_offset + pc_insn_offset) & ~0xfffu);
216   bool wide = (insn & 0x40000000) != 0;
217   uint32_t shift = wide ? 3u : 2u;
218   if (literal_offset == pc_insn_offset) {
219     // Check it's an ADRP with imm == 0 (unset).
220     DCHECK_EQ((insn & 0xffffffe0u), 0x90000000u)
221         << literal_offset << ", " << pc_insn_offset << ", 0x" << std::hex << insn;
222     if (fix_cortex_a53_843419_ && processed_adrp_thunks_ != adrp_thunk_locations_.size() &&
223         adrp_thunk_locations_[processed_adrp_thunks_].first == patch_offset) {
224       DCHECK(NeedsErratum843419Thunk(ArrayRef<const uint8_t>(*code),
225                                      literal_offset, patch_offset));
226       uint32_t thunk_offset = adrp_thunk_locations_[processed_adrp_thunks_].second;
227       uint32_t adrp_disp = target_offset - (thunk_offset & ~0xfffu);
228       uint32_t adrp = PatchAdrp(insn, adrp_disp);
229 
230       uint32_t out_disp = thunk_offset - patch_offset;
231       DCHECK_EQ(out_disp & 3u, 0u);
232       DCHECK((out_disp >> 27) == 0u || (out_disp >> 27) == 31u);  // 28-bit signed.
233       insn = (out_disp & 0x0fffffffu) >> shift;
234       insn |= 0x14000000;  // B <thunk>
235 
236       uint32_t back_disp = -out_disp;
237       DCHECK_EQ(back_disp & 3u, 0u);
238       DCHECK((back_disp >> 27) == 0u || (back_disp >> 27) == 31u);  // 28-bit signed.
239       uint32_t b_back = (back_disp & 0x0fffffffu) >> 2;
240       b_back |= 0x14000000;  // B <back>
241       size_t thunks_code_offset = current_method_thunks_.size();
242       current_method_thunks_.resize(thunks_code_offset + kAdrpThunkSize);
243       SetInsn(&current_method_thunks_, thunks_code_offset, adrp);
244       SetInsn(&current_method_thunks_, thunks_code_offset + 4u, b_back);
245       static_assert(kAdrpThunkSize == 2 * 4u, "thunk has 2 instructions");
246 
247       processed_adrp_thunks_ += 1u;
248     } else {
249       insn = PatchAdrp(insn, disp);
250     }
251     // Write the new ADRP (or B to the erratum 843419 thunk).
252     SetInsn(code, literal_offset, insn);
253   } else {
254     if ((insn & 0xfffffc00) == 0x91000000) {
255       // ADD immediate, 64-bit with imm12 == 0 (unset).
256       if (kUseBakerReadBarrier) {
257         DCHECK(patch.GetType() == LinkerPatch::Type::kIntrinsicReference ||
258                patch.GetType() == LinkerPatch::Type::kMethodRelative ||
259                patch.GetType() == LinkerPatch::Type::kTypeRelative ||
260                patch.GetType() == LinkerPatch::Type::kStringRelative) << patch.GetType();
261       } else {
262         // With the read barrier (non-Baker) enabled, it could be kStringBssEntry or k*TypeBssEntry.
263         DCHECK(patch.GetType() == LinkerPatch::Type::kIntrinsicReference ||
264                patch.GetType() == LinkerPatch::Type::kMethodRelative ||
265                patch.GetType() == LinkerPatch::Type::kTypeRelative ||
266                patch.GetType() == LinkerPatch::Type::kStringRelative ||
267                patch.GetType() == LinkerPatch::Type::kTypeBssEntry ||
268                patch.GetType() == LinkerPatch::Type::kPublicTypeBssEntry ||
269                patch.GetType() == LinkerPatch::Type::kPackageTypeBssEntry ||
270                patch.GetType() == LinkerPatch::Type::kStringBssEntry) << patch.GetType();
271       }
272       shift = 0u;  // No shift for ADD.
273     } else {
274       // LDR/STR 32-bit or 64-bit with imm12 == 0 (unset).
275       DCHECK(patch.GetType() == LinkerPatch::Type::kBootImageRelRo ||
276              patch.GetType() == LinkerPatch::Type::kMethodBssEntry ||
277              patch.GetType() == LinkerPatch::Type::kJniEntrypointRelative ||
278              patch.GetType() == LinkerPatch::Type::kTypeAppImageRelRo ||
279              patch.GetType() == LinkerPatch::Type::kTypeBssEntry ||
280              patch.GetType() == LinkerPatch::Type::kPublicTypeBssEntry ||
281              patch.GetType() == LinkerPatch::Type::kPackageTypeBssEntry ||
282              patch.GetType() == LinkerPatch::Type::kStringBssEntry) << patch.GetType();
283       DCHECK_EQ(insn & 0xbfbffc00, 0xb9000000) << std::hex << insn;
284     }
285     if (kIsDebugBuild) {
286       uint32_t adrp = GetInsn(code, pc_insn_offset);
287       if ((adrp & 0x9f000000u) != 0x90000000u) {
288         CHECK(fix_cortex_a53_843419_);
289         CHECK_EQ(adrp & 0xfc000000u, 0x14000000u);  // B <thunk>
290         CHECK_ALIGNED(current_method_thunks_.size(), kAdrpThunkSize);
291         size_t num_thunks = current_method_thunks_.size() / kAdrpThunkSize;
292         CHECK_LE(num_thunks, processed_adrp_thunks_);
293         uint32_t b_offset = patch_offset - literal_offset + pc_insn_offset;
294         for (size_t i = processed_adrp_thunks_ - num_thunks; ; ++i) {
295           CHECK_NE(i, processed_adrp_thunks_);
296           if (adrp_thunk_locations_[i].first == b_offset) {
297             size_t idx = num_thunks - (processed_adrp_thunks_ - i);
298             adrp = GetInsn(&current_method_thunks_, idx * kAdrpThunkSize);
299             break;
300           }
301         }
302       }
303       CHECK_EQ(adrp & 0x9f00001fu,                    // Check that pc_insn_offset points
304                0x90000000 | ((insn >> 5) & 0x1fu));   // to ADRP with matching register.
305     }
306     uint32_t imm12 = (disp & 0xfffu) >> shift;
307     insn = (insn & ~(0xfffu << 10)) | (imm12 << 10);
308     SetInsn(code, literal_offset, insn);
309   }
310 }
311 
PatchEntrypointCall(std::vector<uint8_t> * code,const LinkerPatch & patch,uint32_t patch_offset)312 void Arm64RelativePatcher::PatchEntrypointCall(std::vector<uint8_t>* code,
313                                                const LinkerPatch& patch,
314                                                uint32_t patch_offset) {
315   DCHECK_ALIGNED(patch_offset, 4u);
316   ThunkKey key = GetEntrypointCallKey(patch);
317   uint32_t target_offset = GetThunkTargetOffset(key, patch_offset);
318   uint32_t displacement = target_offset - patch_offset;
319   PatchBl(code, patch.LiteralOffset(), displacement);
320 }
321 
PatchBakerReadBarrierBranch(std::vector<uint8_t> * code,const LinkerPatch & patch,uint32_t patch_offset)322 void Arm64RelativePatcher::PatchBakerReadBarrierBranch(std::vector<uint8_t>* code,
323                                                        const LinkerPatch& patch,
324                                                        uint32_t patch_offset) {
325   DCHECK_ALIGNED(patch_offset, 4u);
326   uint32_t literal_offset = patch.LiteralOffset();
327   uint32_t insn = GetInsn(code, literal_offset);
328   DCHECK_EQ(insn & 0xffffffe0u, 0xb5000000);  // CBNZ Xt, +0 (unpatched)
329   ThunkKey key = GetBakerThunkKey(patch);
330   uint32_t target_offset = GetThunkTargetOffset(key, patch_offset);
331   DCHECK_ALIGNED(target_offset, 4u);
332   uint32_t disp = target_offset - patch_offset;
333   DCHECK((disp >> 20) == 0u || (disp >> 20) == 4095u);  // 21-bit signed.
334   insn |= (disp << (5 - 2)) & 0x00ffffe0u;              // Shift bits 2-20 to 5-23.
335   SetInsn(code, literal_offset, insn);
336 }
337 
MaxPositiveDisplacement(const ThunkKey & key)338 uint32_t Arm64RelativePatcher::MaxPositiveDisplacement(const ThunkKey& key) {
339   switch (key.GetType()) {
340     case ThunkType::kMethodCall:
341     case ThunkType::kEntrypointCall:
342       return kMaxMethodCallPositiveDisplacement;
343     case ThunkType::kBakerReadBarrier:
344       return kMaxBcondPositiveDisplacement;
345   }
346 }
347 
MaxNegativeDisplacement(const ThunkKey & key)348 uint32_t Arm64RelativePatcher::MaxNegativeDisplacement(const ThunkKey& key) {
349   switch (key.GetType()) {
350     case ThunkType::kMethodCall:
351     case ThunkType::kEntrypointCall:
352       return kMaxMethodCallNegativeDisplacement;
353     case ThunkType::kBakerReadBarrier:
354       return kMaxBcondNegativeDisplacement;
355   }
356 }
357 
PatchAdrp(uint32_t adrp,uint32_t disp)358 uint32_t Arm64RelativePatcher::PatchAdrp(uint32_t adrp, uint32_t disp) {
359   return (adrp & 0x9f00001fu) |  // Clear offset bits, keep ADRP with destination reg.
360       // Bottom 12 bits are ignored, the next 2 lowest bits are encoded in bits 29-30.
361       ((disp & 0x00003000u) << (29 - 12)) |
362       // The next 16 bits are encoded in bits 5-22.
363       ((disp & 0xffffc000u) >> (12 + 2 - 5)) |
364       // Since the target_offset is based on the beginning of the oat file and the
365       // image space precedes the oat file, the target_offset into image space will
366       // be negative yet passed as uint32_t. Therefore we limit the displacement
367       // to +-2GiB (rather than the maximim +-4GiB) and determine the sign bit from
368       // the highest bit of the displacement. This is encoded in bit 23.
369       ((disp & 0x80000000u) >> (31 - 23));
370 }
371 
PatchBl(std::vector<uint8_t> * code,uint32_t literal_offset,uint32_t displacement)372 void Arm64RelativePatcher::PatchBl(std::vector<uint8_t>* code,
373                                    uint32_t literal_offset,
374                                    uint32_t displacement) {
375   DCHECK_ALIGNED(displacement, 4u);
376   DCHECK((displacement >> 27) == 0u || (displacement >> 27) == 31u);  // 28-bit signed.
377   uint32_t insn = (displacement & 0x0fffffffu) >> 2;
378   insn |= 0x94000000;  // BL
379 
380   // Check that we're just overwriting an existing BL.
381   DCHECK_EQ(GetInsn(code, literal_offset) & 0xfc000000u, 0x94000000u);
382   // Write the new BL.
383   SetInsn(code, literal_offset, insn);
384 }
385 
NeedsErratum843419Thunk(ArrayRef<const uint8_t> code,uint32_t literal_offset,uint32_t patch_offset)386 bool Arm64RelativePatcher::NeedsErratum843419Thunk(ArrayRef<const uint8_t> code,
387                                                    uint32_t literal_offset,
388                                                    uint32_t patch_offset) {
389   DCHECK_EQ(patch_offset & 0x3u, 0u);
390   if ((patch_offset & 0xff8) == 0xff8) {  // ...ff8 or ...ffc
391     uint32_t adrp = GetInsn(code, literal_offset);
392     DCHECK_EQ(adrp & 0x9f000000, 0x90000000);
393     uint32_t next_offset = patch_offset + 4u;
394     uint32_t next_insn = GetInsn(code, literal_offset + 4u);
395 
396     // Below we avoid patching sequences where the adrp is followed by a load which can easily
397     // be proved to be aligned.
398 
399     // First check if the next insn is the LDR using the result of the ADRP.
400     // LDR <Wt>, [<Xn>, #pimm], where <Xn> == ADRP destination reg.
401     if ((next_insn & 0xffc00000) == 0xb9400000 &&
402         (((next_insn >> 5) ^ adrp) & 0x1f) == 0) {
403       return false;
404     }
405 
406     // And since LinkerPatch::Type::k{Method,Type,String}Relative is using the result
407     // of the ADRP for an ADD immediate, check for that as well. We generalize a bit
408     // to include ADD/ADDS/SUB/SUBS immediate that either uses the ADRP destination
409     // or stores the result to a different register.
410     if ((next_insn & 0x1f000000) == 0x11000000 &&
411         ((((next_insn >> 5) ^ adrp) & 0x1f) == 0 || ((next_insn ^ adrp) & 0x1f) != 0)) {
412       return false;
413     }
414 
415     // LDR <Wt>, <label> is always aligned and thus it doesn't cause boundary crossing.
416     if ((next_insn & 0xff000000) == 0x18000000) {
417       return false;
418     }
419 
420     // LDR <Xt>, <label> is aligned iff the pc + displacement is a multiple of 8.
421     if ((next_insn & 0xff000000) == 0x58000000) {
422       bool is_aligned_load = (((next_offset >> 2) ^ (next_insn >> 5)) & 1) == 0;
423       return !is_aligned_load;
424     }
425 
426     // LDR <Wt>, [SP, #<pimm>] and LDR <Xt>, [SP, #<pimm>] are always aligned loads, as SP is
427     // guaranteed to be 128-bits aligned and <pimm> is multiple of the load size.
428     if ((next_insn & 0xbfc003e0) == 0xb94003e0) {
429       return false;
430     }
431     return true;
432   }
433   return false;
434 }
435 
SetInsn(std::vector<uint8_t> * code,uint32_t offset,uint32_t value)436 void Arm64RelativePatcher::SetInsn(std::vector<uint8_t>* code, uint32_t offset, uint32_t value) {
437   DCHECK_LE(offset + 4u, code->size());
438   DCHECK_ALIGNED(offset, 4u);
439   uint8_t* addr = &(*code)[offset];
440   addr[0] = (value >> 0) & 0xff;
441   addr[1] = (value >> 8) & 0xff;
442   addr[2] = (value >> 16) & 0xff;
443   addr[3] = (value >> 24) & 0xff;
444 }
445 
GetInsn(ArrayRef<const uint8_t> code,uint32_t offset)446 uint32_t Arm64RelativePatcher::GetInsn(ArrayRef<const uint8_t> code, uint32_t offset) {
447   DCHECK_LE(offset + 4u, code.size());
448   DCHECK_ALIGNED(offset, 4u);
449   const uint8_t* addr = &code[offset];
450   return
451       (static_cast<uint32_t>(addr[0]) << 0) +
452       (static_cast<uint32_t>(addr[1]) << 8) +
453       (static_cast<uint32_t>(addr[2]) << 16)+
454       (static_cast<uint32_t>(addr[3]) << 24);
455 }
456 
457 template <typename Alloc>
GetInsn(std::vector<uint8_t,Alloc> * code,uint32_t offset)458 uint32_t Arm64RelativePatcher::GetInsn(std::vector<uint8_t, Alloc>* code, uint32_t offset) {
459   return GetInsn(ArrayRef<const uint8_t>(*code), offset);
460 }
461 
462 }  // namespace linker
463 }  // namespace art
464