1 // Copyright 2023, The Android Open Source Project
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 //! Utility functions for memory management.
16
17 use crate::read_sysreg;
18 use crate::util::unchecked_align_down;
19 use core::arch::asm;
20 use core::ptr::NonNull;
21 use zeroize::Zeroize;
22
23 /// The size of a 4KB memory in bytes.
24 pub const SIZE_4KB: usize = 4 << 10;
25 /// The size of a 16KB memory in bytes.
26 pub const SIZE_16KB: usize = 16 << 10;
27 /// The size of a 64KB memory in bytes.
28 pub const SIZE_64KB: usize = 64 << 10;
29 /// The size of a 128KB memory in bytes.
30 pub const SIZE_128KB: usize = 128 << 10;
31 /// The size of a 2MB memory in bytes.
32 pub const SIZE_2MB: usize = 2 << 20;
33 /// The size of a 4MB memory in bytes.
34 pub const SIZE_4MB: usize = 4 << 20;
35
36 /// The page size in bytes assumed by vmbase - 4 KiB.
37 pub const PAGE_SIZE: usize = SIZE_4KB;
38
39 /// Reads the number of words in the smallest cache line of all the data caches and unified caches.
40 #[inline]
min_dcache_line_size() -> usize41 pub fn min_dcache_line_size() -> usize {
42 const DMINLINE_SHIFT: usize = 16;
43 const DMINLINE_MASK: usize = 0xf;
44 let ctr_el0 = read_sysreg!("ctr_el0");
45
46 // DminLine: log2 of the number of words in the smallest cache line of all the data caches.
47 let dminline = (ctr_el0 >> DMINLINE_SHIFT) & DMINLINE_MASK;
48
49 1 << dminline
50 }
51
52 /// Flush `size` bytes of data cache by virtual address.
53 #[inline]
flush_region(start: usize, size: usize)54 pub(super) fn flush_region(start: usize, size: usize) {
55 let line_size = min_dcache_line_size();
56 let end = start + size;
57 let start = unchecked_align_down(start, line_size);
58
59 for line in (start..end).step_by(line_size) {
60 // SAFETY: Clearing cache lines shouldn't have Rust-visible side effects.
61 unsafe {
62 asm!(
63 "dc cvau, {x}",
64 x = in(reg) line,
65 options(nomem, nostack, preserves_flags),
66 )
67 }
68 }
69 }
70
71 /// Flushes the slice to the point of unification.
72 #[inline]
flush(reg: &[u8])73 pub fn flush(reg: &[u8]) {
74 flush_region(reg.as_ptr() as usize, reg.len())
75 }
76
77 /// Overwrites the slice with zeroes, to the point of unification.
78 #[inline]
flushed_zeroize(reg: &mut [u8])79 pub fn flushed_zeroize(reg: &mut [u8]) {
80 reg.zeroize();
81 flush(reg)
82 }
83
84 /// Computes the address of the 4KiB page containing a given address.
page_4kb_of(addr: usize) -> usize85 pub const fn page_4kb_of(addr: usize) -> usize {
86 unchecked_align_down(addr, SIZE_4KB)
87 }
88
89 /// Returns the intermediate physical address corresponding to the given virtual address.
90 ///
91 /// As we use identity mapping for everything, this is just a cast, but it's useful to use it to be
92 /// explicit about where we are converting from virtual to physical address.
virt_to_phys(vaddr: NonNull<u8>) -> usize93 pub(crate) fn virt_to_phys(vaddr: NonNull<u8>) -> usize {
94 vaddr.as_ptr() as _
95 }
96
97 /// Returns a pointer for the virtual address corresponding to the given non-zero intermediate
98 /// physical address.
99 ///
100 /// Panics if `paddr` is 0.
phys_to_virt(paddr: usize) -> NonNull<u8>101 pub(crate) fn phys_to_virt(paddr: usize) -> NonNull<u8> {
102 NonNull::new(paddr as _).unwrap()
103 }
104