1 /* 2 * Copyright (C) 2014 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef ART_RUNTIME_ARCH_ARM64_REGISTERS_ARM64_H_ 18 #define ART_RUNTIME_ARCH_ARM64_REGISTERS_ARM64_H_ 19 20 #include <iosfwd> 21 22 #include "base/macros.h" 23 24 namespace art HIDDEN { 25 namespace arm64 { 26 27 // Values for GP XRegisters - 64bit registers. 28 enum XRegister { 29 X0 = 0, 30 X1 = 1, 31 X2 = 2, 32 X3 = 3, 33 X4 = 4, 34 X5 = 5, 35 X6 = 6, 36 X7 = 7, 37 X8 = 8, 38 X9 = 9, 39 X10 = 10, 40 X11 = 11, 41 X12 = 12, 42 X13 = 13, 43 X14 = 14, 44 X15 = 15, 45 X16 = 16, 46 X17 = 17, 47 X18 = 18, 48 X19 = 19, 49 X20 = 20, 50 X21 = 21, 51 X22 = 22, 52 X23 = 23, 53 X24 = 24, 54 X25 = 25, 55 X26 = 26, 56 X27 = 27, 57 X28 = 28, 58 X29 = 29, 59 X30 = 30, 60 SP = 31, // SP and XZR are encoded in instructions using the register 61 XZR = 32, // code `31`, the context deciding which is used. We use a 62 // different enum value to distinguish between the two. 63 kNumberOfXRegisters = 33, 64 // Aliases. 65 TR = X19, // ART Thread Register - Managed Runtime (Callee Saved Reg) 66 MR = X20, // ART Marking Register - Managed Runtime (Callee Saved Reg) 67 IP0 = X16, // Used as scratch by VIXL. 68 IP1 = X17, // Used as scratch by ART JNI Assembler. 69 FP = X29, 70 LR = X30, 71 kNoRegister = -1, 72 }; 73 std::ostream& operator<<(std::ostream& os, const XRegister& rhs); 74 75 // Values for GP WRegisters - 32bit registers. 76 enum WRegister { 77 W0 = 0, 78 W1 = 1, 79 W2 = 2, 80 W3 = 3, 81 W4 = 4, 82 W5 = 5, 83 W6 = 6, 84 W7 = 7, 85 W8 = 8, 86 W9 = 9, 87 W10 = 10, 88 W11 = 11, 89 W12 = 12, 90 W13 = 13, 91 W14 = 14, 92 W15 = 15, 93 W16 = 16, 94 W17 = 17, 95 W18 = 18, 96 W19 = 19, 97 W20 = 20, 98 W21 = 21, 99 W22 = 22, 100 W23 = 23, 101 W24 = 24, 102 W25 = 25, 103 W26 = 26, 104 W27 = 27, 105 W28 = 28, 106 W29 = 29, 107 W30 = 30, 108 WSP = 31, 109 WZR = 32, 110 kNumberOfWRegisters = 33, 111 kNoWRegister = -1, 112 }; 113 std::ostream& operator<<(std::ostream& os, const WRegister& rhs); 114 115 // Values for FP DRegisters - double precision floating point. 116 enum DRegister { 117 D0 = 0, 118 D1 = 1, 119 D2 = 2, 120 D3 = 3, 121 D4 = 4, 122 D5 = 5, 123 D6 = 6, 124 D7 = 7, 125 D8 = 8, 126 D9 = 9, 127 D10 = 10, 128 D11 = 11, 129 D12 = 12, 130 D13 = 13, 131 D14 = 14, 132 D15 = 15, 133 D16 = 16, 134 D17 = 17, 135 D18 = 18, 136 D19 = 19, 137 D20 = 20, 138 D21 = 21, 139 D22 = 22, 140 D23 = 23, 141 D24 = 24, 142 D25 = 25, 143 D26 = 26, 144 D27 = 27, 145 D28 = 28, 146 D29 = 29, 147 D30 = 30, 148 D31 = 31, 149 kNumberOfDRegisters = 32, 150 kNoDRegister = -1, 151 }; 152 std::ostream& operator<<(std::ostream& os, const DRegister& rhs); 153 154 // Values for FP SRegisters - single precision floating point. 155 enum SRegister { 156 S0 = 0, 157 S1 = 1, 158 S2 = 2, 159 S3 = 3, 160 S4 = 4, 161 S5 = 5, 162 S6 = 6, 163 S7 = 7, 164 S8 = 8, 165 S9 = 9, 166 S10 = 10, 167 S11 = 11, 168 S12 = 12, 169 S13 = 13, 170 S14 = 14, 171 S15 = 15, 172 S16 = 16, 173 S17 = 17, 174 S18 = 18, 175 S19 = 19, 176 S20 = 20, 177 S21 = 21, 178 S22 = 22, 179 S23 = 23, 180 S24 = 24, 181 S25 = 25, 182 S26 = 26, 183 S27 = 27, 184 S28 = 28, 185 S29 = 29, 186 S30 = 30, 187 S31 = 31, 188 kNumberOfSRegisters = 32, 189 kNoSRegister = -1, 190 }; 191 std::ostream& operator<<(std::ostream& os, const SRegister& rhs); 192 193 } // namespace arm64 194 } // namespace art 195 196 #endif // ART_RUNTIME_ARCH_ARM64_REGISTERS_ARM64_H_ 197