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Searched defs:reg (Results 1 – 25 of 118) sorted by relevance

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/art/compiler/debug/
Delf_debug_frame_writer.h50 for (int reg = 0; reg < 13; reg++) { in WriteCIE() local
58 for (int reg = 0; reg < 32; reg++) { in WriteCIE() local
73 for (int reg = 0; reg < 30; reg++) { in WriteCIE() local
81 for (int reg = 0; reg < 32; reg++) { in WriteCIE() local
96 for (int reg = 3; reg < 32; reg++) { // Skip X0 (Zero), X1 (RA) and X2 (SP). in WriteCIE() local
104 for (int reg = 0; reg < 32; reg++) { in WriteCIE() local
122 for (int reg = 0; reg < 8; reg++) { in WriteCIE() local
133 for (int reg = 0; reg < 8; reg++) { in WriteCIE() local
146 for (int reg = 0; reg < 16; reg++) { in WriteCIE() local
156 for (int reg = 0; reg < 16; reg++) { in WriteCIE() local
/art/libelffile/dwarf/
Ddebug_frame_opcode_writer.h73 void ALWAYS_INLINE RelOffset(Reg reg, int offset) { in RelOffset()
119 void ALWAYS_INLINE Offset(Reg reg, int offset) { in Offset()
141 void ALWAYS_INLINE Restore(Reg reg) { in Restore()
153 void ALWAYS_INLINE Undefined(Reg reg) { in Undefined()
161 void ALWAYS_INLINE SameValue(Reg reg) { in SameValue()
170 void ALWAYS_INLINE Register(Reg reg, Reg new_reg) { in Register()
193 void ALWAYS_INLINE DefCFA(Reg reg, int offset) { in DefCFA()
210 void ALWAYS_INLINE DefCFARegister(Reg reg) { in DefCFARegister()
236 void ALWAYS_INLINE ValOffset(Reg reg, int offset) { in ValOffset()
263 void ALWAYS_INLINE Expression(Reg reg, uint8_t* expr, int expr_size) { in Expression()
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/art/compiler/utils/x86_64/
Dmanaged_register_x86_64_test.cc26 X86_64ManagedRegister reg = ManagedRegister::NoRegister().AsX86(); in TEST() local
32 X86_64ManagedRegister reg = X86_64ManagedRegister::FromCpuRegister(RAX); in TEST() local
66 X86_64ManagedRegister reg = X86_64ManagedRegister::FromXmmRegister(XMM0); in TEST() local
92 X86_64ManagedRegister reg = X86_64ManagedRegister::FromX87Register(ST0); in TEST() local
118 X86_64ManagedRegister reg = X86_64ManagedRegister::FromRegisterPair(EAX_EDX); in TEST() local
256 X86_64ManagedRegister reg = X86_64ManagedRegister::FromCpuRegister(RAX); in TEST() local
Dassembler_x86_64.h130 bool IsRegister(CpuRegister reg) const { in IsRegister()
196 explicit Operand(CpuRegister reg) : rex_(0), length_(0), fixup_(nullptr) { SetModRM(3, reg); } in Operand()
1000 void LockCmpxchgb(const Address& address, CpuRegister reg) { in LockCmpxchgb()
1004 void LockCmpxchgw(const Address& address, CpuRegister reg) { in LockCmpxchgw()
1016 void LockCmpxchgl(const Address& address, CpuRegister reg) { in LockCmpxchgl()
1020 void LockCmpxchgq(const Address& address, CpuRegister reg) { in LockCmpxchgq()
1024 void LockXaddb(const Address& address, CpuRegister reg) { in LockXaddb()
1028 void LockXaddw(const Address& address, CpuRegister reg) { in LockXaddw()
1040 void LockXaddl(const Address& address, CpuRegister reg) { in LockXaddl()
1044 void LockXaddq(const Address& address, CpuRegister reg) { in LockXaddq()
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Dmanaged_register_x86_64.cc40 RegisterPair reg; // Used to verify that the enum is in sync. member
52 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg) { in operator <<()
109 std::ostream& operator<<(std::ostream& os, const X86_64ManagedRegister& reg) { in operator <<()
/art/compiler/utils/x86/
Dmanaged_register_x86_test.cc27 X86ManagedRegister reg = ManagedRegister::NoRegister().AsX86(); in TEST() local
33 X86ManagedRegister reg = X86ManagedRegister::FromCpuRegister(EAX); in TEST() local
67 X86ManagedRegister reg = X86ManagedRegister::FromXmmRegister(XMM0); in TEST() local
93 X86ManagedRegister reg = X86ManagedRegister::FromX87Register(ST0); in TEST() local
119 X86ManagedRegister reg = X86ManagedRegister::FromRegisterPair(EAX_EDX); in TEST() local
257 X86ManagedRegister reg = X86ManagedRegister::FromCpuRegister(EAX); in TEST() local
Dassembler_x86.h92 bool IsRegister(Register reg) const { in IsRegister()
152 explicit Operand(Register reg) : disp_(0), fixup_(nullptr) { SetModRM(3, reg); } in Operand()
903 void cmpxchgb(const Address& address, Register reg) { in cmpxchgb()
908 void LockCmpxchgb(const Address& address, Register reg) { in LockCmpxchgb()
912 void LockCmpxchgb(const Address& address, ByteRegister reg) { in LockCmpxchgb()
916 void LockCmpxchgw(const Address& address, Register reg) { in LockCmpxchgw()
927 void LockCmpxchgl(const Address& address, Register reg) { in LockCmpxchgl()
936 void LockXaddb(const Address& address, Register reg) { in LockXaddb()
940 void LockXaddb(const Address& address, ByteRegister reg) { in LockXaddb()
944 void LockXaddw(const Address& address, Register reg) { in LockXaddw()
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Dmanaged_register_x86.cc41 RegisterPair reg; // Used to verify that the enum is in sync. member
53 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg) { in operator <<()
114 std::ostream& operator<<(std::ostream& os, const X86ManagedRegister& reg) { in operator <<()
/art/runtime/arch/arm/
Dcontext_arm.h57 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR()
62 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress()
67 uintptr_t GetGPR(uint32_t reg) override { in GetGPR()
75 bool IsAccessibleFPR(uint32_t reg) override { in IsAccessibleFPR()
80 uintptr_t GetFPR(uint32_t reg) override { in GetFPR()
Dcontext_arm.cc61 void ArmContext::SetGPR(uint32_t reg, uintptr_t value) { in SetGPR()
68 void ArmContext::SetFPR(uint32_t reg, uintptr_t value) { in SetFPR()
/art/runtime/arch/x86_64/
Dcontext_x86_64.h56 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR()
61 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress()
66 uintptr_t GetGPR(uint32_t reg) override { in GetGPR()
74 bool IsAccessibleFPR(uint32_t reg) override { in IsAccessibleFPR()
79 uintptr_t GetFPR(uint32_t reg) override { in GetFPR()
Dasm_support_x86_64.S76 #define CFI_DEF_CFA(reg,size) .cfi_def_cfa reg,size argument
77 #define CFI_DEF_CFA_REGISTER(reg) .cfi_def_cfa_register reg argument
78 #define CFI_RESTORE(reg) .cfi_restore reg argument
79 #define CFI_REL_OFFSET(reg,size) .cfi_rel_offset reg,size argument
96 #define CFI_DEF_CFA(reg,size) argument
97 #define CFI_DEF_CFA_REGISTER(reg) argument
98 #define CFI_RESTORE(reg) argument
99 #define CFI_REL_OFFSET(reg,size) argument
127 #define CFI_REG(reg) CFI_REG_##reg argument
/art/runtime/arch/arm64/
Dcontext_arm64.h57 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR()
62 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress()
67 uintptr_t GetGPR(uint32_t reg) override { in GetGPR()
76 bool IsAccessibleFPR(uint32_t reg) override { in IsAccessibleFPR()
81 uintptr_t GetFPR(uint32_t reg) override { in GetFPR()
/art/runtime/arch/riscv64/
Dcontext_riscv64.h49 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR()
54 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress()
59 uintptr_t GetGPR(uint32_t reg) override { in GetGPR()
68 bool IsAccessibleFPR(uint32_t reg) override { in IsAccessibleFPR()
73 uintptr_t GetFPR(uint32_t reg) override { in GetFPR()
Dcontext_riscv64.cc66 void Riscv64Context::SetGPR(uint32_t reg, uintptr_t value) { in SetGPR()
74 void Riscv64Context::SetFPR(uint32_t reg, uintptr_t value) { in SetFPR()
/art/compiler/utils/arm/
Dmanaged_register_arm_test.cc26 ArmManagedRegister reg = ManagedRegister::NoRegister().AsArm(); in TEST() local
32 ArmManagedRegister reg = ArmManagedRegister::FromCoreRegister(R0); in TEST() local
70 ArmManagedRegister reg = ArmManagedRegister::FromSRegister(S0); in TEST() local
127 ArmManagedRegister reg = ArmManagedRegister::FromDRegister(D0); in TEST() local
228 ArmManagedRegister reg = ArmManagedRegister::FromRegisterPair(R0_R1); in TEST() local
460 ArmManagedRegister reg = ArmManagedRegister::FromCoreRegister(R0); in TEST() local
/art/compiler/utils/arm64/
Dmanaged_register_arm64_test.cc28 Arm64ManagedRegister reg = ManagedRegister::NoRegister().AsArm64(); in TEST() local
35 Arm64ManagedRegister reg = Arm64ManagedRegister::FromXRegister(X0); in TEST() local
108 Arm64ManagedRegister reg = Arm64ManagedRegister::FromWRegister(W0); in TEST() local
170 Arm64ManagedRegister reg = Arm64ManagedRegister::FromDRegister(D0); in TEST() local
221 Arm64ManagedRegister reg = Arm64ManagedRegister::FromSRegister(S0); in TEST() local
377 Arm64ManagedRegister reg = Arm64ManagedRegister::FromXRegister(X0); in TEST() local
/art/runtime/arch/x86/
Dcontext_x86.h56 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR()
61 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress()
66 uintptr_t GetGPR(uint32_t reg) override { in GetGPR()
74 bool IsAccessibleFPR(uint32_t reg) override { in IsAccessibleFPR()
79 uintptr_t GetFPR(uint32_t reg) override { in GetFPR()
Dasm_support_x86.S77 #define CFI_DEF_CFA(reg,size) .cfi_def_cfa reg,size argument
78 #define CFI_DEF_CFA_REGISTER(reg) .cfi_def_cfa_register reg argument
79 #define CFI_RESTORE(reg) .cfi_restore reg argument
80 #define CFI_REL_OFFSET(reg,size) .cfi_rel_offset reg,size argument
98 #define CFI_DEF_CFA(reg,size) argument
99 #define CFI_DEF_CFA_REGISTER(reg) argument
100 #define CFI_RESTORE(reg) argument
101 #define CFI_REL_OFFSET(reg,size) argument
120 #define CFI_REG(reg) CFI_REG_##reg argument
/art/compiler/utils/riscv64/
Dmanaged_register_riscv64_test.cc26 Riscv64ManagedRegister reg = ManagedRegister::NoRegister().AsRiscv64(); in TEST() local
31 Riscv64ManagedRegister reg = Riscv64ManagedRegister::FromXRegister(Zero); in TEST() local
99 Riscv64ManagedRegister reg = Riscv64ManagedRegister::FromFRegister(FT0); in TEST() local
/art/runtime/interpreter/
Dcfi_asm_support.h48 #define CFI_DEF_CFA_BREG_PLUS_UCONST_1_1(reg, offset, size) .cfi_escape \ argument
54 #define CFI_DEF_CFA_BREG_PLUS_UCONST_1_2(reg, offset, size) .cfi_escape \ argument
80 #define CFI_DEF_CFA_BREG_PLUS_UCONST_1_1(reg, offset, size) argument
81 #define CFI_DEF_CFA_BREG_PLUS_UCONST_1_2(reg, offset, size) argument
/art/runtime/verifier/
Dregister_line.h371 const uint32_t reg = pair.first; in IterateRegToLockDepths() local
392 bool IsSetLockDepth(size_t reg, size_t depth) { in IsSetLockDepth()
401 bool SetRegToLockDepth(size_t reg, size_t depth) { in SetRegToLockDepth()
417 void ClearAllRegToLockDepths(size_t reg) { in ClearAllRegToLockDepths()
/art/compiler/optimizing/
Dregister_allocator_linear_scan.cc38 static int GetHighForLowRegister(int reg) { return reg + 1; } in GetHighForLowRegister()
39 static bool IsLowRegister(int reg) { return (reg & 1) == 0; } in IsLowRegister()
133 int reg = location.reg(); in BlockRegister() local
717 for (uint32_t reg : LowToHighBits(register_mask)) { in TryAllocateFreeReg() local
768 for (uint32_t reg : LowToHighBits(register_mask)) { in TryAllocateFreeReg() local
777 for (uint32_t reg : LowToHighBits(register_mask)) { in TryAllocateFreeReg() local
784 int reg = kNoRegister; in TryAllocateFreeReg() local
845 int reg = kNoRegister; in FindAvailableRegisterPair() local
882 int reg = kNoRegister; in FindAvailableRegister() local
1001 for (uint32_t reg : LowToHighBits(register_mask)) { in AllocateBlockedReg() local
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Dregister_allocator.cc36 for (size_t reg = 0; reg != num_registers; ++reg) { in GetBlockedRegistersForCall() local
46 num_registers, [&](size_t reg) { return codegen->IsCoreCalleeSaveRegister(reg); }); in GetBlockedCoreRegistersForCall()
51 num_registers, [&](size_t reg) { return codegen->IsFloatingPointCalleeSaveRegister(reg); }); in GetBlockedFpRegistersForCall()
116 int reg, in DumpRegister()
235 for (uint32_t reg : LowToHighBits(get_register_mask(current))) { in ValidateIntervals() local
/art/runtime/interpreter/mterp/riscv64/
Dobject.S591 .macro CLEAR_STATIC_VOLATILE_MARKER reg argument

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