1[
2  "Copyright (C) 2023 The Android Open Source Project",
3  "",
4  "Licensed under the Apache License, Version 2.0 (the “License”);",
5  "you may not use this file except in compliance with the License.",
6  "You may obtain a copy of the License at",
7  "",
8  "     http://www.apache.org/licenses/LICENSE-2.0",
9  "",
10  "Unless required by applicable law or agreed to in writing, software",
11  "distributed under the License is distributed on an “AS IS” BASIS,",
12  "WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.",
13  "See the License for the specific language governing permissions and",
14  "limitations under the License.",
15  {
16    "name": "Adduw",
17    "insn": "Adduw",
18    "in": [ 0, 1 ],
19    "out": [ 0 ]
20  },
21  {
22    "name": "Bclr",
23    "insn": "BtrqRegReg",
24    "in": [ 0, 1 ],
25    "out": [ 0 ]
26  },
27  {
28    "name": "Bext",
29    "insn": "Bext",
30    "in": [ 1, 2 ],
31    "out": [ 0 ]
32  },
33  {
34    "name": "Binv",
35    "insn": "BtcqRegReg",
36    "in": [ 0, 1 ],
37    "out": [ 0 ]
38  },
39  {
40    "name": "Bset",
41    "insn": "BtsqRegReg",
42    "in": [ 0, 1 ],
43    "out": [ 0 ]
44  },
45  {
46    "name": "CanonicalizeNan<Float32>",
47    "insn": "CanonicalizeNanFloat32",
48    "in": [ 1 ],
49    "out": [ 0 ]
50  },
51  {
52    "name": "CanonicalizeNan<Float32>",
53    "insn": "CanonicalizeNanFloat32AVX",
54    "feature": "AVX",
55    "in": [ 1 ],
56    "out": [ 0 ]
57  },
58  {
59    "name": "CanonicalizeNan<Float64>",
60    "insn": "CanonicalizeNanFloat64",
61    "in": [ 1 ],
62    "out": [ 0 ]
63  },
64  {
65    "name": "CanonicalizeNan<Float64>",
66    "insn": "CanonicalizeNanFloat64AVX",
67    "feature": "AVX",
68    "in": [ 1 ],
69    "out": [ 0 ]
70  },
71  {
72    "name": "Clz<int32_t>",
73    "insn": "ClzInt32",
74    "in": [ 1 ],
75    "out": [ 0 ]
76  },
77  {
78    "name": "Clz<int32_t>",
79    "insn": "LzcntlRegReg",
80    "feature": "LZCNT",
81    "in": [ 1 ],
82    "out": [ 0 ]
83  },
84  {
85    "name": "Clz<int64_t>",
86    "insn": "ClzInt64",
87    "in": [ 1 ],
88    "out": [ 0 ]
89  },
90  {
91    "name": "Clz<int64_t>",
92    "insn": "LzcntqRegReg",
93    "feature": "LZCNT",
94    "in": [ 1 ],
95    "out": [ 0 ]
96  },
97  {
98    "name": "Cpop<int32_t>",
99    "insn": "PopcntlRegReg",
100    "feature": "POPCNT",
101    "in": [ 1 ],
102    "out": [ 0 ]
103  },
104  {
105    "name": "Cpop<int64_t>",
106    "insn": "PopcntqRegReg",
107    "feature": "POPCNT",
108    "in": [ 1 ],
109    "out": [ 0 ]
110  },
111  {
112    "name": "Ctz<int32_t>",
113    "insn": "CtzInt32",
114    "in": [ 1 ],
115    "out": [ 0 ]
116  },
117  {
118    "name": "Ctz<int32_t>",
119    "insn": "TzcntlRegReg",
120    "feature": "BMI",
121    "in": [ 1 ],
122    "out": [ 0 ]
123  },
124  {
125    "name": "Ctz<int64_t>",
126    "insn": "CtzInt64",
127    "in": [ 1 ],
128    "out": [ 0 ]
129  },
130  {
131    "name": "Ctz<int64_t>",
132    "insn": "TzcntqRegReg",
133    "feature": "BMI",
134    "in": [ 1 ],
135    "out": [ 0 ]
136  },
137  {
138    "name": "Div<int8_t>",
139    "insn": "DivInt8",
140    "in": [ 1, 0 ],
141    "out": [ 1 ]
142  },
143  {
144    "name": "Div<uint8_t>",
145    "insn": "DivUInt8",
146    "in": [ 1, 0 ],
147    "out": [ 1 ]
148  },
149  {
150    "name": "Div<int16_t>",
151    "insn": "DivInt16",
152    "in": [ 1, 0 ],
153    "out": [ 1 ]
154  },
155  {
156    "name": "Div<uint16_t>",
157    "insn": "DivUInt16",
158    "in": [ 1, 0 ],
159    "out": [ 1 ]
160  },
161  {
162    "name": "Div<int32_t>",
163    "insn": "DivInt32",
164    "in": [ 1, 0 ],
165    "out": [ 1 ]
166  },
167  {
168    "name": "Div<uint32_t>",
169    "insn": "DivUInt32",
170    "in": [ 1, 0 ],
171    "out": [ 1 ]
172  },
173  {
174    "name": "Div<int64_t>",
175    "insn": "DivInt64",
176    "in": [ 1, 0 ],
177    "out": [ 1 ]
178  },
179  {
180    "name": "Div<uint64_t>",
181    "insn": "DivUInt64",
182    "in": [ 1, 0 ],
183    "out": [ 1 ]
184  },
185    {
186    "name": "Rem<int8_t>",
187    "insn": "RemInt8",
188    "in": [ 1, 0 ],
189    "out": [ 1 ]
190  },
191  {
192    "name": "Rem<uint8_t>",
193    "insn": "RemUInt8",
194    "in": [ 1, 0 ],
195    "out": [ 1 ]
196  },
197  {
198    "name": "Rem<int16_t>",
199    "insn": "RemInt16",
200    "in": [ 1, 0 ],
201    "out": [ 2 ]
202  },
203  {
204    "name": "Rem<uint16_t>",
205    "insn": "RemUInt16",
206    "in": [ 1, 0 ],
207    "out": [ 2 ]
208  },
209  {
210    "name": "Rem<int32_t>",
211    "insn": "RemInt32",
212    "in": [ 1, 0 ],
213    "out": [ 2 ]
214  },
215  {
216    "name": "Rem<uint32_t>",
217    "insn": "RemUInt32",
218    "in": [ 1, 0 ],
219    "out": [ 2 ]
220  },
221  {
222    "name": "Rem<int64_t>",
223    "insn": "RemInt64",
224    "in": [ 1, 0 ],
225    "out": [ 2 ]
226  },
227  {
228    "name": "Rem<uint64_t>",
229    "insn": "RemUInt64",
230    "in": [ 1, 0 ],
231    "out": [ 2 ]
232  },
233  {
234    "name": "FAddHostRounding<Float32>",
235    "insn": "AddssXRegXReg",
236    "in": [ 0, 1 ],
237    "out": [ 0 ]
238  },
239  {
240    "name": "FAddHostRounding<Float32>",
241    "insn": "VaddssXRegXRegXReg",
242    "feature": "AVX",
243    "in": [ 1, 2 ],
244    "out": [ 0 ]
245  },
246  {
247    "name": "FAddHostRounding<Float64>",
248    "insn": "AddsdXRegXReg",
249    "in": [ 0, 1 ],
250    "out": [ 0 ]
251  },
252  {
253    "name": "FAddHostRounding<Float64>",
254    "insn": "VaddsdXRegXRegXReg",
255    "feature": "AVX",
256    "in": [ 1, 2 ],
257    "out": [ 0 ]
258  },
259  {
260    "name": "FCvtFloatToIntegerHostRounding<int32_t, Float32>",
261    "insn": "MacroFCvtFloat32ToInt32",
262    "in": [ 1 ],
263    "out": [ 0 ]
264  },
265  {
266    "name": "FCvtFloatToIntegerHostRounding<int32_t, Float64>",
267    "insn": "MacroFCvtFloat64ToInt32",
268    "in": [ 1 ],
269    "out": [ 0 ]
270  },
271  {
272    "name": "FCvtFloatToIntegerHostRounding<int64_t, Float32>",
273    "insn": "MacroFCvtFloat32ToInt64",
274    "in": [ 1 ],
275    "out": [ 0 ]
276  },
277  {
278    "name": "FCvtFloatToIntegerHostRounding<int64_t, Float64>",
279    "insn": "MacroFCvtFloat64ToInt64",
280    "in": [ 1 ],
281    "out": [ 0 ]
282  },
283  {
284    "name": "FDivHostRounding<Float32>",
285    "insn": "DivssXRegXReg",
286    "in": [ 0, 1 ],
287    "out": [ 0 ]
288  },
289  {
290    "name": "FDivHostRounding<Float32>",
291    "insn": "VdivssXRegXRegXReg",
292    "feature": "AVX",
293    "in": [ 1, 2 ],
294    "out": [ 0 ]
295  },
296  {
297    "name": "FDivHostRounding<Float64>",
298    "insn": "DivsdXRegXReg",
299    "in": [ 0, 1 ],
300    "out": [ 0 ]
301  },
302  {
303    "name": "FDivHostRounding<Float64>",
304    "insn": "VdivsdXRegXRegXReg",
305    "feature": "AVX",
306    "in": [ 1, 2 ],
307    "out": [ 0 ]
308  },
309  {
310    "name": "FeGetExceptions",
311    "insn": "MacroFeGetExceptionsTranslate",
312    "usage": "translate-only",
313    "in": [],
314    "out": [ 1 ]
315  },
316  {
317    "name": "FeSetExceptions",
318    "insn": "MacroFeSetExceptionsTranslate",
319    "usage": "translate-only",
320    "in": [ 0 ],
321    "out": []
322  },
323  {
324    "name": "FeSetExceptionsAndRound",
325    "insn": "MacroFeSetExceptionsAndRoundTranslate",
326    "usage": "translate-only",
327    "in": [ 0, 3 ],
328    "out": []
329  },
330  {
331    "name": "FeSetExceptionsImm",
332    "insn": "MacroFeSetExceptionsImmTranslate",
333    "usage": "translate-only",
334    "in": [ 1 ],
335    "out": []
336  },
337  {
338    "name": "FeSetExceptionsAndRoundImm",
339    "insn": "MacroFeSetExceptionsAndRoundImmTranslate",
340    "usage": "translate-only",
341    "in": [ 1 ],
342    "out": []
343  },
344  {
345    "name": "FeSetRound",
346    "insn": "MacroFeSetRound",
347    "in": [ 3 ],
348    "out": []
349  },
350  {
351    "name": "FeSetRoundImm",
352    "insn": "MacroFeSetRound",
353    "usage": "interpret-only",
354    "in": [ 3 ],
355    "out": []
356  },
357  {
358    "name": "FeSetRoundImm",
359    "insn": "MacroFeSetRoundImmTranslate",
360    "usage": "translate-only",
361    "in": [ 2 ],
362    "out": []
363  },
364  {
365    "name": "FMAddHostRounding<Float32>",
366    "insn": "Vfmadd231ssXRegXRegXReg",
367    "feature": "FMA",
368    "in": [ 1, 2, 0 ],
369    "out": [ 0 ]
370  },
371  {
372    "name": "FMAddHostRounding<Float64>",
373    "insn": "Vfmadd231sdXRegXRegXReg",
374    "feature": "FMA",
375    "in": [ 1, 2, 0 ],
376    "out": [ 0 ]
377  },
378  {
379    "name": "FMSubHostRounding<Float32>",
380    "insn": "Vfmsub231ssXRegXRegXReg",
381    "feature": "FMA",
382    "in": [ 1, 2, 0 ],
383    "out": [ 0 ]
384  },
385  {
386    "name": "FMSubHostRounding<Float64>",
387    "insn": "Vfmsub231sdXRegXRegXReg",
388    "feature": "FMA",
389    "in": [ 1, 2, 0 ],
390    "out": [ 0 ]
391  },
392  {
393    "name": "FMulHostRounding<Float32>",
394    "insn": "MulssXRegXReg",
395    "in": [ 0, 1 ],
396    "out": [ 0 ]
397  },
398  {
399    "name": "FMulHostRounding<Float32>",
400    "insn": "VmulssXRegXRegXReg",
401    "feature": "AVX",
402    "in": [ 1, 2 ],
403    "out": [ 0 ]
404  },
405  {
406    "name": "FMulHostRounding<Float64>",
407    "insn": "MulsdXRegXReg",
408    "in": [ 0, 1 ],
409    "out": [ 0 ]
410  },
411  {
412    "name": "FMulHostRounding<Float64>",
413    "insn": "VmulsdXRegXRegXReg",
414    "feature": "AVX",
415    "in": [ 1, 2 ],
416    "out": [ 0 ]
417  },
418  {
419    "name": "FNMAddHostRounding<Float32>",
420    "insn": "Vfnmadd231ssXRegXRegXReg",
421    "feature": "FMA",
422    "in": [ 1, 2, 0 ],
423    "out": [ 0 ]
424  },
425  {
426    "name": "FNMAddHostRounding<Float64>",
427    "insn": "Vfnmadd231sdXRegXRegXReg",
428    "feature": "FMA",
429    "in": [ 1, 2, 0 ],
430    "out": [ 0 ]
431  },
432  {
433    "name": "FNMSubHostRounding<Float32>",
434    "insn": "Vfnmsub231ssXRegXRegXReg",
435    "feature": "FMA",
436    "in": [ 1, 2, 0 ],
437    "out": [ 0 ]
438  },
439  {
440    "name": "FNMSubHostRounding<Float64>",
441    "insn": "Vfnmsub231sdXRegXRegXReg",
442    "feature": "FMA",
443    "in": [ 1, 2, 0 ],
444    "out": [ 0 ]
445  },
446  {
447    "name": "FSubHostRounding<Float32>",
448    "insn": "SubssXRegXReg",
449    "in": [ 0, 1 ],
450    "out": [ 0 ]
451  },
452  {
453    "name": "FSubHostRounding<Float32>",
454    "insn": "VsubssXRegXRegXReg",
455    "feature": "AVX",
456    "in": [ 1, 2 ],
457    "out": [ 0 ]
458  },
459  {
460    "name": "FSubHostRounding<Float64>",
461    "insn": "SubsdXRegXReg",
462    "in": [ 0, 1 ],
463    "out": [ 0 ]
464  },
465  {
466    "name": "FSubHostRounding<Float64>",
467    "insn": "VsubsdXRegXRegXReg",
468    "feature": "AVX",
469    "in": [ 1, 2 ],
470    "out": [ 0 ]
471  },
472  {
473    "name": "Feq<Float32>",
474    "insn": "MacroFeqFloat32",
475    "in": [ 1, 2 ],
476    "out": [ 0 ]
477  },
478  {
479    "name": "Feq<Float32>",
480    "insn": "MacroFeqFloat32AVX",
481    "feature": "AVX",
482    "in": [ 1, 2 ],
483    "out": [ 0 ]
484  },
485  {
486    "name": "Feq<Float64>",
487    "insn": "MacroFeqFloat64",
488    "in": [ 1, 2 ],
489    "out": [ 0 ]
490  },
491  {
492    "name": "Feq<Float64>",
493    "insn": "MacroFeqFloat64AVX",
494    "feature": "AVX",
495    "in": [ 1, 2 ],
496    "out": [ 0 ]
497  },
498  {
499    "name": "Fle<Float32>",
500    "insn": "MacroFleFloat32",
501    "in": [ 1, 2 ],
502    "out": [ 0 ]
503  },
504  {
505    "name": "Fle<Float32>",
506    "insn": "MacroFleFloat32AVX",
507    "feature": "AVX",
508    "in": [ 1, 2 ],
509    "out": [ 0 ]
510  },
511  {
512    "name": "Fle<Float64>",
513    "insn": "MacroFleFloat64",
514    "in": [ 1, 2 ],
515    "out": [ 0 ]
516  },
517  {
518    "name": "Fle<Float64>",
519    "insn": "MacroFleFloat64AVX",
520    "feature": "AVX",
521    "in": [ 1, 2 ],
522    "out": [ 0 ]
523  },
524  {
525    "name": "Flt<Float32>",
526    "insn": "MacroFltFloat32",
527    "in": [ 1, 2 ],
528    "out": [ 0 ]
529  },
530  {
531    "name": "Flt<Float32>",
532    "insn": "MacroFltFloat32AVX",
533    "feature": "AVX",
534    "in": [ 1, 2 ],
535    "out": [ 0 ]
536  },
537  {
538    "name": "Flt<Float64>",
539    "insn": "MacroFltFloat64",
540    "in": [ 1, 2 ],
541    "out": [ 0 ]
542  },
543  {
544    "name": "Flt<Float64>",
545    "insn": "MacroFltFloat64AVX",
546    "feature": "AVX",
547    "in": [ 1, 2 ],
548    "out": [ 0 ]
549  },
550  {
551    "name": "FmvFloatToInteger<int32_t, Float32>",
552    "insn": "MovdRegXReg",
553    "in": [ 1 ],
554    "out": [ 0 ]
555  },
556  {
557    "name": "FmvFloatToInteger<int32_t, Float32>",
558    "insn": "VmovdRegXReg",
559    "feature": "AVX",
560    "in": [ 1 ],
561    "out": [ 0 ]
562  },
563  {
564    "name": "FmvFloatToInteger<int64_t, Float64>",
565    "insn": "MovqRegXReg",
566    "in": [ 1 ],
567    "out": [ 0 ]
568  },
569  {
570    "name": "FmvFloatToInteger<int64_t, Float64>",
571    "insn": "VmovqRegXReg",
572    "feature": "AVX",
573    "in": [ 1 ],
574    "out": [ 0 ]
575  },
576  {
577    "name": "FmvIntegerToFloat<Float32, int32_t>",
578    "insn": "MovdXRegReg",
579    "in": [ 1 ],
580    "out": [ 0 ]
581  },
582  {
583    "name": "FmvIntegerToFloat<Float32, int32_t>",
584    "insn": "VmovdXRegReg",
585    "feature": "AVX",
586    "in": [ 1 ],
587    "out": [ 0 ]
588  },
589  {
590    "name": "FmvIntegerToFloat<Float64, int64_t>",
591    "insn": "MovqXRegReg",
592    "in": [ 1 ],
593    "out": [ 0 ]
594  },
595  {
596    "name": "FmvIntegerToFloat<Float64, int64_t>",
597    "insn": "VmovqXRegReg",
598    "feature": "AVX",
599    "in": [ 1 ],
600    "out": [ 0 ]
601  },
602  {
603    "name": "Max<int64_t>",
604    "insn": "MaxInt64",
605    "in": [ 1, 2 ],
606    "out": [ 0 ]
607  },
608  {
609    "name": "Max<uint64_t>",
610    "insn": "MaxUInt64",
611    "in": [ 1, 2 ],
612    "out": [ 0 ]
613  },
614  {
615    "name": "Min<int64_t>",
616    "insn": "MinInt64",
617    "in": [ 1, 2 ],
618    "out": [ 0 ]
619  },
620  {
621    "name": "Min<uint64_t>",
622    "insn": "MinUInt64",
623    "in": [ 1, 2 ],
624    "out": [ 0 ]
625  },
626  {
627    "name": "NanBox<Float32>",
628    "insn": "MacroNanBoxFloat32",
629    "in": [ 0 ],
630    "out": [ 0 ]
631  },
632  {
633    "name": "NanBox<Float32>",
634    "insn": "MacroNanBoxFloat32AVX",
635    "feature": "AVX",
636    "in": [ 1 ],
637    "out": [ 0 ]
638  },
639  {
640    "name": "Orcb",
641    "insn": "Orcb",
642    "in": [ 0 ],
643    "out": [ 0 ]
644  },
645  {
646    "name": "Orcb",
647    "insn": "OrcbAVX",
648    "feature": "AVX",
649    "in": [ 1 ],
650    "out": [ 0 ]
651  },
652  {
653    "name": "Rev8",
654    "insn": "BswapqReg",
655    "in": [ 0 ],
656    "out": [ 0 ]
657  },
658  {
659    "name": "Rol<int32_t>",
660    "insn": "RollRegReg",
661    "in": [ 0, 1 ],
662    "out": [ 0 ]
663  },
664  {
665    "name": "Rol<int64_t>",
666    "insn": "RolqRegReg",
667    "in": [ 0, 1 ],
668    "out": [ 0 ]
669  },
670  {
671    "name": "Ror<int32_t>",
672    "insn": "RorlRegReg",
673    "in": [ 0, 1 ],
674    "out": [ 0 ]
675  },
676  {
677    "name": "Ror<int64_t>",
678    "insn": "RorqRegReg",
679    "in": [ 0, 1 ],
680    "out": [ 0 ]
681  },
682  {
683    "name": "Sext<int16_t>",
684    "insn": "MovsxwqRegReg",
685    "in": [ 1 ],
686    "out": [ 0 ]
687  },
688  {
689    "name": "Sext<int8_t>",
690    "insn": "MovsxbqRegReg",
691    "in": [ 1 ],
692    "out": [ 0 ]
693  },
694  {
695    "name": "Sh1add",
696    "insn": "Sh1add",
697    "in": [ 0, 1 ],
698    "out": [ 0 ]
699  },
700  {
701    "name": "Sh1adduw",
702    "insn": "Sh1adduw",
703    "in": [ 0, 1 ],
704    "out": [ 0 ]
705  },
706  {
707    "name": "Sh2add",
708    "insn": "Sh2add",
709    "in": [ 0, 1 ],
710    "out": [ 0 ]
711  },
712  {
713    "name": "Sh2adduw",
714    "insn": "Sh2adduw",
715    "in": [ 0, 1 ],
716    "out": [ 0 ]
717  },
718  {
719    "name": "Sh3add",
720    "insn": "Sh3add",
721    "in": [ 0, 1 ],
722    "out": [ 0 ]
723  },
724  {
725    "name": "Sh3adduw",
726    "insn": "Sh3adduw",
727    "in": [ 0, 1 ],
728    "out": [ 0 ]
729  },
730  {
731    "name": "UnboxNan<Float32>",
732    "insn": "MacroUnboxNanFloat32",
733    "in": [ 1 ],
734    "out": [ 0 ]
735  },
736  {
737    "name": "UnboxNan<Float32>",
738    "insn": "MacroUnboxNanFloat32AVX",
739    "feature": "AVX",
740    "in": [ 1 ],
741    "out": [ 0 ]
742  },
743  {
744    "name": "Zexth",
745    "insn": "MovzxwqRegReg",
746    "in": [ 1 ],
747    "out": [ 0 ]
748  }
749]
750