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Searched refs:TMP (Results 1 – 12 of 12) sorted by relevance

/art/test/692-vdex-inmem-loader/src-secondary/
Dgen.sh19 TMP=`mktemp -d`
24 (cd "$TMP" && \
25 javac -d "${TMP}" "$DIR/${CLASS_A}.java" "$DIR/${CLASS_B}.java" && \
26 d8 --output . "$TMP/${CLASS_A}.class" &&
27 mv "$TMP/classes.dex" "$TMP/classesA.dex" &&
28 d8 --output . "$TMP/${CLASS_B}.class" &&
29 mv "$TMP/classes.dex" "$TMP/classesB.dex")
32 base64 "${TMP}/classesA.dex" | sed -E 's/^/ "/' | sed ':a;N;$!ba;s/\n/" +\n/g' | sed -E '$ s/$/"…
35 base64 "${TMP}/classesB.dex" | sed -E 's/^/ "/' | sed ':a;N;$!ba;s/\n/" +\n/g' | sed -E '$ s/$/"…
37 rm -rf "$TMP"
/art/test/693-vdex-inmem-loader-evict/src-secondary/
Dgen.sh28 TMP=`mktemp -d`
38 (cd "$TMP" && \
39 echo "public class MyClass${suffix} { }" > "$TMP/MyClass${suffix}.java" && \
40 javac -d "${TMP}" "$TMP/MyClass${suffix}.java" && \
41 d8 --output "$TMP" "$TMP/MyClass${suffix}.class" && \
42 mv "$TMP/classes.dex" "$TMP/file${suffix}.dex")
45 checksum=`head -c 32 -z "$TMP/file${suffix}.dex" | tail -c 24 -z | base64`
52 base64 "${TMP}/file01.dex" | sed -E 's/^/ "/' | sed ':a;N;$!ba;s/\n/" +\n/g' | sed -E '$ s/$/");…
54 rm -rf "$TMP"
/art/test/999-redefine-hiddenapi/src-redefine/
Dgen.sh19 TMP=`mktemp -d`
23 (cd "$TMP" && \
24 javac -d "${TMP}" "$DIR/${CLASS}.java" && \
25 d8 --output . "$TMP/${CLASS}.class" &&
28 base64 "${TMP}/${CLASS}.class" | sed -E 's/^/ "/' | sed ':a;N;$!ba;s/\n/" +\n/g' | sed -E '$ s/$…
30 base64 "${TMP}/classes.dex" | sed -E 's/^/ "/' | sed ':a;N;$!ba;s/\n/" +\n/g' | sed -E '$ s/$/")…
32 rm -rf "$TMP"
/art/runtime/arch/riscv64/
Dregisters_riscv64.h71 TMP = T6, // Reserved for special uses, such as assembler macro instructions. enumerator
/art/compiler/optimizing/
Dcode_generator_x86_64.cc236 DCHECK(codegen->IsBlockedCoreRegister(TMP)); in EmitNativeCode()
237 __ movl(CpuRegister(TMP), array_len); in EmitNativeCode()
240 __ movl(length_arg.AsRegister<CpuRegister>(), CpuRegister(TMP)); in EmitNativeCode()
1053 __ movq(CpuRegister(TMP), Immediate(counter_address_)); in EmitNativeCode()
1054 __ movw(Address(CpuRegister(TMP), 0), Immediate(ProfilingInfo::GetOptimizeThreshold())); in EmitNativeCode()
1646 blocked_core_registers_[TMP] = true; in SetupBlockedRegisters()
1687 __ movq(CpuRegister(TMP), Immediate(address + offset.Int32Value())); in GenerateMethodEntryExitHook()
1688 __ cmpb(Address(CpuRegister(TMP), 0), in GenerateMethodEntryExitHook()
1697 CpuRegister entry_addr = CpuRegister(TMP); in GenerateMethodEntryExitHook()
1791 method = TMP; in MaybeIncrementHotness()
[all …]
Dintrinsics_x86_64.cc119 __ movl(CpuRegister(TMP), Address(src_curr_addr, 0)); in EmitNativeCode()
120 __ MaybeUnpoisonHeapReference(CpuRegister(TMP)); in EmitNativeCode()
126 int32_t entry_point_offset = Thread::ReadBarrierMarkEntryPointsOffset<kX86_64PointerSize>(TMP); in EmitNativeCode()
129 __ MaybePoisonHeapReference(CpuRegister(TMP)); in EmitNativeCode()
130 __ movl(Address(dst_curr_addr, 0), CpuRegister(TMP)); in EmitNativeCode()
1048 check_non_primitive_array_class(temp2, CpuRegister(TMP)); in VisitSystemArrayCopy()
1058 check_non_primitive_array_class(temp2, CpuRegister(TMP)); in VisitSystemArrayCopy()
1069 check_non_primitive_array_class(temp1, CpuRegister(TMP)); in VisitSystemArrayCopy()
1393 __ movl(CpuRegister(TMP), string_length); in GenerateStringIndexOf()
1417 __ testl(CpuRegister(TMP), Immediate(1)); in GenerateStringIndexOf()
[all …]
Dcode_generator_x86_64.h35 static constexpr Register TMP = R11; variable
Dcode_generator_riscv64.cc739 DCHECK_NE(entrypoint_.AsRegister<XRegister>(), TMP); // A taken branch can clobber `TMP`. in EmitNativeCode()
6299 blocked_core_registers_[TMP] = true; in SetupBlockedRegisters()
/art/compiler/utils/riscv64/
Djni_macro_assembler_riscv64.cc420 __ Andi(TMP, reg, kGlobalOrWeakGlobalMask); in DecodeJNITransitionOrLocalJObject()
421 __ Bnez(TMP, Riscv64JNIMacroLabel::Cast(slow_path)->AsRiscv64()); in DecodeJNITransitionOrLocalJObject()
Dassembler_riscv64_test.cc461 ReplaceReg(REG2_TOKEN, GetRegisterName(TMP), &base); in TestLoadConst64()
694 std::string temp_name = (rd != Zero) ? rd_name : GetRegisterName(TMP); in GetPrintCallRd()
838 std::string tmp_name = GetRegisterName((rs1 != TMP) ? TMP : TMP2); in TestAddConst()
961 return (rs1 != TMP && rd != TMP) in TestLoadStoreArbitraryOffset()
962 ? TMP in TestLoadStoreArbitraryOffset()
965 return rs1 != TMP ? TMP : TMP2; in TestLoadStoreArbitraryOffset()
983 [&](XRegister rs1) { return rs1 != TMP ? TMP : TMP2; }, in TestFPLoadStoreArbitraryOffset()
1009 std::string tmp = GetRegisterName(TMP); in TestLoadLiteral()
8490 srs.ExcludeXRegister(TMP); in TEST_F()
9204 EXPECT_EQ(TMP, tmp); in TEST_F()
Dassembler_riscv64.cc7154 emit_auipc_and_next(TMP, [&](int32_t short_offset) { Jalr(Zero, TMP, short_offset); }); in EmitBranch()
7177 TMP, [&](int32_t short_offset) { FLw(branch->GetFRegister(), TMP, short_offset); }); in EmitBranch()
7181 TMP, [&](int32_t short_offset) { FLd(branch->GetFRegister(), TMP, short_offset); }); in EmitBranch()
Dassembler_riscv64.h235 available_scratch_core_registers_((1u << TMP) | (1u << TMP2)), in Riscv64Assembler()