Searched refs:FA1 (Results 1 – 7 of 7) sorted by relevance
| /art/runtime/arch/riscv64/ |
| D | registers_riscv64.h | 91 FA1 = 11, // F11, argument 1 / return value 1 enumerator
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| D | callee_save_frame_riscv64.h | 61 (1 << art::riscv64::FA0) | (1 << art::riscv64::FA1) | (1 << art::riscv64::FA2) |
80 (1 << art::riscv64::FA0) | (1 << art::riscv64::FA1) | (1 << art::riscv64::FA2) |
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| D | context_riscv64.cc | 114 fprs_[FA1] = nullptr; in SmashCallerSaves()
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| /art/compiler/utils/riscv64/ |
| D | jni_macro_assembler_riscv64_test.cc | 455 ArgumentLocation(Riscv64ManagedRegister::FromFRegister(FA1), kXlenInBytes), in TEST_F()
475 ArgumentLocation(Riscv64ManagedRegister::FromFRegister(FA1), 2 * kVRegSize), in TEST_F()
533 ArgumentLocation(Riscv64ManagedRegister::FromFRegister(FA1), kFloatSize), in TEST_F()
553 ArgumentLocation(Riscv64ManagedRegister::FromFRegister(FA1), kVRegSize), in TEST_F()
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| D | assembler_riscv64_test.cc | 273 FA1, in GetFPRegisters()
311 FA1, in GetFPRegistersShort()
9217 srs.FreeFRegister(FA1); in TEST_F()
9230 EXPECT_EQ(FA1, fa1); in TEST_F()
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| /art/compiler/jni/quick/riscv64/ |
| D | calling_convention_riscv64.cc | 41 FA0, FA1, FA2, FA3, FA4, FA5, FA6, FA7
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| /art/compiler/optimizing/ |
| D | code_generator_riscv64.h | 37 static constexpr FRegister kParameterFpuRegisters[] = {FA0, FA1, FA2, FA3, FA4, FA5, FA6, FA7};
46 FA0, FA1, FA2, FA3, FA4, FA5, FA6, FA7
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