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Searched refs:FA5 (Results 1 – 7 of 7) sorted by relevance

/art/runtime/arch/riscv64/
Dregisters_riscv64.h95 FA5 = 15, // F15, argument 5 enumerator
Dcallee_save_frame_riscv64.h62 (1 << art::riscv64::FA3) | (1 << art::riscv64::FA4) | (1 << art::riscv64::FA5) |
81 (1 << art::riscv64::FA3) | (1 << art::riscv64::FA4) | (1 << art::riscv64::FA5) |
Dcontext_riscv64.cc118 fprs_[FA5] = nullptr; in SmashCallerSaves()
/art/compiler/utils/riscv64/
Djni_macro_assembler_riscv64_test.cc216 __ Store(AsManaged(A3), MemberOffset(384), AsManaged(FA5), kDoubleWordSize); in TEST_F()
256 __ Load(AsManaged(FA5), AsManaged(A3), MemberOffset(384), kDoubleWordSize); in TEST_F()
459 ArgumentLocation(Riscv64ManagedRegister::FromFRegister(FA5), kXlenInBytes), in TEST_F()
479 ArgumentLocation(Riscv64ManagedRegister::FromFRegister(FA5), 2 * kVRegSize), in TEST_F()
537 ArgumentLocation(Riscv64ManagedRegister::FromFRegister(FA5), kFloatSize), in TEST_F()
557 ArgumentLocation(Riscv64ManagedRegister::FromFRegister(FA5), kVRegSize), in TEST_F()
Dassembler_riscv64_test.cc277 FA5, in GetFPRegisters()
315 FA5, in GetFPRegistersShort()
/art/compiler/jni/quick/riscv64/
Dcalling_convention_riscv64.cc41 FA0, FA1, FA2, FA3, FA4, FA5, FA6, FA7
/art/compiler/optimizing/
Dcode_generator_riscv64.h37 static constexpr FRegister kParameterFpuRegisters[] = {FA0, FA1, FA2, FA3, FA4, FA5, FA6, FA7};
46 FA0, FA1, FA2, FA3, FA4, FA5, FA6, FA7