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Searched refs:FT11 (Results 1 – 5 of 5) sorted by relevance

/art/compiler/utils/riscv64/
Dmanaged_register_riscv64_test.cc141 reg = Riscv64ManagedRegister::FromFRegister(FT11); in TEST()
145 EXPECT_EQ(FT11, reg.AsFRegister()); in TEST()
146 EXPECT_TRUE(reg.Equals(Riscv64ManagedRegister::FromFRegister(FT11))); in TEST()
156 EXPECT_FALSE(no_reg.Equals(Riscv64ManagedRegister::FromFRegister(FT11))); in TEST()
164 EXPECT_FALSE(reg_Zero.Equals(Riscv64ManagedRegister::FromFRegister(FT11))); in TEST()
173 EXPECT_FALSE(reg_A1.Equals(Riscv64ManagedRegister::FromFRegister(FT11))); in TEST()
182 EXPECT_FALSE(reg_S2.Equals(Riscv64ManagedRegister::FromFRegister(FT11))); in TEST()
191 EXPECT_FALSE(reg_F0.Equals(Riscv64ManagedRegister::FromFRegister(FT11))); in TEST()
193 Riscv64ManagedRegister reg_F31 = Riscv64ManagedRegister::FromFRegister(FT11); in TEST()
200 EXPECT_TRUE(reg_F31.Equals(Riscv64ManagedRegister::FromFRegister(FT11))); in TEST()
Dassembler_riscv64_test.cc293 FT11, in GetFPRegisters()
/art/runtime/arch/riscv64/
Dregisters_riscv64.h113 FT11 = 31, // F31, temporary 11 enumerator
118 FTMP = FT11, // Reserved for special uses, such as assembler macro instructions.
Dcontext_riscv64.cc112 fprs_[FT11] = nullptr; in SmashCallerSaves()
Dcallee_save_frame_riscv64.h75 (1 << art::riscv64::FT9) | (1 << art::riscv64::FT10) | (1 << art::riscv64::FT11) |