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Searched refs:GetInstructionSetFeatures (Results 1 – 25 of 28) sorted by relevance

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/art/compiler/optimizing/
Dinstruction_simplifier_x86_64.cc38 return codegen_->GetInstructionSetFeatures().HasAVX2(); in HasAVX2()
Dinstruction_simplifier_x86.cc38 return (codegen_->GetInstructionSetFeatures().HasAVX2()); in HasAVX2()
Dintrinsics_arm64.cc3677 if (!codegen_->GetInstructionSetFeatures().HasCRC()) { in VisitCRC32Update()
3692 DCHECK(codegen_->GetInstructionSetFeatures().HasCRC()); in VisitCRC32Update()
3823 if (!codegen_->GetInstructionSetFeatures().HasCRC()) { in VisitCRC32UpdateBytes()
3844 DCHECK(codegen_->GetInstructionSetFeatures().HasCRC()); in VisitCRC32UpdateBytes()
3879 if (!codegen_->GetInstructionSetFeatures().HasCRC()) { in VisitCRC32UpdateByteBuffer()
3906 DCHECK(codegen_->GetInstructionSetFeatures().HasCRC()); in VisitCRC32UpdateByteBuffer()
3922 if (!codegen_->GetInstructionSetFeatures().HasFP16()) { in VisitFP16ToFloat()
3934 DCHECK(codegen_->GetInstructionSetFeatures().HasFP16()); in VisitFP16ToFloat()
3945 if (!codegen_->GetInstructionSetFeatures().HasFP16()) { in VisitFP16ToHalf()
3957 DCHECK(codegen_->GetInstructionSetFeatures().HasFP16()); in VisitFP16ToHalf()
[all …]
Dscheduler_arm.cc1031 bool atomic_ldrd_strd = codegen_->GetInstructionSetFeatures().HasAtomicLdrdAndStrd(); in HandleFieldGetLatencies()
1091 bool atomic_ldrd_strd = codegen_->GetInstructionSetFeatures().HasAtomicLdrdAndStrd(); in HandleFieldSetLatencies()
Doptimizing_compiler.cc415 const InstructionSetFeatures* features = compiler_options.GetInstructionSetFeatures(); in DumpInstructionSetFeaturesToCfg()
1508 const InstructionSetFeatures* features = compiler_options.GetInstructionSetFeatures(); in GenerateJitDebugInfo()
Dcode_generator_x86_64.h474 const X86_64InstructionSetFeatures& GetInstructionSetFeatures() const;
Dintrinsics_x86.cc331 if (!codegen->GetInstructionSetFeatures().HasSSE4_1()) { in CreateSSE41FPToFPLocations()
372 if (!codegen_->GetInstructionSetFeatures().HasSSE4_1()) { in VisitMathRoundFloat()
551 if (codegen->GetInstructionSetFeatures().HasAVX2() && src.IsRegister()) { in GenLowestOneBit()
2768 if (!codegen->GetInstructionSetFeatures().HasPopCnt()) { in CreateBitCountLocations()
4943 DCHECK(codegen_->GetInstructionSetFeatures().HasAVX2()); in VisitMathFmaDouble()
4948 if (codegen_->GetInstructionSetFeatures().HasAVX2()) { in VisitMathFmaDouble()
4954 DCHECK(codegen_->GetInstructionSetFeatures().HasAVX2()); in VisitMathFmaFloat()
4959 if (codegen_->GetInstructionSetFeatures().HasAVX2()) { in VisitMathFmaFloat()
Dintrinsics_x86_64.cc313 if (!codegen->GetInstructionSetFeatures().HasSSE4_1()) { in CreateSSE41FPToFPLocations()
356 if (!codegen->GetInstructionSetFeatures().HasSSE4_1()) { in CreateSSE41FPToIntLocations()
2847 if (!codegen->GetInstructionSetFeatures().HasPopCnt()) { in CreateBitCountLocations()
2948 if (!is_high && codegen->GetInstructionSetFeatures().HasAVX2() && in GenOneBit()
3583 DCHECK(codegen_->GetInstructionSetFeatures().HasAVX2()); in VisitMathFmaDouble()
3588 if (codegen_->GetInstructionSetFeatures().HasAVX2()) { in VisitMathFmaDouble()
3594 DCHECK(codegen_->GetInstructionSetFeatures().HasAVX2()); in VisitMathFmaFloat()
3599 if (codegen_->GetInstructionSetFeatures().HasAVX2()) { in VisitMathFmaFloat()
Dcode_generator_x86.h492 const X86InstructionSetFeatures& GetInstructionSetFeatures() const;
Dcode_generator_riscv64.h498 const Riscv64InstructionSetFeatures& GetInstructionSetFeatures() const;
Dcode_generator_arm_vixl.cc1082 const ArmInstructionSetFeatures& CodeGeneratorARMVIXL::GetInstructionSetFeatures() const { in GetInstructionSetFeatures() function in art::arm::CodeGeneratorARMVIXL
1083 return *GetCompilerOptions().GetInstructionSetFeatures()->AsArmInstructionSetFeatures(); in GetInstructionSetFeatures()
4697 !codegen_->GetInstructionSetFeatures().HasDivideInstruction()) { in VisitDiv()
4724 } else if (codegen_->GetInstructionSetFeatures().HasDivideInstruction()) { in VisitDiv()
4768 } else if (codegen_->GetInstructionSetFeatures().HasDivideInstruction()) { in VisitDiv()
4815 && codegen_->GetInstructionSetFeatures().HasDivideInstruction()) { in VisitRem()
4839 } else if (codegen_->GetInstructionSetFeatures().HasDivideInstruction()) { in VisitRem()
4898 } else if (codegen_->GetInstructionSetFeatures().HasDivideInstruction()) { in VisitRem()
5942 && !codegen_->GetInstructionSetFeatures().HasAtomicLdrdAndStrd(); in HandleFieldSet()
5984 bool atomic_ldrd_strd = codegen_->GetInstructionSetFeatures().HasAtomicLdrdAndStrd(); in HandleFieldSet()
[all …]
Dcode_generator_x86_64.cc1514 const X86_64InstructionSetFeatures& CodeGeneratorX86_64::GetInstructionSetFeatures() const { in GetInstructionSetFeatures() function in art::x86_64::CodeGeneratorX86_64
1515 return *GetCompilerOptions().GetInstructionSetFeatures()->AsX86_64InstructionSetFeatures(); in GetInstructionSetFeatures()
1615 compiler_options.GetInstructionSetFeatures()->AsX86_64InstructionSetFeatures()), in CodeGeneratorX86_64()
7685 DCHECK(codegen_->GetInstructionSetFeatures().HasAVX2()); in VisitX86AndNot()
7695 DCHECK(codegen_->GetInstructionSetFeatures().HasAVX2()); in VisitX86MaskOrResetLeastSetBit()
8549 return codegen_->GetInstructionSetFeatures().HasAVX(); in CpuHasAvxFeatureFlag()
8553 return codegen_->GetInstructionSetFeatures().HasAVX2(); in CpuHasAvx2FeatureFlag()
8557 return codegen_->GetInstructionSetFeatures().HasAVX(); in CpuHasAvxFeatureFlag()
8561 return codegen_->GetInstructionSetFeatures().HasAVX2(); in CpuHasAvx2FeatureFlag()
Dintrinsics_arm_vixl.cc153 features_(codegen->GetInstructionSetFeatures()) {} in IntrinsicLocationsBuilderARMVIXL()
361 DCHECK(codegen_->GetInstructionSetFeatures().HasARMv8AInstructions()); in VisitMathRint()
377 DCHECK(codegen_->GetInstructionSetFeatures().HasARMv8AInstructions()); in VisitMathRoundFloat()
2292 DCHECK(codegen_->GetInstructionSetFeatures().HasARMv8AInstructions()); in VisitMathCeil()
2304 DCHECK(codegen_->GetInstructionSetFeatures().HasARMv8AInstructions()); in VisitMathFloor()
2568 return atomic && !codegen->GetInstructionSetFeatures().HasAtomicLdrdAndStrd(); in Use64BitExclusiveLoadStore()
Dcode_generator_arm_vixl.h592 const ArmInstructionSetFeatures& GetInstructionSetFeatures() const;
Dcode_generator_x86.cc1074 const X86InstructionSetFeatures& CodeGeneratorX86::GetInstructionSetFeatures() const { in GetInstructionSetFeatures() function in art::x86::CodeGeneratorX86
1075 return *GetCompilerOptions().GetInstructionSetFeatures()->AsX86InstructionSetFeatures(); in GetInstructionSetFeatures()
1172 compiler_options.GetInstructionSetFeatures()->AsX86InstructionSetFeatures()), in CodeGeneratorX86()
8334 DCHECK(codegen_->GetInstructionSetFeatures().HasAVX2()); in VisitX86AndNot()
8363 DCHECK(codegen_->GetInstructionSetFeatures().HasAVX2()); in VisitX86MaskOrResetLeastSetBit()
9293 return codegen_->GetInstructionSetFeatures().HasAVX(); in CpuHasAvxFeatureFlag()
9296 return codegen_->GetInstructionSetFeatures().HasAVX2(); in CpuHasAvx2FeatureFlag()
9299 return codegen_->GetInstructionSetFeatures().HasAVX(); in CpuHasAvxFeatureFlag()
9302 return codegen_->GetInstructionSetFeatures().HasAVX2(); in CpuHasAvx2FeatureFlag()
Dcode_generator_arm64.h706 const Arm64InstructionSetFeatures& GetInstructionSetFeatures() const;
Dcode_generator_arm64.cc1010 compiler_options.GetInstructionSetFeatures()->AsArm64InstructionSetFeatures()), in CodeGeneratorARM64()
1041 return GetInstructionSetFeatures().HasSVE(); in ShouldUseSVE()
1046 ? GetInstructionSetFeatures().GetSVEVectorLength() / kBitsPerByte in GetSIMDRegisterWidth()
1637 const Arm64InstructionSetFeatures& CodeGeneratorARM64::GetInstructionSetFeatures() const { in GetInstructionSetFeatures() function in art::arm64::CodeGeneratorARM64
1638 return *GetCompilerOptions().GetInstructionSetFeatures()->AsArm64InstructionSetFeatures(); in GetInstructionSetFeatures()
2678 codegen_->GetInstructionSetFeatures().NeedFixCortexA53_835769()) { in VisitMultiplyAccumulate()
Dcode_generator_riscv64.cc5409 DCHECK(codegen_->GetInstructionSetFeatures().HasZba()); in VisitRiscv64ShiftAdd()
5444 DCHECK(codegen_->GetInstructionSetFeatures().HasZbb()); in VisitBitwiseNegatedRight()
5854 compiler_options.GetInstructionSetFeatures()->AsRiscv64InstructionSetFeatures()), in CodeGeneratorRISCV64()
6351 const Riscv64InstructionSetFeatures& CodeGeneratorRISCV64::GetInstructionSetFeatures() const { in GetInstructionSetFeatures() function in art::riscv64::CodeGeneratorRISCV64
6352 return *GetCompilerOptions().GetInstructionSetFeatures()->AsRiscv64InstructionSetFeatures(); in GetInstructionSetFeatures()
/art/compiler/jit/
Djit_compiler.cc142 const InstructionSetFeatures* features = compiler_options.GetInstructionSetFeatures(); in TypesLoaded()
/art/compiler/driver/
Dcompiler_options.h274 const InstructionSetFeatures* GetInstructionSetFeatures() const { in GetInstructionSetFeatures() function
/art/dex2oat/linker/
Delf_writer_quick.cc254 compiler_options_.GetInstructionSetFeatures(), in PrepareDebugInfo()
Dimage_test.h294 compiler_options_->GetInstructionSetFeatures(), in DoCompile()
Doat_writer_test.cc198 compiler_options_->GetInstructionSetFeatures(), in DoWriteElf()
/art/compiler/jni/quick/
Djni_compiler.cc91 compiler_options.GetInstructionSetFeatures(); in ArtJniCompileMethodInternal()
/art/dex2oat/
Ddex2oat.cc833 if (!compiler_options_->GetInstructionSetFeatures()->Equals(runtime_features.get())) { in ProcessOptions()
835 << *compiler_options_->GetInstructionSetFeatures() in ProcessOptions()
2118 compiler_options_->GetInstructionSetFeatures(), in WriteOutputFiles()

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