Searched refs:LR (Results 1 – 12 of 12) sorted by relevance
| /art/disassembler/ |
| D | disassembler_arm64.cc | 43 LR = 30 enumerator
53 } else if (reg.GetCode() == LR) { in AppendRegisterNameToOutput()
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| /art/compiler/jni/quick/arm64/ |
| D | calling_convention_arm64.cc | 73 Arm64ManagedRegister::FromXRegister(LR),
127 Arm64ManagedRegister::FromXRegister(LR),
320 static_assert((kCoreCalleeSpillMask >> LR) == 1u); // Contains LR as the highest bit. in CalleeSaveRegisters()
323 Arm64ManagedRegister::FromXRegister(LR))); in CalleeSaveRegisters()
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| /art/runtime/arch/arm/ |
| D | registers_arm.h | 50 LR = 14, enumerator
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| D | jni_entrypoints_arm.S | 153 // If we're coming from JNI stub with tail call, it is LR. If we're coming from
155 // If we're coming directly from compiled code, it is LR, set further down.
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| D | callee_save_frame_arm.h | 33 (1 << art::arm::LR);
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| D | quick_entrypoints_arm.S | 528 ldr lr, [sp, #56] @ Load LR from gprs_, 56 = 4 * 14.
666 str lr, [sp, #-8]! @ Save LR with correct stack alignment.
670 ldr lr, [sp], #8 @ Restore LR.
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| /art/compiler/jni/quick/arm/ |
| D | calling_convention_arm.cc | 81 ArmManagedRegister::FromCoreRegister(LR),
138 ArmManagedRegister::FromCoreRegister(LR),
476 static_assert((kCoreCalleeSpillMask >> LR) == 1u); // Contains LR as the highest bit. in CalleeSaveRegisters()
479 ArmManagedRegister::FromCoreRegister(LR))); in CalleeSaveRegisters()
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| /art/runtime/arch/arm64/ |
| D | registers_arm64.h | 70 LR = X30, enumerator
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| D | callee_save_frame_arm64.h | 37 (1 << art::arm64::LR);
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| /art/compiler/utils/arm64/ |
| D | managed_register_arm64_test.cc | 632 EXPECT_TRUE(vixl::aarch64::lr.Is(Arm64Assembler::reg_x(LR))); in TEST()
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| /art/compiler/optimizing/ |
| D | code_generator_arm_vixl.cc | 1967 AddAllocatedRegister(Location::RegisterLocation(LR)); in CodeGeneratorARMVIXL()
2124 blocked_core_registers_[LR] = true; in SetupBlockedRegisters()
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| D | intrinsics_arm64.cc | 130 DCHECK_NE(tmp_.reg(), LR); in EmitNativeCode()
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