| /art/test/411-optimizing-arith/src/ |
| D | MulTest.java | 83 expectEquals(15, $opt$Mul(5, 3)); in mulInt()
84 expectEquals(0, $opt$Mul(0, 0)); in mulInt()
85 expectEquals(0, $opt$Mul(0, 3)); in mulInt()
86 expectEquals(0, $opt$Mul(3, 0)); in mulInt()
87 expectEquals(-3, $opt$Mul(1, -3)); in mulInt()
88 expectEquals(36, $opt$Mul(-12, -3)); in mulInt()
89 expectEquals(33, $opt$Mul(1, 3) * 11); in mulInt()
90 expectEquals(671088645, $opt$Mul(134217729, 5)); // (2^27 + 1) * 5 in mulInt()
94 expectEquals(15L, $opt$Mul(5L, 3L)); in mulLong()
95 expectEquals(0L, $opt$Mul(0L, 0L)); in mulLong()
[all …]
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| /art/test/475-simplify-mul-zero/ |
| D | info.txt | 2 Mul should expect zero constant as input.
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| /art/test/660-clinit/src/ |
| D | Main.java | 43 expectNotPreInit(Mul.class); in main()
195 static Class<?> klazz[] = new Class<?>[]{Add.class, Mul.class};
222 class Mul { class
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| /art/test/594-checker-irreducible-linorder/smali/ |
| D | IrreducibleLoop.smali | 23 ## CHECK-DAG: Mul loop:<<Loop:B\d+>>
28 ## CHECK-DAG: Mul liveness:<<LHeader:\d+>>
72 ## CHECK-DAG: Mul loop:<<Loop:B\d+>>
76 ## CHECK-DAG: Mul liveness:<<LPreEntry2:\d+>>
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| /art/compiler/utils/arm/ |
| D | assembler_arm_vixl.h | 144 void Mul(vixl32::Register rd, vixl32::Register rn, vixl32::Register rm) { in Mul() function
145 MacroAssembler::Mul(vixl32::DontCare, rd, rn, rm); in Mul()
147 using MacroAssembler::Mul;
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| /art/test/596-checker-dead-phi/smali/ |
| D | IrreducibleLoop.smali | 31 ## CHECK-DAG: Mul liveness:<<LPreEntry2:\d+>>
55 # known constant and we eliminate the Mul otherwise.
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| /art/runtime/interpreter/ |
| D | safe_math_test.cc | 96 TEST(SafeMath, Mul) { in TEST() argument
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| /art/test/485-checker-dce-loop-update/smali/ |
| D | TestCase.smali | 142 ## CHECK-DAG: <<Mul9:i\d+>> Mul [<<PhiX>>,<<Cst11>>] loop:<<HeaderY>>
158 ## CHECK-DAG: <<Mul9:i\d+>> Mul [<<PhiX>>,<<Cst11>>] loop:none
174 ## CHECK-DAG: <<Mul9:i\d+>> Mul [<<PhiX>>,<<Cst11>>] loop:none
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| /art/compiler/optimizing/ |
| D | scheduler_arm64.cc | 76 M(Mul , unused) \
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| D | code_generator_vector_arm64_sve.cc | 553 __ Mul(dst.VnB(), p_reg, lhs.VnB(), rhs.VnB()); in VisitVecMul() local
557 __ Mul(dst.VnH(), p_reg, lhs.VnH(), rhs.VnH()); in VisitVecMul() local
560 __ Mul(dst.VnS(), p_reg, lhs.VnS(), rhs.VnS()); in VisitVecMul() local
563 __ Mul(dst.VnD(), p_reg, lhs.VnD(), rhs.VnD()); in VisitVecMul() local
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| D | code_generator_vector_arm64_neon.cc | 635 __ Mul(dst.V16B(), lhs.V16B(), rhs.V16B()); in VisitVecMul() local
640 __ Mul(dst.V8H(), lhs.V8H(), rhs.V8H()); in VisitVecMul() local
644 __ Mul(dst.V4S(), lhs.V4S(), rhs.V4S()); in VisitVecMul() local
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| D | scheduler_arm.cc | 82 M(Mul, unused) \
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| D | nodes.h | 1578 M(Mul, BinaryOperation) \
5516 DECLARE_INSTRUCTION(Mul);
5519 DEFAULT_COPY_CONSTRUCTOR(Mul);
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| D | code_generator_arm_vixl.cc | 4434 __ Mul(OutputRegister(mul), InputRegisterAt(mul, 0), InputRegisterAt(mul, 1)); in VisitMul() local
4460 __ Mul(temp, in1_lo, in2_hi); in VisitMul() local
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| D | code_generator_arm64.cc | 5923 __ Mul(OutputRegister(mul), InputRegisterAt(mul, 0), InputRegisterAt(mul, 1)); in VisitMul() local
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| D | code_generator_riscv64.cc | 4674 __ Mul(locations->Out().AsRegister<XRegister>(), in VisitMul() local
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| /art/test/510-checker-try-catch/smali/ |
| D | SsaBuilder.smali | 214 ## CHECK-NOT: Mul
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| /art/compiler/utils/riscv64/ |
| D | assembler_riscv64_test.cc | 2741 TEST_F(AssemblerRISCV64Test, Mul) { in TEST_F() argument
2742 DriverStr(RepeatRRR(&Riscv64Assembler::Mul, "mul {reg1}, {reg2}, {reg3}"), "Mul"); in TEST_F()
2747 DriverStr(RepeatRRR(&Riscv64Assembler::Mul, "mul {reg1}, {reg2}, {reg3}"), "Mul_WithoutC"); in TEST_F()
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| D | assembler_riscv64.h | 336 void Mul(XRegister rd, XRegister rs1, XRegister rs2);
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| D | assembler_riscv64.cc | 648 void Riscv64Assembler::Mul(XRegister rd, XRegister rs1, XRegister rs2) { in Mul() function in art::riscv64::Riscv64Assembler
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