Searched refs:S1 (Results 1 – 12 of 12) sorted by relevance
| /art/runtime/arch/riscv64/ |
| D | registers_riscv64.h | 39 S1 = 9, // X9, callee-saved 1 / ART thread register enumerator
70 TR = S1, // ART Thread Register - managed runtime
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| /art/compiler/utils/arm/ |
| D | managed_register_arm_test.cc | 79 reg = ArmManagedRegister::FromSRegister(S1); in TEST()
86 EXPECT_EQ(S1, reg.AsSRegister()); in TEST()
136 EXPECT_EQ(S1, reg.AsOverlappingDRegisterHigh()); in TEST()
313 EXPECT_TRUE(!reg_R1.Equals(ArmManagedRegister::FromSRegister(S1))); in TEST()
323 EXPECT_TRUE(!reg_R8.Equals(ArmManagedRegister::FromSRegister(S1))); in TEST()
332 EXPECT_TRUE(!reg_S0.Equals(ArmManagedRegister::FromSRegister(S1))); in TEST()
337 ArmManagedRegister reg_S1 = ArmManagedRegister::FromSRegister(S1); in TEST()
342 EXPECT_TRUE(reg_S1.Equals(ArmManagedRegister::FromSRegister(S1))); in TEST()
466 EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S1))); in TEST()
488 EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S1))); in TEST()
[all …]
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| /art/compiler/utils/arm64/ |
| D | managed_register_arm64_test.cc | 183 sreg = Arm64ManagedRegister::FromSRegister(S1); in TEST()
191 EXPECT_EQ(S1, reg.AsOverlappingSRegister()); in TEST()
296 EXPECT_TRUE(!reg_X1.Equals(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
312 EXPECT_TRUE(!reg_W8.Equals(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
322 EXPECT_TRUE(!reg_W12.Equals(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
330 EXPECT_TRUE(!reg_S0.Equals(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
334 Arm64ManagedRegister reg_S1 = Arm64ManagedRegister::FromSRegister(S1); in TEST()
340 EXPECT_TRUE(reg_S1.Equals(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
389 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
411 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
[all …]
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| /art/runtime/arch/arm/ |
| D | registers_arm.h | 61 S1 = 1, enumerator
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| D | context_arm.cc | 83 fprs_[S1] = nullptr; in SmashCallerSaves()
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| D | callee_save_frame_arm.h | 48 (1 << art::arm::S0) | (1 << art::arm::S1) | (1 << art::arm::S2) | (1 << art::arm::S3) |
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| /art/runtime/arch/arm64/ |
| D | registers_arm64.h | 157 S1 = 1, enumerator
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| /art/compiler/utils/riscv64/ |
| D | managed_register_riscv64_test.cc | 179 EXPECT_FALSE(reg_S2.Equals(Riscv64ManagedRegister::FromXRegister(S1))); in TEST()
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| D | assembler_riscv64_test.cc | 173 secondary_register_names_.emplace(S1, "s1"); in SetUpHelpers()
219 S1, in GetRegisters()
249 S1, in GetRegistersShort()
9247 srs.ExcludeXRegister(S1); // No-op as the register was not available. in TEST_F()
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| /art/compiler/jni/quick/riscv64/ |
| D | calling_convention_riscv64.cc | 105 Riscv64ManagedRegister::FromXRegister(S1),
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| /art/compiler/jni/quick/arm64/ |
| D | calling_convention_arm64.cc | 46 S0, S1, S2, S3, S4, S5, S6, S7
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| /art/compiler/jni/quick/arm/ |
| D | calling_convention_arm.cc | 56 S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15
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