Searched refs:S6 (Results 1 – 12 of 12) sorted by relevance
| /art/runtime/arch/arm/ |
| D | registers_arm.h | 66 S6 = 6, enumerator
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| D | context_arm.cc | 88 fprs_[S6] = nullptr; in SmashCallerSaves()
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| D | callee_save_frame_arm.h | 49 (1 << art::arm::S4) | (1 << art::arm::S5) | (1 << art::arm::S6) | (1 << art::arm::S7) |
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| /art/runtime/arch/riscv64/ |
| D | registers_riscv64.h | 54 S6 = 22, // X22, callee-saved 6 enumerator
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| D | callee_save_frame_riscv64.h | 38 (1 << art::riscv64::S4) | (1 << art::riscv64::S5) | (1 << art::riscv64::S6) |
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| /art/runtime/arch/arm64/ |
| D | registers_arm64.h | 162 S6 = 6, enumerator
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| /art/compiler/jni/quick/riscv64/ |
| D | calling_convention_riscv64.cc | 53 Riscv64ManagedRegister::FromXRegister(S6),
110 Riscv64ManagedRegister::FromXRegister(S6),
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| /art/compiler/jni/quick/arm64/ |
| D | calling_convention_arm64.cc | 46 S0, S1, S2, S3, S4, S5, S6, S7
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| /art/compiler/jni/quick/arm/ |
| D | calling_convention_arm.cc | 56 S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15
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| /art/compiler/utils/arm64/ |
| D | managed_register_arm64_test.cc | 713 EXPECT_TRUE(vixl::aarch64::s6.Is(Arm64Assembler::reg_s(S6))); in TEST()
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| /art/compiler/utils/riscv64/ |
| D | assembler_riscv64_test.cc | 186 secondary_register_names_.emplace(S6, "s6"); in SetUpHelpers()
232 S6, in GetRegisters()
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| /art/compiler/optimizing/ |
| D | code_generator_riscv64.cc | 62 S0, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, RA
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