Searched refs:aimm5 (Results 1 – 2 of 2) sorted by relevance
| /art/compiler/utils/riscv64/ |
| D | assembler_riscv64.cc | 4266 void Riscv64Assembler::VMsltu_vi(VRegister vd, VRegister vs2, int32_t aimm5, VM vm) { in VMsltu_vi() argument
4267 CHECK(IsUint<4>(aimm5 - 1)) << "Should be between [1, 16]" << aimm5; in VMsltu_vi()
4268 VMsleu_vi(vd, vs2, aimm5 - 1, vm); in VMsltu_vi()
4296 void Riscv64Assembler::VMslt_vi(VRegister vd, VRegister vs2, int32_t aimm5, VM vm) { in VMslt_vi() argument
4297 VMsle_vi(vd, vs2, aimm5 - 1, vm); in VMslt_vi()
4314 void Riscv64Assembler::VMsgeu_vi(VRegister vd, VRegister vs2, int32_t aimm5, VM vm) { in VMsgeu_vi() argument
4316 CHECK(IsUint<4>(aimm5 - 1)) << "Should be between [1, 16]" << aimm5; in VMsgeu_vi()
4317 VMsgtu_vi(vd, vs2, aimm5 - 1, vm); in VMsgeu_vi()
4334 void Riscv64Assembler::VMsge_vi(VRegister vd, VRegister vs2, int32_t aimm5, VM vm) { in VMsge_vi() argument
4335 VMsgt_vi(vd, vs2, aimm5 - 1, vm); in VMsge_vi()
|
| D | assembler_riscv64.h | 1183 void VMsltu_vi(VRegister vd, VRegister vs2, int32_t aimm5, VM vm = VM::kUnmasked);
1192 void VMslt_vi(VRegister vd, VRegister vs2, int32_t aimm5, VM vm = VM::kUnmasked);
1199 void VMsgeu_vi(VRegister vd, VRegister vs2, int32_t aimm5, VM vm = VM::kUnmasked);
1206 void VMsge_vi(VRegister vd, VRegister vs2, int32_t aimm5, VM vm = VM::kUnmasked);
|