| /art/compiler/optimizing/ |
| D | code_generator_arm64.cc | 638 Register index_reg = RegisterFrom(index_, DataType::Type::kInt32); in EmitNativeCode() local
664 __ Mov(free_reg.W(), index_reg); in EmitNativeCode()
665 index_reg = free_reg; in EmitNativeCode()
666 index = LocationFrom(index_reg); in EmitNativeCode()
677 __ Lsl(index_reg, index_reg, DataType::SizeShift(type)); in EmitNativeCode()
681 __ Add(index_reg, index_reg, Operand(offset_)); in EmitNativeCode()
2640 Register index_reg = InputRegisterAt(instruction, 0); in VisitIntermediateAddressIndex() local
2645 __ Add(OutputRegister(instruction), index_reg, offset); in VisitIntermediateAddressIndex()
2648 __ Add(OutputRegister(instruction), offset_reg, Operand(index_reg, LSL, shift)); in VisitIntermediateAddressIndex()
7006 Register index_reg = RegisterFrom(index, DataType::Type::kInt32); in GenerateArrayLoadWithBakerReadBarrier() local
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| D | code_generator_x86_64.cc | 841 Register index_reg = index_.AsRegister<CpuRegister>().AsRegister(); in EmitNativeCode() local
842 DCHECK(locations->GetLiveRegisters()->ContainsCoreRegister(index_reg)); in EmitNativeCode()
843 if (codegen->IsCoreCalleeSaveRegister(index_reg)) { in EmitNativeCode()
867 __ movl(CpuRegister(free_reg), CpuRegister(index_reg)); in EmitNativeCode()
868 index_reg = free_reg; in EmitNativeCode()
869 index = Location::RegisterLocation(index_reg); in EmitNativeCode()
880 __ shll(CpuRegister(index_reg), Immediate(TIMES_4)); in EmitNativeCode()
884 __ AddImmediate(CpuRegister(index_reg), Immediate(offset_)); in EmitNativeCode()
6189 CpuRegister index_reg = index_loc.AsRegister<CpuRegister>(); in VisitBoundsCheck() local
6190 __ cmpl(index_reg, Immediate(length)); in VisitBoundsCheck()
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| D | code_generator_arm_vixl.cc | 771 vixl32::Register index_reg = RegisterFrom(index_); in EmitNativeCode() local
772 DCHECK(locations->GetLiveRegisters()->ContainsCoreRegister(index_reg.GetCode())); in EmitNativeCode()
773 if (codegen->IsCoreCalleeSaveRegister(index_reg.GetCode())) { in EmitNativeCode()
797 __ Mov(free_reg, index_reg); in EmitNativeCode()
798 index_reg = free_reg; in EmitNativeCode()
799 index = LocationFrom(index_reg); in EmitNativeCode()
810 __ Lsl(index_reg, index_reg, TIMES_4); in EmitNativeCode()
814 __ Add(index_reg, index_reg, offset_); in EmitNativeCode()
9342 vixl32::Register index_reg = RegisterFrom(index, DataType::Type::kInt32); in GenerateArrayLoadWithBakerReadBarrier() local
9363 __ ldr(ref_reg, MemOperand(data_reg, index_reg, vixl32::LSL, scale_factor)); in GenerateArrayLoadWithBakerReadBarrier()
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| D | code_generator_x86.cc | 792 Register index_reg = index_.AsRegister<Register>(); in EmitNativeCode() local
793 DCHECK(locations->GetLiveRegisters()->ContainsCoreRegister(index_reg)); in EmitNativeCode()
794 if (codegen->IsCoreCalleeSaveRegister(index_reg)) { in EmitNativeCode()
818 __ movl(free_reg, index_reg); in EmitNativeCode()
819 index_reg = free_reg; in EmitNativeCode()
820 index = Location::RegisterLocation(index_reg); in EmitNativeCode()
831 __ shll(index_reg, Immediate(TIMES_4)); in EmitNativeCode()
835 __ AddImmediate(index_reg, Immediate(offset_)); in EmitNativeCode()
6880 Register index_reg = index_loc.AsRegister<Register>(); in VisitBoundsCheck() local
6881 __ cmpl(index_reg, Immediate(length)); in VisitBoundsCheck()
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| D | instruction_builder.cc | 2397 uint8_t index_reg = instruction.VRegC_23x(); in BuildArrayAccess() local
2402 HInstruction* index = LoadLocal(index_reg, DataType::Type::kInt32); in BuildArrayAccess()
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| /art/dex2oat/linker/arm/ |
| D | relative_patcher_thumb2_test.cc | 1141 uint32_t index_reg = (base_reg == 0u) ? 1u : 0u; in TEST_F() local
1143 return kLdrRegLsl2 | index_reg | (base_reg << 16) | (ref_reg << 12); in TEST_F()
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| /art/dex2oat/linker/arm64/ |
| D | relative_patcher_arm64_test.cc | 1320 uint32_t index_reg = (base_reg == 0u) ? 1u : 0u; in TEST_F() local
1322 return kLdrWLsl2Insn | (index_reg << 16) | (base_reg << 5) | ref_reg; in TEST_F()
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| /art/runtime/arch/arm/ |
| D | quick_entrypoints_arm.S | 1956 .macro BRBMI_ARRAY_LOAD index_reg argument
1957 ldr ip, [ip, \index_reg, lsl #2] // 4 bytes.
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| /art/runtime/arch/arm64/ |
| D | quick_entrypoints_arm64.S | 2205 .macro INTROSPECTION_ARRAY_LOAD index_reg argument
2206 ldr wIP0, [xIP0, \index_reg, lsl #2]
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