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/art/runtime/interpreter/mterp/armng/
Dinvoke.S17 FETCH r1, 2
19 and r1, r1, #0xf
21 GET_VREG r1, r1
22 cmp r1, #0
27 ldr r1, [sp]
59 FETCH r1, 2
60 and r1, r1, #0xf
61 GET_VREG r1, r1
62 cmp r1, #0
70 FETCH r1, 2
[all …]
Darithmetic.S22 GET_VREG r1, r3 @ r1<- vCC
25 cmp r1, #0 @ is second operand zero?
55 GET_VREG r1, r3 @ r1<- vB
58 cmp r1, #0 @ is second operand zero?
84 FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended)
89 cmp r1, #0 @ is second operand zero?
123 $extract @ optional; typically r1<- ssssssCC (sign extended)
125 @cmp r1, #0 @ is second operand zero?
160 GET_VREG_WIDE_BY_ADDR r0, r1, r2 @ r0/r1<- vBB/vBB+1
191 mov r1, rINST, lsr #12 @ r1<- B
[all …]
Dobject.S13 cmp r1, r2
22 ldr r1, [sp]
25 mov r1, r0
29 ldr r3, [r1, #MIRROR_CLASS_ACCESS_FLAGS_OFFSET]
32 ldr r3, [r1, #MIRROR_CLASS_COMPONENT_TYPE_OFFSET]
39 cmp r1, r2
85 cmp r1, r2
90 ubfx r1, rINST, #8, #4 // r1<- A
91 SET_VREG r0, r1
98 ldr r1, [sp]
[all …]
Dother.S8 FETCH r1, 2 @ r1<- BBBB (high)
10 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb
26 sbfx r1, rINST, #12, #4 @ r1<- sssssssB (sign-extended)
30 SET_VREG r1, r0 @ fp[A]<- r1
49 mov r1, rINST, lsr #8 @ r1<- AA
56 SET_VREG_OBJECT r0, r1 // vAA <- value
61 ldr r1, [sp]
89 FETCH r1, 2 @ r1<- BBBB (low middle)
91 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word)
94 orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word)
[all …]
Darray.S12 GET_VREG r1, r3 @ r1<- vCC (requested index)
16 add r0, r0, r1, lsl #$shift @ r0<- arrayObj + index*width
17 cmp r1, r3 @ compare unsigned index, length
74 GET_VREG r1, r3 @ r1<- vCC (requested index)
78 cmp r1, r3 @ compare unsigned index, length
87 add r0, r0, r1, lsl #$shift @ r0<- arrayObj + index*width
94 add r0, r0, r1, lsl #$shift @ r0<- arrayObj + index*width
124 mov r1, rINST, lsr #12 @ r1<- B
126 GET_VREG r0, r1 @ r0<- vB (object ref)
139 FETCH r1, 2 @ r1<- BBBB (hi)
[all …]
Dcontrol_flow.S9 mov r1, rINST, lsr #12 @ r1<- B
11 GET_VREG r3, r1 @ r3<- vB
77 FETCH r1, 2 // r1<- AAAA (hi)
78 orrs rINST, r0, r1, lsl #16 // wINST<- AAAAaaaa
129 FETCH r1, 2 @ r1<- BBBB (hi)
131 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb
132 GET_VREG r1, r3 @ r1<- vAA
152 GET_VREG_WIDE_BY_ADDR r0, r1, r2 // r0,r1 <- vAA
155 vmov d0, r0, r1
186 mov r1, rSELF
Dmain.S462 mov r1, #0
608 str r1, [rNEW_FP, rINST]
609 str r1, [r4, rINST]
664 str r1, [rNEW_FP, r0]
665 str r1, [r4, r0]
681 mov r1, rPC
685 mov r1, rPC
689 FETCH r1, 1
918 vmov r0, r1, d0
928 FETCH r1, 1
[all …]
/art/runtime/arch/arm/
Dmemcmp16_arm.S33 pld [r1, #0]
36 cmp r0, r1
56 pld [r1, #32]
59 ldrh ip, [r1], #2
78 ldrh ip, [r1], #2
91 eor r0, r3, r1
101 ldr ip, [r1]
107 pld [r1, #64]
109 ldr lr, [r1, #4]!
112 ldreq ip, [r1, #4]!
[all …]
Djni_entrypoints_arm.S66 push {r0-r1, r4, lr}
75 mov r1, \arg2 @ Pass arg2.
82 pop {r0-r1, r4, pc}
92 push {r0, r1, r2, r3, lr} @ spill regs
118 pop {r0, r1, r2, r3, lr} @ restore regs
170 pop {r0, r1, r2, r3}
178 stmia ip, {r1-r3, r5-r8, r10-r11, lr} // LR: Save return address for tail call from JNI stub.
192 pop {r1, lr}
200 ldr ip, [r1, #ART_METHOD_ACCESS_FLAGS_OFFSET] // Load access flags.
210 LOAD_RUNTIME_INSTANCE r1
[all …]
Dquick_entrypoints_arm.S74 .cfi_rel_offset r1, 4
97 .cfi_restore r1
501 strd r0, [r10] @ Store r0/r1 into result pointer
511 mov r1, r0
513 bl memcpy @ memcpy (dest r0, src r1, bytes r2)
523 vldm r1, {s0-s31} @ Load all fprs from argument fprs_.
550 LOCK_OBJECT_FAST_PATH r0, r1, r2, r3, .Llock_object_slow, /*can_be_null*/ 1
563 SETUP_SAVE_REFS_ONLY_FRAME r1 @ save callee saves in case we block
564 mov r1, rSELF @ pass Thread::Current
578 UNLOCK_OBJECT_FAST_PATH r0, r1, r2, r3, .Lunlock_object_slow, /*can_be_null*/ 1
[all …]
Dinstruction_set_features_assembly_tests.S30 mov r1,#1
54 vmov r1, s0
62 vmov s0, r1
Dasm_support_arm.S181 CONDITIONAL_CBZ \reg, r1, \dest
206 push {r1-r3, r5-r8, r10-r11, lr} @ 10 words of callee saves and args.
233 pop {r1-r3, r5-r8, r10-r11, lr} @ 10 words of callee saves and args.
/art/runtime/interpreter/mterp/arm64ng/
Dfloating_point.S21 %def fbinopWide(instr="fadd d0, d1, d2", result="d0", r1="d1", r2="d2"):
31 GET_VREG_DOUBLE $r1, w1 // w1<- vBB
57 %def fbinopWide2addr(instr="fadd d0, d0, d1", r0="d0", r1="d1"):
64 GET_VREG_DOUBLE $r1, w1 // x1<- vB
72 %def fcmp(r1="s1", r2="s2", cond="lt"):
79 % if r1.startswith("d"):
84 GET_VREG_DOUBLE_PRESCALED $r1, w2
90 GET_VREG $r1, w2
93 fcmp $r1, $r2
183 % fbinopWide(instr="fadd d0, d1, d2", result="d0", r1="d1", r2="d2")
[all …]
Darithmetic.S130 %def binopWide(preinstr="", instr="add x0, x1, x2", result="x0", r1="x1", r2="x2", chkzero="0"):
150 GET_VREG_WIDE_PRESCALED $r1, w1 // w1<- vBB
162 %def binopWide2addr(preinstr="", instr="add x0, x0, x1", r0="x0", r1="x1", chkzero="0"):
179 GET_VREG_WIDE $r1, w1 // x1<- vB
182 cbz $r1, common_errDivideByZero
/art/test/1922-owned-monitors-info/src/art/
DTest1922.java194 for (Function<Runnable, Runnable> r1 = li1.next(); li1.hasNext(); r1 = li1.next()) { in runTestsOtherThread()
203 r1.apply(null).getClass(), in runTestsOtherThread()
209 final Thread thr = new Thread(r1.apply(r2.apply(r3.apply(pause)))); in runTestsOtherThread()
238 for (Function<Runnable, Runnable> r1 = li1.next(); li1.hasNext(); r1 = li1.next()) { in runTestsCurrentThread()
247 r1.apply(null).getClass(), in runTestsCurrentThread()
251 r1.apply(r2.apply(r3.apply(printer))).run(); in runTestsCurrentThread()
/art/test/1978-regular-obsolete-then-structural-obsolescence/src/art/
DTest1978.java40 public static void sayHi(Runnable r1, Runnable r2) { in sayHi() argument
42 r1.run(); in sayHi()
/art/test/800-smali/smali/
Db_134061982.smali22 # Start with r1 == null
32 # Make r1 not-reference.
Db_134061983_2.smali22 # Start with r1 == null
32 # Make r1 not-reference.
/art/runtime/gc/
Dallocation_record.h150 bool operator()(const T* r1, const T* r2) const { in operator()
151 if (r1 == r2) return true; in operator()
152 if (r1 == nullptr || r2 == nullptr) return false; in operator()
153 return *r1 == *r2; in operator()
/art/test/140-field-packing/src/
DGapOrder.java39 public Object r1; field in GapOrder
/art/compiler/utils/arm/
Dassembler_arm_vixl.h178 void Mrrc(vixl32::Register r1, vixl32::Register r2, int coproc, int opc1, int crm) { in Mrrc() argument
185 (r1.GetCode() << 12) | in Mrrc()
193 (r1.GetCode() << 12) | in Mrrc()
/art/openjdkjvmti/
Djvmti_weak_table.h206 bool operator()(const art::GcRoot<art::mirror::Object>& r1, in operator()
209 return r1.Read<art::kWithoutReadBarrier>() == r2.Read<art::kWithoutReadBarrier>(); in operator()
/art/compiler/utils/
Dassembler_thumb_test_expected.cc.inc6 " c: 9119 str r1, [sp, #100]\n"
35 " 68: a909 add r1, sp, #36\n"
44 " 84: 460a mov r2, r1\n"
45 " 86: e9dd 0108 ldrd r0, r1, [sp, #32]\n"
46 " 8a: e9cd 0100 strd r0, r1, [sp]\n"
50 " 98: 4619 mov r1, r3\n"
/art/compiler/optimizing/
Dcode_generator_arm_vixl.h54 vixl::aarch32::r1,
101 vixl::aarch32::r1,
297 return helpers::LocationFrom(vixl::aarch32::r1); in GetObjectLocation()
304 ? helpers::LocationFrom(vixl::aarch32::r0, vixl::aarch32::r1) in GetReturnLocation()
312 : helpers::LocationFrom(vixl::aarch32::r1)); in GetSetValueLocation()
/art/runtime/verifier/
Dreg_type_test.cc992 for (auto r1 : all) { in TEST_F() local
994 if (r1 == r2) { in TEST_F()
1036 bfs(compute_grey, r1); in TEST_F()
1066 ASSERT_EQ(no_in_edge.size(), 1u) << r1->Dump() << " u " << r2->Dump() in TEST_F()
1070 expectations.emplace_back(*r1, *r2, **no_in_edge.begin()); in TEST_F()

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