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Searched refs:vs1 (Results 1 – 4 of 4) sorted by relevance

/art/test/123-compiler-regressions-mt/src/
DMain.java69 int[] vs1 = values; in thread2() local
73 int v1 = vs1[0]; in thread2()
99 int[] vs1; in thread2() local
101 vs1 = values; in thread2()
113 int v1 = vs1[0]; in thread2()
/art/compiler/utils/riscv64/
Dassembler_riscv64.h1052 void VAdd_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm = VM::kUnmasked);
1057 void VSub_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm = VM::kUnmasked);
1068 void VMinu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm = VM::kUnmasked);
1072 void VMin_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm = VM::kUnmasked);
1076 void VMaxu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm = VM::kUnmasked);
1080 void VMax_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm = VM::kUnmasked);
1084 void VAnd_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm = VM::kUnmasked);
1089 void VOr_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm = VM::kUnmasked);
1094 void VXor_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm = VM::kUnmasked);
1102 void VRgather_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm = VM::kUnmasked);
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Dassembler_riscv64.cc3792 void Riscv64Assembler::VAdd_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VAdd_vv() argument
3796 EmitR(funct7, vs2, vs1, enum_cast<uint32_t>(VAIEncoding::kOPIVV), vd, 0x57); in VAdd_vv()
3813 void Riscv64Assembler::VSub_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VSub_vv() argument
3817 EmitR(funct7, vs2, vs1, enum_cast<uint32_t>(VAIEncoding::kOPIVV), vd, 0x57); in VSub_vv()
3843 void Riscv64Assembler::VMinu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VMinu_vv() argument
3847 EmitR(funct7, vs2, vs1, enum_cast<uint32_t>(VAIEncoding::kOPIVV), vd, 0x57); in VMinu_vv()
3857 void Riscv64Assembler::VMin_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VMin_vv() argument
3861 EmitR(funct7, vs2, vs1, enum_cast<uint32_t>(VAIEncoding::kOPIVV), vd, 0x57); in VMin_vv()
3871 void Riscv64Assembler::VMaxu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VMaxu_vv() argument
3875 EmitR(funct7, vs2, vs1, enum_cast<uint32_t>(VAIEncoding::kOPIVV), vd, 0x57); in VMaxu_vv()
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Dassembler_riscv64_test.cc1941 return [](VRegister vd, Reg2, VRegister vs1, Riscv64Assembler::VM vm) { in VXVVmSkipV0VmAndNoR1R3Overlap() argument
1942 return IsVdAllowed(vd, vm) && vd != vs1; in VXVVmSkipV0VmAndNoR1R3Overlap()
1954 return [](VRegister vd, VRegister vs2, VRegister vs1, Riscv64Assembler::VM vm) { in VXVVmSkipV0VmAndNoR1R2R3Overlap() argument
1955 return IsVdAllowed(vd, vm) && vd != vs1 && vd != vs2; in VXVVmSkipV0VmAndNoR1R2R3Overlap()
1985 return [](VRegister vd, VRegister vs2, VRegister vs1) { return vd != vs1 && vd != vs2; }; in VVVNoR1R2R3Overlap() argument