1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef _UAPI_LINUX_ETHTOOL_H 8 #define _UAPI_LINUX_ETHTOOL_H 9 #include <linux/const.h> 10 #include <linux/types.h> 11 #include <linux/if_ether.h> 12 #include <limits.h> 13 struct ethtool_cmd { 14 __u32 cmd; 15 __u32 supported; 16 __u32 advertising; 17 __u16 speed; 18 __u8 duplex; 19 __u8 port; 20 __u8 phy_address; 21 __u8 transceiver; 22 __u8 autoneg; 23 __u8 mdio_support; 24 __u32 maxtxpkt; 25 __u32 maxrxpkt; 26 __u16 speed_hi; 27 __u8 eth_tp_mdix; 28 __u8 eth_tp_mdix_ctrl; 29 __u32 lp_advertising; 30 __u32 reserved[2]; 31 }; 32 #define ETH_MDIO_SUPPORTS_C22 1 33 #define ETH_MDIO_SUPPORTS_C45 2 34 #define ETHTOOL_FWVERS_LEN 32 35 #define ETHTOOL_BUSINFO_LEN 32 36 #define ETHTOOL_EROMVERS_LEN 32 37 struct ethtool_drvinfo { 38 __u32 cmd; 39 char driver[32]; 40 char version[32]; 41 char fw_version[ETHTOOL_FWVERS_LEN]; 42 char bus_info[ETHTOOL_BUSINFO_LEN]; 43 char erom_version[ETHTOOL_EROMVERS_LEN]; 44 char reserved2[12]; 45 __u32 n_priv_flags; 46 __u32 n_stats; 47 __u32 testinfo_len; 48 __u32 eedump_len; 49 __u32 regdump_len; 50 }; 51 #define SOPASS_MAX 6 52 struct ethtool_wolinfo { 53 __u32 cmd; 54 __u32 supported; 55 __u32 wolopts; 56 __u8 sopass[SOPASS_MAX]; 57 }; 58 struct ethtool_value { 59 __u32 cmd; 60 __u32 data; 61 }; 62 #define PFC_STORM_PREVENTION_AUTO 0xffff 63 #define PFC_STORM_PREVENTION_DISABLE 0 64 enum tunable_id { 65 ETHTOOL_ID_UNSPEC, 66 ETHTOOL_RX_COPYBREAK, 67 ETHTOOL_TX_COPYBREAK, 68 ETHTOOL_PFC_PREVENTION_TOUT, 69 ETHTOOL_TX_COPYBREAK_BUF_SIZE, 70 __ETHTOOL_TUNABLE_COUNT, 71 }; 72 enum tunable_type_id { 73 ETHTOOL_TUNABLE_UNSPEC, 74 ETHTOOL_TUNABLE_U8, 75 ETHTOOL_TUNABLE_U16, 76 ETHTOOL_TUNABLE_U32, 77 ETHTOOL_TUNABLE_U64, 78 ETHTOOL_TUNABLE_STRING, 79 ETHTOOL_TUNABLE_S8, 80 ETHTOOL_TUNABLE_S16, 81 ETHTOOL_TUNABLE_S32, 82 ETHTOOL_TUNABLE_S64, 83 }; 84 struct ethtool_tunable { 85 __u32 cmd; 86 __u32 id; 87 __u32 type_id; 88 __u32 len; 89 void * data[]; 90 }; 91 #define DOWNSHIFT_DEV_DEFAULT_COUNT 0xff 92 #define DOWNSHIFT_DEV_DISABLE 0 93 #define ETHTOOL_PHY_FAST_LINK_DOWN_ON 0 94 #define ETHTOOL_PHY_FAST_LINK_DOWN_OFF 0xff 95 #define ETHTOOL_PHY_EDPD_DFLT_TX_MSECS 0xffff 96 #define ETHTOOL_PHY_EDPD_NO_TX 0xfffe 97 #define ETHTOOL_PHY_EDPD_DISABLE 0 98 enum phy_tunable_id { 99 ETHTOOL_PHY_ID_UNSPEC, 100 ETHTOOL_PHY_DOWNSHIFT, 101 ETHTOOL_PHY_FAST_LINK_DOWN, 102 ETHTOOL_PHY_EDPD, 103 __ETHTOOL_PHY_TUNABLE_COUNT, 104 }; 105 struct ethtool_regs { 106 __u32 cmd; 107 __u32 version; 108 __u32 len; 109 __u8 data[]; 110 }; 111 struct ethtool_eeprom { 112 __u32 cmd; 113 __u32 magic; 114 __u32 offset; 115 __u32 len; 116 __u8 data[]; 117 }; 118 struct ethtool_eee { 119 __u32 cmd; 120 __u32 supported; 121 __u32 advertised; 122 __u32 lp_advertised; 123 __u32 eee_active; 124 __u32 eee_enabled; 125 __u32 tx_lpi_enabled; 126 __u32 tx_lpi_timer; 127 __u32 reserved[2]; 128 }; 129 struct ethtool_modinfo { 130 __u32 cmd; 131 __u32 type; 132 __u32 eeprom_len; 133 __u32 reserved[8]; 134 }; 135 struct ethtool_coalesce { 136 __u32 cmd; 137 __u32 rx_coalesce_usecs; 138 __u32 rx_max_coalesced_frames; 139 __u32 rx_coalesce_usecs_irq; 140 __u32 rx_max_coalesced_frames_irq; 141 __u32 tx_coalesce_usecs; 142 __u32 tx_max_coalesced_frames; 143 __u32 tx_coalesce_usecs_irq; 144 __u32 tx_max_coalesced_frames_irq; 145 __u32 stats_block_coalesce_usecs; 146 __u32 use_adaptive_rx_coalesce; 147 __u32 use_adaptive_tx_coalesce; 148 __u32 pkt_rate_low; 149 __u32 rx_coalesce_usecs_low; 150 __u32 rx_max_coalesced_frames_low; 151 __u32 tx_coalesce_usecs_low; 152 __u32 tx_max_coalesced_frames_low; 153 __u32 pkt_rate_high; 154 __u32 rx_coalesce_usecs_high; 155 __u32 rx_max_coalesced_frames_high; 156 __u32 tx_coalesce_usecs_high; 157 __u32 tx_max_coalesced_frames_high; 158 __u32 rate_sample_interval; 159 }; 160 struct ethtool_ringparam { 161 __u32 cmd; 162 __u32 rx_max_pending; 163 __u32 rx_mini_max_pending; 164 __u32 rx_jumbo_max_pending; 165 __u32 tx_max_pending; 166 __u32 rx_pending; 167 __u32 rx_mini_pending; 168 __u32 rx_jumbo_pending; 169 __u32 tx_pending; 170 }; 171 struct ethtool_channels { 172 __u32 cmd; 173 __u32 max_rx; 174 __u32 max_tx; 175 __u32 max_other; 176 __u32 max_combined; 177 __u32 rx_count; 178 __u32 tx_count; 179 __u32 other_count; 180 __u32 combined_count; 181 }; 182 struct ethtool_pauseparam { 183 __u32 cmd; 184 __u32 autoneg; 185 __u32 rx_pause; 186 __u32 tx_pause; 187 }; 188 enum ethtool_link_ext_state { 189 ETHTOOL_LINK_EXT_STATE_AUTONEG, 190 ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE, 191 ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH, 192 ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY, 193 ETHTOOL_LINK_EXT_STATE_NO_CABLE, 194 ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE, 195 ETHTOOL_LINK_EXT_STATE_EEPROM_ISSUE, 196 ETHTOOL_LINK_EXT_STATE_CALIBRATION_FAILURE, 197 ETHTOOL_LINK_EXT_STATE_POWER_BUDGET_EXCEEDED, 198 ETHTOOL_LINK_EXT_STATE_OVERHEAT, 199 ETHTOOL_LINK_EXT_STATE_MODULE, 200 }; 201 enum ethtool_link_ext_substate_autoneg { 202 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED = 1, 203 ETHTOOL_LINK_EXT_SUBSTATE_AN_ACK_NOT_RECEIVED, 204 ETHTOOL_LINK_EXT_SUBSTATE_AN_NEXT_PAGE_EXCHANGE_FAILED, 205 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED_FORCE_MODE, 206 ETHTOOL_LINK_EXT_SUBSTATE_AN_FEC_MISMATCH_DURING_OVERRIDE, 207 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_HCD, 208 }; 209 enum ethtool_link_ext_substate_link_training { 210 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_FRAME_LOCK_NOT_ACQUIRED = 1, 211 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_INHIBIT_TIMEOUT, 212 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_PARTNER_DID_NOT_SET_RECEIVER_READY, 213 ETHTOOL_LINK_EXT_SUBSTATE_LT_REMOTE_FAULT, 214 }; 215 enum ethtool_link_ext_substate_link_logical_mismatch { 216 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_BLOCK_LOCK = 1, 217 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_AM_LOCK, 218 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_GET_ALIGN_STATUS, 219 ETHTOOL_LINK_EXT_SUBSTATE_LLM_FC_FEC_IS_NOT_LOCKED, 220 ETHTOOL_LINK_EXT_SUBSTATE_LLM_RS_FEC_IS_NOT_LOCKED, 221 }; 222 enum ethtool_link_ext_substate_bad_signal_integrity { 223 ETHTOOL_LINK_EXT_SUBSTATE_BSI_LARGE_NUMBER_OF_PHYSICAL_ERRORS = 1, 224 ETHTOOL_LINK_EXT_SUBSTATE_BSI_UNSUPPORTED_RATE, 225 ETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_REFERENCE_CLOCK_LOST, 226 ETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_ALOS, 227 }; 228 enum ethtool_link_ext_substate_cable_issue { 229 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE = 1, 230 ETHTOOL_LINK_EXT_SUBSTATE_CI_CABLE_TEST_FAILURE, 231 }; 232 enum ethtool_link_ext_substate_module { 233 ETHTOOL_LINK_EXT_SUBSTATE_MODULE_CMIS_NOT_READY = 1, 234 }; 235 #define ETH_GSTRING_LEN 32 236 enum ethtool_stringset { 237 ETH_SS_TEST = 0, 238 ETH_SS_STATS, 239 ETH_SS_PRIV_FLAGS, 240 ETH_SS_NTUPLE_FILTERS, 241 ETH_SS_FEATURES, 242 ETH_SS_RSS_HASH_FUNCS, 243 ETH_SS_TUNABLES, 244 ETH_SS_PHY_STATS, 245 ETH_SS_PHY_TUNABLES, 246 ETH_SS_LINK_MODES, 247 ETH_SS_MSG_CLASSES, 248 ETH_SS_WOL_MODES, 249 ETH_SS_SOF_TIMESTAMPING, 250 ETH_SS_TS_TX_TYPES, 251 ETH_SS_TS_RX_FILTERS, 252 ETH_SS_UDP_TUNNEL_TYPES, 253 ETH_SS_STATS_STD, 254 ETH_SS_STATS_ETH_PHY, 255 ETH_SS_STATS_ETH_MAC, 256 ETH_SS_STATS_ETH_CTRL, 257 ETH_SS_STATS_RMON, 258 ETH_SS_COUNT 259 }; 260 enum ethtool_mac_stats_src { 261 ETHTOOL_MAC_STATS_SRC_AGGREGATE, 262 ETHTOOL_MAC_STATS_SRC_EMAC, 263 ETHTOOL_MAC_STATS_SRC_PMAC, 264 }; 265 enum ethtool_module_power_mode_policy { 266 ETHTOOL_MODULE_POWER_MODE_POLICY_HIGH = 1, 267 ETHTOOL_MODULE_POWER_MODE_POLICY_AUTO, 268 }; 269 enum ethtool_module_power_mode { 270 ETHTOOL_MODULE_POWER_MODE_LOW = 1, 271 ETHTOOL_MODULE_POWER_MODE_HIGH, 272 }; 273 enum ethtool_podl_pse_admin_state { 274 ETHTOOL_PODL_PSE_ADMIN_STATE_UNKNOWN = 1, 275 ETHTOOL_PODL_PSE_ADMIN_STATE_DISABLED, 276 ETHTOOL_PODL_PSE_ADMIN_STATE_ENABLED, 277 }; 278 enum ethtool_podl_pse_pw_d_status { 279 ETHTOOL_PODL_PSE_PW_D_STATUS_UNKNOWN = 1, 280 ETHTOOL_PODL_PSE_PW_D_STATUS_DISABLED, 281 ETHTOOL_PODL_PSE_PW_D_STATUS_SEARCHING, 282 ETHTOOL_PODL_PSE_PW_D_STATUS_DELIVERING, 283 ETHTOOL_PODL_PSE_PW_D_STATUS_SLEEP, 284 ETHTOOL_PODL_PSE_PW_D_STATUS_IDLE, 285 ETHTOOL_PODL_PSE_PW_D_STATUS_ERROR, 286 }; 287 enum ethtool_mm_verify_status { 288 ETHTOOL_MM_VERIFY_STATUS_UNKNOWN, 289 ETHTOOL_MM_VERIFY_STATUS_INITIAL, 290 ETHTOOL_MM_VERIFY_STATUS_VERIFYING, 291 ETHTOOL_MM_VERIFY_STATUS_SUCCEEDED, 292 ETHTOOL_MM_VERIFY_STATUS_FAILED, 293 ETHTOOL_MM_VERIFY_STATUS_DISABLED, 294 }; 295 struct ethtool_gstrings { 296 __u32 cmd; 297 __u32 string_set; 298 __u32 len; 299 __u8 data[]; 300 }; 301 struct ethtool_sset_info { 302 __u32 cmd; 303 __u32 reserved; 304 __u64 sset_mask; 305 __u32 data[]; 306 }; 307 enum ethtool_test_flags { 308 ETH_TEST_FL_OFFLINE = (1 << 0), 309 ETH_TEST_FL_FAILED = (1 << 1), 310 ETH_TEST_FL_EXTERNAL_LB = (1 << 2), 311 ETH_TEST_FL_EXTERNAL_LB_DONE = (1 << 3), 312 }; 313 struct ethtool_test { 314 __u32 cmd; 315 __u32 flags; 316 __u32 reserved; 317 __u32 len; 318 __u64 data[]; 319 }; 320 struct ethtool_stats { 321 __u32 cmd; 322 __u32 n_stats; 323 __u64 data[]; 324 }; 325 struct ethtool_perm_addr { 326 __u32 cmd; 327 __u32 size; 328 __u8 data[]; 329 }; 330 enum ethtool_flags { 331 ETH_FLAG_TXVLAN = (1 << 7), 332 ETH_FLAG_RXVLAN = (1 << 8), 333 ETH_FLAG_LRO = (1 << 15), 334 ETH_FLAG_NTUPLE = (1 << 27), 335 ETH_FLAG_RXHASH = (1 << 28), 336 }; 337 struct ethtool_tcpip4_spec { 338 __be32 ip4src; 339 __be32 ip4dst; 340 __be16 psrc; 341 __be16 pdst; 342 __u8 tos; 343 }; 344 struct ethtool_ah_espip4_spec { 345 __be32 ip4src; 346 __be32 ip4dst; 347 __be32 spi; 348 __u8 tos; 349 }; 350 #define ETH_RX_NFC_IP4 1 351 struct ethtool_usrip4_spec { 352 __be32 ip4src; 353 __be32 ip4dst; 354 __be32 l4_4_bytes; 355 __u8 tos; 356 __u8 ip_ver; 357 __u8 proto; 358 }; 359 struct ethtool_tcpip6_spec { 360 __be32 ip6src[4]; 361 __be32 ip6dst[4]; 362 __be16 psrc; 363 __be16 pdst; 364 __u8 tclass; 365 }; 366 struct ethtool_ah_espip6_spec { 367 __be32 ip6src[4]; 368 __be32 ip6dst[4]; 369 __be32 spi; 370 __u8 tclass; 371 }; 372 struct ethtool_usrip6_spec { 373 __be32 ip6src[4]; 374 __be32 ip6dst[4]; 375 __be32 l4_4_bytes; 376 __u8 tclass; 377 __u8 l4_proto; 378 }; 379 union ethtool_flow_union { 380 struct ethtool_tcpip4_spec tcp_ip4_spec; 381 struct ethtool_tcpip4_spec udp_ip4_spec; 382 struct ethtool_tcpip4_spec sctp_ip4_spec; 383 struct ethtool_ah_espip4_spec ah_ip4_spec; 384 struct ethtool_ah_espip4_spec esp_ip4_spec; 385 struct ethtool_usrip4_spec usr_ip4_spec; 386 struct ethtool_tcpip6_spec tcp_ip6_spec; 387 struct ethtool_tcpip6_spec udp_ip6_spec; 388 struct ethtool_tcpip6_spec sctp_ip6_spec; 389 struct ethtool_ah_espip6_spec ah_ip6_spec; 390 struct ethtool_ah_espip6_spec esp_ip6_spec; 391 struct ethtool_usrip6_spec usr_ip6_spec; 392 struct ethhdr ether_spec; 393 __u8 hdata[52]; 394 }; 395 struct ethtool_flow_ext { 396 __u8 padding[2]; 397 unsigned char h_dest[ETH_ALEN]; 398 __be16 vlan_etype; 399 __be16 vlan_tci; 400 __be32 data[2]; 401 }; 402 struct ethtool_rx_flow_spec { 403 __u32 flow_type; 404 union ethtool_flow_union h_u; 405 struct ethtool_flow_ext h_ext; 406 union ethtool_flow_union m_u; 407 struct ethtool_flow_ext m_ext; 408 __u64 ring_cookie; 409 __u32 location; 410 }; 411 #define ETHTOOL_RX_FLOW_SPEC_RING 0x00000000FFFFFFFFLL 412 #define ETHTOOL_RX_FLOW_SPEC_RING_VF 0x000000FF00000000LL 413 #define ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF 32 414 struct ethtool_rxnfc { 415 __u32 cmd; 416 __u32 flow_type; 417 __u64 data; 418 struct ethtool_rx_flow_spec fs; 419 union { 420 __u32 rule_cnt; 421 __u32 rss_context; 422 }; 423 __u32 rule_locs[]; 424 }; 425 struct ethtool_rxfh_indir { 426 __u32 cmd; 427 __u32 size; 428 __u32 ring_index[]; 429 }; 430 struct ethtool_rxfh { 431 __u32 cmd; 432 __u32 rss_context; 433 __u32 indir_size; 434 __u32 key_size; 435 __u8 hfunc; 436 __u8 input_xfrm; 437 __u8 rsvd8[2]; 438 __u32 rsvd32; 439 __u32 rss_config[]; 440 }; 441 #define ETH_RXFH_CONTEXT_ALLOC 0xffffffff 442 #define ETH_RXFH_INDIR_NO_CHANGE 0xffffffff 443 struct ethtool_rx_ntuple_flow_spec { 444 __u32 flow_type; 445 union { 446 struct ethtool_tcpip4_spec tcp_ip4_spec; 447 struct ethtool_tcpip4_spec udp_ip4_spec; 448 struct ethtool_tcpip4_spec sctp_ip4_spec; 449 struct ethtool_ah_espip4_spec ah_ip4_spec; 450 struct ethtool_ah_espip4_spec esp_ip4_spec; 451 struct ethtool_usrip4_spec usr_ip4_spec; 452 struct ethhdr ether_spec; 453 __u8 hdata[72]; 454 } h_u, m_u; 455 __u16 vlan_tag; 456 __u16 vlan_tag_mask; 457 __u64 data; 458 __u64 data_mask; 459 __s32 action; 460 #define ETHTOOL_RXNTUPLE_ACTION_DROP (- 1) 461 #define ETHTOOL_RXNTUPLE_ACTION_CLEAR (- 2) 462 }; 463 struct ethtool_rx_ntuple { 464 __u32 cmd; 465 struct ethtool_rx_ntuple_flow_spec fs; 466 }; 467 #define ETHTOOL_FLASH_MAX_FILENAME 128 468 enum ethtool_flash_op_type { 469 ETHTOOL_FLASH_ALL_REGIONS = 0, 470 }; 471 struct ethtool_flash { 472 __u32 cmd; 473 __u32 region; 474 char data[ETHTOOL_FLASH_MAX_FILENAME]; 475 }; 476 struct ethtool_dump { 477 __u32 cmd; 478 __u32 version; 479 __u32 flag; 480 __u32 len; 481 __u8 data[]; 482 }; 483 #define ETH_FW_DUMP_DISABLE 0 484 struct ethtool_get_features_block { 485 __u32 available; 486 __u32 requested; 487 __u32 active; 488 __u32 never_changed; 489 }; 490 struct ethtool_gfeatures { 491 __u32 cmd; 492 __u32 size; 493 struct ethtool_get_features_block features[]; 494 }; 495 struct ethtool_set_features_block { 496 __u32 valid; 497 __u32 requested; 498 }; 499 struct ethtool_sfeatures { 500 __u32 cmd; 501 __u32 size; 502 struct ethtool_set_features_block features[]; 503 }; 504 struct ethtool_ts_info { 505 __u32 cmd; 506 __u32 so_timestamping; 507 __s32 phc_index; 508 __u32 tx_types; 509 __u32 tx_reserved[3]; 510 __u32 rx_filters; 511 __u32 rx_reserved[3]; 512 }; 513 enum ethtool_sfeatures_retval_bits { 514 ETHTOOL_F_UNSUPPORTED__BIT, 515 ETHTOOL_F_WISH__BIT, 516 ETHTOOL_F_COMPAT__BIT, 517 }; 518 #define ETHTOOL_F_UNSUPPORTED (1 << ETHTOOL_F_UNSUPPORTED__BIT) 519 #define ETHTOOL_F_WISH (1 << ETHTOOL_F_WISH__BIT) 520 #define ETHTOOL_F_COMPAT (1 << ETHTOOL_F_COMPAT__BIT) 521 #define MAX_NUM_QUEUE 4096 522 struct ethtool_per_queue_op { 523 __u32 cmd; 524 __u32 sub_command; 525 __u32 queue_mask[__KERNEL_DIV_ROUND_UP(MAX_NUM_QUEUE, 32)]; 526 char data[]; 527 }; 528 struct ethtool_fecparam { 529 __u32 cmd; 530 __u32 active_fec; 531 __u32 fec; 532 __u32 reserved; 533 }; 534 enum ethtool_fec_config_bits { 535 ETHTOOL_FEC_NONE_BIT, 536 ETHTOOL_FEC_AUTO_BIT, 537 ETHTOOL_FEC_OFF_BIT, 538 ETHTOOL_FEC_RS_BIT, 539 ETHTOOL_FEC_BASER_BIT, 540 ETHTOOL_FEC_LLRS_BIT, 541 }; 542 #define ETHTOOL_FEC_NONE (1 << ETHTOOL_FEC_NONE_BIT) 543 #define ETHTOOL_FEC_AUTO (1 << ETHTOOL_FEC_AUTO_BIT) 544 #define ETHTOOL_FEC_OFF (1 << ETHTOOL_FEC_OFF_BIT) 545 #define ETHTOOL_FEC_RS (1 << ETHTOOL_FEC_RS_BIT) 546 #define ETHTOOL_FEC_BASER (1 << ETHTOOL_FEC_BASER_BIT) 547 #define ETHTOOL_FEC_LLRS (1 << ETHTOOL_FEC_LLRS_BIT) 548 #define ETHTOOL_GSET 0x00000001 549 #define ETHTOOL_SSET 0x00000002 550 #define ETHTOOL_GDRVINFO 0x00000003 551 #define ETHTOOL_GREGS 0x00000004 552 #define ETHTOOL_GWOL 0x00000005 553 #define ETHTOOL_SWOL 0x00000006 554 #define ETHTOOL_GMSGLVL 0x00000007 555 #define ETHTOOL_SMSGLVL 0x00000008 556 #define ETHTOOL_NWAY_RST 0x00000009 557 #define ETHTOOL_GLINK 0x0000000a 558 #define ETHTOOL_GEEPROM 0x0000000b 559 #define ETHTOOL_SEEPROM 0x0000000c 560 #define ETHTOOL_GCOALESCE 0x0000000e 561 #define ETHTOOL_SCOALESCE 0x0000000f 562 #define ETHTOOL_GRINGPARAM 0x00000010 563 #define ETHTOOL_SRINGPARAM 0x00000011 564 #define ETHTOOL_GPAUSEPARAM 0x00000012 565 #define ETHTOOL_SPAUSEPARAM 0x00000013 566 #define ETHTOOL_GRXCSUM 0x00000014 567 #define ETHTOOL_SRXCSUM 0x00000015 568 #define ETHTOOL_GTXCSUM 0x00000016 569 #define ETHTOOL_STXCSUM 0x00000017 570 #define ETHTOOL_GSG 0x00000018 571 #define ETHTOOL_SSG 0x00000019 572 #define ETHTOOL_TEST 0x0000001a 573 #define ETHTOOL_GSTRINGS 0x0000001b 574 #define ETHTOOL_PHYS_ID 0x0000001c 575 #define ETHTOOL_GSTATS 0x0000001d 576 #define ETHTOOL_GTSO 0x0000001e 577 #define ETHTOOL_STSO 0x0000001f 578 #define ETHTOOL_GPERMADDR 0x00000020 579 #define ETHTOOL_GUFO 0x00000021 580 #define ETHTOOL_SUFO 0x00000022 581 #define ETHTOOL_GGSO 0x00000023 582 #define ETHTOOL_SGSO 0x00000024 583 #define ETHTOOL_GFLAGS 0x00000025 584 #define ETHTOOL_SFLAGS 0x00000026 585 #define ETHTOOL_GPFLAGS 0x00000027 586 #define ETHTOOL_SPFLAGS 0x00000028 587 #define ETHTOOL_GRXFH 0x00000029 588 #define ETHTOOL_SRXFH 0x0000002a 589 #define ETHTOOL_GGRO 0x0000002b 590 #define ETHTOOL_SGRO 0x0000002c 591 #define ETHTOOL_GRXRINGS 0x0000002d 592 #define ETHTOOL_GRXCLSRLCNT 0x0000002e 593 #define ETHTOOL_GRXCLSRULE 0x0000002f 594 #define ETHTOOL_GRXCLSRLALL 0x00000030 595 #define ETHTOOL_SRXCLSRLDEL 0x00000031 596 #define ETHTOOL_SRXCLSRLINS 0x00000032 597 #define ETHTOOL_FLASHDEV 0x00000033 598 #define ETHTOOL_RESET 0x00000034 599 #define ETHTOOL_SRXNTUPLE 0x00000035 600 #define ETHTOOL_GRXNTUPLE 0x00000036 601 #define ETHTOOL_GSSET_INFO 0x00000037 602 #define ETHTOOL_GRXFHINDIR 0x00000038 603 #define ETHTOOL_SRXFHINDIR 0x00000039 604 #define ETHTOOL_GFEATURES 0x0000003a 605 #define ETHTOOL_SFEATURES 0x0000003b 606 #define ETHTOOL_GCHANNELS 0x0000003c 607 #define ETHTOOL_SCHANNELS 0x0000003d 608 #define ETHTOOL_SET_DUMP 0x0000003e 609 #define ETHTOOL_GET_DUMP_FLAG 0x0000003f 610 #define ETHTOOL_GET_DUMP_DATA 0x00000040 611 #define ETHTOOL_GET_TS_INFO 0x00000041 612 #define ETHTOOL_GMODULEINFO 0x00000042 613 #define ETHTOOL_GMODULEEEPROM 0x00000043 614 #define ETHTOOL_GEEE 0x00000044 615 #define ETHTOOL_SEEE 0x00000045 616 #define ETHTOOL_GRSSH 0x00000046 617 #define ETHTOOL_SRSSH 0x00000047 618 #define ETHTOOL_GTUNABLE 0x00000048 619 #define ETHTOOL_STUNABLE 0x00000049 620 #define ETHTOOL_GPHYSTATS 0x0000004a 621 #define ETHTOOL_PERQUEUE 0x0000004b 622 #define ETHTOOL_GLINKSETTINGS 0x0000004c 623 #define ETHTOOL_SLINKSETTINGS 0x0000004d 624 #define ETHTOOL_PHY_GTUNABLE 0x0000004e 625 #define ETHTOOL_PHY_STUNABLE 0x0000004f 626 #define ETHTOOL_GFECPARAM 0x00000050 627 #define ETHTOOL_SFECPARAM 0x00000051 628 #define SPARC_ETH_GSET ETHTOOL_GSET 629 #define SPARC_ETH_SSET ETHTOOL_SSET 630 enum ethtool_link_mode_bit_indices { 631 ETHTOOL_LINK_MODE_10baseT_Half_BIT = 0, 632 ETHTOOL_LINK_MODE_10baseT_Full_BIT = 1, 633 ETHTOOL_LINK_MODE_100baseT_Half_BIT = 2, 634 ETHTOOL_LINK_MODE_100baseT_Full_BIT = 3, 635 ETHTOOL_LINK_MODE_1000baseT_Half_BIT = 4, 636 ETHTOOL_LINK_MODE_1000baseT_Full_BIT = 5, 637 ETHTOOL_LINK_MODE_Autoneg_BIT = 6, 638 ETHTOOL_LINK_MODE_TP_BIT = 7, 639 ETHTOOL_LINK_MODE_AUI_BIT = 8, 640 ETHTOOL_LINK_MODE_MII_BIT = 9, 641 ETHTOOL_LINK_MODE_FIBRE_BIT = 10, 642 ETHTOOL_LINK_MODE_BNC_BIT = 11, 643 ETHTOOL_LINK_MODE_10000baseT_Full_BIT = 12, 644 ETHTOOL_LINK_MODE_Pause_BIT = 13, 645 ETHTOOL_LINK_MODE_Asym_Pause_BIT = 14, 646 ETHTOOL_LINK_MODE_2500baseX_Full_BIT = 15, 647 ETHTOOL_LINK_MODE_Backplane_BIT = 16, 648 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT = 17, 649 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT = 18, 650 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT = 19, 651 ETHTOOL_LINK_MODE_10000baseR_FEC_BIT = 20, 652 ETHTOOL_LINK_MODE_20000baseMLD2_Full_BIT = 21, 653 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT = 22, 654 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT = 23, 655 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT = 24, 656 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT = 25, 657 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT = 26, 658 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT = 27, 659 ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT = 28, 660 ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT = 29, 661 ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT = 30, 662 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT = 31, 663 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT = 32, 664 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT = 33, 665 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT = 34, 666 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT = 35, 667 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT = 36, 668 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT = 37, 669 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT = 38, 670 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT = 39, 671 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT = 40, 672 ETHTOOL_LINK_MODE_1000baseX_Full_BIT = 41, 673 ETHTOOL_LINK_MODE_10000baseCR_Full_BIT = 42, 674 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT = 43, 675 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT = 44, 676 ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT = 45, 677 ETHTOOL_LINK_MODE_10000baseER_Full_BIT = 46, 678 ETHTOOL_LINK_MODE_2500baseT_Full_BIT = 47, 679 ETHTOOL_LINK_MODE_5000baseT_Full_BIT = 48, 680 ETHTOOL_LINK_MODE_FEC_NONE_BIT = 49, 681 ETHTOOL_LINK_MODE_FEC_RS_BIT = 50, 682 ETHTOOL_LINK_MODE_FEC_BASER_BIT = 51, 683 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT = 52, 684 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT = 53, 685 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT = 54, 686 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT = 55, 687 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT = 56, 688 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT = 57, 689 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT = 58, 690 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT = 59, 691 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT = 60, 692 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT = 61, 693 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT = 62, 694 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT = 63, 695 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT = 64, 696 ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT = 65, 697 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT = 66, 698 ETHTOOL_LINK_MODE_100baseT1_Full_BIT = 67, 699 ETHTOOL_LINK_MODE_1000baseT1_Full_BIT = 68, 700 ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT = 69, 701 ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT = 70, 702 ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT = 71, 703 ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT = 72, 704 ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT = 73, 705 ETHTOOL_LINK_MODE_FEC_LLRS_BIT = 74, 706 ETHTOOL_LINK_MODE_100000baseKR_Full_BIT = 75, 707 ETHTOOL_LINK_MODE_100000baseSR_Full_BIT = 76, 708 ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT = 77, 709 ETHTOOL_LINK_MODE_100000baseCR_Full_BIT = 78, 710 ETHTOOL_LINK_MODE_100000baseDR_Full_BIT = 79, 711 ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT = 80, 712 ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT = 81, 713 ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT = 82, 714 ETHTOOL_LINK_MODE_200000baseDR2_Full_BIT = 83, 715 ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT = 84, 716 ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT = 85, 717 ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT = 86, 718 ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT = 87, 719 ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT = 88, 720 ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT = 89, 721 ETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90, 722 ETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91, 723 ETHTOOL_LINK_MODE_10baseT1L_Full_BIT = 92, 724 ETHTOOL_LINK_MODE_800000baseCR8_Full_BIT = 93, 725 ETHTOOL_LINK_MODE_800000baseKR8_Full_BIT = 94, 726 ETHTOOL_LINK_MODE_800000baseDR8_Full_BIT = 95, 727 ETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT = 96, 728 ETHTOOL_LINK_MODE_800000baseSR8_Full_BIT = 97, 729 ETHTOOL_LINK_MODE_800000baseVR8_Full_BIT = 98, 730 ETHTOOL_LINK_MODE_10baseT1S_Full_BIT = 99, 731 ETHTOOL_LINK_MODE_10baseT1S_Half_BIT = 100, 732 ETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT = 101, 733 __ETHTOOL_LINK_MODE_MASK_NBITS 734 }; 735 #define __ETHTOOL_LINK_MODE_LEGACY_MASK(base_name) (1UL << (ETHTOOL_LINK_MODE_ ##base_name ##_BIT)) 736 #define SUPPORTED_10baseT_Half __ETHTOOL_LINK_MODE_LEGACY_MASK(10baseT_Half) 737 #define SUPPORTED_10baseT_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(10baseT_Full) 738 #define SUPPORTED_100baseT_Half __ETHTOOL_LINK_MODE_LEGACY_MASK(100baseT_Half) 739 #define SUPPORTED_100baseT_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(100baseT_Full) 740 #define SUPPORTED_1000baseT_Half __ETHTOOL_LINK_MODE_LEGACY_MASK(1000baseT_Half) 741 #define SUPPORTED_1000baseT_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(1000baseT_Full) 742 #define SUPPORTED_Autoneg __ETHTOOL_LINK_MODE_LEGACY_MASK(Autoneg) 743 #define SUPPORTED_TP __ETHTOOL_LINK_MODE_LEGACY_MASK(TP) 744 #define SUPPORTED_AUI __ETHTOOL_LINK_MODE_LEGACY_MASK(AUI) 745 #define SUPPORTED_MII __ETHTOOL_LINK_MODE_LEGACY_MASK(MII) 746 #define SUPPORTED_FIBRE __ETHTOOL_LINK_MODE_LEGACY_MASK(FIBRE) 747 #define SUPPORTED_BNC __ETHTOOL_LINK_MODE_LEGACY_MASK(BNC) 748 #define SUPPORTED_10000baseT_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(10000baseT_Full) 749 #define SUPPORTED_Pause __ETHTOOL_LINK_MODE_LEGACY_MASK(Pause) 750 #define SUPPORTED_Asym_Pause __ETHTOOL_LINK_MODE_LEGACY_MASK(Asym_Pause) 751 #define SUPPORTED_2500baseX_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(2500baseX_Full) 752 #define SUPPORTED_Backplane __ETHTOOL_LINK_MODE_LEGACY_MASK(Backplane) 753 #define SUPPORTED_1000baseKX_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(1000baseKX_Full) 754 #define SUPPORTED_10000baseKX4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(10000baseKX4_Full) 755 #define SUPPORTED_10000baseKR_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(10000baseKR_Full) 756 #define SUPPORTED_10000baseR_FEC __ETHTOOL_LINK_MODE_LEGACY_MASK(10000baseR_FEC) 757 #define SUPPORTED_20000baseMLD2_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(20000baseMLD2_Full) 758 #define SUPPORTED_20000baseKR2_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(20000baseKR2_Full) 759 #define SUPPORTED_40000baseKR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(40000baseKR4_Full) 760 #define SUPPORTED_40000baseCR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(40000baseCR4_Full) 761 #define SUPPORTED_40000baseSR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(40000baseSR4_Full) 762 #define SUPPORTED_40000baseLR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(40000baseLR4_Full) 763 #define SUPPORTED_56000baseKR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(56000baseKR4_Full) 764 #define SUPPORTED_56000baseCR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(56000baseCR4_Full) 765 #define SUPPORTED_56000baseSR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(56000baseSR4_Full) 766 #define SUPPORTED_56000baseLR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(56000baseLR4_Full) 767 #define ADVERTISED_10baseT_Half __ETHTOOL_LINK_MODE_LEGACY_MASK(10baseT_Half) 768 #define ADVERTISED_10baseT_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(10baseT_Full) 769 #define ADVERTISED_100baseT_Half __ETHTOOL_LINK_MODE_LEGACY_MASK(100baseT_Half) 770 #define ADVERTISED_100baseT_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(100baseT_Full) 771 #define ADVERTISED_1000baseT_Half __ETHTOOL_LINK_MODE_LEGACY_MASK(1000baseT_Half) 772 #define ADVERTISED_1000baseT_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(1000baseT_Full) 773 #define ADVERTISED_Autoneg __ETHTOOL_LINK_MODE_LEGACY_MASK(Autoneg) 774 #define ADVERTISED_TP __ETHTOOL_LINK_MODE_LEGACY_MASK(TP) 775 #define ADVERTISED_AUI __ETHTOOL_LINK_MODE_LEGACY_MASK(AUI) 776 #define ADVERTISED_MII __ETHTOOL_LINK_MODE_LEGACY_MASK(MII) 777 #define ADVERTISED_FIBRE __ETHTOOL_LINK_MODE_LEGACY_MASK(FIBRE) 778 #define ADVERTISED_BNC __ETHTOOL_LINK_MODE_LEGACY_MASK(BNC) 779 #define ADVERTISED_10000baseT_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(10000baseT_Full) 780 #define ADVERTISED_Pause __ETHTOOL_LINK_MODE_LEGACY_MASK(Pause) 781 #define ADVERTISED_Asym_Pause __ETHTOOL_LINK_MODE_LEGACY_MASK(Asym_Pause) 782 #define ADVERTISED_2500baseX_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(2500baseX_Full) 783 #define ADVERTISED_Backplane __ETHTOOL_LINK_MODE_LEGACY_MASK(Backplane) 784 #define ADVERTISED_1000baseKX_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(1000baseKX_Full) 785 #define ADVERTISED_10000baseKX4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(10000baseKX4_Full) 786 #define ADVERTISED_10000baseKR_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(10000baseKR_Full) 787 #define ADVERTISED_10000baseR_FEC __ETHTOOL_LINK_MODE_LEGACY_MASK(10000baseR_FEC) 788 #define ADVERTISED_20000baseMLD2_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(20000baseMLD2_Full) 789 #define ADVERTISED_20000baseKR2_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(20000baseKR2_Full) 790 #define ADVERTISED_40000baseKR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(40000baseKR4_Full) 791 #define ADVERTISED_40000baseCR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(40000baseCR4_Full) 792 #define ADVERTISED_40000baseSR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(40000baseSR4_Full) 793 #define ADVERTISED_40000baseLR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(40000baseLR4_Full) 794 #define ADVERTISED_56000baseKR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(56000baseKR4_Full) 795 #define ADVERTISED_56000baseCR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(56000baseCR4_Full) 796 #define ADVERTISED_56000baseSR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(56000baseSR4_Full) 797 #define ADVERTISED_56000baseLR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(56000baseLR4_Full) 798 #define SPEED_10 10 799 #define SPEED_100 100 800 #define SPEED_1000 1000 801 #define SPEED_2500 2500 802 #define SPEED_5000 5000 803 #define SPEED_10000 10000 804 #define SPEED_14000 14000 805 #define SPEED_20000 20000 806 #define SPEED_25000 25000 807 #define SPEED_40000 40000 808 #define SPEED_50000 50000 809 #define SPEED_56000 56000 810 #define SPEED_100000 100000 811 #define SPEED_200000 200000 812 #define SPEED_400000 400000 813 #define SPEED_800000 800000 814 #define SPEED_UNKNOWN - 1 815 #define DUPLEX_HALF 0x00 816 #define DUPLEX_FULL 0x01 817 #define DUPLEX_UNKNOWN 0xff 818 #define MASTER_SLAVE_CFG_UNSUPPORTED 0 819 #define MASTER_SLAVE_CFG_UNKNOWN 1 820 #define MASTER_SLAVE_CFG_MASTER_PREFERRED 2 821 #define MASTER_SLAVE_CFG_SLAVE_PREFERRED 3 822 #define MASTER_SLAVE_CFG_MASTER_FORCE 4 823 #define MASTER_SLAVE_CFG_SLAVE_FORCE 5 824 #define MASTER_SLAVE_STATE_UNSUPPORTED 0 825 #define MASTER_SLAVE_STATE_UNKNOWN 1 826 #define MASTER_SLAVE_STATE_MASTER 2 827 #define MASTER_SLAVE_STATE_SLAVE 3 828 #define MASTER_SLAVE_STATE_ERR 4 829 #define RATE_MATCH_NONE 0 830 #define RATE_MATCH_PAUSE 1 831 #define RATE_MATCH_CRS 2 832 #define RATE_MATCH_OPEN_LOOP 3 833 #define PORT_TP 0x00 834 #define PORT_AUI 0x01 835 #define PORT_MII 0x02 836 #define PORT_FIBRE 0x03 837 #define PORT_BNC 0x04 838 #define PORT_DA 0x05 839 #define PORT_NONE 0xef 840 #define PORT_OTHER 0xff 841 #define XCVR_INTERNAL 0x00 842 #define XCVR_EXTERNAL 0x01 843 #define XCVR_DUMMY1 0x02 844 #define XCVR_DUMMY2 0x03 845 #define XCVR_DUMMY3 0x04 846 #define AUTONEG_DISABLE 0x00 847 #define AUTONEG_ENABLE 0x01 848 #define ETH_TP_MDI_INVALID 0x00 849 #define ETH_TP_MDI 0x01 850 #define ETH_TP_MDI_X 0x02 851 #define ETH_TP_MDI_AUTO 0x03 852 #define WAKE_PHY (1 << 0) 853 #define WAKE_UCAST (1 << 1) 854 #define WAKE_MCAST (1 << 2) 855 #define WAKE_BCAST (1 << 3) 856 #define WAKE_ARP (1 << 4) 857 #define WAKE_MAGIC (1 << 5) 858 #define WAKE_MAGICSECURE (1 << 6) 859 #define WAKE_FILTER (1 << 7) 860 #define WOL_MODE_COUNT 8 861 #define RXH_XFRM_SYM_XOR (1 << 0) 862 #define RXH_XFRM_NO_CHANGE 0xff 863 #define TCP_V4_FLOW 0x01 864 #define UDP_V4_FLOW 0x02 865 #define SCTP_V4_FLOW 0x03 866 #define AH_ESP_V4_FLOW 0x04 867 #define TCP_V6_FLOW 0x05 868 #define UDP_V6_FLOW 0x06 869 #define SCTP_V6_FLOW 0x07 870 #define AH_ESP_V6_FLOW 0x08 871 #define AH_V4_FLOW 0x09 872 #define ESP_V4_FLOW 0x0a 873 #define AH_V6_FLOW 0x0b 874 #define ESP_V6_FLOW 0x0c 875 #define IPV4_USER_FLOW 0x0d 876 #define IP_USER_FLOW IPV4_USER_FLOW 877 #define IPV6_USER_FLOW 0x0e 878 #define IPV4_FLOW 0x10 879 #define IPV6_FLOW 0x11 880 #define ETHER_FLOW 0x12 881 #define GTPU_V4_FLOW 0x13 882 #define GTPU_V6_FLOW 0x14 883 #define GTPC_V4_FLOW 0x15 884 #define GTPC_V6_FLOW 0x16 885 #define GTPC_TEID_V4_FLOW 0x17 886 #define GTPC_TEID_V6_FLOW 0x18 887 #define GTPU_EH_V4_FLOW 0x19 888 #define GTPU_EH_V6_FLOW 0x1a 889 #define GTPU_UL_V4_FLOW 0x1b 890 #define GTPU_UL_V6_FLOW 0x1c 891 #define GTPU_DL_V4_FLOW 0x1d 892 #define GTPU_DL_V6_FLOW 0x1e 893 #define FLOW_EXT 0x80000000 894 #define FLOW_MAC_EXT 0x40000000 895 #define FLOW_RSS 0x20000000 896 #define RXH_L2DA (1 << 1) 897 #define RXH_VLAN (1 << 2) 898 #define RXH_L3_PROTO (1 << 3) 899 #define RXH_IP_SRC (1 << 4) 900 #define RXH_IP_DST (1 << 5) 901 #define RXH_L4_B_0_1 (1 << 6) 902 #define RXH_L4_B_2_3 (1 << 7) 903 #define RXH_GTP_TEID (1 << 8) 904 #define RXH_DISCARD (1 << 31) 905 #define RX_CLS_FLOW_DISC 0xffffffffffffffffULL 906 #define RX_CLS_FLOW_WAKE 0xfffffffffffffffeULL 907 #define RX_CLS_LOC_SPECIAL 0x80000000 908 #define RX_CLS_LOC_ANY 0xffffffff 909 #define RX_CLS_LOC_FIRST 0xfffffffe 910 #define RX_CLS_LOC_LAST 0xfffffffd 911 #define ETH_MODULE_SFF_8079 0x1 912 #define ETH_MODULE_SFF_8079_LEN 256 913 #define ETH_MODULE_SFF_8472 0x2 914 #define ETH_MODULE_SFF_8472_LEN 512 915 #define ETH_MODULE_SFF_8636 0x3 916 #define ETH_MODULE_SFF_8636_LEN 256 917 #define ETH_MODULE_SFF_8436 0x4 918 #define ETH_MODULE_SFF_8436_LEN 256 919 #define ETH_MODULE_SFF_8636_MAX_LEN 640 920 #define ETH_MODULE_SFF_8436_MAX_LEN 640 921 enum ethtool_reset_flags { 922 ETH_RESET_MGMT = 1 << 0, 923 ETH_RESET_IRQ = 1 << 1, 924 ETH_RESET_DMA = 1 << 2, 925 ETH_RESET_FILTER = 1 << 3, 926 ETH_RESET_OFFLOAD = 1 << 4, 927 ETH_RESET_MAC = 1 << 5, 928 ETH_RESET_PHY = 1 << 6, 929 ETH_RESET_RAM = 1 << 7, 930 ETH_RESET_AP = 1 << 8, 931 ETH_RESET_DEDICATED = 0x0000ffff, 932 ETH_RESET_ALL = 0xffffffff, 933 }; 934 #define ETH_RESET_SHARED_SHIFT 16 935 struct ethtool_link_settings { 936 __u32 cmd; 937 __u32 speed; 938 __u8 duplex; 939 __u8 port; 940 __u8 phy_address; 941 __u8 autoneg; 942 __u8 mdio_support; 943 __u8 eth_tp_mdix; 944 __u8 eth_tp_mdix_ctrl; 945 __s8 link_mode_masks_nwords; 946 __u8 transceiver; 947 __u8 master_slave_cfg; 948 __u8 master_slave_state; 949 __u8 rate_matching; 950 __u32 reserved[7]; 951 __u32 link_mode_masks[]; 952 }; 953 #endif 954