1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef __ARM_KVM_H__ 8 #define __ARM_KVM_H__ 9 #define KVM_SPSR_EL1 0 10 #define KVM_SPSR_SVC KVM_SPSR_EL1 11 #define KVM_SPSR_ABT 1 12 #define KVM_SPSR_UND 2 13 #define KVM_SPSR_IRQ 3 14 #define KVM_SPSR_FIQ 4 15 #define KVM_NR_SPSR 5 16 #ifndef __ASSEMBLY__ 17 #include <linux/psci.h> 18 #include <linux/types.h> 19 #include <asm/ptrace.h> 20 #include <asm/sve_context.h> 21 #define __KVM_HAVE_IRQ_LINE 22 #define __KVM_HAVE_VCPU_EVENTS 23 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 24 #define KVM_DIRTY_LOG_PAGE_OFFSET 64 25 #define KVM_REG_SIZE(id) (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) 26 struct kvm_regs { 27 struct user_pt_regs regs; 28 __u64 sp_el1; 29 __u64 elr_el1; 30 __u64 spsr[KVM_NR_SPSR]; 31 struct user_fpsimd_state fp_regs; 32 }; 33 #define KVM_ARM_TARGET_AEM_V8 0 34 #define KVM_ARM_TARGET_FOUNDATION_V8 1 35 #define KVM_ARM_TARGET_CORTEX_A57 2 36 #define KVM_ARM_TARGET_XGENE_POTENZA 3 37 #define KVM_ARM_TARGET_CORTEX_A53 4 38 #define KVM_ARM_TARGET_GENERIC_V8 5 39 #define KVM_ARM_NUM_TARGETS 6 40 #define KVM_ARM_DEVICE_TYPE_SHIFT 0 41 #define KVM_ARM_DEVICE_TYPE_MASK __GENMASK(KVM_ARM_DEVICE_TYPE_SHIFT + 15, KVM_ARM_DEVICE_TYPE_SHIFT) 42 #define KVM_ARM_DEVICE_ID_SHIFT 16 43 #define KVM_ARM_DEVICE_ID_MASK __GENMASK(KVM_ARM_DEVICE_ID_SHIFT + 15, KVM_ARM_DEVICE_ID_SHIFT) 44 #define KVM_ARM_DEVICE_VGIC_V2 0 45 #define KVM_VGIC_V2_ADDR_TYPE_DIST 0 46 #define KVM_VGIC_V2_ADDR_TYPE_CPU 1 47 #define KVM_VGIC_V2_DIST_SIZE 0x1000 48 #define KVM_VGIC_V2_CPU_SIZE 0x2000 49 #define KVM_VGIC_V3_ADDR_TYPE_DIST 2 50 #define KVM_VGIC_V3_ADDR_TYPE_REDIST 3 51 #define KVM_VGIC_ITS_ADDR_TYPE 4 52 #define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION 5 53 #define KVM_VGIC_V3_DIST_SIZE SZ_64K 54 #define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K) 55 #define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K) 56 #define KVM_ARM_VCPU_POWER_OFF 0 57 #define KVM_ARM_VCPU_EL1_32BIT 1 58 #define KVM_ARM_VCPU_PSCI_0_2 2 59 #define KVM_ARM_VCPU_PMU_V3 3 60 #define KVM_ARM_VCPU_SVE 4 61 #define KVM_ARM_VCPU_PTRAUTH_ADDRESS 5 62 #define KVM_ARM_VCPU_PTRAUTH_GENERIC 6 63 #define KVM_ARM_VCPU_HAS_EL2 7 64 struct kvm_vcpu_init { 65 __u32 target; 66 __u32 features[7]; 67 }; 68 struct kvm_sregs { 69 }; 70 struct kvm_fpu { 71 }; 72 #define KVM_ARM_MAX_DBG_REGS 16 73 struct kvm_guest_debug_arch { 74 __u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS]; 75 __u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS]; 76 __u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS]; 77 __u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS]; 78 }; 79 #define KVM_DEBUG_ARCH_HSR_HIGH_VALID (1 << 0) 80 struct kvm_debug_exit_arch { 81 __u32 hsr; 82 __u32 hsr_high; 83 __u64 far; 84 }; 85 #define KVM_GUESTDBG_USE_SW_BP (1 << 16) 86 #define KVM_GUESTDBG_USE_HW (1 << 17) 87 struct kvm_sync_regs { 88 __u64 device_irq_level; 89 }; 90 #define KVM_ARM_DEV_EL1_VTIMER (1 << 0) 91 #define KVM_ARM_DEV_EL1_PTIMER (1 << 1) 92 #define KVM_ARM_DEV_PMU (1 << 2) 93 struct kvm_pmu_event_filter { 94 __u16 base_event; 95 __u16 nevents; 96 #define KVM_PMU_EVENT_ALLOW 0 97 #define KVM_PMU_EVENT_DENY 1 98 __u8 action; 99 __u8 pad[3]; 100 }; 101 struct kvm_vcpu_events { 102 struct { 103 __u8 serror_pending; 104 __u8 serror_has_esr; 105 __u8 ext_dabt_pending; 106 __u8 pad[5]; 107 __u64 serror_esr; 108 } exception; 109 __u32 reserved[12]; 110 }; 111 struct kvm_arm_copy_mte_tags { 112 __u64 guest_ipa; 113 __u64 length; 114 void * addr; 115 __u64 flags; 116 __u64 reserved[2]; 117 }; 118 struct kvm_arm_counter_offset { 119 __u64 counter_offset; 120 __u64 reserved; 121 }; 122 #define KVM_ARM_TAGS_TO_GUEST 0 123 #define KVM_ARM_TAGS_FROM_GUEST 1 124 #define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000 125 #define KVM_REG_ARM_COPROC_SHIFT 16 126 #define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT) 127 #define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32)) 128 #define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT) 129 #define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00 130 #define KVM_REG_ARM_DEMUX_ID_SHIFT 8 131 #define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT) 132 #define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF 133 #define KVM_REG_ARM_DEMUX_VAL_SHIFT 0 134 #define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT) 135 #define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000 136 #define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14 137 #define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800 138 #define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11 139 #define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780 140 #define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7 141 #define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078 142 #define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3 143 #define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007 144 #define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0 145 #define ARM64_SYS_REG_SHIFT_MASK(x,n) (((x) << KVM_REG_ARM64_SYSREG_ ##n ##_SHIFT) & KVM_REG_ARM64_SYSREG_ ##n ##_MASK) 146 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | ARM64_SYS_REG_SHIFT_MASK(op2, OP2)) 147 #define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64) 148 #define KVM_REG_ARM_PTIMER_CTL ARM64_SYS_REG(3, 3, 14, 2, 1) 149 #define KVM_REG_ARM_PTIMER_CVAL ARM64_SYS_REG(3, 3, 14, 2, 2) 150 #define KVM_REG_ARM_PTIMER_CNT ARM64_SYS_REG(3, 3, 14, 0, 1) 151 #define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1) 152 #define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2) 153 #define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2) 154 #define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT) 155 #define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_FW | ((r) & 0xffff)) 156 #define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0) 157 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1 KVM_REG_ARM_FW_REG(1) 158 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL 0 159 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL 1 160 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED 2 161 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2 KVM_REG_ARM_FW_REG(2) 162 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL 0 163 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN 1 164 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL 2 165 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED 3 166 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED (1U << 4) 167 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3 KVM_REG_ARM_FW_REG(3) 168 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_AVAIL 0 169 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_AVAIL 1 170 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_REQUIRED 2 171 #define KVM_REG_ARM64_SVE (0x15 << KVM_REG_ARM_COPROC_SHIFT) 172 #define KVM_REG_ARM64_SVE_ZREG_BASE 0 173 #define KVM_REG_ARM64_SVE_PREG_BASE 0x400 174 #define KVM_REG_ARM64_SVE_FFR_BASE 0x600 175 #define KVM_ARM64_SVE_NUM_ZREGS __SVE_NUM_ZREGS 176 #define KVM_ARM64_SVE_NUM_PREGS __SVE_NUM_PREGS 177 #define KVM_ARM64_SVE_MAX_SLICES 32 178 #define KVM_REG_ARM64_SVE_ZREG(n,i) (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_ZREG_BASE | KVM_REG_SIZE_U2048 | (((n) & (KVM_ARM64_SVE_NUM_ZREGS - 1)) << 5) | ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) 179 #define KVM_REG_ARM64_SVE_PREG(n,i) (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_PREG_BASE | KVM_REG_SIZE_U256 | (((n) & (KVM_ARM64_SVE_NUM_PREGS - 1)) << 5) | ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) 180 #define KVM_REG_ARM64_SVE_FFR(i) (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_FFR_BASE | KVM_REG_SIZE_U256 | ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) 181 #define KVM_ARM64_SVE_VQ_MIN __SVE_VQ_MIN 182 #define KVM_ARM64_SVE_VQ_MAX __SVE_VQ_MAX 183 #define KVM_REG_ARM64_SVE_VLS (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_SIZE_U512 | 0xffff) 184 #define KVM_ARM64_SVE_VLS_WORDS ((KVM_ARM64_SVE_VQ_MAX - KVM_ARM64_SVE_VQ_MIN) / 64 + 1) 185 #define KVM_REG_ARM_FW_FEAT_BMAP (0x0016 << KVM_REG_ARM_COPROC_SHIFT) 186 #define KVM_REG_ARM_FW_FEAT_BMAP_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_FW_FEAT_BMAP | ((r) & 0xffff)) 187 #define KVM_REG_ARM_STD_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(0) 188 enum { 189 KVM_REG_ARM_STD_BIT_TRNG_V1_0 = 0, 190 }; 191 #define KVM_REG_ARM_STD_HYP_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(1) 192 enum { 193 KVM_REG_ARM_STD_HYP_BIT_PV_TIME = 0, 194 }; 195 #define KVM_REG_ARM_VENDOR_HYP_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(2) 196 enum { 197 KVM_REG_ARM_VENDOR_HYP_BIT_FUNC_FEAT = 0, 198 KVM_REG_ARM_VENDOR_HYP_BIT_PTP = 1, 199 }; 200 #define KVM_ARM_VM_SMCCC_CTRL 0 201 #define KVM_ARM_VM_SMCCC_FILTER 0 202 #define KVM_DEV_ARM_VGIC_GRP_ADDR 0 203 #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1 204 #define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2 205 #define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32 206 #define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT) 207 #define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32 208 #define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT) 209 #define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0 210 #define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) 211 #define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff) 212 #define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3 213 #define KVM_DEV_ARM_VGIC_GRP_CTRL 4 214 #define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5 215 #define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6 216 #define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7 217 #define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8 218 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10 219 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) 220 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff 221 #define VGIC_LEVEL_INFO_LINE_LEVEL 0 222 #define KVM_DEV_ARM_VGIC_CTRL_INIT 0 223 #define KVM_DEV_ARM_ITS_SAVE_TABLES 1 224 #define KVM_DEV_ARM_ITS_RESTORE_TABLES 2 225 #define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3 226 #define KVM_DEV_ARM_ITS_CTRL_RESET 4 227 #define KVM_ARM_VCPU_PMU_V3_CTRL 0 228 #define KVM_ARM_VCPU_PMU_V3_IRQ 0 229 #define KVM_ARM_VCPU_PMU_V3_INIT 1 230 #define KVM_ARM_VCPU_PMU_V3_FILTER 2 231 #define KVM_ARM_VCPU_PMU_V3_SET_PMU 3 232 #define KVM_ARM_VCPU_TIMER_CTRL 1 233 #define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0 234 #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 235 #define KVM_ARM_VCPU_TIMER_IRQ_HVTIMER 2 236 #define KVM_ARM_VCPU_TIMER_IRQ_HPTIMER 3 237 #define KVM_ARM_VCPU_PVTIME_CTRL 2 238 #define KVM_ARM_VCPU_PVTIME_IPA 0 239 #define KVM_ARM_IRQ_VCPU2_SHIFT 28 240 #define KVM_ARM_IRQ_VCPU2_MASK 0xf 241 #define KVM_ARM_IRQ_TYPE_SHIFT 24 242 #define KVM_ARM_IRQ_TYPE_MASK 0xf 243 #define KVM_ARM_IRQ_VCPU_SHIFT 16 244 #define KVM_ARM_IRQ_VCPU_MASK 0xff 245 #define KVM_ARM_IRQ_NUM_SHIFT 0 246 #define KVM_ARM_IRQ_NUM_MASK 0xffff 247 #define KVM_ARM_IRQ_TYPE_CPU 0 248 #define KVM_ARM_IRQ_TYPE_SPI 1 249 #define KVM_ARM_IRQ_TYPE_PPI 2 250 #define KVM_ARM_IRQ_CPU_IRQ 0 251 #define KVM_ARM_IRQ_CPU_FIQ 1 252 #define KVM_ARM_IRQ_GIC_MAX 127 253 #define KVM_NR_IRQCHIPS 1 254 #define KVM_PSCI_FN_BASE 0x95c1ba5e 255 #define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n)) 256 #define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0) 257 #define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1) 258 #define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2) 259 #define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3) 260 #define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS 261 #define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED 262 #define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS 263 #define KVM_PSCI_RET_DENIED PSCI_RET_DENIED 264 #define KVM_SYSTEM_EVENT_RESET_FLAG_PSCI_RESET2 (1ULL << 0) 265 #define KVM_EXIT_FAIL_ENTRY_CPU_UNSUPPORTED (1ULL << 0) 266 enum kvm_smccc_filter_action { 267 KVM_SMCCC_FILTER_HANDLE = 0, 268 KVM_SMCCC_FILTER_DENY, 269 KVM_SMCCC_FILTER_FWD_TO_USER, 270 }; 271 struct kvm_smccc_filter { 272 __u32 base; 273 __u32 nr_functions; 274 __u8 action; 275 __u8 pad[15]; 276 }; 277 #define KVM_HYPERCALL_EXIT_SMC (1U << 0) 278 #define KVM_HYPERCALL_EXIT_16BIT (1U << 1) 279 #define KVM_ARM_FEATURE_ID_RANGE_IDX(op0,op1,crn,crm,op2) ({ __u64 __op1 = (op1) & 3; __op1 -= (__op1 == 3); (__op1 << 6 | ((crm) & 7) << 3 | (op2)); }) 280 #define KVM_ARM_FEATURE_ID_RANGE 0 281 #define KVM_ARM_FEATURE_ID_RANGE_SIZE (3 * 8 * 8) 282 struct reg_mask_range { 283 __u64 addr; 284 __u32 range; 285 __u32 reserved[13]; 286 }; 287 #endif 288 #endif 289