1 /*
2  * This file is auto-generated. Modifications will be lost.
3  *
4  * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/
5  * for more information.
6  */
7 #ifndef _UAPI_LINUX_PERF_EVENT_H
8 #define _UAPI_LINUX_PERF_EVENT_H
9 #include <linux/types.h>
10 #include <linux/ioctl.h>
11 #include <asm/byteorder.h>
12 enum perf_type_id {
13   PERF_TYPE_HARDWARE = 0,
14   PERF_TYPE_SOFTWARE = 1,
15   PERF_TYPE_TRACEPOINT = 2,
16   PERF_TYPE_HW_CACHE = 3,
17   PERF_TYPE_RAW = 4,
18   PERF_TYPE_BREAKPOINT = 5,
19   PERF_TYPE_MAX,
20 };
21 #define PERF_PMU_TYPE_SHIFT 32
22 #define PERF_HW_EVENT_MASK 0xffffffff
23 enum perf_hw_id {
24   PERF_COUNT_HW_CPU_CYCLES = 0,
25   PERF_COUNT_HW_INSTRUCTIONS = 1,
26   PERF_COUNT_HW_CACHE_REFERENCES = 2,
27   PERF_COUNT_HW_CACHE_MISSES = 3,
28   PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4,
29   PERF_COUNT_HW_BRANCH_MISSES = 5,
30   PERF_COUNT_HW_BUS_CYCLES = 6,
31   PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7,
32   PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8,
33   PERF_COUNT_HW_REF_CPU_CYCLES = 9,
34   PERF_COUNT_HW_MAX,
35 };
36 enum perf_hw_cache_id {
37   PERF_COUNT_HW_CACHE_L1D = 0,
38   PERF_COUNT_HW_CACHE_L1I = 1,
39   PERF_COUNT_HW_CACHE_LL = 2,
40   PERF_COUNT_HW_CACHE_DTLB = 3,
41   PERF_COUNT_HW_CACHE_ITLB = 4,
42   PERF_COUNT_HW_CACHE_BPU = 5,
43   PERF_COUNT_HW_CACHE_NODE = 6,
44   PERF_COUNT_HW_CACHE_MAX,
45 };
46 enum perf_hw_cache_op_id {
47   PERF_COUNT_HW_CACHE_OP_READ = 0,
48   PERF_COUNT_HW_CACHE_OP_WRITE = 1,
49   PERF_COUNT_HW_CACHE_OP_PREFETCH = 2,
50   PERF_COUNT_HW_CACHE_OP_MAX,
51 };
52 enum perf_hw_cache_op_result_id {
53   PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0,
54   PERF_COUNT_HW_CACHE_RESULT_MISS = 1,
55   PERF_COUNT_HW_CACHE_RESULT_MAX,
56 };
57 enum perf_sw_ids {
58   PERF_COUNT_SW_CPU_CLOCK = 0,
59   PERF_COUNT_SW_TASK_CLOCK = 1,
60   PERF_COUNT_SW_PAGE_FAULTS = 2,
61   PERF_COUNT_SW_CONTEXT_SWITCHES = 3,
62   PERF_COUNT_SW_CPU_MIGRATIONS = 4,
63   PERF_COUNT_SW_PAGE_FAULTS_MIN = 5,
64   PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6,
65   PERF_COUNT_SW_ALIGNMENT_FAULTS = 7,
66   PERF_COUNT_SW_EMULATION_FAULTS = 8,
67   PERF_COUNT_SW_DUMMY = 9,
68   PERF_COUNT_SW_BPF_OUTPUT = 10,
69   PERF_COUNT_SW_CGROUP_SWITCHES = 11,
70   PERF_COUNT_SW_MAX,
71 };
72 enum perf_event_sample_format {
73   PERF_SAMPLE_IP = 1U << 0,
74   PERF_SAMPLE_TID = 1U << 1,
75   PERF_SAMPLE_TIME = 1U << 2,
76   PERF_SAMPLE_ADDR = 1U << 3,
77   PERF_SAMPLE_READ = 1U << 4,
78   PERF_SAMPLE_CALLCHAIN = 1U << 5,
79   PERF_SAMPLE_ID = 1U << 6,
80   PERF_SAMPLE_CPU = 1U << 7,
81   PERF_SAMPLE_PERIOD = 1U << 8,
82   PERF_SAMPLE_STREAM_ID = 1U << 9,
83   PERF_SAMPLE_RAW = 1U << 10,
84   PERF_SAMPLE_BRANCH_STACK = 1U << 11,
85   PERF_SAMPLE_REGS_USER = 1U << 12,
86   PERF_SAMPLE_STACK_USER = 1U << 13,
87   PERF_SAMPLE_WEIGHT = 1U << 14,
88   PERF_SAMPLE_DATA_SRC = 1U << 15,
89   PERF_SAMPLE_IDENTIFIER = 1U << 16,
90   PERF_SAMPLE_TRANSACTION = 1U << 17,
91   PERF_SAMPLE_REGS_INTR = 1U << 18,
92   PERF_SAMPLE_PHYS_ADDR = 1U << 19,
93   PERF_SAMPLE_AUX = 1U << 20,
94   PERF_SAMPLE_CGROUP = 1U << 21,
95   PERF_SAMPLE_DATA_PAGE_SIZE = 1U << 22,
96   PERF_SAMPLE_CODE_PAGE_SIZE = 1U << 23,
97   PERF_SAMPLE_WEIGHT_STRUCT = 1U << 24,
98   PERF_SAMPLE_MAX = 1U << 25,
99 };
100 #define PERF_SAMPLE_WEIGHT_TYPE (PERF_SAMPLE_WEIGHT | PERF_SAMPLE_WEIGHT_STRUCT)
101 enum perf_branch_sample_type_shift {
102   PERF_SAMPLE_BRANCH_USER_SHIFT = 0,
103   PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1,
104   PERF_SAMPLE_BRANCH_HV_SHIFT = 2,
105   PERF_SAMPLE_BRANCH_ANY_SHIFT = 3,
106   PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4,
107   PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5,
108   PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6,
109   PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7,
110   PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8,
111   PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9,
112   PERF_SAMPLE_BRANCH_COND_SHIFT = 10,
113   PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11,
114   PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12,
115   PERF_SAMPLE_BRANCH_CALL_SHIFT = 13,
116   PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14,
117   PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15,
118   PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16,
119   PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT = 17,
120   PERF_SAMPLE_BRANCH_PRIV_SAVE_SHIFT = 18,
121   PERF_SAMPLE_BRANCH_COUNTERS_SHIFT = 19,
122   PERF_SAMPLE_BRANCH_MAX_SHIFT
123 };
124 enum perf_branch_sample_type {
125   PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT,
126   PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT,
127   PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT,
128   PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT,
129   PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT,
130   PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT,
131   PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT,
132   PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT,
133   PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT,
134   PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT,
135   PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT,
136   PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT,
137   PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT,
138   PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT,
139   PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT,
140   PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT,
141   PERF_SAMPLE_BRANCH_TYPE_SAVE = 1U << PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT,
142   PERF_SAMPLE_BRANCH_HW_INDEX = 1U << PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT,
143   PERF_SAMPLE_BRANCH_PRIV_SAVE = 1U << PERF_SAMPLE_BRANCH_PRIV_SAVE_SHIFT,
144   PERF_SAMPLE_BRANCH_COUNTERS = 1U << PERF_SAMPLE_BRANCH_COUNTERS_SHIFT,
145   PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT,
146 };
147 enum {
148   PERF_BR_UNKNOWN = 0,
149   PERF_BR_COND = 1,
150   PERF_BR_UNCOND = 2,
151   PERF_BR_IND = 3,
152   PERF_BR_CALL = 4,
153   PERF_BR_IND_CALL = 5,
154   PERF_BR_RET = 6,
155   PERF_BR_SYSCALL = 7,
156   PERF_BR_SYSRET = 8,
157   PERF_BR_COND_CALL = 9,
158   PERF_BR_COND_RET = 10,
159   PERF_BR_ERET = 11,
160   PERF_BR_IRQ = 12,
161   PERF_BR_SERROR = 13,
162   PERF_BR_NO_TX = 14,
163   PERF_BR_EXTEND_ABI = 15,
164   PERF_BR_MAX,
165 };
166 enum {
167   PERF_BR_SPEC_NA = 0,
168   PERF_BR_SPEC_WRONG_PATH = 1,
169   PERF_BR_NON_SPEC_CORRECT_PATH = 2,
170   PERF_BR_SPEC_CORRECT_PATH = 3,
171   PERF_BR_SPEC_MAX,
172 };
173 enum {
174   PERF_BR_NEW_FAULT_ALGN = 0,
175   PERF_BR_NEW_FAULT_DATA = 1,
176   PERF_BR_NEW_FAULT_INST = 2,
177   PERF_BR_NEW_ARCH_1 = 3,
178   PERF_BR_NEW_ARCH_2 = 4,
179   PERF_BR_NEW_ARCH_3 = 5,
180   PERF_BR_NEW_ARCH_4 = 6,
181   PERF_BR_NEW_ARCH_5 = 7,
182   PERF_BR_NEW_MAX,
183 };
184 enum {
185   PERF_BR_PRIV_UNKNOWN = 0,
186   PERF_BR_PRIV_USER = 1,
187   PERF_BR_PRIV_KERNEL = 2,
188   PERF_BR_PRIV_HV = 3,
189 };
190 #define PERF_BR_ARM64_FIQ PERF_BR_NEW_ARCH_1
191 #define PERF_BR_ARM64_DEBUG_HALT PERF_BR_NEW_ARCH_2
192 #define PERF_BR_ARM64_DEBUG_EXIT PERF_BR_NEW_ARCH_3
193 #define PERF_BR_ARM64_DEBUG_INST PERF_BR_NEW_ARCH_4
194 #define PERF_BR_ARM64_DEBUG_DATA PERF_BR_NEW_ARCH_5
195 #define PERF_SAMPLE_BRANCH_PLM_ALL (PERF_SAMPLE_BRANCH_USER | PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_HV)
196 enum perf_sample_regs_abi {
197   PERF_SAMPLE_REGS_ABI_NONE = 0,
198   PERF_SAMPLE_REGS_ABI_32 = 1,
199   PERF_SAMPLE_REGS_ABI_64 = 2,
200 };
201 enum {
202   PERF_TXN_ELISION = (1 << 0),
203   PERF_TXN_TRANSACTION = (1 << 1),
204   PERF_TXN_SYNC = (1 << 2),
205   PERF_TXN_ASYNC = (1 << 3),
206   PERF_TXN_RETRY = (1 << 4),
207   PERF_TXN_CONFLICT = (1 << 5),
208   PERF_TXN_CAPACITY_WRITE = (1 << 6),
209   PERF_TXN_CAPACITY_READ = (1 << 7),
210   PERF_TXN_MAX = (1 << 8),
211   PERF_TXN_ABORT_MASK = (0xffffffffULL << 32),
212   PERF_TXN_ABORT_SHIFT = 32,
213 };
214 enum perf_event_read_format {
215   PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0,
216   PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1,
217   PERF_FORMAT_ID = 1U << 2,
218   PERF_FORMAT_GROUP = 1U << 3,
219   PERF_FORMAT_LOST = 1U << 4,
220   PERF_FORMAT_MAX = 1U << 5,
221 };
222 #define PERF_ATTR_SIZE_VER0 64
223 #define PERF_ATTR_SIZE_VER1 72
224 #define PERF_ATTR_SIZE_VER2 80
225 #define PERF_ATTR_SIZE_VER3 96
226 #define PERF_ATTR_SIZE_VER4 104
227 #define PERF_ATTR_SIZE_VER5 112
228 #define PERF_ATTR_SIZE_VER6 120
229 #define PERF_ATTR_SIZE_VER7 128
230 #define PERF_ATTR_SIZE_VER8 136
231 struct perf_event_attr {
232   __u32 type;
233   __u32 size;
234   __u64 config;
235   union {
236     __u64 sample_period;
237     __u64 sample_freq;
238   };
239   __u64 sample_type;
240   __u64 read_format;
241   __u64 disabled : 1, inherit : 1, pinned : 1, exclusive : 1, exclude_user : 1, exclude_kernel : 1, exclude_hv : 1, exclude_idle : 1, mmap : 1, comm : 1, freq : 1, inherit_stat : 1, enable_on_exec : 1, task : 1, watermark : 1, precise_ip : 2, mmap_data : 1, sample_id_all : 1, exclude_host : 1, exclude_guest : 1, exclude_callchain_kernel : 1, exclude_callchain_user : 1, mmap2 : 1, comm_exec : 1, use_clockid : 1, context_switch : 1, write_backward : 1, namespaces : 1, ksymbol : 1, bpf_event : 1, aux_output : 1, cgroup : 1, text_poke : 1, build_id : 1, inherit_thread : 1, remove_on_exec : 1, sigtrap : 1, __reserved_1 : 26;
242   union {
243     __u32 wakeup_events;
244     __u32 wakeup_watermark;
245   };
246   __u32 bp_type;
247   union {
248     __u64 bp_addr;
249     __u64 kprobe_func;
250     __u64 uprobe_path;
251     __u64 config1;
252   };
253   union {
254     __u64 bp_len;
255     __u64 kprobe_addr;
256     __u64 probe_offset;
257     __u64 config2;
258   };
259   __u64 branch_sample_type;
260   __u64 sample_regs_user;
261   __u32 sample_stack_user;
262   __s32 clockid;
263   __u64 sample_regs_intr;
264   __u32 aux_watermark;
265   __u16 sample_max_stack;
266   __u16 __reserved_2;
267   __u32 aux_sample_size;
268   __u32 __reserved_3;
269   __u64 sig_data;
270   __u64 config3;
271 };
272 struct perf_event_query_bpf {
273   __u32 ids_len;
274   __u32 prog_cnt;
275   __u32 ids[];
276 };
277 #define PERF_EVENT_IOC_ENABLE _IO('$', 0)
278 #define PERF_EVENT_IOC_DISABLE _IO('$', 1)
279 #define PERF_EVENT_IOC_REFRESH _IO('$', 2)
280 #define PERF_EVENT_IOC_RESET _IO('$', 3)
281 #define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64)
282 #define PERF_EVENT_IOC_SET_OUTPUT _IO('$', 5)
283 #define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *)
284 #define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *)
285 #define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32)
286 #define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32)
287 #define PERF_EVENT_IOC_QUERY_BPF _IOWR('$', 10, struct perf_event_query_bpf *)
288 #define PERF_EVENT_IOC_MODIFY_ATTRIBUTES _IOW('$', 11, struct perf_event_attr *)
289 enum perf_event_ioc_flags {
290   PERF_IOC_FLAG_GROUP = 1U << 0,
291 };
292 struct perf_event_mmap_page {
293   __u32 version;
294   __u32 compat_version;
295   __u32 lock;
296   __u32 index;
297   __s64 offset;
298   __u64 time_enabled;
299   __u64 time_running;
300   union {
301     __u64 capabilities;
302     struct {
303       __u64 cap_bit0 : 1, cap_bit0_is_deprecated : 1, cap_user_rdpmc : 1, cap_user_time : 1, cap_user_time_zero : 1, cap_user_time_short : 1, cap_____res : 58;
304     };
305   };
306   __u16 pmc_width;
307   __u16 time_shift;
308   __u32 time_mult;
309   __u64 time_offset;
310   __u64 time_zero;
311   __u32 size;
312   __u32 __reserved_1;
313   __u64 time_cycles;
314   __u64 time_mask;
315   __u8 __reserved[116 * 8];
316   __u64 data_head;
317   __u64 data_tail;
318   __u64 data_offset;
319   __u64 data_size;
320   __u64 aux_head;
321   __u64 aux_tail;
322   __u64 aux_offset;
323   __u64 aux_size;
324 };
325 #define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0)
326 #define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0)
327 #define PERF_RECORD_MISC_KERNEL (1 << 0)
328 #define PERF_RECORD_MISC_USER (2 << 0)
329 #define PERF_RECORD_MISC_HYPERVISOR (3 << 0)
330 #define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0)
331 #define PERF_RECORD_MISC_GUEST_USER (5 << 0)
332 #define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT (1 << 12)
333 #define PERF_RECORD_MISC_MMAP_DATA (1 << 13)
334 #define PERF_RECORD_MISC_COMM_EXEC (1 << 13)
335 #define PERF_RECORD_MISC_FORK_EXEC (1 << 13)
336 #define PERF_RECORD_MISC_SWITCH_OUT (1 << 13)
337 #define PERF_RECORD_MISC_EXACT_IP (1 << 14)
338 #define PERF_RECORD_MISC_SWITCH_OUT_PREEMPT (1 << 14)
339 #define PERF_RECORD_MISC_MMAP_BUILD_ID (1 << 14)
340 #define PERF_RECORD_MISC_EXT_RESERVED (1 << 15)
341 struct perf_event_header {
342   __u32 type;
343   __u16 misc;
344   __u16 size;
345 };
346 struct perf_ns_link_info {
347   __u64 dev;
348   __u64 ino;
349 };
350 enum {
351   NET_NS_INDEX = 0,
352   UTS_NS_INDEX = 1,
353   IPC_NS_INDEX = 2,
354   PID_NS_INDEX = 3,
355   USER_NS_INDEX = 4,
356   MNT_NS_INDEX = 5,
357   CGROUP_NS_INDEX = 6,
358   NR_NAMESPACES,
359 };
360 enum perf_event_type {
361   PERF_RECORD_MMAP = 1,
362   PERF_RECORD_LOST = 2,
363   PERF_RECORD_COMM = 3,
364   PERF_RECORD_EXIT = 4,
365   PERF_RECORD_THROTTLE = 5,
366   PERF_RECORD_UNTHROTTLE = 6,
367   PERF_RECORD_FORK = 7,
368   PERF_RECORD_READ = 8,
369   PERF_RECORD_SAMPLE = 9,
370   PERF_RECORD_MMAP2 = 10,
371   PERF_RECORD_AUX = 11,
372   PERF_RECORD_ITRACE_START = 12,
373   PERF_RECORD_LOST_SAMPLES = 13,
374   PERF_RECORD_SWITCH = 14,
375   PERF_RECORD_SWITCH_CPU_WIDE = 15,
376   PERF_RECORD_NAMESPACES = 16,
377   PERF_RECORD_KSYMBOL = 17,
378   PERF_RECORD_BPF_EVENT = 18,
379   PERF_RECORD_CGROUP = 19,
380   PERF_RECORD_TEXT_POKE = 20,
381   PERF_RECORD_AUX_OUTPUT_HW_ID = 21,
382   PERF_RECORD_MAX,
383 };
384 enum perf_record_ksymbol_type {
385   PERF_RECORD_KSYMBOL_TYPE_UNKNOWN = 0,
386   PERF_RECORD_KSYMBOL_TYPE_BPF = 1,
387   PERF_RECORD_KSYMBOL_TYPE_OOL = 2,
388   PERF_RECORD_KSYMBOL_TYPE_MAX
389 };
390 #define PERF_RECORD_KSYMBOL_FLAGS_UNREGISTER (1 << 0)
391 enum perf_bpf_event_type {
392   PERF_BPF_EVENT_UNKNOWN = 0,
393   PERF_BPF_EVENT_PROG_LOAD = 1,
394   PERF_BPF_EVENT_PROG_UNLOAD = 2,
395   PERF_BPF_EVENT_MAX,
396 };
397 #define PERF_MAX_STACK_DEPTH 127
398 #define PERF_MAX_CONTEXTS_PER_STACK 8
399 enum perf_callchain_context {
400   PERF_CONTEXT_HV = (__u64) - 32,
401   PERF_CONTEXT_KERNEL = (__u64) - 128,
402   PERF_CONTEXT_USER = (__u64) - 512,
403   PERF_CONTEXT_GUEST = (__u64) - 2048,
404   PERF_CONTEXT_GUEST_KERNEL = (__u64) - 2176,
405   PERF_CONTEXT_GUEST_USER = (__u64) - 2560,
406   PERF_CONTEXT_MAX = (__u64) - 4095,
407 };
408 #define PERF_AUX_FLAG_TRUNCATED 0x01
409 #define PERF_AUX_FLAG_OVERWRITE 0x02
410 #define PERF_AUX_FLAG_PARTIAL 0x04
411 #define PERF_AUX_FLAG_COLLISION 0x08
412 #define PERF_AUX_FLAG_PMU_FORMAT_TYPE_MASK 0xff00
413 #define PERF_AUX_FLAG_CORESIGHT_FORMAT_CORESIGHT 0x0000
414 #define PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW 0x0100
415 #define PERF_FLAG_FD_NO_GROUP (1UL << 0)
416 #define PERF_FLAG_FD_OUTPUT (1UL << 1)
417 #define PERF_FLAG_PID_CGROUP (1UL << 2)
418 #define PERF_FLAG_FD_CLOEXEC (1UL << 3)
419 #ifdef __LITTLE_ENDIAN_BITFIELD
420 union perf_mem_data_src {
421   __u64 val;
422   struct {
423     __u64 mem_op : 5, mem_lvl : 14, mem_snoop : 5, mem_lock : 2, mem_dtlb : 7, mem_lvl_num : 4, mem_remote : 1, mem_snoopx : 2, mem_blk : 3, mem_hops : 3, mem_rsvd : 18;
424   };
425 };
426 #elif defined(__BIG_ENDIAN_BITFIELD)
427 union perf_mem_data_src {
428   __u64 val;
429   struct {
430     __u64 mem_rsvd : 18, mem_hops : 3, mem_blk : 3, mem_snoopx : 2, mem_remote : 1, mem_lvl_num : 4, mem_dtlb : 7, mem_lock : 2, mem_snoop : 5, mem_lvl : 14, mem_op : 5;
431   };
432 };
433 #else
434 #error "Unknown endianness"
435 #endif
436 #define PERF_MEM_OP_NA 0x01
437 #define PERF_MEM_OP_LOAD 0x02
438 #define PERF_MEM_OP_STORE 0x04
439 #define PERF_MEM_OP_PFETCH 0x08
440 #define PERF_MEM_OP_EXEC 0x10
441 #define PERF_MEM_OP_SHIFT 0
442 #define PERF_MEM_LVL_NA 0x01
443 #define PERF_MEM_LVL_HIT 0x02
444 #define PERF_MEM_LVL_MISS 0x04
445 #define PERF_MEM_LVL_L1 0x08
446 #define PERF_MEM_LVL_LFB 0x10
447 #define PERF_MEM_LVL_L2 0x20
448 #define PERF_MEM_LVL_L3 0x40
449 #define PERF_MEM_LVL_LOC_RAM 0x80
450 #define PERF_MEM_LVL_REM_RAM1 0x100
451 #define PERF_MEM_LVL_REM_RAM2 0x200
452 #define PERF_MEM_LVL_REM_CCE1 0x400
453 #define PERF_MEM_LVL_REM_CCE2 0x800
454 #define PERF_MEM_LVL_IO 0x1000
455 #define PERF_MEM_LVL_UNC 0x2000
456 #define PERF_MEM_LVL_SHIFT 5
457 #define PERF_MEM_REMOTE_REMOTE 0x01
458 #define PERF_MEM_REMOTE_SHIFT 37
459 #define PERF_MEM_LVLNUM_L1 0x01
460 #define PERF_MEM_LVLNUM_L2 0x02
461 #define PERF_MEM_LVLNUM_L3 0x03
462 #define PERF_MEM_LVLNUM_L4 0x04
463 #define PERF_MEM_LVLNUM_UNC 0x08
464 #define PERF_MEM_LVLNUM_CXL 0x09
465 #define PERF_MEM_LVLNUM_IO 0x0a
466 #define PERF_MEM_LVLNUM_ANY_CACHE 0x0b
467 #define PERF_MEM_LVLNUM_LFB 0x0c
468 #define PERF_MEM_LVLNUM_RAM 0x0d
469 #define PERF_MEM_LVLNUM_PMEM 0x0e
470 #define PERF_MEM_LVLNUM_NA 0x0f
471 #define PERF_MEM_LVLNUM_SHIFT 33
472 #define PERF_MEM_SNOOP_NA 0x01
473 #define PERF_MEM_SNOOP_NONE 0x02
474 #define PERF_MEM_SNOOP_HIT 0x04
475 #define PERF_MEM_SNOOP_MISS 0x08
476 #define PERF_MEM_SNOOP_HITM 0x10
477 #define PERF_MEM_SNOOP_SHIFT 19
478 #define PERF_MEM_SNOOPX_FWD 0x01
479 #define PERF_MEM_SNOOPX_PEER 0x02
480 #define PERF_MEM_SNOOPX_SHIFT 38
481 #define PERF_MEM_LOCK_NA 0x01
482 #define PERF_MEM_LOCK_LOCKED 0x02
483 #define PERF_MEM_LOCK_SHIFT 24
484 #define PERF_MEM_TLB_NA 0x01
485 #define PERF_MEM_TLB_HIT 0x02
486 #define PERF_MEM_TLB_MISS 0x04
487 #define PERF_MEM_TLB_L1 0x08
488 #define PERF_MEM_TLB_L2 0x10
489 #define PERF_MEM_TLB_WK 0x20
490 #define PERF_MEM_TLB_OS 0x40
491 #define PERF_MEM_TLB_SHIFT 26
492 #define PERF_MEM_BLK_NA 0x01
493 #define PERF_MEM_BLK_DATA 0x02
494 #define PERF_MEM_BLK_ADDR 0x04
495 #define PERF_MEM_BLK_SHIFT 40
496 #define PERF_MEM_HOPS_0 0x01
497 #define PERF_MEM_HOPS_1 0x02
498 #define PERF_MEM_HOPS_2 0x03
499 #define PERF_MEM_HOPS_3 0x04
500 #define PERF_MEM_HOPS_SHIFT 43
501 #define PERF_MEM_S(a,s) (((__u64) PERF_MEM_ ##a ##_ ##s) << PERF_MEM_ ##a ##_SHIFT)
502 struct perf_branch_entry {
503   __u64 from;
504   __u64 to;
505   __u64 mispred : 1, predicted : 1, in_tx : 1, abort : 1, cycles : 16, type : 4, spec : 2, new_type : 4, priv : 3, reserved : 31;
506 };
507 #define PERF_BRANCH_ENTRY_INFO_BITS_MAX 33
508 union perf_sample_weight {
509   __u64 full;
510 #ifdef __LITTLE_ENDIAN_BITFIELD
511   struct {
512     __u32 var1_dw;
513     __u16 var2_w;
514     __u16 var3_w;
515   };
516 #elif defined(__BIG_ENDIAN_BITFIELD)
517   struct {
518     __u16 var3_w;
519     __u16 var2_w;
520     __u32 var1_dw;
521   };
522 #else
523 #error "Unknown endianness"
524 #endif
525 };
526 #endif
527