1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef _UAPI_LINUX_FPGA_DFL_H 8 #define _UAPI_LINUX_FPGA_DFL_H 9 #include <linux/types.h> 10 #include <linux/ioctl.h> 11 #define DFL_FPGA_API_VERSION 0 12 #define DFL_FPGA_MAGIC 0xB6 13 #define DFL_FPGA_BASE 0 14 #define DFL_PORT_BASE 0x40 15 #define DFL_FME_BASE 0x80 16 #define DFL_FPGA_GET_API_VERSION _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0) 17 #define DFL_FPGA_CHECK_EXTENSION _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1) 18 #define DFL_FPGA_PORT_RESET _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0) 19 struct dfl_fpga_port_info { 20 __u32 argsz; 21 __u32 flags; 22 __u32 num_regions; 23 __u32 num_umsgs; 24 }; 25 #define DFL_FPGA_PORT_GET_INFO _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1) 26 struct dfl_fpga_port_region_info { 27 __u32 argsz; 28 __u32 flags; 29 #define DFL_PORT_REGION_READ (1 << 0) 30 #define DFL_PORT_REGION_WRITE (1 << 1) 31 #define DFL_PORT_REGION_MMAP (1 << 2) 32 __u32 index; 33 #define DFL_PORT_REGION_INDEX_AFU 0 34 #define DFL_PORT_REGION_INDEX_STP 1 35 __u32 padding; 36 __u64 size; 37 __u64 offset; 38 }; 39 #define DFL_FPGA_PORT_GET_REGION_INFO _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 2) 40 struct dfl_fpga_port_dma_map { 41 __u32 argsz; 42 __u32 flags; 43 __u64 user_addr; 44 __u64 length; 45 __u64 iova; 46 }; 47 #define DFL_FPGA_PORT_DMA_MAP _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 3) 48 struct dfl_fpga_port_dma_unmap { 49 __u32 argsz; 50 __u32 flags; 51 __u64 iova; 52 }; 53 #define DFL_FPGA_PORT_DMA_UNMAP _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 4) 54 struct dfl_fpga_irq_set { 55 __u32 start; 56 __u32 count; 57 __s32 evtfds[]; 58 }; 59 #define DFL_FPGA_PORT_ERR_GET_IRQ_NUM _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 5, __u32) 60 #define DFL_FPGA_PORT_ERR_SET_IRQ _IOW(DFL_FPGA_MAGIC, DFL_PORT_BASE + 6, struct dfl_fpga_irq_set) 61 #define DFL_FPGA_PORT_UINT_GET_IRQ_NUM _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 7, __u32) 62 #define DFL_FPGA_PORT_UINT_SET_IRQ _IOW(DFL_FPGA_MAGIC, DFL_PORT_BASE + 8, struct dfl_fpga_irq_set) 63 struct dfl_fpga_fme_port_pr { 64 __u32 argsz; 65 __u32 flags; 66 __u32 port_id; 67 __u32 buffer_size; 68 __u64 buffer_address; 69 }; 70 #define DFL_FPGA_FME_PORT_PR _IO(DFL_FPGA_MAGIC, DFL_FME_BASE + 0) 71 #define DFL_FPGA_FME_PORT_RELEASE _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 1, int) 72 #define DFL_FPGA_FME_PORT_ASSIGN _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 2, int) 73 #define DFL_FPGA_FME_ERR_GET_IRQ_NUM _IOR(DFL_FPGA_MAGIC, DFL_FME_BASE + 3, __u32) 74 #define DFL_FPGA_FME_ERR_SET_IRQ _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 4, struct dfl_fpga_irq_set) 75 #endif 76