Searched refs:SPI (Results 1 – 18 of 18) sorted by relevance
96 static struct StmSpi *SPI; variable384 (void)SPI->DR; in blResetRxData()385 while (!(SPI->SR & 1)); in blResetRxData()386 (void)SPI->DR; in blResetRxData()391 while (!(SPI->SR & 2)); in blSpiTxRxByte()392 SPI->DR = val; in blSpiTxRxByte()393 while (!(SPI->SR & 1)); in blSpiTxRxByte()394 return SPI->DR; in blSpiTxRxByte()413 SPI = (struct StmSpi*)SPI1_BASE; in blSetup()461 SPI->CR1 = 0x00000040; //spi is on, configured same as bootloader would in blConfigIo()[all …]
533 void SPI##_n##_IRQHandler(); \534 void SPI##_n##_IRQHandler() \
23 Those macros define specific configuration that is platform dependent (SPI bus,24 SPI frequency, etc).34 #define LSM6DSM_SPI_SLAVE_BUS_ID 1 /* SPI bus ID, on S…35 #define LSM6DSM_SPI_SLAVE_FREQUENCY_HZ 8000000 /* SPI frequency in…36 #define LSM6DSM_SPI_SLAVE_CS_GPIO GPIO_PB(12) /* SPI NSS pin, on …
39 # enables CHPP for SPI port40 …nt the *chpp* lines below (and comment gnss_device-data_port_kepslim_present above) to use SPI+CHPP
44 # enables CHPP for SPI port45 …nt the *chpp* lines below (and comment gnss_device-data_port_kepslim_present above) to use SPI+CHPP
16 # SecureElement SPI device
18 # SecureElement SPI device
20 # SecureElement SPI device
36 # SecureElement SPI device
53 # Allow secure_element group to read / write ST33 SPI state
35 # Allow secure_element group to read / write ST33 SPI state
45 # Allow secure_element group to read / write ST33 SPI state
136 # Allow secure_element group to read / write ST33 SPI state