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Searched refs:TIM2 (Results 1 – 2 of 2) sorted by relevance

/device/google/contexthub/firmware/os/platform/stm32/
Dplatform.c95 #define TIM2 ((struct StmTim*)TIM2_BASE) macro
287 TIM2->CR1 = (TIM2->CR1 &~ 0x03E1) | 0x0010; //count down mode with no clock division, disabled in platInitialize()
288 TIM2->PSC = 15; // prescale by 16, so that at 16MHz CPU clock, we get 1MHz timer in platInitialize()
289 TIM2->DIER |= 1; // interrupt when updated (underflowed) in platInitialize()
290 TIM2->ARR = 0xffffffff; in platInitialize()
291 TIM2->EGR = TIM_EGR_UG; // force a reload of the prescaler in platInitialize()
Dcrt_stm32.c65 VECI(TIM2);