Searched refs:vemul (Results 1 – 2 of 2) sorted by relevance
630 int vemul = SignExtend<3>(vlmul); in TestVleXX() local631 vemul += vsew; // Multiply by SEW. in TestVleXX()632 vemul -= veew; // Divide by EEW. in TestVleXX()633 if (vemul < -3 || vemul > 3) { in TestVleXX()646 if (vemul == 2) { in TestVleXX()666 if (vemul >= 0) { in TestVleXX()667 for (size_t index = 0; index < 1 << vemul; ++index) { in TestVleXX()668 if (index == 0 && vemul == 2) { in TestVleXX()675 } else if (index == 2 && vemul == 2) { in TestVleXX()683 } else if (index == 3 && vemul == 2 && vta) { in TestVleXX()[all …]
612 auto vemul = Decoder::SignExtend<3>(vtype & 0b111); in OpVector() local613 vemul -= ((vtype >> 3) & 0b111); // Divide by SEW. in OpVector()614 vemul += in OpVector()616 if (vemul < -3 || vemul > 3) [[unlikely]] { in OpVector()622 if ((vemul > 0) && ((args.nf + 1) * (1 << vemul) > 8)) { in OpVector()626 args, static_cast<VectorRegisterGroupMultiplier>(vemul & 0b111), vtype, extra_args...); in OpVector()