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/frameworks/libs/binary_translation/lite_translator/riscv64_to_x86_64/
Dallocator_tests.cc28 Allocator<x86_64::Assembler::Register> allocator; in TEST()
29 EXPECT_EQ(allocator.Alloc().value(), x86_64::Assembler::rbx); in TEST()
30 EXPECT_EQ(allocator.Alloc().value(), x86_64::Assembler::rsi); in TEST()
31 EXPECT_EQ(allocator.Alloc().value(), x86_64::Assembler::rdi); in TEST()
32 EXPECT_EQ(allocator.Alloc().value(), x86_64::Assembler::r8); in TEST()
33 EXPECT_EQ(allocator.Alloc().value(), x86_64::Assembler::r9); in TEST()
34 EXPECT_EQ(allocator.Alloc().value(), x86_64::Assembler::r10); in TEST()
35 EXPECT_EQ(allocator.Alloc().value(), x86_64::Assembler::r11); in TEST()
36 EXPECT_EQ(allocator.Alloc().value(), x86_64::Assembler::r12); in TEST()
37 EXPECT_EQ(allocator.Alloc().value(), x86_64::Assembler::r13); in TEST()
[all …]
Dallocator.h38 inline constexpr x86_64::Assembler::Register kAllocatableRegisters<x86_64::Assembler::Register>[] =
39 {x86_64::Assembler::rbx,
40 x86_64::Assembler::rsi,
41 x86_64::Assembler::rdi,
42 x86_64::Assembler::r8,
43 x86_64::Assembler::r9,
44 x86_64::Assembler::r10,
45 x86_64::Assembler::r11,
46 x86_64::Assembler::r12,
47 x86_64::Assembler::r13,
[all …]
Dcall_intrinsic.h32 constexpr x86_64::Assembler::Register kCallerSavedRegs[] = {
33 x86_64::Assembler::rax,
34 x86_64::Assembler::rcx,
35 x86_64::Assembler::rdx,
36 x86_64::Assembler::rdi,
37 x86_64::Assembler::rsi,
38 x86_64::Assembler::r8,
39 x86_64::Assembler::r9,
40 x86_64::Assembler::r10,
41 x86_64::Assembler::r11,
[all …]
Dregister_maintainer_test.cc28 RegMaintainer<x86_64::Assembler::Register> maintainer = in TEST()
29 RegMaintainer<x86_64::Assembler::Register>(); in TEST()
32 maintainer.Map(x86_64::Assembler::rbx); in TEST()
34 EXPECT_EQ(maintainer.GetMapped(), x86_64::Assembler::rbx); in TEST()
41 auto maintainer = RegisterFileMaintainer<x86_64::Assembler::Register, 16>(); in TEST()
44 maintainer.Map(15, x86_64::Assembler::rbp); in TEST()
46 EXPECT_EQ(maintainer.GetMapped(15), x86_64::Assembler::rbp); in TEST()
53 auto maintainer = RegisterFileMaintainer<x86_64::Assembler::XMMRegister, 16>(); in TEST()
56 maintainer.Map(15, x86_64::Assembler::xmm11); in TEST()
58 EXPECT_EQ(maintainer.GetMapped(15), x86_64::Assembler::xmm11); in TEST()
/frameworks/libs/binary_translation/backend/x86_64/
Dmachine_ir_exec_test.cc46 void Init(x86_64::MachineIR& machine_ir) { in Init()
54 EXPECT_EQ(x86_64::CheckMachineIR(machine_ir), x86_64::kMachineIRCheckSuccess); in Init()
124 x86_64::MachineIR machine_ir(&arena); in TEST()
126 x86_64::MachineIRBuilder builder(&machine_ir); in TEST()
130 builder.Gen<x86_64::MovqRegImm>(x86_64::kMachineRegRBP, reinterpret_cast<uintptr_t>(&data)); in TEST()
133 builder.Gen<x86_64::MovqRegMemBaseDisp>( in TEST()
134 x86_64::kMachineRegRAX, x86_64::kMachineRegRBP, offsetof(Data, x)); in TEST()
135 builder.Gen<x86_64::MovqMemBaseDispReg>( in TEST()
136 x86_64::kMachineRegRBP, offsetof(Data, y), x86_64::kMachineRegRAX); in TEST()
150 x86_64::MachineIR machine_ir(&arena); in TEST()
[all …]
Dmachine_ir_check_test.cc34 x86_64::MachineIR machine_ir(&arena); in TEST()
46 EXPECT_EQ(x86_64::CheckMachineIR(machine_ir), x86_64::kMachineIRCheckFail); in TEST()
51 x86_64::MachineIR machine_ir(&arena); in TEST()
63 EXPECT_EQ(x86_64::CheckMachineIR(machine_ir), x86_64::kMachineIRCheckFail); in TEST()
68 x86_64::MachineIR machine_ir(&arena); in TEST()
76 x86_64::MachineIRBuilder builder(&machine_ir); in TEST()
82 EXPECT_EQ(x86_64::CheckMachineIR(machine_ir), x86_64::kMachineIRCheckDanglingEdge); in TEST()
87 x86_64::MachineIR machine_ir(&arena); in TEST()
97 x86_64::MachineIRBuilder builder(&machine_ir); in TEST()
103 EXPECT_EQ(x86_64::CheckMachineIR(machine_ir), x86_64::kMachineIRCheckDanglingEdge); in TEST()
[all …]
Dmachine_ir_opt_test.cc36 x86_64::MachineIR machine_ir(&arena); in TEST()
40 x86_64::MachineIRBuilder builder(&machine_ir); in TEST()
45 builder.Gen<x86_64::MovqRegReg>(vreg1, vreg1); in TEST()
46 builder.Gen<x86_64::MovqRegImm>(vreg1, 1); in TEST()
51 x86_64::RemoveDeadCode(&machine_ir); in TEST()
65 x86_64::MachineIR machine_ir(&arena); in TEST()
69 x86_64::MachineIRBuilder builder(&machine_ir); in TEST()
75 builder.Gen<x86_64::MovqRegImm>(vreg1, 4); in TEST()
76 builder.Gen<x86_64::MovqMemBaseDispReg>(vreg2, 0, vreg1); in TEST()
81 x86_64::RemoveDeadCode(&machine_ir); in TEST()
[all …]
Dlocal_guest_context_optimizer_test.cc34 x86_64::MachineIR machine_ir(&arena); in TEST()
36 x86_64::MachineIRBuilder builder(&machine_ir); in TEST()
46 x86_64::RemoveLocalGuestContextAccesses(&machine_ir); in TEST()
47 ASSERT_EQ(x86_64::CheckMachineIR(machine_ir), x86_64::kMachineIRCheckSuccess); in TEST()
53 auto disp = x86_64::AsMachineInsnX86_64(store_insn)->disp(); in TEST()
56 ASSERT_EQ(store_insn->RegAt(0), x86_64::kMachineRegRBP); in TEST()
66 x86_64::MachineIR machine_ir(&arena); in TEST()
68 x86_64::MachineIRBuilder builder(&machine_ir); in TEST()
78 x86_64::RemoveLocalGuestContextAccesses(&machine_ir); in TEST()
79 ASSERT_EQ(x86_64::CheckMachineIR(machine_ir), x86_64::kMachineIRCheckSuccess); in TEST()
[all …]
Dliveness_analyzer_test.cc32 void ExpectNoLiveIns(const x86_64::LivenessAnalyzer* liveness, in ExpectNoLiveIns()
40 void ExpectSingleLiveIn(const x86_64::LivenessAnalyzer* liveness, in ExpectSingleLiveIn()
50 void ExpectTwoLiveIns(const x86_64::LivenessAnalyzer* liveness, in ExpectTwoLiveIns()
67 x86_64::MachineIR machine_ir(&arena); in TEST()
69 x86_64::MachineIRBuilder builder(&machine_ir); in TEST()
75 builder.Gen<x86_64::MovqRegReg>(x86_64::kMachineRegRAX, vreg); in TEST()
78 x86_64::LivenessAnalyzer liveness(&machine_ir); in TEST()
98 MachineRegKind FakeInsnWithDefEarlyClobber::reg_kind_ = {&x86_64::kGeneralReg64,
103 x86_64::MachineIR machine_ir(&arena); in TEST()
105 x86_64::MachineIRBuilder builder(&machine_ir); in TEST()
[all …]
Drename_vregs_local_test.cc31 x86_64::MachineIR machine_ir(&arena); in TEST()
35 x86_64::MachineIRBuilder builder(&machine_ir); in TEST()
41 builder.Gen<x86_64::MovqRegImm>(vreg1, 0); in TEST()
42 builder.Gen<x86_64::MovqRegImm>(vreg2, 0); in TEST()
48 x86_64::RenameVRegsLocal(&machine_ir); in TEST()
64 x86_64::MachineIR machine_ir(&arena); in TEST()
68 x86_64::MachineIRBuilder builder(&machine_ir); in TEST()
74 builder.Gen<x86_64::MovqRegReg>(vreg2, MachineReg{4}); in TEST()
75 builder.Gen<x86_64::MovqRegReg>(vreg1, vreg2); in TEST()
82 x86_64::RenameVRegsLocal(&machine_ir); in TEST()
[all …]
Dmachine_ir_test_corpus.cc34 BuildDataFlowAcrossBasicBlocks(x86_64::MachineIR* machine_ir) { in BuildDataFlowAcrossBasicBlocks()
35 x86_64::MachineIRBuilder builder(machine_ir); in BuildDataFlowAcrossBasicBlocks()
47 builder.Gen<x86_64::MovqRegImm>(vreg1, 0); in BuildDataFlowAcrossBasicBlocks()
48 builder.Gen<x86_64::MovqRegImm>(vreg2, 0); in BuildDataFlowAcrossBasicBlocks()
52 builder.Gen<x86_64::MovqRegReg>(x86_64::kMachineRegRAX, vreg2); in BuildDataFlowAcrossBasicBlocks()
56 builder.Gen<x86_64::MovqRegReg>(x86_64::kMachineRegRAX, vreg1); in BuildDataFlowAcrossBasicBlocks()
63 BuildDataFlowFromTwoPreds(x86_64::MachineIR* machine_ir) { in BuildDataFlowFromTwoPreds()
64 x86_64::MachineIRBuilder builder(machine_ir); in BuildDataFlowFromTwoPreds()
79 builder.Gen<x86_64::MovqRegImm>(vreg, 0); in BuildDataFlowFromTwoPreds()
83 builder.Gen<x86_64::MovqRegImm>(vreg, 1); in BuildDataFlowFromTwoPreds()
[all …]
Dmachine_ir_test.cc32 x86_64::MachineIR machine_ir(&arena); in TEST()
34 x86_64::MachineIRBuilder builder(&machine_ir); in TEST()
38 builder.Gen<x86_64::MovqRegImm>(x86_64::kMachineRegRBP, 0); in TEST()
39 builder.Gen<x86_64::MovqRegImm>(x86_64::kMachineRegRBP, 0); in TEST()
40 builder.Gen<x86_64::MovqRegImm>(x86_64::kMachineRegRBP, 1); in TEST()
41 builder.Gen<x86_64::MovqRegImm>(x86_64::kMachineRegRBP, 1); in TEST()
42 builder.Gen<x86_64::MovqRegImm>(x86_64::kMachineRegRBP, 1); in TEST()
49 ASSERT_EQ(x86_64::CheckMachineIR(machine_ir), x86_64::kMachineIRCheckSuccess); in TEST()
58 x86_64::MachineIR machine_ir(&arena); in TEST()
59 x86_64::MachineIRBuilder builder(&machine_ir); in TEST()
[all …]
Dmachine_ir_analysis_test.cc35 void CheckLoopContent(x86_64::Loop* loop, std::vector<MachineBasicBlock*> body) { in CheckLoopContent()
48 x86_64::MachineIR machine_ir(&arena); in TEST()
50 x86_64::MachineIRBuilder builder(&machine_ir); in TEST()
66 builder.Gen<PseudoCondBranch>(CodeEmitter::Condition::kZero, bb2, bb3, x86_64::kMachineRegFLAGS); in TEST()
71 ASSERT_EQ(x86_64::CheckMachineIR(machine_ir), x86_64::kMachineIRCheckSuccess); in TEST()
72 auto loops = x86_64::FindLoops(&machine_ir); in TEST()
80 x86_64::MachineIR machine_ir(&arena); in TEST()
82 x86_64::MachineIRBuilder builder(&machine_ir); in TEST()
103 builder.Gen<PseudoCondBranch>(CodeEmitter::Condition::kZero, bb2, bb4, x86_64::kMachineRegFLAGS); in TEST()
108 ASSERT_EQ(x86_64::CheckMachineIR(machine_ir), x86_64::kMachineIRCheckSuccess); in TEST()
[all …]
Dcontext_liveness_analyzer_test.cc36 void CheckBBLiveIn(const x86_64::ContextLivenessAnalyzer* analyzer, in CheckBBLiveIn()
54 x86_64::MachineIR machine_ir(&arena); in TEST()
57 x86_64::MachineIRBuilder builder(&machine_ir); in TEST()
64 EXPECT_EQ(x86_64::CheckMachineIR(machine_ir), x86_64::kMachineIRCheckSuccess); in TEST()
65 x86_64::ContextLivenessAnalyzer analyzer(&machine_ir); in TEST()
73 x86_64::MachineIR machine_ir(&arena); in TEST()
78 x86_64::MachineIRBuilder builder(&machine_ir); in TEST()
89 EXPECT_EQ(x86_64::CheckMachineIR(machine_ir), x86_64::kMachineIRCheckSuccess); in TEST()
90 x86_64::ContextLivenessAnalyzer analyzer(&machine_ir); in TEST()
100 x86_64::MachineIR machine_ir(&arena); in TEST()
[all …]
Drename_copy_uses_test.cc26 namespace berberis::x86_64 { namespace
32 x86_64::MachineIR machine_ir(&arena); in TEST()
36 x86_64::MachineIRBuilder builder(&machine_ir); in TEST()
44 auto* add_insn = builder.Gen<x86_64::AddqRegReg>(vreg3, vreg1, kMachineRegFLAGS); in TEST()
66 x86_64::MachineIR machine_ir(&arena); in TEST()
70 x86_64::MachineIRBuilder builder(&machine_ir); in TEST()
78 auto* add_insn = builder.Gen<x86_64::AddqRegReg>(vreg3, vreg1, kMachineRegFLAGS); in TEST()
89 x86_64::MachineIR machine_ir(&arena); in TEST()
93 x86_64::MachineIRBuilder builder(&machine_ir); in TEST()
103 auto* add_insn = builder.Gen<x86_64::AddqRegReg>(vreg4, vreg3, kMachineRegFLAGS); in TEST()
[all …]
Drename_vregs_test.cc33 x86_64::MachineIR machine_ir(&arena); in TEST()
35 x86_64::MachineIRBuilder builder(&machine_ir); in TEST()
41 builder.Gen<x86_64::MovqRegImm>(vreg, 0); in TEST()
42 builder.Gen<x86_64::MovqRegReg>(x86_64::kMachineRegRAX, vreg); in TEST()
45 x86_64::VRegMap vreg_map(&machine_ir); in TEST()
55 EXPECT_EQ(x86_64::kMachineRegRAX, (*it)->RegAt(0)); in TEST()
60 x86_64::MachineIR machine_ir(&arena); in TEST()
62 x86_64::MachineIRBuilder builder(&machine_ir); in TEST()
71 builder.Gen<x86_64::MovqRegImm>(vreg, 0); in TEST()
75 builder.Gen<x86_64::MovqRegReg>(x86_64::kMachineRegRAX, vreg); in TEST()
[all …]
Dmachine_insn_intrinsics_tests.cc28 static_assert(x86_64::has_n_mem_v<
31 static_assert(!x86_64::has_n_mem_v<1>);
32 static_assert(!x86_64::has_n_mem_v<
35 static_assert(x86_64::has_n_mem_v<2,
38 static_assert(!x86_64::has_n_mem_v<
44 std::is_same_v<x86_64::constructor_args_t<
48 std::is_same_v<x86_64::constructor_args_t<TmpArg<intrinsics::bindings::GeneralReg64,
51 static_assert(std::is_same_v<x86_64::constructor_args_t<
56 x86_64::constructor_args_t<
/frameworks/libs/binary_translation/heavy_optimizer/riscv64/
Dfrontend.cc48 Gen<x86_64::CmpqRegReg>(arg1, arg2, GetFlagsRegister()); in CompareAndBranch()
68 Gen<x86_64::AddqRegImm>(target, offset, GetFlagsRegister()); in BranchRegister()
71 Gen<x86_64::AndqRegImm>(target, ~int32_t{1}, GetFlagsRegister()); in BranchRegister()
75 x86_64::Assembler::Condition HeavyOptimizerFrontend::ToAssemblerCond(BranchOpcode opcode) { in ToAssemblerCond()
78 return x86_64::Assembler::Condition::kEqual; in ToAssemblerCond()
80 return x86_64::Assembler::Condition::kNotEqual; in ToAssemblerCond()
82 return x86_64::Assembler::Condition::kLess; in ToAssemblerCond()
84 return x86_64::Assembler::Condition::kGreaterEqual; in ToAssemblerCond()
86 return x86_64::Assembler::Condition::kBelow; in ToAssemblerCond()
88 return x86_64::Assembler::Condition::kAboveEqual; in ToAssemblerCond()
[all …]
Dcall_intrinsic.h38 void SignExtend64(x86_64::MachineIRBuilder* builder, MachineReg dst, MachineReg src) { in SignExtend64()
44 builder->Gen<x86_64::MovsxbqRegReg>(dst, src); in SignExtend64()
46 builder->Gen<x86_64::MovzxbqRegReg>(dst, src); in SignExtend64()
50 builder->Gen<x86_64::MovsxwqRegReg>(dst, src); in SignExtend64()
52 builder->Gen<x86_64::MovzxwqRegReg>(dst, src); in SignExtend64()
55 builder->Gen<x86_64::MovsxlqRegReg>(dst, src); in SignExtend64()
63 void SignExtend64Result(x86_64::MachineIRBuilder* builder, MachineReg dst, MachineReg src) { in SignExtend64Result()
78 x86_64::CallImm::Arg GenPrepareCallImmArg(x86_64::MachineIRBuilder* builder, AssemblerType val) { in GenPrepareCallImmArg()
84 builder->Gen<x86_64::MovlRegImm>(temp_reg, static_cast<uint32_t>(val)); in GenPrepareCallImmArg()
86 return {reg, x86_64::CallImm::kIntRegType}; in GenPrepareCallImmArg()
[all …]
Dfrontend.h58 explicit HeavyOptimizerFrontend(x86_64::MachineIR* machine_ir, GuestAddr pc) in HeavyOptimizerFrontend()
178 Gen<x86_64::AndqRegImm>(aligned_addr, ~int32_t{sizeof(Reservation) - 1}, GetFlagsRegister()); in Lr()
184 Gen<x86_64::SubqRegReg>(addr_offset, aligned_addr, GetFlagsRegister()); in Lr()
188 x86_64::kMachineRegRBP, in Lr()
199 Gen<x86_64::AndqRegImm>(aligned_addr, ~int32_t{sizeof(Reservation) - 1}, GetFlagsRegister()); in Sc()
204 Gen<x86_64::MovqRegMemBaseDisp>(reservation_value, x86_64::kMachineRegRBP, value_offset); in Sc()
207 Gen<x86_64::SubqRegReg>(addr_offset, aligned_addr, GetFlagsRegister()); in Sc()
211 x86_64::kMachineRegRBP, in Sc()
242 builder_.Gen<x86_64::MacroUnboxNanFloat32AVX>(unboxed_result.machine_reg(), in GetFRegAndUnboxNan()
245 builder_.Gen<x86_64::MacroUnboxNanFloat32>(unboxed_result.machine_reg(), in GetFRegAndUnboxNan()
[all …]
/frameworks/libs/binary_translation/backend/
DAndroid.bp47 srcs: ["x86_64/lir_instructions.json"],
52 srcs: ["x86_64/reg_class_def.json"],
180 "x86_64/code.cc",
181 "x86_64/code_debug.cc",
182 "x86_64/code_emit.cc",
183 "x86_64/context_liveness_analyzer.cc",
184 "x86_64/insn_folding.cc",
185 "x86_64/liveness_analyzer.cc",
186 "x86_64/local_guest_context_optimizer.cc",
187 "x86_64/loop_guest_context_optimizer.cc",
[all …]
/frameworks/libs/binary_translation/code_gen_lib/include/berberis/code_gen_lib/
Dcode_gen_lib.h45 void EmitSyscall(x86_64::Assembler* as, GuestAddr pc);
46 void EmitDirectDispatch(x86_64::Assembler* as, GuestAddr pc, bool check_pending_signals);
47 void EmitIndirectDispatch(x86_64::Assembler* as, x86_64::Assembler::Register target);
48 void EmitExitGeneratedCode(x86_64::Assembler* as, x86_64::Assembler::Register target);
49 void EmitAllocStackFrame(x86_64::Assembler* as, uint32_t frame_size);
50 void EmitFreeStackFrame(x86_64::Assembler* as, uint32_t frame_size);
/frameworks/libs/binary_translation/backend/include/berberis/backend/x86_64/
Dmachine_ir_builder.h29 namespace berberis::x86_64 {
48 Gen<x86_64::MovqRegMemBaseDisp>(dst_reg, x86_64::kMachineRegRBP, offset); in GenGet()
52 Gen<x86_64::MovqMemBaseDispReg>(x86_64::kMachineRegRBP, offset, src_reg); in GenPut()
58 Gen<x86_64::MovsdXRegMemBaseDisp>(dst_reg, x86_64::kMachineRegRBP, offset); in GenGetSimd()
60 Gen<x86_64::MovdqaXRegMemBaseDisp>(dst_reg, x86_64::kMachineRegRBP, offset); in GenGetSimd()
69 Gen<x86_64::MovsdMemBaseDispXReg>(x86_64::kMachineRegRBP, offset, src_reg); in GenSetSimd()
71 Gen<x86_64::MovdqaMemBaseDispXReg>(x86_64::kMachineRegRBP, offset, src_reg); in GenSetSimd()
99 call->SetRegAt(x86_64::CallImm::GetFlagsArgIndex(), flag_register); in GenCallImm()
/frameworks/libs/binary_translation/code_gen_lib/
Dcode_gen_lib_riscv64_to_x86_64.cc42 void EmitCheckSignalsAndMaybeReturn(x86_64::Assembler* as) { in EmitCheckSignalsAndMaybeReturn()
50 as->Cmpb({.base = x86_64::Assembler::rbp, .disp = offset}, kPendingSignalsPresent); in EmitCheckSignalsAndMaybeReturn()
51 as->Jcc(x86_64::Assembler::Condition::kEqual, kEntryExitGeneratedCode); in EmitCheckSignalsAndMaybeReturn()
61 x86_64::Assembler as(mc); in GenTrampolineAdaptor()
100 void EmitSyscall(x86_64::Assembler* as, GuestAddr pc) { in EmitSyscall()
120 void EmitDirectDispatch(x86_64::Assembler* as, GuestAddr pc, bool check_pending_signals) { in EmitDirectDispatch()
139 void EmitExitGeneratedCode(x86_64::Assembler* as, x86_64::Assembler::Register target) { in EmitExitGeneratedCode()
148 void EmitIndirectDispatch(x86_64::Assembler* as, x86_64::Assembler::Register target) { in EmitIndirectDispatch()
170 as->Movq(as->rcx, {.base = as->rcx, .index = as->rax, .scale = x86_64::Assembler::kTimesEight}); in EmitIndirectDispatch()
174 as->Movq(as->rcx, {.base = as->rcx, .index = as->rax, .scale = x86_64::Assembler::kTimesEight}); in EmitIndirectDispatch()
[all …]
/frameworks/libs/binary_translation/tests/
Drun_host_tests.mk45 host_libc_root := prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.17-4.8
83 -$(4) LD_LIBRARY_PATH=$(host_libc_root)/x86_64-linux/lib64:$(host_libc_root)/sysroot/usr/lib \
122 …$(TARGET_OUT_TESTCASES)/berberis_ndk_program_tests_static.native_bridge/x86_64/berberis_ndk_progra…
127 …$(TARGET_OUT_TESTCASES)/berberis_ndk_program_tests_static.native_bridge/x86_64/berberis_ndk_progra…
132 …$(TARGET_OUT_TESTCASES)/berberis_ndk_program_tests_static.native_bridge/x86_64/berberis_ndk_progra…
137 …$(TARGET_OUT_TESTCASES)/berberis_ndk_program_tests_static.native_bridge/x86_64/berberis_ndk_progra…
144 $(TARGET_OUT_TESTCASES)/inline_asm_tests_riscv64.native_bridge/x86_64/inline_asm_tests_riscv64,\
149 $(TARGET_OUT_TESTCASES)/inline_asm_tests_riscv64.native_bridge/x86_64/inline_asm_tests_riscv64,\
154 $(TARGET_OUT_TESTCASES)/inline_asm_tests_riscv64.native_bridge/x86_64/inline_asm_tests_riscv64,\
159 $(TARGET_OUT_TESTCASES)/inline_asm_tests_riscv64.native_bridge/x86_64/inline_asm_tests_riscv64,\

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