1 /*
2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #include <debug.h>
29 #include <dev/uart.h>
30 #include <imx-regs.h>
31 #include <reg.h>
32
33 #define READ32(addr) (*REG32(addr))
34 #define WRITE32(val, addr) (READ32(addr) = val)
35
36 /* Register definitions */
37 #define URXD 0x0 /* Receiver Register */
38 #define UTXD 0x40 /* Transmitter Register */
39 #define UCR1 0x80 /* Control Register 1 */
40 #define UCR2 0x84 /* Control Register 2 */
41 #define UCR3 0x88 /* Control Register 3 */
42 #define UCR4 0x8c /* Control Register 4 */
43 #define UFCR 0x90 /* FIFO Control Register */
44 #define USR1 0x94 /* Status Register 1 */
45 #define USR2 0x98 /* Status Register 2 */
46 #define UESC 0x9c /* Escape Character Register */
47 #define UTIM 0xa0 /* Escape Timer Register */
48 #define UBIR 0xa4 /* BRM Incremental Register */
49 #define UBMR 0xa8 /* BRM Modulator Register */
50 #define UBRC 0xac /* Baud Rate Count Register */
51 #define UTS 0xb4 /* UART Test Register (mx31) */
52
53 /* UART Control Register Bit Fields.*/
54 #define URXD_CHARRDY (1 << 15)
55 #define URXD_ERR (1 << 14)
56 #define URXD_OVRRUN (1 << 13)
57 #define URXD_FRMERR (1 << 12)
58 #define URXD_BRK (1 << 11)
59 #define URXD_PRERR (1 << 10)
60 #define URXD_RX_DATA (0xFF)
61 #define UCR1_ADEN (1 << 15) /* Auto dectect interrupt */
62 #define UCR1_ADBR (1 << 14) /* Auto detect baud rate */
63 #define UCR1_TRDYEN (1 << 13) /* Transmitter ready interrupt enable */
64 #define UCR1_IDEN (1 << 12) /* Idle condition interrupt */
65 #define UCR1_RRDYEN (1 << 9) /* Recv ready interrupt enable */
66 #define UCR1_RDMAEN (1 << 8) /* Recv ready DMA enable */
67 #define UCR1_IREN (1 << 7) /* Infrared interface enable */
68 #define UCR1_TXMPTYEN (1 << 6) /* Transimitter empty interrupt enable */
69 #define UCR1_RTSDEN (1 << 5) /* RTS delta interrupt enable */
70 #define UCR1_SNDBRK (1 << 4) /* Send break */
71 #define UCR1_TDMAEN (1 << 3) /* Transmitter ready DMA enable */
72 #define UCR1_UARTCLKEN (1 << 2) /* UART clock enabled */
73 #define UCR1_DOZE (1 << 1) /* Doze */
74 #define UCR1_UARTEN (1 << 0) /* UART enabled */
75
76 #define UTS_FRCPERR (1 << 13) /* Force parity error */
77 #define UTS_LOOP (1 << 12) /* Loop tx and rx */
78 #define UTS_TXEMPTY (1 << 6) /* TxFIFO empty */
79 #define UTS_RXEMPTY (1 << 5) /* RxFIFO empty */
80 #define UTS_TXFULL (1 << 4) /* TxFIFO full */
81 #define UTS_RXFULL (1 << 3) /* RxFIFO full */
82 #define UTS_SOFTRST (1 << 0) /* Software reset */
83 #define UART_BASE (SOC_REGS_VIRT + (CONFIG_CONSOLE_TTY_BASE - SOC_REGS_PHY))
84
uart_init(void)85 void uart_init(void) {
86 /*
87 * Do nothing, debug uart share with normal world,
88 * everything for uart intialization were done in bootloader.
89 */
90 }
91
uart_flush_tx(int port)92 void uart_flush_tx(int port) {
93 while (!(READ32(UART_BASE + UTS) & UTS_TXEMPTY))
94 ;
95 }
96
uart_getc(int port,bool wait)97 int uart_getc(int port, bool wait) {
98 if (wait)
99 while (READ32(UART_BASE + UTS) & UTS_RXEMPTY)
100 ;
101 else if (!(READ32(UART_BASE + UTS) & UTS_RXEMPTY))
102 return -1;
103
104 return (READ32(UART_BASE + URXD) & URXD_RX_DATA);
105 }
106
uart_putc(int port,char c)107 int uart_putc(int port, char c) {
108 if (c == '\n')
109 uart_putc(0, '\r');
110
111 WRITE32(c, UART_BASE + UTXD);
112
113 /* wait until sent */
114 while (!(READ32(UART_BASE + UTS) & UTS_TXEMPTY))
115 ;
116
117 return 0;
118 }
119